FXLS93333 [NXP]
Dual channel inertial sensor;
| 型号： | FXLS93333 |
| 厂家： | 
NXP |
| 描述： | Dual channel inertial sensor |
| 文件： | 总254页 (文件大小：3592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FXLS9xxxx
Dual channel inertial sensor
Rev. 6 — 8 February 2021
Product data sheet
1 General description
The FXLS9xxxx is a dual channel DSI3, PSI5, SPI, and I2C compatible lateral (X-axis or
Y-axis) or vertical (Z-axis) inertial sensor.
2 Features
• Independent X-axis, Y-axis, or Z-axis ranges for each channel
– Medium g ranges from ± 15.5 g to ± 150 g nominal full-scale range
– High g ranges from ± 50 g to ± 500 g nominal full-scale range
• –40 °C to 125 °C operating temperature range
• DSI3 compatible
– Discovery mode for physical location identification
– High side bus switch output driver
– Command and response mode support for device configuration
– Periodic data collection mode support for sensor data transfers.
– Background diagnostic mode support during periodic data collection mode
• PSI5 Version 2.1 compatible
– Compatible modes:
– P10P-500/3L
– P10P-500/4H
– A10P-228/1L
– P10CRC-xxx/xx
– P16CRC-xxx/xx
– and many others
– Programmable time slots with 1 µs resolution
– Selectable baud rate: 125 kBd or 189 kBd
– 10- and 16-bit data options
– Selectable error detection: even parity, or 3-bit CRC
– Optional daisy chain with external low side switch
– Two-wire programming mode
• 32-bit SPI compatible serial interface
– 3.3 V or 5 V single supply operation
– Register read and write commands
– Sensor data transmission commands
– 12-bit data, left justified in a 16-bit data field
– Command echo with 3-bit source identification
– 2-bit basic status and 2-bit detailed status fields
– 8-bit CRC
NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
I2C compatible serial interface (UM10204[1])
•
– Slave mode operation
– Standard mode, fast mode, and fast mode plus support
• Independent programmable arming functions for each channel
• DSP
– Dual, independent signal chains from ADC to Communications Interface
– Up to a fourth order low-pass filter with rolloff frequency options from 12.5 Hz to 1500
Hz
– Optional single pole high pass filter with fast startup and output rate
• Limiting
– Optional moving average
– Optional 16 to 1 output interpolation
• Pb-free 16-Pin QFN 4 mm x 4 mm x 1.45 mm package
3 Applications
3.1 Automotive
• Airbag, Collision/Crash detection
• Active suspension vibration monitoring
3.2 Industrial
• Machine condition monitoring
4 Ordering information
Table 1.ꢀOrdering information
Type number
Package
Name
Description
Version
Plastic, thermal enhanced low profile quad flat non-leaded package; 16 SOT1688-1(SC)
terminals; 0.8 mm pitch; 4 mm x 4 mm x 1.45 mm body
FXLS9xxxxAESR2
FXLS9xxxxAEBR2
HLQFN16
Plastic, thermal enhanced low profile quad flat non-leaded package,
dimple wettable flank; 16 terminals; 0.8 mm pitch; 4 mm x 4 mm x 1.45
mm body
SOT1688-1(DD)
4.1 Ordering options
Table 2.ꢀOrdering options
Device
Channel 0
Channel 1
Protocol
Axis
X
Range
Axis
Y
Range
FXLS90322
FXLS90422
FXLS90722
FXLS90333
FXLS90433
M
M
M
H
H
M
M
M
H
H
SPI/DSI3
SPI/DSI3
SPI/DSI3
SPI/DSI3
SPI/DSI3
X
Z
Y
Z
X
Y
X
Z
FXLS9xxxx
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Product data sheet
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FXLS9xxxx
Dual channel inertial sensor
Table 2.ꢀOrdering options...continued
Device
Channel 0
Channel 1
Protocol
Range
Axis
Y
Range
Axis
Z
FXLS90733
FXLS93322
FXLS93422
FXLS93722
FXLS93421
FXLS93333
FXLS93433
FXLS93733
H
M
M
M
M
H
H
H
H
M
M
M
L
SPI/DSI3
PSI5
X
Y
X
Z
PSI5
Y
Z
PSI5
X
Z
PSI5
X
Y
H
H
H
PSI5
X
Z
PSI5
Y
Z
PSI5
5 Marking
Data Code Legend:
F: ASECL assembly site
WL: 2 alpha character representation of the wafer lot
YW: 2 alpha character representation of the year and work week
Z: Assembly Split
Fxxxxx
WLYWZ
Data Code Legend:
N: ATBK assembly site
WL: 2 alpha character representation of the wafer lot
YW: 2 alpha character representation of the year and work week
Z: Assembly Split
Nxxxxx
WLYWZ
aaa-030573
Figure 1.ꢀPart marking
FXLS9xxxx
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Product data sheet
Rev. 6 — 8 February 2021
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FXLS9xxxx
Dual channel inertial sensor
6 Application diagrams
6.1 DSI3 application diagrams
6.1.1 DSI3 discovery mode application diagram
Optional
Bus Termination
V
BUS_I
IDATA
BUF
BUSIN
C2
R1
C4
V
C1
SS
BUSRTN
BUS_O
BUSRTN
BUSOUT
C3
aaa-030552
Figure 2.ꢀDSI3 discovery mode application diagram
Table 3.ꢀDSI3 discovery mode external component recommendations
Ref
Des
Type
Typical value
description
Component value selection and range
Comment
R1
General
purpose
330 Ω, 5 %,
200 PPM
The system level communication, EMC, and
ESD testing determine the optimal value of this
component.
Optional bus termination for high inductance bus
wire connections. For optimal EMC performance,
this component along with C4 are to be placed as
close to the BUS_I and BUSRTN connector pins
as possible.
C1
C2
Ceramic
Ceramic
220 pF,
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
For optimal EMC performance, this component
along with R1 are to be placed as close to the
BUS_I and BUSRTN connector pins as possible.
10 %, 50 V
minimum,
X7R
0.47 µF,
10 %, 10 V
minimum,
X7R
The optimal value of this component should be
determined based on the system level micro-cut to be placed as close to the VBUF and BUSRTN
immunity requirement. To achieve the specified
power supply rejection, the minimum value
including all tolerances is 0.22 µF. The maximum
specified value including all tolerances is 2 µF.
For optimal EMC performance, this component is
pins as possible.
C3
C4
Ceramic
Ceramic
100 pF,
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
For optimal EMC performance, this component
is to be placed as close to the BUS_O and
BUSRTN connector pins as possible.
10 %, 50 V
minimum,
X7R
2.2 nF,
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
Optional bus termination for high inductance bus
wire connections. For optimal EMC performance,
this component along with R1 are to be placed as
close to the BUS_I and BUSRTN connector pins
as possible.
10 %, 50 V
minimum,
X7R
The total bus capacitance must not exceed the values specified in the DSI3[2] standard.
Note:
The external components are dependent on the bus master and bus impedance and may vary from application to application.
FXLS9xxxx
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Product data sheet
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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
6.2 PSI5 application diagrams
6.2.1 PSI5 parallel or universal mode application diagram
R1
V
V
V
V
BUF
CE
SS
CC
R2
I
DATA
C4
C2
C3
C1
V
SS
aaa-030556
Figure 3.ꢀPSI5 parallel or universal mode application diagram
Table 4.ꢀPSI5 parallel or universal mode external component recommendations
Ref
Type
Description Component value selection and range
Purpose
Des
R1
General
purpose
82 Ω, 5 %,
200 PPM
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
VCC filtering and signal damping
For proper device function, the minimum value
can be 0 Ω. The maximum value is determined
by the minimum bus voltage provided at the
module pin and the minimum operating voltage of
the device. To meet the minimum PSI5 operating
voltage at the module pin, the maximum
resistance including all tolerances is 89.0 Ω.[1]
R2
General
purpose
27 Ω, 5 %,
200 PPM
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
IDATA filtering and signal damping
For proper device function, the minimum value
can be 0 Ω. The maximum value is determined
by the minimum bus voltage provided at the
module pin. To meet the minimum PSI5 operating
voltage at the module pin, the maximum
resistance including all tolerances is 66.6 Ω. If
the low response current is used, the maximum
resistance including all tolerances is 133 Ω.
C1
C2
C3
Ceramic
Ceramic
Ceramic
2.2 nF, 10
%, 50 V
minimum,
X7R
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing
VCC power supply decoupling and signal
damping. For optimal EMC performance, this
component is to be placed as close to the BUS_I
and BUSRTN connector pins as possible.
15 nF, 10
%, 50 V
minimum,
X7R
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing[2]
VCC power supply decoupling. For optimal EMC
performance, this component is to be placed
as close to the BUS_I and BUSRTN pins as
possible.
470 pF, 10
%, 50 V
minimum,
X7R
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing
IDATA Filtering and Signal Damping
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
Table 4.ꢀPSI5 parallel or universal mode external component recommendations...continued
Ref
Type
Description Component value selection and range
Purpose
Des
C4
Ceramic
0.47 µF,
10 %, 10 V
minimum,
X7R
The optimal value of this component should be
determined based on the system level micro-cut to be placed as close to the VBUF and BUSRTN
immunity requirement. To achieve the specified
power supply rejection, the minimum value
including all tolerances is 0.22 µF. The maximum
specified value including all tolerances is 2 µF.
For optimal EMC performance, this component is
pins as possible.
Note:
The total bus capacitance must not exceed the values specified in the PSI5 standard.
[1] R1 must be sized to handle both the programming current at the maximum rated temperature for programming and the operating current at the maximum
rated temperature for operation.
[2] If the high baud rate is used, NXP recommends reducing the value of C2. The actual value depends on the bus configuration and number of slaves.
6.2.2 PSI5 daisy chain mode application diagram
R1
V
V
CC
CE
V
BUF
R2
I
DATA
C2
R3
C3
C1
C4
V
V
V
SS
SS
R4
BUSSW_L
M1
SS_OUT
aaa-030558
Figure 4.ꢀPSI5 daisy chain mode application diagram
Table 5.ꢀPSI5 daisy chain mode external component recommendations
Ref
Des
Type
Description Component value selection and range
Purpose
VCC filtering and signal damping
R1
General
purpose
82 Ω, 5 %,
200 PPM
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
For proper device function, the minimum
value can be 0 Ohms. The maximum value is
determined by the minimum bus voltage provided
at the module pin and the minimum operating
voltage of the device. To meet the minimum
PSI5 operating voltage at the module pin, the
maximum resistance including all tolerances is
89.0 Ohms.
R2
General
purpose
27 Ω, 5 %,
200 PPM
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
IDATA filtering and signal damping
For proper device function, the minimum
value can be 0 Ohms. The maximum value
is determined by the minimum bus voltage
provided at the module pin. To meet the minimum
PSI5 operating voltage at the module pin, the
maximum resistance including all tolerances is
66.6 Ohms. If the low response current is used,
the maximum resistance including all tolerances
is 133 Ohms.
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
Table 5.ꢀPSI5 daisy chain mode external component recommendations...continued
Ref
Type
Description Component value selection and range
Purpose
Des
R3
General
purpose
20 kΩ, 5 %,
200 PPM
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
Gate resistor for external low side daisy chain
FET
C1
Ceramic
Ceramic
Ceramic
Ceramic
2.2 nF, 10
%, 50 V
minimum,
X7R
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
VCC power supply decoupling and signal
damping. For optimal EMC performance, this
component is to be placed as close to the BUS_I
and BUSRTN connector pins as possible.
C2
C3
C4
15 nF, 10
%, 50 V
minimum,
X7R
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
VCC power supply decoupling. For optimal EMC
performance, this component is to be placed
as close to the BUS_I and BUSRTN pins as
possible.
470 pF, 10
%, 50 V
minimum,
X7R
The optimal value of this component should be
determined by the system level communication,
EMC, and ESD testing.
IDATA Filtering and Signal Damping
0.47 µF,
10 %, 10 V
minimum,
X7R
The optimal value of this component should be
determined based on the system level micro-cut to be placed as close to the VBUF and BUSRTN
immunity requirement. To achieve the specified
power supply rejection, the minimum value
including all tolerances is 0.22 µF. The maximum
specified value including all tolerances is 2 µF.
For optimal EMC performance, this component is
pins as possible.
R4
General
purpose
100 kΩ, 5 %, The optimal value of this component should be
Gate pulldown resistor for external low side daisy
chain FET
200 PPM
determined by the system level communication,
EMC, and ESD testing.
M1
N-Channel NTR4501NT1GT, he optimal value of this component should be
Low side daisy chain transistor
or similar
determined by the system level communication,
EMC, and ESD testing.
MOSFET
Note:
The total bus capacitance must not exceed the values specified in the PSI5 standard.
R1 must be sized to handle both the programming current at the maximum rated temperature for programming and the operating
current at the maximum rated temperature for operation.
If the high baud rate is used, NXP recommends reducing the value of C2. The actual value depends on the bus configuration and
number of slaves.
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
6.3 SPI application diagram
V
CC
V
SS_B
SCLK
MOSI
MISO
CC
V
CCIO
C1
V
SS
PCM
aaa-030560
Figure 5.ꢀSPI application diagram
Table 6.ꢀSPI external component recommendations
Ref Des
Type
Typical value description
Comment
C1
Ceramic
0.1 µF, 10 %, 10 V Minimum,
X7R
VCC power supply decoupling.
For optimal EMC performance,
this component is to be placed
as close to the VCC and VSS pins
as possible.
6.4 I2C application diagram
V
V
V
CC
CC
CC
V
CC
R1
SS_B
SCL
R2
R3
V
BUF
C1
V
SS
SDA
aaa-030561
Figure 6.ꢀI2C application diagram
Table 7.ꢀI2C external component recommendations
Ref Des
Type
Description
Purpose
R1
General purpose
General purpose
General purpose
Ceramic
1000 Ω, 5 %, 200 PPM
1000 Ω, 5 %, 200 PPM
1000 Ω, 5 %, 200 PPM
I2C selection pin pull-up resistor
Serial clock pull-up resistor
Serial data pull-up resistor
VCC power supply decoupling
R2
R3
C1
0.1 µF, 10 %, 10 V Minimum,
X7R
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
7 Block diagram
BUFFER
VOLTAGE
REGULATOR
V
V
BUF
REF
BUS_I
V
BUF
V
V
REG
INTERNAL
VOLTAGE
REGULATOR
REGA
REFERENCE
VOLTAGE
BUS_I
LOW VOLTAGE
DETECTION
COMMAND
DECODER
V
SS
OTP
OSCILLATOR
PROGRAMMING
INTERFACE
OTP
IDATA
ARRAY
SERIAL
SS_B
ENCODER
SPI
SCLK/SCL
MOSI
BUSRTN
CONTROL
LOGIC
IDATA
MISO/SDA
2
I C
R
SENSE
BUS_O
ARM AND
PCM LOGIC
ARM/PCM0
ARM/PCM1
DAISY CHAIN
SWITCH DRIVER
ARM AND
PCM LOGIC
BUSSW_L
OFFSET
DAC
CH0 DSP
OVER-
DAMPED
G-CELL
OFFSET
MONITOR
SINC
FILTER
IIR
LPF
USER
SENSE
SCALING
INTERPOLATION
∑
DIGITAL
CLIPPING
OUTPUT
SCALING
HPF
TRIM
CONVERTER
SELF TEST
OFFSET
DAC
CH1 DSP
OVER-
DAMPED
G-CELL
OFFSET
MONITOR
SINC
FILTER
IIR
LPF
USER
SENSE
SCALING
INTERPOLATION
∑
DIGITAL
CLIPPING
OUTPUT
SCALING
HPF
TRIM
CONVERTER
SELF TEST
aaa-030564
Figure 7.ꢀDual channel internal block diagram
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
8 Device orientation diagrams
+1 g
aaa-030567
Figure 8.ꢀOrientation diagram
Table 8.ꢀDual axis device orientation
Ch0: 0 g
Ch1: –1 g
Ch0: 0 g
Ch1: 0 g
Ch0: –1 g
Ch1: 0 g
Ch0: +1 g
Ch1: 0 g
Ch0: +1 g
Ch1: 0 g
Ch0: 0 g
Ch1: 0 g
Ch0: 0 g
Ch1: +1 g
Ch0: 0 g
Ch1: 0 g
Ch0: +1 g
Ch1: 0 g
Ch0: –1 g
Ch1: 0 g
Ch0: –1 g
Ch1: 0 g
Ch0: 0 g
Ch1: 0 g
Ch0: 0 g
Ch1: 0 g
Ch0: 0 g
Ch1: +1 g
Ch0: 0 g
Ch1: +1 g
Ch0: 0 g
Ch1: 0 g
Ch0: 0 g
Ch1: –1 g
Ch0: 0 g
Ch1: –1 g
XY
XZ
YZ
9 Pinning information
9.1 Pinning: SPI or I2C mode
terminal 1
index area
16 15 14 13
17
FXLS9xxxx
V
1
2
3
4
12 PCM0/ARM0
CC
PCM1/ARM1
TEST0
11 MISO/SDA
10 MOSI
TEST1
9
SCLK/SCL
5
6
7
8
aaa-030596
Transparent topview
Figure 9.ꢀDevice pinout: SPI or I2C mode
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
9.2 Pin description: SPI or I2C mode
Table 9.ꢀDevice pinout: SPI or I2C mode
Pin
Pin Name
Definition
Description
1
VCC
Supply
NXP recommends that this pin be connected to VCC. Optionally, this pin can
be unterminated.
2
PCM1 / ARM1 Channel 1
PCM
This pin has multiplexed functions:
• When the channel 1 arming output is selected, the pin can be configured
as an open-drain, active low output with a pull-up current; or an open-drain,
active high output with a pull-down current.
Channel 1 Arm
• When PCM mode is selected, this pin can be configured as a digital output
with PCM signal proportional to the channel 1 sensor data.
If unused, or in I2C mode, NXP recommends that this pin be unterminated.
3, 4, 5, 6 TEST
Test Pin
NXP recommends that these pins be unterminated. Optionally, this pin can be
tied to VSS
.
7, 14
8
VSS
Supply Return This pin is the supply return node.
SS_B
Slave select
SPI Clock
In SPI mode, this input pin provides the slave select for the SPI port. An
internal pull-up device is connected to this pin.
In I2C mode, this pin must be connected to VBUF with an external pull-up
resistor as shown in Figure 6.
9
SCLK/SCL
MOSI
In SPI mode, this input pin provides the serial clock. An internal pull-down
device is connected to this pin.
In I2C mode, this input pin provides the serial clock. This pin must be
connected to VBUF with an external pull-up resistor as shown in Figure 6.
10
SPI Data In
SPI Data Out
In SPI mode, this pin functions as the serial data input to the SPI port. An
internal pull-down device is connected to this pin.
In I2C mode, NXP recommends that this pin be unterminated. Optionally, this
pin can be connected to VSS
.
11
12
MISO/SDA
In SPI mode, this pin functions as the serial data output.
In I2C mode, this pin functions as the serial data input/output. This pin must be
connected to VBUF with an external pull-up resistor as shown in Figure 6.
PCM0 / ARM0 Channel 0
PCM
This pin has multiplexed functions:
• When the channel 0 arming output is selected, the pin can be configured
as an open-drain, active low output with a pull-up current; or an open-drain,
active high output with a pull-down current.
Channel 0 Arm
• When PCM mode is selected, this pin can be configured as a digital output
with PCM signal proportional to the channel 0 sensor data.
If unused, or in I2C mode, NXP recommends that this pin be unterminated.
13, 15, 16 VCC
Supply
This pin is connected to the supply for the device. An external capacitor must
be connected between this pin and VSS as shown in Figure 5 and Figure 6.
17
PAD
Die Attach Pad This pin is the die attach flag, and must be connected to VSS. See Section 16
for die attach pad connection details.
FXLS9xxxx
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Product data sheet
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FXLS9xxxx
Dual channel inertial sensor
9.3 Pinning: DSI3 or PSI5 mode
terminal 1
index area
16 15 14 13
17
BUS_O
1
2
3
4
12 TEST4
TEST5
BUSSW_L
TEST1
11 TEST_MISO
10 TEST_MOSI
FXLS9xxxx
9
TEST_SCLK
5
6
7
8
aaa-030598
Transparent topview
Figure 10.ꢀDevice pinout: DSI3 or PSI5 mode pinout
9.4 Pin description: DSI3 or PSI5 mode
Table 10.ꢀDevice pinout: DSI3 or PSI5 mode pinout
Pin
Pin Name
Definition
Description
1
BUS_O
Supply Out
This pin is connected to the IDATA pin through an internal sense resistor
and provides the supply connection to the next slave in a daisy chain
configuration.
In DSI3 mode, an external capacitor must be connected between this pin and
VSS as shown in Figure 2.
In PSI5 mode, NXP recommends that this pin be unterminated. Optionally,
this pin can be connected to IDATA.
2, 4, 6, 12 TEST
Test Pin
NXP recommends that these pins be unterminated. Optionally, this pin can be
tied to VSS
.
3, 5
BUSSW_L
Low Side Bus In PSI5 daisy chain mode, these pins are connected to the gate of an N-
Switch Driver
channel FET which connects BUSRTN to the next slave in the daisy chain.
An external pulldown resistor is required on the gate of the N-channel FET
as shown in Figure 4. Note: both pins provide the identical function. It is
necessary to connect only one pin is to the bus switch gate.
If unused, or in DSI3 mode, NXP recommends that this pin be unterminated.
Optionally, this pin can be tied to VSS
.
7, 14
8
BUSRTN/VSS Supply Return This pin is the supply return node.
TEST_SS_B Slave select
TEST_SCLK SPI Clock
TEST_MOSI SPI Data In
TEST_MISO SPI Data Out
NXP recommends that this pin be unterminated. Optionally, this pin can be
connected to VBUF
.
9
NXP recommends that this pin be unterminated. Optionally, this pin can be
connected to VSS
.
10
11
NXP recommends that this pin be unterminated. Optionally, this pin can be
connected to VSS
.
This pin must be left unconnected.
FXLS9xxxx
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Product data sheet
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FXLS9xxxx
Dual channel inertial sensor
Table 10.ꢀDevice pinout: DSI3 or PSI5 mode pinout...continued
Pin
Pin Name
Definition
Description
13
VBUF
Power
Supply
This pin is connected to a buffer regulator for the internal circuitry. The buffer
regulator supplies the internal regulators to provide immunity from EMC and
supply dropouts. An external capacitor must be connected between this pin
and VSS as shown in Figure 2, Figure 3, and Figure 4.
15
BUS_I
Supply and
This pin is connected to the supply line and supplies power to the device. An
external filter must be connected between this pin and BUSRTN as shown in
Figure 2, Figure 3, and Figure 4.
Communication
Receiver
16
17
IDATA
PAD
Communication This pin modulates the response current for DSI3 and PSI5 communication.
Transmitter
An external filter must be connected between this pin and BUSRTN as shown
in Figure 2, Figure 3, and Figure 4.
Die Attach Pad This pin is the die attach flag, and must be connected to VSS. See Section 16
for die attach pad connection details.
10 Electrical characteristics
Section 10.1 through Section 10.20 contain tables with "Test notes". The note identifiers
cross reference to the identifiers and descriptions found in Table 11.
Table 11.ꢀTest notes legend
Identifier Description
*
Indicates critical characteristic.
1
Parameter tested 100 % at final test. Temperature = –40 °C, 25 °C, and 105 °C, VBUS_I
= 7 V, Unless otherwise stated
2
3
4
5
6
7
8
Parameter tested 100 % at final test during safe launch
Parameter verified by pass/fail testing at final test
Parameter verified by pass/fail testing at final test during safe launch
Parameter verified by qualification testing
Parameter verified by characterization
Functionality verified by modeling, simulation and/or design verification.
Circuit integrity assured through IDDQ and scan testing. Timing is determined by
internal system clock frequency.
9
Parameter verified by functional evaluation
10
Thermal resistance provided with device mounted to a 2 layer, 1.6 mm FR4 PCB as
documented in AN1902 with 1 signal layer and 1 ground layer.
11
Digital low-pass filter characteristics are specified independently and do not include g-
cell characteristics. Higher frequency filters will have lower system cut-off frequencies
due to the g-cell damping.
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10.1 Maximum ratings
Maximum ratings are the extreme limits to which the device can be exposed without
permanently damaging it.
Table 12.ꢀMaximum ratings
#
Rating
Symbol
Value
Unit
Test
notes
Supply Voltage (BUS_I/VCC, IDATA, BUS_O)
6
6
6
6
6
5
5
9
9
5
3381
3383
3384
3385
3386
3387
3390
3389
3388
3391
Reverse Current externally limited to ≤ 160 mA, t ≤ 100 ms
Continuous
BUS_IREV
BUS_IMAX
VBUFMAX
VIOMAX
ISUPMAX
gpms
–0.7
+20.0
V
V
VBUF
–0.3 to +7.0
–0.3 to VBUF +0.3
200
V
SCLK, SS_B, MOSI, MISO (High Z), PCM0/ARM0, PCM1/ARM1
BUS_I/VCC, IDATA, and BUS_O Continuous Current
Powered Shock (six sides, 0.5 ms duration)
Unpowered Shock (six sides, 0.5 ms duration)
Powered Shock (six sides, 0.5 ms duration)
Unpowered Shock (six sides, 0.5 ms duration)
Drop Shock (to concrete, tile or steel surface, 10 drops, any orientation)
V
mA
g
±2000
gshock
±2000
g
gpms
±4000
g
gshock
±4000
g
hDROP
1.5
m
Electrostatic Discharge (per AEC-Q100[4]), External Pins
3392 BUS_I/VCC, IDATA, BUS_O, BUSRTN, HBM (100 pF, 1.5 kΩ)
5
VESD
±4000
V
Electrostatic Discharge (per AEC-Q100[4]
)
5
5
3393
3395
HBM (100 pF, 1.5 kΩ)
CDM (R = 0 Ω)
VESD
VESD
±2000
±750
V
V
Temperature Range
5
7
3396
3397
3400
Storage
Tstg
TJ
–55 to +150
–55 to +150
47
°C
°C
Junction
7, 10
Thermal Resistance
θJA
°C/W
10.2 Operating range - DSI / PSI5
Table 13.ꢀOperating range - DSI / PSI5
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
*
*
*
5, 6, 7
3398
DSI3 Supply Voltage (VHIGH), Measured at BUS_I
DSI3 Supply Voltage (VLOW) Measured at BUS_I
PSI5 Supply Voltage (Excluding Sync Pulse)
Supply Voltage (Undervoltage)
VHIGH
V LOW
V PSI5
—
20.0
—
V
V
V
V
1
1
10468
10467
10466
4.0
4.0
—
—
16.5
3, 6
V BUS_I_UV VBUS_I_UV_F
—
10.0
—
VLOW_min
Programming Voltage (IPP ≤ 5 mA, 10 °C ≤ TA ≤ 40 °C)
10469 Applied to BUS_I
3, 6
7, 9
VPP
9.0
11.0
V
V
ESD Operating Voltage (No Device Reset, CBUS_IN = 220 pF)
10470
Maximum ±15 kV Air Discharge, 330 pF, 2.0 kΩ
VBUS_I_ESD
V
10.0
BUS_I_LOW_min
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Table 13.ꢀOperating range - DSI / PSI5...continued
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Operating Temperature Range
TL
TH
1
5, 6, 7
6
10471
10490
10472
Production Tested Operating Temperature Range
TA
TA
–40
—
—
—
+105
°C
°C
Guaranteed Operating Temperature Range
Supply Power On Ramp Rate
–40
+125
10
VCC_RAMP_SAT 0.00001
V / µs
10.3 Operating range - SPI / I2C
Table 14.ꢀOperating range - SPI / I2C
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
5, 6, 7
10501
10502
10504
Supply Voltage (VCC = VBUF) Measured at VBUF
Supply Voltage (VCC = VBUF) Measured at VBUF
Supply Voltage (Undervoltage)
VCC_BUF
VCC_BUF
—
—
—
—
5.25
—
V
V
V
*
1
3.135
3, 6
V
VBUF_UV_F
VCC_BUF_min
BUF_UV_OP
Operating Temperature Range
TL
TH
1
5, 6, 7
6
10507
10508
10509
Production Tested Operating Temperature Range
TA
TA
–40
—
—
—
+105
°C
°C
Guaranteed Operating Temperature Range
Supply Power On Ramp Rate
–40
+125
10
VCC_RAMP_SPI 0.00001
V/µs
10.4 Electrical characteristics - supply and I/O
Table 15.ꢀElectrical characteristics - supply and I/O
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Quiescent Supply Current
*
*
*
1
1
39203
39204
39205
VBUS_I = 4 V, DSI, PSI5
Iq_4_2
Iq_20_2
Iq_31_2
4.0
4.0
—
9.2
9.2
—
10.0
10.0
10.0
mA
mA
mA
VBUS_I = 20 V, DSI / PSI5
VBUS_I = 3.135 V, SPI, I2C
3, 6
Response Current
*
*
1
1
10515
10519
DSI Low
DSI High
IR_DSI_1
IR_DSI_2
Iq + 10.5
Iq + 12.0
Iq + 13.5
mA
mA
IR_DSI_1
+ 10.5
IR_DSI_1
+ 12.0
IR_DSI_1
+ 13.5
*
*
1
6
6
1
10518
10517
PSI5 Normal
IR_PSI5
IR_PSI5_Low
tINRUSH
VBUF
Iq + 22.0
Iq + 11.0
—
Iq + 26.0
Iq + 13.0
—
Iq + 30.0
Iq + 15.0
40
mA
mA
mA
V
PSI5 Low
In-Rush Current (No external Components)
Internally Regulated Voltage (VBUF, VBUS_I = 4 V, VBUS_I = 20 V)
10522
2.85
3.00
3.15
Low Voltage Detection Threshold
*
*
3, 6
6
10523
10542
BUS_I Falling, COMMTYPE = 2, 3, 4, 5, 6, 7
VBUS_I_UV_F
VBUS_I_UV_01
VBUF_UV_F
3.85
3.31
2.64
3.95
3.50
2.74
4.00
3.67
2.84
V
V
V
BUS_I Falling, COMMTYPE = 0, 1
VBUF Falling
3, 6
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Table 15.ꢀElectrical characteristics - supply and I/O...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
VBUF External Capacitor
7, 9
7, 9
10525
10543
Capacitance
CVBUF
ESR
100
0
1000
—
2000
200
nF
ESR (including interconnect resistance)
mΩ
DSI3 VLOW Detection Threshold (Section 12.1.1)
VLOW_min ≤ (VBUS_I – VSS) ≤ VHIGH_max
3, 6
10526
VLOW Detection Threshold
*VDELTA_THRESH VHIGH
– 1.25
VHIGH
– 1.0
VHIGH
0.75
–
V
DSI3 Discovery Mode Current Sense (Section 12.2.3)
6
10527
10545
Sense Resistor
RSENSE
1.0
6
1.3
12
3.0
18
Ω
3, 6
IRESP Detection Threshold (IBUS_O_q ≤ 24 mA)
IRESP_Offset
mA
PSI5 Synchronization Pulse
VPSI5_min ≤ (VBUS_I – VSS) ≤ BUS_IMAX
3, 6
7
10528
10529
10530
DC Sync Pulse Detection Threshold
ΔVSYNC
ISYNC_PD
V PSI5+1.0 V PSI5+1.5 V PSI5+2.0
V
mA
V
PSI5 Sync Pulse Pulldown Current
—
IR_PSI5
—
—
3, 6
Bus Switch Output High Voltage (BUSSW_L, ILoad = –100 µA)
VBUSSW_L_OH
VBUF
VBUF
– 0.35
3, 6
3, 6
3, 6
10546
10549
10536
Bus Switch Output Low Voltage (BUSSW_L, ILoad = 100 µA)
Open-Drain Output Pulldown Current (ARM0, ARM1, VARM = 1.5 V)
Open-Drain Output Pullup Current (ARM0, ARM1, VARM = 1.5 V)
VBUSSW_L_OL
IODPD
—
10
—
20
0.1
100
–10
V
µA
µA
IODPU
–100
–20
Output High Voltage (MISO/SDA, PCM0/ARM0, PCM1/ARM1
3, 6
3, 6
21205
10547
VBUF = VCC, ILoad = –1 mA
VOH
VBUF – 0.2
VBUF – 0.2
—
—
VBUF
VBUF
V
V
VBUF internally regulated, ILoad = –1 mA
VOH_SAT
Output Low Voltage (MISO/SDA, PCM0/ARM0, PCM1/ARM1
3, 6
3, 7
3, 7
7
10547
10537
10560
10561
10562
10565
10563
ILoad = 2 mA
VOL
VIH
—
2.0
—
—
—
0.4
—
V
V
Input High Voltage SS_B, SCLK/SCL, MOSI
Input Low Voltage SS_B, SCLK/SCL, MOSI
Input Voltage Hysteresis SS_B, SCLK, MOSI
Input Current High (at VIH) (SCLK/SCL, MOSI)
Input Current Low (at VIL) (SS_B)
MISO Output Leakage
VIL
—
1.0
—
V
VI_HYST
IIH
—
0.250
20
V
6
10
70
µA
µA
µA
6
IIL
–70
–10
–20
—
–10
10
6
IMISO_Lkg
10.5 Electrical characteristics - temperature sensor signal chain
Table 16.ꢀElectrical characteristics - temperature sensor signal chain
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
7, 9
10520
10559
Temperature Measurement Range
Temperature Output at 25 °C
TRANGE
T25
–50
83
—
+160
103
°C
6, 7
93
LSB
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Table 16.ꢀElectrical characteristics - temperature sensor signal chain...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Range of Output (8 bit)
7, 8, 9
6, 7
10558
10557
10556
Unsigned Temperature
TRANGE
TSENSE
TACC
0
—
255
LSB
LSB/°C
°C
Temperature Output Sensitivity (8 bit)
Temperature Output Accuracy (8 bit)
1.10
6, 7
–20
+20
+2
Temperature Output Noise RMS (8 bit)
10555 Standard Deviation of 50 readings, fSamp = 8 kHz
6, 7
TRMS
⎯
⎯
LSB
10.6 Electrical characteristics - inertial sensor signal chain: High g
Table 17.ꢀElectrical characteristics - inertial sensor signal chain: High g
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Sensitivity
Total Sensitivity Error Including Linearity (From Trim Target, Output @ 0 Hz)
*
*
1
1
10584
High g, lateral, or Z-Axis, verified with a 50 g Range
SENSERRH
SENS50H
–5
—
+5
%
High g Standard Trim Range 12-bit Sensitivity Target, lateral, or Z-Axis
10612
± 50 g Range (± 2047 LSB, U_SNS_SHIFT = 0x3, U_SNS_MULT = 0xDF)
38.9157 40.9639 43.0121 LSB/g
Offset
Digital Offset Before Offset Cancellation 12 bit, lateral, or Z-Axis
*
1
10626
10583
High g (100 g Range, scales with user sensitivity scaling)
OFFHigh_1
–100
–1
—
0
+100
+1
LSB
LSB
6, 8, 9
Digital Offset After Offset Cancellation, lateral, or Z-Axis, All Ranges, 12
bit
OFFCANC12Bit
7, 8, 9
7, 8, 9
Digital Offset After Offset Cancellation with rate limiter, lateral, or Z-Axis,
All Ranges, 12 bit
OFFCANCRL12Bit
–2
0
+2
LSB
LSB
Continuous Offset Monitor Limit (U_SNS_SHIFT = 0x2, U_SNS_MULT = 0x00)
10619
12 bit: Scales with user gain, High g = ~15 g
OFFMON
–164
—
+164
Sensor
Range of Output (SPI, DSI3, lateral, or Z-Axis, All Ranges)
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
10635
10628
10636
10637
Signed Sensor Data, 10 bit
Signed Sensor Data, 12 bit
Signed Error Code, 10 bit
Signed Error Code, 12 bit
RANGESigned_10
RANGESigned_12
ERRSigned_10
–511
–2047
—
—
—
+511
+2047
—
LSB
LSB
LSB
LSB
–512
–2048
ERRSigned_12
—
—
Range of Output (SPI, DSI3, lateral, or Z-Axis, All Ranges)
7, 8, 9
7, 8, 9
7, 8, 9
10638
10639
10640
Unsigned Sensor Data, 10 bit
Unsigned Sensor Data, 12 bit
Unsigned Error Code, 10 bit, 12 bit
RANGEUnsigned_10
RANGEUnsigned_12
ERRUnsigned
1
1
—
—
0
1023
4095
—
LSB
LSB
LSB
—
Range of Output (PSI5, lateral, or Z-Axis, All Ranges)
10634 Signed Sensor Data, 10 bit
7, 8, 9
RANGESigned_10
–480
—
+480
LSB
Cross-Axis Sensitivity, lateral, or Z-Axis, All Ranges
6
6
10645
10647
Z-axis to X-Axis, Y-axis to X-Axis, Z-axis to Y-Axis, X-axis to Y-Axis
X-axis to Z-Axis, Y-axis to Z-Axis
VZX, VYX
VXZ, VYZ
–5
–5
—
—
+5
+5
%
%
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Table 17.ꢀElectrical characteristics - inertial sensor signal chain: High g...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Non-Linearity (12 bit, lateral, or Z-Axis, All Ranges)
*
*
7
6
10669
10670
Differential Non-Linearity (No Missing Codes)
End Point Non-Linearity (Least Squares BFSL)
DNL
INL
—
—
—
—
+1.0
LSB
LSB
+20.0
Supply Coupling (CBUF = 1 µf, 12 bit, DSI3, PSI5, lateral, or Z-Axis, All Ranges)
6
6
6
10663
10682
10681
1 kHz ≤ fn ≤ 10 kHz, BUS_I = 8.0 V ± 2.0 V (Represents PSI5 Sync Pulse)
10 kHz ≤ fn ≤ 100 kHz, BUS_I = 6.0 V ± 1.0 V (Represents DSI3 BRC)
PSCPSI5
PSCDSI3C
PSCDSI3R
—
—
—
—
—
—
1
1
1
LSB
LSB
LSB
100 kHz ≤ fn ≤ 1 MHz, BUS_I = 6.0 V ± 0.5 V (Represents DSI3/PSI5
Response)
6
10680
1 MHz ≤ fn ≤ 20 MHz, BUS_I = 6.0 V ± 0.1 V(Represents Response
Harmonics)
PSCSATH
—
—
1
LSB
Supply Coupling (CBUF = 0.1 µf, 12 bit, SPI, lateral, or Z-Axis, All Ranges)
6
6
10675
10683
1 kHz ≤ fn ≤ 20 MHz, VBUF = 5.0 V ± 0.1 V
1 kHz ≤ fn ≤ 20 MHz, VBUF = 3.3 V ± 0.1 V
PSCSPI5
PSCSPI3
—
—
—
—
2
2
LSB
LSB
Noise: Lateral Sensor
System Output Noise Peak (12 bit), High g Range = 125 g, Lateral
*
*
6
1
10653
Max. Deviation from Mean, Min. 2000 values, Min. fSamp = 2 kHz, LPF =
400 Hz, 4-Pole
nPeakX_400C
–4
–4
—
—
+4
+4
LSB
LSB
10655
Max. Deviation from Mean, Min. 50 values, Min. fSamp = 2 kHz, LPF = 400
Hz, 4-Pole
nPeakX_400T
System Output Noise Average (12 bit), High g Range = 125 g, Lateral
*
*
6
1
10654
Standard Deviation, Min. 2000 values, Min. fSamp = 2 kHz, LPF = 400 Hz,
4-Pole
nRMSX_400C
—
—
—
—
+1.0
+1.0
LSB
LSB
10656
Standard Deviation, Min. 50 values, Min. fSamp = 2 kHz, LPF = 400 Hz, 4-
Pole
nRMSX_400T
Noise: Z-Axis Sensor
System Output Noise Peak (12 bit), High g Range = 125 g, Z-Axis
*
*
6
1
10659
Max. Deviation from Mean, Min. 2000 values, Min. fSamp = 2 kHz, LPF =
400 Hz, 4-Pole
nPeakZ_400C
–8
–8
—
—
+8
+8
LSB
LSB
10661
Max. Deviation from Mean, Min. 50 values, Min. fSamp = 2 kHz, LPF = 400
Hz, 4-Pole
nPeakZ_400T
System Output Noise Average (12 bit), High g Range = 125 g, Z-Axis
*
*
6
1
10660
Standard Deviation, Min. 2000 values, Min. fSamp = 2 kHz, LPF = 400 Hz,
4-Pole
nRMSZ_400C
—
—
—
—
+2.0
+2.0
LSB
LSB
10662
Standard Deviation, Min. 50 values, Min. fSamp = 2 kHz, LPF = 400 Hz, 4-
Pole
nRMSZ_400T
The offset before offset cancellation scales with the user gain. The higher the gain (lower
range), the higher the offset. Table 18 lists the adjusted offset specification limits for some
SPI and DSI3 12-bit user gain settings.
Table 18.ꢀHigh g adjusted offset specification limits
User range (g)
Offset (LSB, 12 bit)
50
60
± 200
± 167
± 162
± 160
62
62.5
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Table 18.ꢀHigh g adjusted offset specification limits...continued
User range (g)
100
Offset (LSB, 12 bit)
± 100
± 96
± 89
± 80
± 79
± 67
± 54
± 40
± 32
± 27
± 20
105
112.5
125
128
150
187
250
312.5
375
500
Table 19 lists the offset before offset cancellation limits for some PSI5 10-bit user gain
settings.
Table 19.ꢀPSI5, High g offset cancellation limits
User range (g)
Offset (LSB, 10 bit)
60
± 40
± 20
± 10
± 5
120
240
480
The signal noise scales with the user gain and with signal bandwidth. The higher the
gain (lower range), the higher the noise, the wider the bandwidth, the higher the noise.
Table 20 and Table 21 lists the adjusted specification limits for some user gain settings
and low-pass filter selections on the lateral, and Z-axis.
Note: Peak values indicate the maximum deviation from the mean.
Table 20.ꢀLateral, High g, SPI/DSI3 12-bit noise specification
LPF 400 Hz, 4p LPF 400 Hz, 3p LPF 180 Hz, 2p LPF 325 Hz, 3p LPF 1500 Hz, 4p LPF 800 Hz, 4p
User
range
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
(g)
50
62.5
100
11
9
3
3
2
1
1
1
1
11
9
3
3
2
1
1
1
1
8
6
4
3
2
2
2
2
2
1
1
1
1
1
10
8
3
2
2
1
1
1
1
21
17
11
8
5
4
3
2
2
1
1
15
12
8
4
3
2
2
1
1
1
5
6
5
125
4
4
4
6
187
3
3
3
6
4
250
3
3
2
4
3
312.5
2
2
2
4
3
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Table 20.ꢀLateral, High g, SPI/DSI3 12-bit noise specification...continued
LPF 400 Hz, 4p LPF 400 Hz, 3p LPF 180 Hz, 2p LPF 325 Hz, 3p LPF 1500 Hz, 4p LPF 800 Hz, 4p
User
range
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
(g)
375
500
2
2
1
1
2
2
1
1
1
1
1
1
2
1
1
1
3
2
1
1
2
2
1
1
Table 21.ꢀZ-Axis, High g, SPI/DSI3 12-bit noise specification
LPF 400 Hz, 4p LPF 400 Hz, 3p LPF 180 Hz, 2p LPF 325 Hz, 3p LPF 1500 Hz, 4p LPF 800 Hz, 4p
User
range
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
Peak
RMS
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
LSB
12 bit
(g)
50
62.5
100
125
187
250
312.5
375
500
21
17
11
8
6
5
3
2
2
2
1
1
1
22
18
11
9
6
5
3
2
2
2
1
1
1
15
12
8
4
3
2
2
1
1
1
1
1
20
16
10
8
5
4
3
2
2
1
1
1
1
41
33
21
16
11
9
11
9
6
4
3
2
2
2
1
30
24
15
12
8
8
6
4
3
2
2
2
1
1
6
6
6
4
6
5
5
3
4
6
4
3
3
3
7
5
3
3
2
2
6
4
3
3
2
2
5
3
Table 22 and Table 23 list the adjusted specification limits for some PSI5 10-bit user gain
settings and low-pass filter selections on the lateral, and Z-axis.
Table 22.ꢀLateral, High g, PSI5 10-bit noise specification
LPF 400 Hz, 4p
LPF 400 Hz, 3p
LPF 800 Hz, 4p
User
range
Peak
RMS
Peak
RMS
Peak
RMS
(g)
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
60, PSI5
120, PSI5
240 PSI5
480 PSI5
3
2
1
1
0.6
0.5
0.5
0.5
3
2
2
2
0.7
0.6
0.6
0.6
4
2
2
2
0.9
0.8
0.8
0.8
Table 23.ꢀZ-Axis, High g, PSI5 10-bit noise specification
LPF 400 Hz, 4p
LPF 400 Hz, 3p
LPF 800 Hz, 4p
User
range
Peak
RMS
Peak
RMS
Peak
RMS
(g)
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
60, PSI5
5
3
1.1
0.6
5
3
1.2
0.7
6
4
1.6
0.9
120, PSI5
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Table 23.ꢀZ-Axis, High g, PSI5 10-bit noise specification...continued
LPF 400 Hz, 4p LPF 400 Hz, 3p
LPF 800 Hz, 4p
User
range
Peak
RMS
Peak
RMS
Peak
RMS
(g)
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
240 PSI5
480 PSI5
2
1
0.5
0.5
2
2
0.6
0.6
2
2
0.8
0.8
10.7 Electrical characteristics - inertial sensor signal chain: Medium g
Table 24.ꢀElectrical characteristics - inertial sensor signal chain: Medium g
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Sensitivity
Total Sensitivity Error Including Linearity (From Trim Target, Output @ 0 Hz)
*
*
1
1
10585
Medium g, lateral, or Z-Axis, Verified with a 15 g Range
SENSERRM
SENS016M
–5
—
+5
%
Medium g Standard Trim Range 12-bit Sensitivity Target, lateral, or Z-Axis
10602
± 16 g Range (±2047 LSB, U_SNS_SHIFT = 0x3, U_SNS_MULT = 0xF0)
121.
127.
134.
LSB/g
5406
9375
3344
Offset
Digital Offset Before Offset Cancellation 12 bit, lateral, or Z-Axis
*
1
10627
10583
Medium g (25 g Range, scales with user sensitivity scaling)
OFFMed_1
–100
–1
—
0
+100
+1
LSB
LSB
6, 8, 9
Digital Offset After Offset Cancellation, lateral, or Z-Axis, All Ranges, 12
bit
OFFCANC12Bit
7, 8, 9
7, 8, 9
Digital Offset After Offset Cancellation with rate limiter, lateral, or Z-Axis,
All Ranges, 12 bit
OFFCANCRL12Bit
–2
0
+2
LSB
LSB
Continuous Offset Monitor Limit (U_SNS_SHIFT = 0x2, U_SNS_MULT = 0x00)
10619
12 bit: Scales with user gain, Medium g = ~5 g
OFFMON
–164
—
+164
Sensor
Range of Output (SPI, DSI3, lateral, or Z-Axis, All Ranges)
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
10635
10628
10636
10637
Signed Sensor Data, 10 bit
Signed Sensor Data, 12 bit
Signed Error Code, 10 bit
Signed Error Code, 12 bit
RANGESigned_10
RANGESigned_12
ERRSigned_10
–511
–2047
—
—
—
+511
+2047
—
LSB
LSB
LSB
LSB
–512
–2048
ERRSigned_12
—
—
Range of Output (SPI, DSI3, lateral, or Z-Axis, All Ranges)
7, 8, 9
7, 8, 9
7, 8, 9
10638
10639
10640
Unsigned Sensor Data, 10 bit
Unsigned Sensor Data, 12 bit
Unsigned Error Code, 10 bit, 12 bit
RANGEUnsigned_10
RANGEUnsigned_12
ERRUnsigned
1
1
—
—
0
1023
4095
—
LSB
LSB
LSB
—
Range of Output (PSI5, lateral, or Z-Axis, All Ranges)
10634 Signed Sensor Data, 10 bit
7, 8, 9
RANGESigned_10
–480
—
+480
LSB
Cross-Axis Sensitivity, lateral, or Z-Axis, All Ranges
6
6
10645
10647
Z-axis to X-Axis, Y-axis to X-Axis, Z-axis to Y-Axis, X-axis to Y-Axis
X-axis to Z-Axis, Y-axis to Z-Axis
VZX, VYX
VXZ, VYZ
–5
–5
—
—
+5
+5
%
%
Non-Linearity (12 bit, lateral, or Z-Axis, All Ranges)
*
*
7
6
10669
10670
Differential Non-Linearity (No Missing Codes)
End Point Non-Linearity (Least Squares BFSL)
DNL
INL
—
—
—
—
+1.0
LSB
LSB
+20.0
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Table 24.ꢀElectrical characteristics - inertial sensor signal chain: Medium g...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Supply Coupling (CBUF = 1 µf, 12 bit, DSI3, PSI5, lateral, or Z-Axis, All Ranges)
6
6
6
10663
10682
10681
1 kHz ≤ fn ≤ 10 kHz, BUS_I = 8.0 V ± 2.0 V (Represents PSI5 Sync Pulse)
10 kHz ≤ fn ≤ 100 kHz, BUS_I = 6.0 V ± 1.0 V (Represents DSI3 BRC)
PSCPSI5
PSCDSI3C
PSCDSI3R
—
—
—
—
—
—
1
1
1
LSB
LSB
LSB
100 kHz ≤ fn ≤ 1 MHz, BUS_I = 6.0 V ± 0.5 V (Represents DSI3/PSI5
Response)
6
10680
1 MHz ≤ fn ≤ 20 MHz, BUS_I = 6.0 V ± 0.1 V(Represents Response
Harmonics)
PSCSATH
—
—
1
LSB
Supply Coupling (CBUF = 0.1 µf, 12 bit, SPI, lateral, or Z-Axis, All Ranges)
6
6
10675
10683
1 kHz ≤ fn ≤ 20 MHz, VBUF = 5.0 V ± 0.1 V
1 kHz ≤ fn ≤ 20 MHz, VBUF = 3.3 V ± 0.1 V
PSCSPI5
PSCSPI3
—
—
—
—
2
2
LSB
LSB
Noise: Lateral Sensor
System Output Noise Peak (12 bit), Medium g Range = 50 g, Lateral
6
1
10653
Max. Deviation from Mean, Min. 2000 values, Min. fSamp = 2 kHz, LPF =
400 Hz, 4-Pole
nPeakX_400C
–4
–4
—
—
+4
+4
LSB
LSB
*
*
10655
Max. Deviation from Mean, Min. 50 values, Min. fSamp = 2 kHz, LPF = 400
Hz, 4-Pole
nPeakX_400T
System Output Noise Average (12 bit), Medium g Range = 50 g, Lateral
*
*
6
1
10654
Standard Deviation, Min. 2000 values, Min. fSamp = 2 kHz, LPF = 400 Hz,
4-Pole
nRMSX_400C
—
—
—
—
+1.0
+1.0
LSB
LSB
10656
Standard Deviation, Min. 50 values, Min. fSamp = 2 kHz, LPF = 400 Hz, 4-
Pole
nRMSX_400T
Noise: Z-Axis Sensor
System Output Noise Peak (12 bit), Medium g Range = 50 g, Z-Axis
*
*
6
1
10659
Max. Deviation from Mean, Min. 2000 values, Min. fSamp = 2 kHz, LPF =
400 Hz, 4-Pole
nPeakZ_400C
–8
–8
—
—
+8
+8
LSB
LSB
10661
Max. Deviation from Mean, Min. 50 values, Min. fSamp = 2 kHz, LPF = 400
Hz, 4-Pole
nPeakZ_400T
System Output Noise Average (12 bit), Medium g Range = 50 g, Z-Axis
*
*
6
1
10660
Standard Deviation, Min. 2000 values, Min. fSamp = 2 kHz, LPF = 400 Hz,
4-Pole
nRMSZ_400C
—
—
—
—
+2.0
+2.0
LSB
LSB
10662
Standard Deviation, Min. 50 values, Min. fSamp = 2 kHz, LPF = 400 Hz, 4-
Pole
nRMSZ_400T
The offset before offset cancellation scales with the user gain. The higher the gain (lower
range), the higher the offset. Table 25 lists the adjusted offset specification limits for some
SPI and DSI3 12-bit user gain settings.
Table 25.ꢀMedium g, SPI/DSI3 12-bit offset specification
User range (g)
Offset (LSB, 12 bit)
15.5
16
± 162
± 157
± 126
± 100
± 72
20
25
35
50
± 50
60
± 42
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Table 25.ꢀMedium g, SPI/DSI3 12-bit offset specification...continued
User range (g)
Offset (LSB, 12 bit)
62
62.5
75
± 41
± 41
± 34
± 30
± 25
± 24
± 23
± 21
± 20
± 17
85.3
100
105
112.5
125
128
150
Table 26 lists the offset before offset cancellation limits for some PSI5 10-bit user gain
settings.
Table 26.ꢀMedium g, PSI5 10-bit offset specification
User range (g)
Offset (LSB, 10 bit)
15
20
± 40
± 30
± 20
± 10
± 5
30
60
120
The signal noise scales with the user gain and with signal bandwidth. The higher the
gain (lower range), the higher the noise, the wider the bandwidth, the higher the noise.
Table 27 lists the adjusted specification limits for some user gain settings and low-pass
filter selections.
Note: Peak values indicate the maximum deviation from the mean.
Table 27.ꢀLateral, Medium g, SPI/DSI3 12-bit noise specification
LPF 400 Hz, 4p
Peak RMS
LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit
LPF 400 Hz, 3p
LPF 180 Hz, 2p
LPF 325 Hz, 3p
LPF 1500 Hz, 4p
LPF 800 Hz, 4p
User range
(g)
Peak RMS
Peak RMS
Peak RMS
Peak RMS
Peak RMS
15.5
25
14
9
4
3
1
1
1
1
1
14
9
4
3
1
1
1
1
1
10
6
3
2
1
1
1
1
1
13
8
4
2
1
1
1
1
1
26
17
8
7
4
2
2
1
1
1
20
12
6
5
3
2
2
1
1
1
50
4
5
3
4
62.5
100
125
150
4
4
3
4
7
5
3
3
2
2
4
3
2
2
2
2
4
3
2
2
1
2
3
2
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Table 28.ꢀZ-axis, Medium g, SPI/DSI3 12-bit noise specification
LPF 400 Hz, 4p
Peak RMS
LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit LSB 12 bit
LPF 400 Hz, 3p
LPF 180 Hz, 2p
LPF 325 Hz, 3p
LPF 1500 Hz, 4p
LPF 800 Hz, 4p
User range
(g)
Peak RMS
Peak RMS
Peak RMS
Peak RMS
Peak RMS
15.5
25
27
17
8
7
5
2
2
1
1
1
28
18
9
7
5
2
2
2
1
1
20
12
6
5
3
2
2
1
1
1
25
16
8
7
4
2
2
1
1
1
53
33
16
13
9
14
9
39
24
12
10
6
10
6
50
4
3
62.5
100
125
150
7
7
5
7
4
3
5
5
3
4
2
2
4
4
3
4
7
2
5
2
3
3
2
3
6
2
4
1
Table 29 and Table 30 list the adjusted specification limits for some PSI5 10-bit user gain
settings and low-pass filter selections.
Table 29.ꢀLateral, Medium g, PSI5 10-bit noise specifications
LPF 400 Hz, 4p
LPF 400 Hz, 3p
LPF 800 Hz, 4p
User range
(g)
Peak
RMS
Peak
RMS
Peak
RMS
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
30, PSI5
60, PSI5
120, PSI5
2
1
1
0.5
0.5
0.5
3
2
2
0.6
0.6
0.6
3
2
2
0.8
0.8
0.8
Table 30.ꢀZ-axis, Medium g, PSI5 10-bit noise specification
LPF 400 Hz, 4p
User range
LPF 400 Hz, 3p
LPF 800 Hz, 4p
Peak
RMS
Peak
RMS
Peak
RMS
(g)
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
LSB 10 bit
30, PSI5
60, PSI5
120, PSI5
4
2
1
0.8
0.5
0.5
4
3
2
0.9
0.6
0.6
5
3
2
1.2
0.8
0.8
10.8 Electrical characteristics - inertial sensor self-test
Table 31.ꢀElectrical characteristics - inertial sensor self-test
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Med g Lateral Self-test, 62 g, U_SNS_SHIFT = 0x2, U_SNS_MULT = 0x00
ΔSTMIN
54
ΔSTNOM
121
ΔSTMAX
188
7
7
7
7
7
Low self-test, 14.80 g, 10-bit Signed Delta from Offset
STML_62X_10
STMH_62X_10
STML_62X_12
STMH_62X_12
STML_62X_16
LSB
LSB
LSB
LSB
LSB
High self-test, 44.50 g, 10-bit Signed Delta from Offset
Low self-test, 14.80 g, 12-bit Signed Delta from Offset
High self-test, 44.50 g, 12-bit Signed Delta from Offset
220
218
367
485
511
752
881
1470
7744
2047
12032
Low self-test, 14.80 g, 16-bit SPI/PSI5 Extended Signed Delta from
Offset
3456
7
1
1
High self-test, 44.50 g, 16-bit SPI/PSI5 Extended Signed Delta from
Offset
STMH_62X_16
STML_62X_13
STMH_62X_13
14080
436
23488
970
32767
1504
4115
LSB
LSB
LSB
*
*
10687
10688
Low self-test, 14.80 g, 16-bit Signed SNSDATAx Register Delta from
Offset
High self-test, 44.50 g, 16-bit Signed SNSDATAx Register Delta from
Offset
1763
2939
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Table 31.ꢀElectrical characteristics - inertial sensor self-test...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Med g Z-Axis Self-test, 62 g, U_SNS_SHIFT = 0x2, U_SNS_MULT = 0x00
ΔSTMIN
34
ΔSTNOM
78
ΔSTMAX
121
7
7
7
7
7
Low self-test, 8.66 g, 10-bit Signed Delta from Offset
STML_62Z_10
STMH_62Z_10
STML_62Z_12
STMH_62Z_12
STML_62Z_16
LSB
LSB
LSB
LSB
LSB
High self-test, 21.65 g, 10-bit Signed Delta from Offset
Low self-test, 8.66 g, 12-bit Signed Delta from Offset
High self-test, 21.65 g, 12-bit Signed Delta from Offset
107
139
178
310
251
481
428
715
1001
7744
Low self-test, 8.66 g, 16-bit SPI/PSI5 Extended Signed Delta from
Offset
2176
4928
7
1
1
High self-test, 21.65 g, 16-bit SPI/PSI5 Extended Signed Delta from
Offset
STMH_62Z_16
STML_62Z_13
STMH_62Z_13
6848
278
11392
620
16064
962
LSB
LSB
LSB
*
*
30134
30135
Low self-test, 8.66 g, 16-bit Signed SNSDATAx Register Delta from
Offset
High self-test, 21.65 g, 16-bit Signed SNSDATAx Register Delta from
Offset
857
1430
2002
High g Lateral Self-test, 187 g, U_SNS_SHIFT = 0x2, U_SNS_MULT = 0x00
ΔSTMIN
24
ΔSTNOM
55
ΔSTMAX
86
7
7
7
7
7
Low self-test, 18.33 g, 10-bit Signed Delta from Offset
STHL_187X_10
STHH_187X_10
STHL_187X_12
STHH_187X_12
STHL_187X_16
LSB
LSB
LSB
LSB
LSB
High self-test, 55.00 g, 10-bit Signed Delta from Offset
Low self-test, 18.33 g, 12-bit Signed Delta from Offset
High self-test, 55.00 g, 12-bit Signed Delta from Offset
90
99
150
220
212
341
361
1536
603
845
Low self-test, 18.33 g, 16-bit SPI/PSI5 Extended Signed Delta from
Offset
3520
5504
7
1
1
High self-test, 55.00 g, 16-bit SPI/PSI5 Extended Signed Delta from
Offset
STHH_187X_16
STHL_187X_13
STHH_187X_13
5760
198
9600
1206
440
13568
682
LSB
LSB
LSB
*
*
10685
10686
Low self-test, 18.33 g, 16-bit Signed SNSDATAx Register Delta from
Offset
High self-test, 55.00 g, 16-bit Signed SNSDATAx Register Delta from
Offset
723
1689
High g Z-Axis Self-test, 187 g, U_SNS_SHIFT = 0x2, U_SNS_MULT = 0x00
ΔSTMIN
31
ΔSTNOM
70
ΔSTMAX
109
7
7
7
7
7
Low self-test, 25.40 g, 10-bit Signed Delta from Offset
STHL_187Z_10
STHH_187Z_10
STHL_187Z_12
STHH_187Z_12
STHL_187Z_16
LSB
LSB
LSB
LSB
LSB
High self-test, 63.50 g, 10-bit Signed Delta from Offset
Low self-test, 25.40 g, 12-bit Signed Delta from Offset
High self-test, 63.50 g, 12-bit Signed Delta from Offset
104
125
173
279
244
433
417
695
974
Low self-test, 25.40 g, 16-bit SPI/PSI5 Extended Signed Delta from
Offset
1984
4416
6976
7
1
1
High self-test, 63.50 g, 16-bit SPI/PSI5 Extended Signed Delta from
Offset
STHH_187Z_16
STHL_187Z_13
STHH_187Z_13
6656
250
11072
558
15616
866
LSB
LSB
LSB
*
*
30136
30137
Low self-test, 25.40 g, 16-bit Signed SNSDATAx Register Delta from
Offset
High self-test, 63.50 g, 16-bit Signed SNSDATAx Register Delta from
Offset
834
1390
1947
High self-test Accuracy: Δ from Stored Value, including Sensitivity Error
(12 bit, Lateral, or Z-Axis, All Ranges)
*
*
6
1
10678
25 °C, Post Pre-conditioning
ΔSTHACC_
25P
–2
—
—
+2
%
%
10690
–40 °C ≤ TA ≤ 125 °C
ΔSTHACC_T
–10
+10
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Table 31.ꢀElectrical characteristics - inertial sensor self-test...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Self-test Delta Offset: Δ Offset from Pre-Self-test to Post Self-test
(12 bit, Lateral, or Z-Axis, All Ranges)
1
1
10692
10692
25 °C
ΔSTOFF_25
ΔSTOFF_T
–2
–4
—
—
+2
+4
LSB
LSB
–40 °C ≤ TA ≤ 125 °C
Digital Self-test
7
7
7
7
44629
44630
44631
44632
Digital Self-test 0xC, 16-bit Signed SNSDATAx Register Value
DSTC0
DSTD0
DSTE0
DSTF0
E77F
0FA3
EFA2
07B7
E780
0FA4
EFA3
07B8
E781
0FA5
EFA4
07B9
HEX
HEX
HEX
HEX
Digital Self-test 0xD, 16-bit Signed SNSDATAx Register Value
Digital Self-test 0xE, 16-bit Signed SNSDATAx Register Value
Digital Self-test 0xF, 16-bit Signed SNSDATAx Register Value
10.9 Electrical characteristics - lateral inertial sensor overload
Table 32.ꢀElectrical characteristics - lateral inertial sensor overload
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Acceleration Range, Lateral Transducer
7
7
7
10694
10693
21074
Medium g
High g
gg-cell_ClipMedX
gg-cell_ClipHiX
gDig_ClipMedXHi
± 500
± 2000
± 400
—
—
—
—
—
—
g
g
g
Digital Clipping Limit (Medium g Lateral, must clip before transducer
and ADC)
7
21082
Digital Clipping Limit (High g Lateral, must clip before transducer and
ADC)
gDig_ClipHiXHi
± 1500
—
—
g
10.10 Electrical characteristics - Z-axis inertial sensor overload
Table 33.ꢀElectrical characteristics - Z-axis inertial sensor overload
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Acceleration Range, Z-Axis Transducer
7
7
7
10698
10699
21105
Medium g
High g
gg-cell_ClipMedZ
gg-cell_ClipHiZ
gDig_ClipMedZHi
± 500
± 2000
± 400
—
—
—
—
—
—
g
g
g
Digital Clipping Limit (Medium g Z-Axis, must clip before transducer
and ADC)
7
21113
Digital Clipping Limit (High g Z-Axis, must clip before transducer and
ADC)
gDig_ClipHiZHi
± 1500
—
—
g
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10.11 Dynamic electrical characteristics - DSI3
Table 34.ꢀDynamic electrical characteristics - DSI3
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Command Reception (General)
7, 9
7, 9
7, 9
10709
10722
10721
VHIGH low-pass filter time constant (Section 12.1.1)
tVHIGH_RC
tVHIGH_Delay
tCmd_Valid
60
—
—
120
—
2
180
600
—
µs
ns
µs
VHIGH Detection Analog Delay (Section 12.1.1)
Command Valid time (Section 12.1.1)
Response Transmission (General, Slew Control Enabled, Section 12.3.3)
1, 7, 9
1, 7, 9
7, 9
10710
10726
10725
10724
10723
Response Slew Time: 2.0 mA to 10.0 mA, 10.0 mA to 2.0 mA
Response Slew Time: 4.0 mA to 20.0 mA, 20.0 mA to 4.0 mA
tSLEW1_RESP – tSLEW2_RESP
tSLEW1_RESP
tSLEW2_RESP
ΔtSLEW
350
350
400
400
—
500
500
100
250
400
ns
ns
ns
ns
ns
–100
–250
200
7, 9
tSLEW1_RESP_Rise – tSLEW2_RESP_Fall
ΔtSLEW_rf
—
3, 7, 9
Response Current Activation Time: Current Activated to 50 %
tACT_RESP
—
Response Transmission (General, Slew Control Disabled, Section 12.3.3)
7, 9
7, 9
7, 9
7, 9
7, 9
10727
10728
10729
10730
10731
Response Slew Time: 2.0 mA to 10.0 mA, 10.0 mA to 2.0 mA
Response Slew Time: 4.0 mA to 20.0 mA, 20.0 mA to 4.0 mA
tSLEW1_RESP – tSLEW2_RESP
tnSLEW1_RESP
tnSLEW2_RESP
ΔtnSLEW
—
—
—
—
—
—
—
300
300
300
300
300
ns
ns
ns
ns
ns
–300
–300
—
tSLEW1_RESP_Rise – tSLEW2_RESP_Fall
ΔtnSLEW_rf
tnACT_RESP
Response Current Activation Time: Current Activated to 50 %
Command Reception (Discovery Mode)
10719
10734
Command Start Time (Section 12.2)
Command Bit Time (Section 12.2)
tSTART_DISC
tDISC_BitTime
tPOR_DSI
14
—
13.5
18
ms
µs
7, 8, 9
7, 8, 9
16
7, 8, 9
7, 8, 9
10733
10732
Command Transmission Period (Section 12.2)
tPER_DISC
125
—
—
—
—
µs
µs
Command Blocking Time, Discovery Mode (Section 12.1.1)
tCmdBlock_DISC
80
Response Transmission (Discovery Mode)
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
30078
30079
10718
10738
10737
10736
10735
30081
30080
Idle Current Sample Delay (Section 12.2)
Idle Current Sample Time (Section 12.2)
Response Start Delay (Section 12.2)
Response Ramp Time (Section 12.2)
Response Ramp Rate (Section 12.2)
Response Idle Time (Section 12.2)
tDISC_DLY
tDISC_ICCQ_SAMP
tSTART_DISC_RSP
tDISC_Ramp_RSP
IDISC_Ramp
—
—
—
—
—
—
—
—
—
48
15
—
—
—
—
—
—
—
—
—
µs
µs
64
µs
16
µs
1.5
16
mA/µs
µs
tDISC_Idle_RSP
IDISC_Peak
tIDISC_Samp_Dly
tIDISC_Samp
Response Peak Current (Section 12.2)
Response Current Sample Delay (Section 12.2)
Response Current Sample Time (Section 12.2)
2*IRESP
65
mA
µs
31
µs
Command Reception (Command and Response Mode)
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
10717
10741
10740
10739
Command Bit Time (Section 12.3)
tCmd_BitTime
tPER_CRM
tCmdBlock_CRM
tCmdBlock_ST_CRM
—
475
—
8
—
—
—
—
µs
µs
µs
µs
Command Transmission Period (Section 12.3)
Command Blocking Time, CRM (Section 12.1.1)
Command Blocking Start Time, CRM (Section 12.1.1)
—
455
290
—
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Table 34.ꢀDynamic electrical characteristics - DSI3...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Response Transmission (Command and Response Mode)
7, 8, 9
7, 8, 9
10716
10742
Response Chip Time
tCHIP_CRM
—
—
5
—
—
µs
µs
Response Start Time (Section 12.3)
tSTART_CRM
295
Command Reception (Periodic Data Collection Mode)
7, 8, 9
7, 8, 9
10715
10743
Command Bit Time (Section 12.4)
tCmd_BitTime
tPER_PDCM
—
8
—
—
µs
µs
Command Transmission Period (Section 12.4)
50
—
Response Transmission (Periodic Data Collection Mode)
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
10714
10746
10745
10744
Response Chip Time Typical (Section 11.2.15.4)
Min Programmed Start Time: PDCM_RSPSTx < 0x0015
Min Programmed Start Time: BDM Enabled
tCHIP_PDCM
1.0
—
—
—
—
20
5.0
—
—
—
µs
µs
µs
µs
tSTART_PDCM_Min
tSTART_PDCMBDMMin
tSTART_PDCM_Max
51
Max Programmed Start Time: PDCM_RSPSTx = 0x1FFF
8191
Response Transmission (Background Diagnostic Mode)
7, 8, 9
7, 8, 9
7, 8
49314
10747
10712
Response Chip Time
tCHIP_BDM
tSTART_BDM
tLAT_DSI
—
—
0
tCHIP_PDCM
—
—
µs
µs
µs
Response Start Time (Section 12.4)
DSI Data Latency
20
—
2.00
OTP Program Timing
10711 Time to program an OTP User Region
7, 8, 9
tOTP_WRITE_MAX
—
—
10
ms
10.12 Dynamic electrical characteristics - PSI5
Table 35.ꢀDynamic electrical characteristics - PSI5
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Initialization Timing
7, 8, 9
7, 8, 9
7, 8, 9
10748
10758
10757
Phase 1
tPSI5_INIT1
—
—
—
133
—
—
—
ms
s
Phase 2 (Synchronous Mode, k = 4, tS-S = 500 µs)
Phase 2 (Asynchronous Mode, k = 8)
tPSI5_INIT2_10s
tPSI5_INIT2_10a
256 * tS-S
512 *
s
tASYNC
7, 8, 9
7, 8, 9
7, 8
10756
10755
10754
10753
41756
Phase 3 (Synchronous Mode, tS-S = 500 µs)
Phase 3 (Asynchronous Mode)
tPSI5_INIT3_10s
tPSI5_INIT3_10a
tPSI5ST_START
tST
—
—
—
—
—
2 * tS-S
2 * tASYNC
30
—
—
—
—
—
s
s
PSI5 Self-test Start Time
ms
ms
ms
7, 8
PSI5 Self-test Time, including Post OC Startup Offset
Programming Mode Entry Window
223
7, 8, 9
tPME
127
Synchronization Pulse
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 9
10759
10779
10778
10777
10776
Reset to first sync pulse (Program Mode Entry)
tRS_PM
tRS
6
tPSI5_INIT1
175
—
—
—
—
—
—
—
ms
s
Reset to first sync pulse (Normal Mode)
Sync Pulse Period
tS-S
—
µs
µs
µs
Sync Pulse Width
tSYNC
tSYNC_LPF
9
—
Sync Pulse Reference LPF time constant
120
280
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Table 35.ꢀDynamic electrical characteristics - PSI5...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
7, 9
10775
10774
10773
10772
10771
10770
10769
10768
10767
Sync Pulse Reference Discharge Start Time
Sync Pulse Reference Discharge Activation Time
Sync Pulse Detection Disable Time (PDCM_CMD_B = 0)
Analog Delay of Sync Pulse Detection
tSYNC_LPF_RST_ST
tSYNC_LPF_RST
tSYNC_OFF_500
tA_SYNC_DLY
tPD_DLY
—
—
—
50
—
—
0
9.0
154
450
—
—
—
µs
µs
µs
ns
µs
µs
µs
µs
µs
7, 9
7, 8, 9
7, 9
—
600
—
7, 9
Sync Pulse Pulldown Function Delay Time
Sync Pulse Pulldown Function Activate Time
Sync Pulse Detection Jitter
9.0
16
7, 8
tPD_ON
—
7, 8
tSYNC_JIT
—
0.5
—
7, 8, 9
7, 8, 9
Data Transmission Single Bit Time (PSI5 Standard Bit Rate)
Data Transmission Single Bit Time (PSI5 High Bit Rate)
tBIT_Standard
tBIT_HI
—
—
8.00
5.30
—
Response Current Transmission (No external Components)
1 ,7, 9
8, 9
10766
10765
10780
10764
Response Slew Time: 20 % to 80 % of IR_PSI5
Position of bit transition (All except 5.3 µs)
Position of bit transition (5.3 us)
tSLEW1_RESP
tBittrans_LowBaud
tBittrans_HighBaud
tASYNC
350
49
49
—
400
50
500
51
51
—
ns
%
8, 9
⎯
%
7, 8, 9
Asynchronous Response Time
228
µs
Time Slots
Min Programmed Time Slot: PDCM_RSPSTx < 0x0014
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8, 9
7, 8
10763
10790
10789
10788
10787
10786
10785
10784
10783
10782
10781
10762
tTIMESLOTx_MIN
tTIMESLOTx_MAX
tTIMESLOT_DFLT
tTIMESLOTx_RES
tTIMESLOT_DC0
tTIMESLOT_DC1_L
tTIMESLOT_DC2_L
tTIMESLOT_DC1_H
tTIMESLOT_DC2_H
tTIMESLOT_DC3_H
tTIMESLOT_DCP
tLAT_PSI5
—
—
—
—
—
—
—
—
—
—
—
0
20
8191
20
—
—
µs
µs
Max Programmed Time Slot: PDCM_RSPSTx = 0x1FFF
Default Time Slot (PDCM_RSPSTx = 0x0000)
Time Slot Resolution
—
µs
1.0
—
µs/LSB
µs
Sync pulse to Daisy Chain Default Time Slot 0
Sync pulse to Daisy Chain Default Time Slot 1 (Low)
Sync pulse to Daisy Chain Default Time Slot 2 (Low)
Sync pulse to Daisy Chain Default Time Slot 1 (High)
Sync pulse to Daisy Chain Default Time Slot 2 (High)
Sync pulse to Daisy Chain Default Time Slot 3 (High)
Sync pulse to Daisy Chain Programming Time Slot
PSI5 Data Latency
46.5
192
350
150
260
380
46.5
—
—
—
µs
—
µs
—
µs
—
µs
—
µs
—
µs
1.00
µs
Bus Switch Output Activation Time (C = 50 pF)
10761 From last bit of "SetAdr" Response to 80 % of VBUS_SW_OH
7
tBUS_SW
⎯
⎯
300
µs
PSI5 Programming Mode Sync Pulse Period
7, 8, 9
7, 8, 9
10760
The user must provide a sync pulse period within this range to
guarantee Programming Mode communications
tS-S_PM
245
—
250
200
255
—
µs
µs
PSI5 Programming Mode Command Blanking Time
tSYNC_OFF_250
Daisy Chain Mode Sync Pulse Period
39810 The user must provide a sync pulse period within this range to
7, 8, 9
7, 8, 9
tS-S_DC
490
—
500
—
510
10
µs
guarantee communications
OTP Program Timing
10793
Time to program one OTP User Region
tOTP_WRITE_MAX
ms
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10.13 Dynamic electrical characteristics - SPI
Table 36.ꢀDynamic electrical characteristics - SPI
VCC_BUF_min ≤ (VBUS_I – VSS) ≤ VCC_BUF_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
10794 Clock (SCLK) period (10 % of VCC to 10 % of VCC
6
)
tSCLK
88
—
—
ns
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
6
6
10801
10802
Clock (SCLK) high time (90 % of VCC to 90 % of VCC
)
tSCLKH
tSCLKL
30
30
—
—
—
—
ns
ns
Clock (SCLK) low time (10 % of VCC to 10 % of VCC
)
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
7
7
10800
10803
Clock (SCLK) rise time (10 % of VCC to 90 % of VCC
)
tSCLKR
tSCLKF
—
—
10
10
25
25
ns
ns
Clock (SCLK) fall time (90 % of VCC to 10 % of VCC
)
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
10799 SS_B asserted to SCLK high (SS_B = 10 % of VCC to SCLK = 10 % of
6
6
6
tLEAD
tACCESS
tSETUP
50
—
20
—
—
—
—
50
—
ns
ns
ns
VCC
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
10798 SS_B asserted to MISO valid (SS_B = 10 % of VCC to MISO = 10/90 %
)
of VCC
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
10797 Data setup time (MOSI = 10/90 % of VCC to SCLK = 10 % of VCC
)
)
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
6
6
10796
10804
MOSI Data hold time (SCLK = 90 % of VCC to MOSI = 10/90 % of VCC
)
)
tHOLD_IN
10
0
—
—
—
—
ns
ns
MISO Data hold time (SCLK = 90 % of VCC to MISO = 10/90 % of VCC
tHOLD_OUT
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
10795 SCLK low to data valid (SCLK = 10 % of VCC to MISO = 10/90 % of
6
tVALID
—
—
30
ns
VCC
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
10807 SCLK low to SS_B high (SCLK = 10 % of VCC to SS_B = 90 % of VCC
)
6
6
)
tLAG
60
—
—
—
—
ns
ns
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
10806 SS_B high to MISO disable (SS_B = 90 % of VCC to MISO = High Z)
tDISABLE
60
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
SS_B high to SS_B low (SS_B = 90 % of VCC to SS_B = 90 % of VCC
)
6
6
6
6
10805
10813
10812
10810
Following Sensor Data Request Commands
Following Register Reads/Writes Registers
tSSN_SENSE
tSSN_R
tSSN_UF01
tACC_REQ_x
500
500
50
—
—
—
—
—
—
—
—
ns
ns
µs
µs
Following Register Write to the UF_REGION_W Register
Time Between Sensor Data Requests (Same Channel, SPI Only, Arm
Enabled)
15
Arming Output Activation Time (ARM0, ARM1, IARM = 200 µA)
6
6
6
10809
10817
10816
Moving Average and Count Arming Modes
Unfiltered Mode Activation Delay
tARM
0
0
—
—
—
1.50
1.50
6.00
µs
µs
µs
tARM_UF_DLY
tARM_UF_ASSERT
Unfiltered Mode Arm Assertion Time
5.00
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
6
10808
SCLK low to SS_B low (SCLK = 10 % of VCC to SS_B = 90 % of VCC
)
tCLKSS
50
—
—
ns
FXLS9xxxx
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Dual channel inertial sensor
Table 36.ꢀDynamic electrical characteristics - SPI...continued
VCC_BUF_min ≤ (VBUS_I – VSS) ≤ VCC_BUF_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Serial Interface Timing (See Figure 97, CMISO ≤ 80 pF, RMISO ≥ 10 kΩ)
7
7, 8
7
10815
10818
SS_B high to SCLK high (SS_B = 90 % of VCC to SCLK = 90 % of VCC
)
tSSCLK
tLAT_SPI
CSPI_PIN
50
—
—
—
—
—
—
1
ns
µs
pF
SPI Data Latency
Pin Capacitance (MISO, MOSI, SCLK, SS_B to VSS)
10
10.14 Dynamic electrical characteristics - I2C
Table 37.ꢀDynamic electrical characteristics - I2C
VCC_BUF_min ≤ (VBUS_I – VSS) ≤ VCC_BUF_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Clock (SCL) Period (30 % of VCC to 30 % of VCC
)
6
6
6
10819
10820
10821
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tSCLK_100
tSCLK_400
tSCLK_1000
9.50
2.37
1.00
—
—
—
—
—
—
µs
µs
µs
Clock (SCL) High Time (70 % of VCC to 70 % of VCC
)
6
6
6
10823
10837
10836
100 kHz Mode
400 kHz Mode
tSCLH_100
tSCLH_400
tSCLH_1000
4.00
0.60
0.50
—
—
—
—
—
—
µs
µs
µs
1000 kHz Mode (note: not compliant with UM10204[1]
Clock (SCL) Low Time (30 % of VCC to 30 % of VCC
)
6
6
6
10835
10839
10838
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tSCLL_100
tSCLL_400
tSCLL_1000
4.70
1.30
0.50
—
—
—
—
—
—
µs
µs
µs
Clock (SCL) and Data (SDA) Rise Time (30 % of VCC to 70 % of VCC
)
6
6
6
10834
10841
10840
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tSRISE_100
tSRISE_400
tSRISE_1000
—
—
—
—
—
—
1000
300
ns
ns
ns
120
Clock (SCL) and Data (SDA) Fall Time (70 % of VCC to 30 % of VCC
)
6
6
6
10833
10844
10843
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tSFALL_100
tSFALL_400
tSFALL_1000
—
—
—
—
—
—
300
300
120
ns
ns
ns
Data Input Setup Time (SDA = 30/70 % of VCC to SCL = 30 % of VCC
)
6
6
6
10832
10846
10845
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tSETUP_100
tSETUP_400
tSETUP_1000
250
100
50
—
—
—
—
—
—
ns
ns
ns
Data Input Hold Time (SCL = 70 % of VCC to SDA = 30/70 % of VCC
)
6
10831
100 kHz Mode
tHOLD_100
0
—
900
ns
10848
10847
400 kHz Mode
1000 kHz Mode
tHOLD_400
0
0
—
—
900
300
ns
ns
6
6
tHOLD_1000
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Table 37.ꢀDynamic electrical characteristics - I2C...continued
VCC_BUF_min ≤ (VBUS_I – VSS) ≤ VCC_BUF_max, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Start Condition Setup Time (SDA = 30/70 % of VCC to SCL = 30 % of VCC
)
6
6
6
10830
10851
10850
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tSTARTSETUP_100
tSTARTSETUP_400
tSTARTSETUP_1000
4.70
0.60
0.26
—
—
—
—
—
—
µs
µs
µs
Start Condition Hold Time (SCL = 70 % of VCC to SDA = 30/70 % of VCC
)
6
6
6
10829
10853
10852
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tSTARTHOLD_100
tSTARTHOLD_400
tSTARTHOLD_1000
4.00
0.60
0.26
—
—
—
—
—
—
µs
µs
µs
Stop Condition Setup Time (SDA = 30/70 % of VCC to SCL = 30 % of VCC
)
6
6
6
10828
10855
10854
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tSTOPSETUP_100
tSTOPSETUP_400
tSTOPSETUP_1000
4.00
0.60
0.26
—
—
—
—
—
—
µs
µs
µs
SCLK low to data valid (SCL = 30 % of VCC to SDA = 30/70 % of VCC
)
6
6
6
10827
10857
10856
100 kHz Mode
400 kHz Mode
1000 kHz Mode
tVALID_100
tVALID_400
tVALID_1000
—
—
—
—
—
—
3.45
0.90
0.45
µs
µs
µs
Bus Free Time (SDA = 70 % of VCC to SDA = 70 % of VCC
)
6
6
10826
10859
10859
10825
100 kHz Mode
tFREE_100
tFREE_400
tFREE_1000
CBUS
4.00
1.30
0.50
—
—
—
—
—
—
—
µs
µs
µs
pF
400 kHz Mode
6
1000 kHz Mode
Bus Capacitive Load
—
7, 9
400
10.15 Dynamic electrical characteristics - signal chain, low-pass filter
Table 38.ꢀDynamic electrical characteristics - signal chain, low-pass filter
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test notes
DSP Low-Pass Filters Sample Times
*
7, 8, 9
10872
SAMPLERATE = 00, 01
tSigChain00
,
—
16
—
µs
tSigChain01
*
*
7, 8, 9
7, 8, 9
10872
10871
SAMPLERATE = 10
SAMPLERATE = 11
tSigChain10
—
—
32
64
—
—
µs
µs
tSigChain11
DSP Low-Pass Filters (Signal Chain Sample Time = 16 µs)
*
*
*
*
*
*
*
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
21379
21380
21381
21382
21383
21384
21385
Cutoff Frequency, Filter Option #0, and #2, 4-Pole
Cutoff Frequency, Filter Option #1, and #3, 3-Pole
Cutoff Frequency, Filter Option #4, 3-Pole
Cutoff Frequency, Filter Option #5, 2-Pole
Cutoff Frequency, Filter Option #6, 2-Pole
Cutoff Frequency, Filter Option #7, 2-Pole
Cutoff Frequency, Filter Option #8, 4-Pole
fc0_16, fc2_16
fc1_16, fc3_16
fc4_16
—
—
—
—
—
—
—
400
400
325
370
180
100
1500
—
—
—
—
—
—
—
Hz
Hz
Hz
Hz
Hz
Hz
Hz
fc5_16
fc6_16
fc7_16
fc8_16
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Table 38.ꢀDynamic electrical characteristics - signal chain, low-pass filter...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test notes
*
*
*
*
*
*
*
7, 8, 9, 11
26413
Cutoff Frequency, Filter Option #9, 4-Pole
fc9_16
—
500
—
Hz
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
10860
10870
10869
Cutoff Frequency, Filter Option #10, 4-Pole
Cutoff Frequency, Filter Option #11, 3-Pole
Cutoff Frequency, Filter Option #12, 3-Pole
Cutoff Frequency, Filter Option #13, 3-Pole
Cutoff Frequency, Filter Option #14, 2-Pole
Cutoff Frequency, Filter Option #15, 2-Pole
fc10_16
fc11_16
fc12_16
fc13_16
fc14_16
fc15_16
—
—
—
—
—
—
800
1200
120
—
—
—
—
—
—
Hz
Hz
Hz
Hz
Hz
Hz
20,000
120
10868
38364
50
DSP Low-Pass Filters (Signal Chain Sample Time = 32 µs)
*
*
*
*
*
*
*
*
*
*
*
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
38378
38379
38380
38381
38382
38383
38384
38385
38386
38387
38388
Cutoff Frequency, Filter Option #0, and #2, 4-Pole
Cutoff Frequency, Filter Option #1, and #3, 3-Pole
Cutoff Frequency, Filter Option #4, 3-Pole
Cutoff Frequency, Filter Option #5, 2-Pole
Cutoff Frequency, Filter Option #6, 2-Pole
Cutoff Frequency, Filter Option #7, 2-Pole
Cutoff Frequency, Filter Option #8, 4-Pole
Cutoff Frequency, Filter Option #9, 3-Pole
Cutoff Frequency, Filter Option #10, 4-Pole
Cutoff Frequency, Filter Option #11, 4-Pole
Cutoff Frequency, Filter Option #12, 3-Pole
Cutoff Frequency, Filter Option #13, 2-Pole
Cutoff Frequency, Filter Option #14, 2-Pole
Cutoff Frequency, Filter Option #15, 4-Pole
fc0_32, fc2_32
fc1_32, fc3_32
fc4_32
—
—
—
—
—
—
—
—
—
—
—
—
—
—
200
200
162.5
185
90
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
fc5_32
fc6_32
fc7_32
50
fc8_32
750
250
400
600
60
fc9_32
fc10_32
fc11_32
fc12_32
fc13_32
fc14_32
fc15_32
10,000
60
*
*
38389
38390
25
DSP Low-Pass Filters (Signal Chain Sample Time = 64 µs)
*
*
*
*
*
*
*
*
*
*
*
*
*
*
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
7, 8, 9, 11
38365
38366
38367
38368
38369
38370
38371
38372
38373
38374
38375
Cutoff Frequency, Filter Option #0, and #2, 4-Pole
Cutoff Frequency, Filter Option #1, and #3, 3-Pole
Cutoff Frequency, Filter Option #4, 3-Pole
Cutoff Frequency, Filter Option #5, 2-Pole
Cutoff Frequency, Filter Option #6, 2-Pole
Cutoff Frequency, Filter Option #7, 2-Pole
Cutoff Frequency, Filter Option #8, 4-Pole
Cutoff Frequency, Filter Option #9, 3-Pole
Cutoff Frequency, Filter Option #10, 4-Pole
Cutoff Frequency, Filter Option #11, 4-Pole
Cutoff Frequency, Filter Option #12, 3-Pole
Cutoff Frequency, Filter Option #13, 2-Pole
Cutoff Frequency, Filter Option #14, 2-Pole
Cutoff Frequency, Filter Option #15, 4-Pole
fc0_64, fc2_64
fc1_64, fc3_64
fc4_64
—
—
—
—
—
—
—
—
—
—
—
—
—
—
100
100
81.25
92.75
45
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
Hz
fc5_64
fc6_64
fc7_64
25
fc8_64
375
125
200
300
30
fc9_64
fc10_64
fc11_64
fc12_64
fc13_64
fc14_64
fc15_64
5,000
30
38376
38377
12.5
FXLS9xxxx
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Dual channel inertial sensor
10.16 Dynamic electrical characteristics - signal chain
Table 39.ꢀDynamic electrical characteristics - signal chain
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Offset Cancellation Low-Pass Filter
7, 8
7, 8
7, 8
10863
10874
10875
Sample Time, Phase 0
Cutoff Frequency, Phase 0, 1-Pole
Time in Phase 0
t0CSAMP0
fOC0
—
—
—
256
—
—
—
µs
Hz
ms
163.8
4.096
tOC0
Offset Cancellation Low-Pass Filter
7, 8
7, 8
7, 8
10888
10889
10890
Sample Time, Phase 1
Cutoff Frequency, Phase 1, 1-Pole
Time in Phase 1
t0CSAMP1
fOC1
—
—
—
256
—
—
—
µs
Hz
ms
40.96
4.096
tOC1
Offset Cancellation Low-Pass Filter
7, 8
7, 8
7, 8
10885
10886
10887
Sample Time, Phase 2
Cutoff Frequency, Phase 2, 1-Pole
Time in Phase 2
t0CSAMP2
fOC2
—
—
—
256
—
—
—
µs
Hz
ms
10.24
16.388
tOC2
Offset Cancellation Low-Pass Filter
7, 8
7, 8
7, 8
10900
10901
10902
Sample Time, Phase 3
Cutoff Frequency, Phase 3, 1-Pole
Time in Phase 3
t0CSAMP3
fOC3
—
—
—
256
—
—
—
µs
Hz
ms
2.560
65.53
tOC3
Offset Cancellation Low-Pass Filter
7, 8
7, 8
7, 8
10897
10898
10899
Sample Time, Phase 4
Cutoff Frequency, Phase 4, 1-Pole
Time in Phase 4
t0CSAMP4
fOC4
—
—
—
256
—
—
—
µs
Hz
ms
0.6400
262.19
tOC4
Offset Cancellation Low-Pass Filter
7, 8
7, 8
7, 8
10894
10895
10896
Sample Time, Phase 5
Cutoff Frequency, Phase 5, 1-Pole
Time in Phase 5
t0CSAMP5
fOC5
—
—
—
256
0.1600
1049
—
—
—
µs
Hz
ms
tOC5
Offset Cancellation Low-Pass Filter
7, 8
7, 8
39811
39812
Sample Time, Phase 6a
t0CSAMP6a
fOC6a
—
—
256
—
—
µs
*
*
Cutoff Frequency, Phase 6a, 1-Pole
0.0400
Hz
Offset Cancellation Low-Pass Filter
7, 8
7, 8
39813
39814
Sample Time, Phase 6b
t0CSAMP6b
fOC6b
—
—
1024
—
—
µs
Cutoff Frequency, Phase 6b, 1-Pole
0.005
Hz
Offset Cancellation Output Rate Limiting (0.04 Hz Offset LPF only)
7, 8, 9
7, 8, 9
7, 8
10882
10903
Rate Limiting Output Update Time
tRL_Rate
OFFStep10
OFFStep16
—
—
—
2
—
—
—
s
Rate Limiting Output Step Size (10 bit)
Rate Limiting Output Step Size (16 bit, PSI5, SPI)
0.5
32
LSB
LSB
FXLS9xxxx
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Dual channel inertial sensor
Table 39.ꢀDynamic electrical characteristics - signal chain...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Offset Monitor
7, 8
7, 8
7, 8
7, 8
10883
10905
10904
10881
Update Rate
OFFMONOSC
OFFMONCNTLIMIT
OFFMONCNTSIZE
tSigDelay
—
—
—
—
0.5
4096
8192
—
—
—
ms
1
Count Limit
Counter Size
—
1
Signal Delay (Sinc Filter to Output Delay, excluding LPF)
128
µs
Interpolation
7, 8
7, 8
7, 8
7, 8
20923
20922
20921
10877
tSigChain = tSigChain00, tSigChain01
tINTERP_00, 01
tINTERP_02
—
—
—
—
1
—
—
—
—
µs
µs
µs
tSigChain = tSigChain02
tSigChain = tSigChain03
Interpolation Latency
2
4
tINTERP_03
tLAT_INTERP
tSigChainxx
s
10.17 Dynamic electrical characteristics - analog self-test response time
Table 40.ꢀDynamic electrical characteristics - analog self-test response time
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Medium g, Lateral
Self-test Response Time: Self-test Activation/Deactivation to 99 %/1 % gST
7, 8
7, 8
10878
44634
Medium g Lateral, LPF = 800 Hz, 4-Pole
Medium g Lateral, LPF = 1500 Hz, 4-Pole
tST_Resp_MedX_800_4
tST_Resp_MedX_1500_4
750
395
795
415
1020
725
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
7, 8
7, 8
7, 8
38147
38151
38150
Medium g Lateral, LPF = 400 Hz, 4-Pole
Medium g Lateral, LPF = 400 Hz, 3-Pole
Medium g Lateral, LPF = 180 Hz, 2-Pole
tST_Resp_MedX_400_4
tST_Resp_MedX_400_3
tST_Resp_MedX_180_2
1510
1420
3030
1590
1490
3190
1810
1710
3470
µs
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
38149 Medium g Lateral, LPF = 300 Hz, 4-Pole
7, 8
7, 8
tST_Resp_MedX_300_4
2010
3210
2120
3380
2360
3680
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
38148 Medium g Lateral, LPF = 188 Hz, 4-Pole
tST_Resp_MedX_188_4
High g, Lateral
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
7, 8
7, 8
38152
44636
High g Lateral, LPF = 800 Hz, 4-Pole
High g Lateral, LPF = 1500 Hz, 4-Pole
tST_Resp_HiX_800_4
tST_Resp_HiX_1500_4
750
395
795
415
892
490
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
7, 8
7, 8
7, 8
38153
38154
38155
High g Lateral, LPF = 400 Hz, 4-Pole
High g Lateral, LPF = 400 Hz, 3-Pole
High g Lateral, LPF = 180 Hz, 2-Pole
tST_Resp_HiX_400_4
tST_Resp_HiX_400_3
tST_Resp_HiX_180_2
1510
1420
3030
1590
1490
3190
1720
1620
3400
µs
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
7, 8
38156
High g Lateral, LPF = 300 Hz, 4-Pole
tST_Resp_HiX_300_4
2010
2120
2280
µs
FXLS9xxxx
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NXP Semiconductors
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Dual channel inertial sensor
Table 40.ꢀDynamic electrical characteristics - analog self-test response time...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
38157 High g Lateral, LPF = 188 Hz, 4-Pole
7, 8
tST_Resp_HiX_188_4
3210
3380
3600
µs
Medium g, Z-Axis
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
7, 8
7, 8
38158
44637
Medium g Z-Axis, LPF = 800 Hz, 4-Pole
Medium g Z-Axis, LPF = 1500 Hz, 4-Pole
tST_Resp_MedZ_800_4
tST_Resp_MedZ_1500_4
750
395
795
415
1010
710
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
7, 8
7, 8
7, 8
38159
38160
38161
Medium g Z-Axis, LPF = 400 Hz, 4-Pole
Medium g Z-Axis, LPF = 400 Hz, 3-Pole
Medium g Z-Axis, LPF = 180 Hz, 2-Pole
tST_Resp_MedZ_400_4
tST_Resp_MedZ_400_3
tST_Resp_MedZ_180_2
1510
1420
3030
1590
1490
3190
1810
1700
3470
µs
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
38162 Medium g Z-Axis, LPF = 300 Hz, 4-Pole
7, 8
7, 8
tST_Resp_MedZ_300_4
2010
3210
2120
3380
2360
3680
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
38163 Medium g Z-Axis, LPF = 188 Hz, 4-Pole
tST_Resp_MedZ_188_4
High g, Z-Axis
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
7, 8
7, 8
38164
44638
High g Z-Axis, LPF = 800 Hz, 4-Pole
High g Z-Axis, LPF = 1500 Hz, 4-Pole
tST_Resp_HiZ_800_4
tST_Resp_HiZ_1500_4
750
395
795
415
994
675
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
7, 8
7, 8
7, 8
38165
38166
38167
High g Z-Axis, LPF = 400 Hz, 4-Pole
High g Z-Axis, LPF = 400 Hz, 3-Pole
High g Z-Axis, LPF = 180 Hz, 2-Pole
tST_Resp_HiZ_400_4
tST_Resp_HiZ_400_3
tST_Resp_HiZ_180_2
1510
1420
3030
1590
1490
3190
1800
1690
3470
µs
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
38168 High g Z-Axis, LPF = 300 Hz, 4-Pole
7, 8
7, 8
tST_Resp_HiZ_300_4
2010
3210
2120
3380
2360
3680
µs
µs
Self-test Response Time: Self-test Activation/Deactivation to 99 % / 1 % gST
38169 High g Z-Axis, LPF = 188 Hz, 4-Pole
tST_Resp_HiZ_188_4
10.18 Dynamic electrical characteristics - digital self-test response time
Table 41.ꢀDynamic electrical characteristics - digital self-test response time
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Self-test Response Time: Self-test Activation/Deactivation to Final Value
44639 LPF ≤ 60 Hz
7, 8
7, 8
tDST_Resp_50
—
—
—
—
50
25
ms
ms
Self-test Response Time: Self-test Activation/Deactivation to Final Value
44641 60 Hz ≤ LPF ≤ 200 Hz
tDST_Resp_100
Self-test Response Time: Self-test Activation/Deactivation to Final Value
7, 8
7, 8
44640
38176
300 Hz ≤ LPF ≤ 1500 Hz
tDST_Resp_400
tST_FP_Resp
—
—
—
—
12
ms
µs
Fixed Pattern Response Time: Self-test Activation/Deactivation
100
FXLS9xxxx
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10.19 Dynamic electrical characteristics - transducer
Table 42.ꢀDynamic electrical characteristics - transducer
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Lateral Transducer Rolloff Frequency (–3 db)
7
7
10917
10915
Medium g
High g
fgcell_3dB_mid
fgcell_3dB_hi
1500
4000
2500
7000
4500
Hz
Hz
13000
Lateral Transducer Delay (@100 Hz)
7
7
10921
10919
Medium g
High g
fgcell_delay100_mid
fgcell_delay100_hi
—
—
—
—
250
250
µs
µs
Z-Axis Transducer Rolloff Frequency (–3 db)
7
7
10923
10925
Medium g
High g
fgcell_3dB_mid
fgcell_3dB_hi
1500
1500
2500
2500
4500
7500
Hz
Hz
Z-Axis Transducer Delay (@100 Hz)
7
7
7
10927
10929
10912
Medium g
fgcell_delay100_mid
fgcell_delay100_hi
fPackage
—
—
—
—
—
250
250
—
µs
µs
High g
Package Resonance Frequency
100
kHz
10.20 Dynamic electrical characteristics - supply and support circuitry
Table 43.ꢀDynamic electrical characteristics - supply and support circuitry
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Reset Recovery (All Modes, excluding VBUS_I voltage ramp time)
7, 8, 9
7, 8, 9
7, 8
10930
10939
10938
10937
10936
10935
VCC = VCCMIN to POR Release
tVCC_POR
tPOR_DSI
—
—
—
—
—
—
—
—
1
6
ms
ms
ms
ms
ms
ms
POR to first DSI Command (Section 12.1)
POR to PSI5 Initialization Phase 1 Start (Section 13.4)
POR to first SPI Command
tPOR_PSI5
—
6
7, 8, 9
7, 8, 9
7, 8, 9
tPOR_SPI
0.400
—
0.700
30
6
POR to Sensor Data Valid
tPOR_DataValid
tRANGE_DataValid
DSP Setting Change to Sensor Data Valid: DS3, SPI, I2C
—
Soft Reset Activation Time
7, 8
7, 8
7, 8
7, 8
10934
30152
30151
41495
SPI: SS_B high to Reset
tSOFT_RESET_SPI
tSOFT_RESET_I2C
tSOFT_RESET_DSI
tSOFT_RESET_PSI
—
—
—
—
—
—
—
—
700
700
11
ns
ns
µs
µs
I2C: Command Complete to Reset (No ACK follows)
DSI3: Command/Response Complete to Reset
PSI5: Command/Response Complete to Reset
120
Internal Oscillator Period
*
1, 7, 8, 9
7, 8, 9
10933
10940
Untrained
fOSC
9.560
9.900
10.000
10.000
10.440
10.100
MHz
MHz
With Oscillator Training
fOSC_TRAIN
FXLS9xxxx
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Table 43.ꢀDynamic electrical characteristics - supply and support circuitry...continued
VBUS_I_L_min ≤ (VBUS_I – VSS) ≤ VBUS_I_H_min, TL ≤ TA ≤ TH, ΔT ≤ 25 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
Test
notes
Oscillator Training (Section 11.5.1)
7, 8
7, 8
7, 8
7, 8
7, 8
7, 9
10932
10942
10944
10943
10941
10946
Oscillator Training Time
tOscTrain
nOSC_4ms_TYP
OscTrainWIN
OscTrainADJ
OscTrainRES
tSET
—
—
4
40000
—
—
—
ms
Oscillator Cycles in Training Time
1/fOSC
1/fOSC
1/fOSC
1/fOSC
ms
Oscillator Training Window
38000
–400
42000
400
Oscillator Training Adjustment Threshold
Oscillator Training Step Size
—
250
—
Quiescent Current Settling Time (Power Applied to Iq = IIDLE ± 2 mA)
—
4
BUS_I Micro-cut
7, 9
7, 9
7, 9
7, 9
10931
10952
10953
10954
Survival Time (BUS_I disconnect without Reset, CBUF=1 µF, Bus with 1
slave)
tBUS_I_MICROCUT
30
—
15
—
—
—
—
—
—
1000
—
µs
µs
µs
µs
Reset Time (BUS_I disconnect time to Reset, CBUF=1 µF, Bus with 1
slave)
tBUS_I_RESET
Survival Time (BUS_I disconnect without Reset, CBUF=470 nF, Bus with
1 slave)
tBUS_I_MICROCUT
Reset Time (BUS_I disconnect time to Reset, CBUF=470 nF, Bus with 1
slave)
tBUS_I_RESET
1000
BUS_I Undervoltage Detection Delay
7
10947
BUS_I < VBUS_I_UV_F to IRESP Deactivation
tBUS_I_POR
—
—
5
µs
VBUF Undervoltage Detection Delay
7
7
10958
10957
VBUF < VBUF_UV_F to IRESP Deactivation
Undervoltage/Overvoltage Recovery Delay
tVBUF_POR
tUVOV_RCV
—
—
—
5
µs
µs
100
—
VBUF Capacitor Monitor
7
7
7
7
36817
36821
36823
36822
DSI Command Start to Capacitor Test
tD_CAPTEST
tP_CAPTEST
tA_CAPTEST
tCAPTST_TIME
—
—
—
—
3.0
9.2
—
—
—
—
µs
µs
µs
µs
PSI5 Synchronous Command Start to Capacitor Test
PSI5 Asynchronous Response Start to Capacitor Test
Capacitor Test Disconnect Time
179.2
1
11 Functional description
11.1 User accessible data array
A user accessible data array allows for each device to be customized. The array consists
of an OTP factory programmable block, an OTP user programmable block, and read-
only registers for data and device status. The OTP blocks incorporate independent data
verification.
11.1.1 User accessible data - general device information
Table 44.ꢀUser accessible data - general device information
Bit
Type
R
Address
$00
Register
7
6
5
4
3
2
1
0
COUNT
COUNT[7:0]
R
$01
DEVSTAT
DEVSTAT1
DEVSTAT2
CH0_ERR
VBUFUV_ERR
F_OTP_ERR
CH1_ERR
BUSINUV_ERR
U_OTP_ERR
COMM_ERR
VBUFOV_ERR
U_RW_ERR
MEMTEMP_ERR
RESERVED
SUPPLY_ERR
INTREGA_ERR
TEMP1_ERR
TESTMODE
INTREG_ERR
TEMP0_ERR
DEVRES
INTREGF_ERR
RESERVED
DEVINIT
R
$02
CONT_ERR
RESERVED
R
$03
U_W_ACTIVE
FXLS9xxxx
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Table 44.ꢀUser accessible data - general device information...continued
Bit
Type
R
Address
$04
Register
7
6
OSCTRAIN_ERR
0
5
4
3
2
1
0
DEVSTAT3
COMMREV
MREAD_STAT
RESERVED
TEMPERATURE
RESERVED
MISO_ERR
0
RESERVED
0
RESERVED
0
RESERVED
RESERVED
RESERVED
RESERVED
R
$05
COMMREV[3:0]
RESERVED MARGIN_RD_ACT MARGIN_RD_ERR
R
$06
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R
$07 - $0D
$0E
RESERVED
TEMP[7:0]
R
R
$0F
RESERVED
11.1.2 User accessible data - communication information
Table 45.ꢀUser accessible data - communication information
Bit
Type[1] Address Register
7
6
5
4
3
2
1
0
R/W
R/W
$10
$11
DEVLOCK_WR
ENDINIT
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SUP_ERR_DIS
RESERVED
EX_PADDR
RESET[1:0]
WRITE_OTP_
EN
UOTP_
WR_INIT
MARGIN_
RD_EN
EX_
COMMTYPE
UOTP_REGION[1:0]
R/W
R/W
R/W
R
$12
$13
$14
$15
$16
$17
$18
$19
$1A
$1B
$1C
$1D
BUSSW_CTRL
PSI5_TEST
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BUSSW_CTRL[1:0]
RESERVED
RESERVED
RESERVED
PSI5_TEST
UF_REGION_W
UF_REGION_R
COMMTYPE
RESERVED
REGION_LOAD[3:0]
REGION_ACTIVE[3:0]
RESERVED RESERVED
0
0
0
0
0
0
0
0
UF2
UF2
UF2
UF2
UF2
UF2
UF2
UF2
RESERVED
0
RESERVED
RESERVED
COMMTYPE[2:0]
RESERVED
PHYSADDR
0
0
0
PADDR[3:0]
RESERVED
RESERVED
SOURCEID_0
SOURCEID_1
SOURCEID_2
SOURCEID_3
SID0_EN
SID1_EN
SID2_EN
SID3_EN
PDCMFORMAT[2:0]
RESERVED
SOURCEID_0[3:0]
SOURCEID_1[3:0]
SOURCEID_2[3:0]
SOURCEID_3[3:0]
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
UF2 $1E - $21 RESERVED
RESERVED
UF2
UF2
UF2
$22
$23
$24
TIMING_CFG
PDCM_PER[2:0]
OSCTRAIN_
SEL
CK_CAL_RST
CRM_PER[1:0]
CHIPTIME[3:0]
CK_CAL_EN
CHIPTIME
ST_RPT[1:0]
PSI5_
ERRLATCH
SS_EN
TIMING_CFG2
PSI5_CFG
PSI5_
INIT2_D19
OSCTRAIN_ERRCNT[2:0]
CAPTEST_OFF
EMSG_EXT
RESERVED
P_CRC
BDM_
FRAGSIZE
BDM_EN
ASYNC
UF2
UF2
$25
$26
SYNC_PD
DAISY_CHAIN
PSI5_ILOW
RESERVED
DUALTRANS
INIT2_EXT
PDCM_
RSPST0_L
PDCM_RSPST0[7:0]
PDCM_RSPST1[7:0]
PDCM_RSPST2[7:0]
PDCM_RSPST3[7:0]
UF2
UF2
UF2
UF2
UF2
UF2
UF2
$27
$28
$29
$2A
$2B
$2C
$2D
PDCM_
RSPST0_H
BRC_RSP0[1:0]
PDCM_RSPST0[12:8]
PDCM_RSPST1[12:8]
PDCM_RSPST2[12:8]
PDCM_RSPST3[12:8]
PDCM_
RSPST1_L
PDCM_
RSPST1_H
BRC_RSP1[1:0]
BRC_RSP2[1:0]
BRC_RSP3[1:0]
RESERVED
RESERVED
RESERVED
PDCM_
RSPST2_L
PDCM_
RSPST2_H
PDCM_
RSPST3_L
PDCM_
RSPST3_H
UF2 $2E - $37 RESERVED
RESERVED
UF2
$38
PDCM_CMD_
B_L
PDCM_CMD_B[7:0]
UF2
$39
PDCM_CMD_
B_H
RESERVED
RESERVED
RESERVED
PDCM_CMD_B[12:8]
FXLS9xxxx
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Dual channel inertial sensor
Table 45.ꢀUser accessible data - communication information...continued
Bit
Type[1] Address Register
7
6
5
4
3
2
1
0
UF2
$3A -
$3C
RESERVED
RESERVED
UF2
UF2
UF2
$3D
$3E
$3F
SPI_CFG
SPI_STATUS
DATASIZE
SPI_CRC_LEN[1:0]
SPICRCSEED[3:0]
WHO_AM_I
I2C_ADDRESS
WHO_AM_I[7:0]
I2C_ADDRESS[7:0]
[1] Memory Type Codes
R - Readable Register with No OTP
F – User Readable Register with OTP
UF0 – One Time User Programmable OTP Location Region 0
UF1 – One Time User Programmable OTP Location Region 1
UF2 – One Time User Programmable OTP Location Region 2
R/W – User Writable Register
11.1.3 User accessible data - sensor specific information
Table 46.ꢀUser accessible data - sensor specific information
Bit
Type[1] Address Register
7
6
5
4
3
2
1
0
UF2
UF2
UF2
$40
$41
$42
CH0_CFG_U1
CH0_CFG_U2
CH0_CFG_U3
LPF[3:0]
SAMPLERATE[1:0]
USER_SNS_SHIFT[1:0]
U_SNS_MULT[7:0]
UNSIGN
EDDATA
DATATYPE0[1:0]
DATATYPE1[2:0]
MOVEAVG[1:0]
UF2
UF2
UF2
$43
$44
$45
CH0_CFG_U4
CH0_CFG_U5
RESET_OC
INVERT
OC_FILT[1:0]
ARM_PS[1:0]
PCM
ARM_CFG[2:0]
ST_CTRL[3:0]
OC_LIMIT[2:0]
ARM_WS_N[1:0]
DSP_DIS
ARM_WS_P[1:0]
CH0_ARM_
CFG
ARM_DS[1:0]
UF2
UF2
UF2
UF2
UF2
$46
$47
$48
$49
$4A
CH0_ARM_T_P
CH0_ARM_T_N
CH1_CFG_U1
CH1_CFG_U2
CH1_CFG_U3
ARM_T_P[7:0]
ARM_T_N[7:0]
LPF[3:0]
SAMPLERATE[1:0]
U_SNS_MULT[7:0]
DATATYPE1[2:0]
USER_SNS_SHIFT[1:0]
MOVEAVG[1:0]
UNSIGN
EDDATA
DATATYPE0[1:0]
UF2
UF2
UF2
$4B
$4C
$4D
CH1_CFG_U4
CH1_CFG_U5
RESET_OC
INVERT
ST_CTRL[3:0]
OC_FILT[1:0]
ARM_PS[1:0]
PCM
ARM_CFG[2:0]
OC_LIMIT[2:0]
ARM_WS_N[1:0]
DSP_DIS
ARM_WS_P[1:0]
CH1_ARM_
CFG
ARM_DS[1:0]
UF2
UF2
UF2
$4E
$4F
$50
CH1_ARM_T_P
CH1_ARM_T_N
ARM_T_P[7:0]
ARM_T_N[7:0]
RESERVED RESERVED
OC_PHASE_
CFG
CH0_OCFINAL CH1_OCFINAL
RESERVED
RESERVED
RESERVED
RESERVED
UF2
UF2
$51-$54 RESERVED
RESERVED
$55
CH0_U_
CH0_U_OFFSET[7:0]
OFFSET_L
UF2
$56
CH0_U_
CH0_U_OFFSET[15:8]
OFFSET_H
UF2
UF2
$57-$5C RESERVED
RESERVED
$5D
CH1_U_
CH1_U_OFFSET[7:0]
OFFSET_L
UF2
$5E
CH1_U_
CH1_U_OFFSET[15:8]
OFFSET_H
F
R
R
$5F
$60
$61
CRC_UF2
CH0_STAT
LOCK_UF2
SIGNALCLIP
CH0_ERR
0
0
0
CRC_UF2[3:0]
OCPHASE[2:0]
COMM_ERR
ST_INCMPLT
SUPPLY_ERR
ST_ACTIVE
TESTMODE
OFFSET_ERR
DEVRES
ST_ERROR
DEVINIT
DEVSTAT_
COPY
CH1_ERR
MEMTEMP_
ERR
R
$62
CH0_
CH0_SNSDATA0[7:0]
SNSDATA0_L
FXLS9xxxx
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Dual channel inertial sensor
Table 46.ꢀUser accessible data - sensor specific information...continued
Bit
Type[1] Address Register
7
6
5
4
3
2
1
0
R
R
R
$63
$64
$65
CH0_
SNSDATA0_H
CH0_SNSDATA0[15:8]
CH0_SNSDATA1[7:0]
CH0_SNSDATA1[15:8]
RESERVED
CH0_
SNSDATA1_L
CH0_
SNSDATA1_H
R
R
R
R
$66-$6F RESERVED
$70
$71
$72
CH1_STAT
SIGNALCLIP
OCPHASE[2:0]
ST_INCMPLT
ST_ACTIVE
OFFSET_ERR
ST_ERROR
RESERVED
RESERVED
CH1_
CH1_SNSDATA0[7:0]
SNSDATA0_L
R
R
R
R
$73
$74
$75
CH1_
SNSDATA0_H
CH1_SNSDATA0[15:8]
CH1_SNSDATA1[7:0]
CH1_SNSDATA1[15:8]
RESERVED
CH1_
SNSDATA1_L
CH1_
SNSDATA1_H
$76-$9F RESERVED
[1] Memory Type Codes
R - Readable Register with No OTP
F – User Readable Register with OTP
UF0 – One Time User Programmable OTP Location Region 0
UF1 – One Time User Programmable OTP Location Region 1
UF2 – One Time User Programmable OTP Location Region 2
R/W – User Writable Register
11.1.4 User accessible data - sensor specific information
Table 47.ꢀUser accessible data - sensor specific information
Bit
Type[1Address Register
7
6
5
4
3
2
1
0
F
F
F
F
F
F
F
F
F
F
F
$A0
$A1
$A2
$A3
$A4
$A5
$A6
$A7
$A8
$A9
CH0_CFG_F
DEV_RANGE[3:0]
RESERVED
RESERVED
RESERVED
AXIS[1:0]
RESERVED
CH0_STL_P_L
CH0_STL_P_H
CH0_STH_P_L
CH0_STH_P_H
CH0_STL_N_L
CH0_STL_N_H
CH0_STH_N_L
CH0_STH_N_H
RESERVED
CH0_STL_P[7:0]
CH0_STL_P[15:8]
CH0_STH_P[7:0]
CH0_STH_P[15:8]
CH0_STL_N[7:0]
CH0_STL_N[15:8]
CH0_STH_N[7:0]
CH0_STH_N[15:8]
RESERVED
$AA-
$AE
F
F
F
F
F
F
F
F
F
F
F
$AF
$B0
$B1
$B2
$B3
$B4
$B5
$B6
$B7
$B8
$B9
CRC_F_A
LOCK_F_A
REGA_BLOCKID[2:0]
CRC_F_A[3:0]
RESERVED
CH1_CFG_F
DEV_RANGE[3:0]
RESERVED
RESERVED
AXIS[1:0]
RESERVED
CH1_STL_P_L
CH1_STL_P_H
CH1_STH_P_L
CH1_STH_P_H
CH1_STL_N_L
CH1_STL_N_H
CH1_STH_N_L
CH1_STH_N_H
CH1_STL_P[7:0]
CH1_STL_P[15:8]
CH1_STH_P[7:0]
CH1_STH_P[15:8]
CH1_STL_N[7:0]
CH1_STL_N[15:8]
CH1_STH_N[7:0]
CH1_STH_N[15:8]
FXLS9xxxx
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Dual channel inertial sensor
Table 47.ꢀUser accessible data - sensor specific information...continued
Bit
Type[1] Address Register
7
6
5
4
3
2
1
0
F
$BA-
$BE
RESERVED
RESERVED
F
$BF
CRC_F_B
LOCK_F_B
REGB_BLOCKID[2:0]
CRC_F_B[3:0]
[1] Memory Type Codes
R - Readable Register with No OTP
F – User Readable Register with OTP
UF0 – One Time User Programmable OTP Location Region 0
UF1 – One Time User Programmable OTP Location Region 1
UF2 – One Time User Programmable OTP Location Region 2
R/W – User Writable Register
11.1.5 User accessible data - traceability information
Table 48.ꢀUser accessible data - traceability information
Bit
Type[1] Address Register
7
6
5
4
3
2
1
0
F
F
$C0
$C1
$C2
$C3
$C4
$C5
$C6
$C7
$C8
$C9
$CA
$CB
$CC
$CD
$CE
$CF
$D0
$D1
$D2
$D3
$D4
$D5
ICTYPEID
ICREVID
ICTYPEID[7:0]
ICREVID[7:0]
ICMFGID[7:0]
RESERVED
PN0[7:0]
F
ICMFGID
RESERVED
PN0
F
F
F
PN1
PN1[7:0]
F
SN0
SN[7:0]
F
SN1
SN[15:8]
F
SN2
SN[23:16]
SN[31:24]
F
SN3
F
SN4
SN[39:36] = DEVICE_REV[3:0]
SN[35:32]
F
ASICWFR#
ASICWFR_X
ASICWFR_Y
RESERVED
CRC_F_C
ASICWLOT_L
ASICWLOT_H
TRNS1WFR_X
TRNS1WFR_Y
TRNS1LOT_L
TRNS1LOT_H
ASICWFR#[7:0]
F
ASICWFR_X[7:0]
ASICWFR_Y[7:0]
RESERVED
F
F
F
LOCK_F_C
REGC_BLOCKID[2:0]
CRC_F_C[3:0]
F
ASICWLOT_L[7:0]
ASICWLOT_H[7:0]
TRNS1WFR_X[7:0]
TRNS1WFR_Y[7:0]
TRNS1LOT_L[7:0]
TRNS1LOT_H[7:0]
RESERVED
F
F
F
F
F
F
$D6-$D9 RESERVED
$DA TRNS1WFR#
$DB-$DE RESERVED
F
TRNS_ASSY_REV[2:0]
REGD_BLOCKID[2:0]
TRNS1WFR#[4:0]
F
RESERVED
F
$DF
$E0
$E1
$E2
$E3
$E4
$E5
$E6
$E7
$E8
CRC_F_D
LOCK_F_D
CRC_F_D[3:0]
UF0
UF0
UF0
UF0
UF0
UF0
UF0
UF0
UF0
USERDATA_0
USERDATA_1
USERDATA_2
USERDATA_3
USERDATA_4
USERDATA_5
USERDATA_6
USERDATA_7
USERDATA_8
USERDATA_0[7:0]
USERDATA_1[7:0]
USERDATA_2[7:0]
USERDATA_3[7:0]
USERDATA_4[7:0]
USERDATA_5[7:0]
USERDATA_6[7:0]
USERDATA_7[7:0]
USERDATA_8[7:0]
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Table 48.ꢀUser accessible data - traceability information...continued
Bit
Type[1] Address Register
7
6
5
4
3
2
1
0
UF0
UF0
UF0
UF0
UF0
UF0
F
$E9
$EA
$EB
$EC
$ED
$EE
$EF
$F0
$F1
$F2
$F3
$F4
$F5
$F6
$F7
$F8
$F9
$FA
$FB
$FC
$FD
$FE
$FF
USERDATA_9
USERDATA_A
USERDATA_B
USERDATA_C
USERDATA_D
USERDATA_E
CRC_UF0
USERDATA_9[7:0]
USERDATA_A[7:0]
USERDATA_B[7:0]
USERDATA_C[7:0]
USERDATA_D[7:0]
USERDATA_E[7:0]
LOCK_UF0
REGE_BLOCKID[2:0]
CRC_UF0[3:0]
UF1
UF1
UF1
UF1
UF1
UF1
UF1
UF1
UF1
UF1
UF1
UF1
UF1
UF1
UF1
F
USERDATA_10
USERDATA_11
USERDATA_12
USERDATA_13
USERDATA_14
USERDATA_15
USERDATA_16
USERDATA_17
USERDATA_18
USERDATA_19
USERDATA_1A
USERDATA_1B
USERDATA_1C
USERDATA_1D
USERDATA_1E
CRC_UF1
USERDATA_10[7:0]
USERDATA_11[7:0]
USERDATA_12[7:0]
USERDATA_13[7:0]
USERDATA_14[7:0]
USERDATA_15[7:0]
USERDATA_16[7:0]
USERDATA_17[7:0]
USERDATA_18[7:0]
USERDATA_19[7:0]
USERDATA_1A[7:0]
USERDATA_1B[7:0]
USERDATA_1C[7:0]
USERDATA_1D[7:0]
USERDATA_1E[7:0]
LOCK_UF1
REGF_BLOCKID[2:0]
CRC_UF1[3:0]
[1] Memory Type Codes
R - Readable Register with No OTP
F – User Readable Register with OTP
UF0 – One Time User Programmable OTP Location Region 0
UF1 – One Time User Programmable OTP Location Region 1
UF2 – One Time User Programmable OTP Location Region 2
R/W – User Writable Register
11.2 Register definitions
11.2.1 Rolling counter register (COUNT)
The count register is a read-only register which provides the current value of a free-
running 8-bit counter derived from the primary oscillator. A 10-bit prescaler divides the
primary oscillator frequency by 1000. Thus, the value in the register increases by one
count every 100 µs and the counter rolls over every 25.6 ms.
This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode.
Table 49.ꢀRolling counter register (COUNT)
Location
Bit
Address Register
7
6
5
4
3
2
1
0
$00
COUNT
COUNT[7:0]
Reset Value
0
0
0
0
0
0
0
0
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11.2.2 Device status registers (DEVSTATx)
The device status registers are read-only registers which contain device status
information.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode.
Table 50.ꢀDevice status registers (DEVSTATx)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$01
DEVSTAT
CH0_ERR
CH1_ERR
COMM_ERR
MEMTEMP_
ERR
SUPPLY_ERR
TESTMODE
DEVRES
DEVINIT
Reset Value
DEVSTAT1
Reset Value
DEVSTAT2
Reset Value
DEVSTAT3
1
1
0
0
x
0
1
1
$02
$03
$04
VBUFUV_ERR BUSINUV_ERR VBUFOV_ERR
RESERVED
INTREGA_ERR INTREG_ERR
INTREGF_ERR
CONT_ERR
x
x
x
x
x
x
x
0
F_OTP_ERR
0
U_OTP_ERR
0
U_RW_ERR
0
U_W_ACTIVE
0
TEMP1_ERR
0
TEMP0_ERR
0
RESERVED
x
RESERVED
x
MISO_ERR
OSCTRAIN_
ERR
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Reset Value
0
0
x
x
x
x
x
x
11.2.2.1 Channel 0 error flag (CH0_ERR)
The channel 0 error flag is set if a channel 0 specific error is present in the channel 0
DSP:
CH0_ERR = CH0_STAT[SIGNALCLIP] | CH0_STAT[ST_INCMPLT] |
CH0_STAT[OFFSET_ERR] | CH0_STAT[ST_ERROR]
11.2.2.2 Channel 1 error flag (CH1_ERR)
The channel 1 error flag is set if a channel 1 specific error is present in the channel 1
DSP:
CH1_ERR = CH1_STAT[SIGNALCLIP] | CH1_STAT[ST_INCMPLT] |
CH1_STAT[OFFSET_ERR] | CH1_STAT[ST_ERROR]
11.2.2.3 Communication error flag (COMM_ERR)
The communication error flag is set if any bit in DEVSTAT3 is set:
COMM_ERR = MISO_ERR | OSCTRAIN_ERR
11.2.2.4 Memory or temperature error flag (MEMTEMP_ERR)
The memory error flag is set if any bit in DEVSTAT2 is set:
MEMTEMP_ERR = F_OTP_ERR | U_OTP_ERR | U_RW_ERR | U_W_ACTIVE |
TEMP1_ERR | TEMP0_ERR
11.2.2.5 Supply error flag (SUPPLY_ERR)
The supply error flag is set if any bit in DEVSTAT1 is set:
SUPPLY_ERR = VBUFUV_ERR | BUSINUV_ERR | VBUFOV_ERR | INTREG_ERR |
INTREGA_ERR | INTREGF_ERR | CONT_ERR
A common timer is used for all error bits in the DEVSTAT1 register. If any bit in
DEVSTAT1 is set, the timer is reset to tUVOV_RCV. When no supply errors are present, the
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timer is decremented until it reaches zero. This error is cleared based on the state of the
SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Table 51.
Table 51.ꢀSupply error flag (SUPPLY_ERR)
SUP_
DSI3 and SPI operating modes
(COMMTYPE =0, 2, 3 and 4)
PSI5 operating modes
(COMMTYPE =1 and 5)
I2C operating modes
(COMMTYPE =6, 7)
ERR_DIS
0
No Response until the supply
monitor timer expires. The
Sensor Data Field Error Code is
transmitted for one response after normal transmissions resume.
the supply monitor timer expires.
No transmissions occur if the timer No response until the supply
is non-zero. The error is cleared
when the timer reaches zero and
monitor timer expires.
A read of the DEVSTAT1 register
clears all supply errors.
A read of the DEVSTAT1 register
clears all supply errors, using any
communication interface or on a
data transmission that includes the
error in the status field, if and only if
the timer has reached zero.
1
No transmissions occur if the timer
is non-zero. The error is cleared
when the timer reaches zero and
normal transmissions resume.
11.2.2.6 Test mode (TESTMODE)
The test mode bit is set if the device is in test mode. The TESTMODE bit can be cleared
by a test mode operation or by a power cycle.
Table 52.ꢀTest mode (TESTMODE)
TESTMODE
Operating mode
0
1
Test mode is not active
Test mode is active
11.2.2.7 Device reset (DEVRES)
The device reset bit is set following a device reset. This error is cleared by a read of the
DEVSTAT register through any communication interface or on a data transmission that
includes the error in the status field.
Table 53.ꢀDevice reset (DEVRES)
DEVRES
Error condition
0
1
Normal operation
Device reset occurred
11.2.2.8 Device initialization (DEVINIT)
The device initialization bit is set following either a device reset or a change to any of the
following bits: CHx_CFG_U1[7:2] or CHx_CFG_U3[1:0]. The bit is cleared once sensor
data is valid for read through one of the device communication inter-faces (tPOR_DataValid).
Note: Some LPF selections have a step response time longer than the tPOR_DataValid
delay. If any of these filters are used, the filter may not have achieved the final value once
DEVINIT is cleared.
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Table 54.ꢀDevice initialization (DEVINIT)
DEVINIT
Condition
0
1
Normal operation
Device Initialization in Process
11.2.2.9 VBUF under-voltage error (VBUFUV_ERR)
The VBUF under-voltage error bit is set if the VBUF voltage falls below the voltage
specified in Section 10.4. See Section 11.4 for details on the VBUF under-voltage monitor.
A common timer is used for all error bits in the DEVSTAT1 register. If any supply error
is present, the timer is reset to tUVOV_RCV. This bit is cleared based on the state of the
SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.
Table 55.ꢀVBUF under-voltage error (VBUFUV_ERR)
VBUFUV_ERR
Error condition
No error detected
VBUF Voltage Low
0
1
11.2.2.10 BUS IN under-voltage error (BUSINUV_ERR)
The BUS IN under-voltage error bit is set if the BUS_IN voltage falls below the voltage
specified in Section 10.4. See Section 11.4 for details on the BUS IN under-voltage
monitor. A common timer is used for all error bits in the DEVSTAT1 register. If any supply
error is present, the timer is reset to tUVOV_RCV. This bit is cleared based on the state of
the SUP_ER-R_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.
Table 56.ꢀBUS IN under-voltage error (BUSINUV_ERR)
BUSINUV_ERR
Error condition
0
1
No error detected
BUS_IN Voltage Low
11.2.2.11 VBUF over-voltage error (VBUFOV_ERR)
The VBUF over-voltage error bit is set if the VBUF voltage rises above the voltage
specified in Section 10.4. See Section 11.4 for details on the VBUF over-voltage monitor.
A common timer is used for all error bits in the DEVSTAT1 register. If any supply error
is present, the timer is reset to tUVOV_RCV. This bit is cleared based on the state of the
SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Section 11.2.2.5.
Table 57.ꢀVBUF over-voltage error (VBUFOV_ERR)
VBUFUV_ERR
Error condition
No error detected
VBUF Voltage High
0
1
11.2.2.12 Internal analog regulator voltage out of range error (INTREGA_ERR)
The internal analog regulator voltage out of range error bit is set if the internal analog
regulator voltage falls outside expected limits. A common timer is used for all error bits
in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV
This bit is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR
register as shown in Section 11.2.2.5.
.
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Table 58.ꢀInternal analog regulator voltage out of range error (INTREGA_ERR)
INTREGA_ERR
Error condition
0
1
No error detected
Internal Analog Regulator Voltage Out of Range
11.2.2.13 Internal digital regulator voltage out of range error (INTREG_ERR)
The internal digital regulator voltage out of range error bit is set if the internal digital
regulator voltage falls outside expected limits. A common timer is used for all error bits
in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV
This bit is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR
register as shown in Section 11.2.2.5.
.
Table 59.ꢀInternal digital regulator voltage out of range error (INTREG_ERR)
INTREG_ERR
Error condition
0
1
No error detected
Internal Digital Regulator Voltage Out of Range
11.2.2.14 Internal OTP regulator voltage out of range error (INTREGF_ERR)
The internal OTP regulator voltage out of range error bit is set if the internal OTP
regulator voltage falls outside expected limits. A common timer is used for all error bits
in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV
This bit is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR
register as shown in Section 11.2.2.5.
.
Table 60.ꢀInternal OTP regulator voltage out of range error (INTREGF_ERR)
INTREGF_ERR
Error condition
0
1
No error detected
Internal OTP Regulator Voltage Out of Range
11.2.2.15 Continuity monitor error (CONT_ERR)
The continuity monitor passes a low current through a connection around the perimeter
of the device and monitors the continuity of the connection. The error bit is set if a
discontinuity is detected in the connection. A common timer is used for all error bits in the
DEVSTAT1 register. If the CONT_ERR bit is set, the timer is reset to tUVOV_RCV. This bit
is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as
shown in Section 11.2.2.5.
Table 61.ꢀContinuity monitor error (CONT_ERR)
CONT_ERR
Error condition
0
1
No error detected
Error detected in the continuity of the monitor circuit
11.2.2.16 NXP OTP array error (F_OTP_ERR)
The factory OTP array error bit is set if a fault is detected in the factory OTP array. This
error is cleared by a device reset. See Section 11.2.15.2 for details on a method to
disable the automatic clearing of this error in PSI5 mode.
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Table 62.ꢀNXP OTP array error (F_OTP_ERR)
F_OTP_ERR
Error condition
0
1
No error detected
Error Detected in the Factory OTP Array
11.2.2.17 User OTP array error (U_OTP_ERR)
The user OTP array error bit is set if a fault is detected in the user OTP array. This error
is cleared by a device reset. See Section 11.2.15.2 for details on a method to disable the
automatic clearing of this error in PSI5 mode.
Table 63.ꢀUser OTP array error (U_OTP_ERR)
U_OTP_ERR
Error condition
0
1
No error detected
Error Detected in the User OTP Array
11.2.2.18 User read/write array error (U_RW_ERR)
When ENDINIT is set, an error detection is enabled for all user writable registers. The
error detection code is continuously calculated on the user writable registers and verified
against a previously calculated error detection code. If a mismatch is detected in the error
detection, the U_RW_ERR bit is set. This error is cleared by a read of the DEVSTAT2
register through any communication interface or on a data transmission that includes
the error in the status field. See Section 11.2.15.2 for details on a method to disable the
automatic clearing of this error in PSI5 mode.
Table 64.ꢀUser read/write array error (U_RW_ERR)
U_RW_ERR
Error condition
0
1
No error detected
Error Detected in the User Read/Write Array
11.2.2.19 User OTP write in process status bit (U_W_ACTIVE)
The user OTP write in process status bit is set if a user initiated write to OTP is currently
in process. The U_W_ACTIVE bit is automatically cleared once the write to OTP is
complete.
Table 65.ꢀUser OTP write in process status bit (U_W_ACTIVE)
U_W_ACTIVE
Status condition
0
1
No OTP Write in Process
OTP Write in Process
11.2.2.20 Channel 1 temperature sensor error (TEMP1_ERR)
The channel 1 temperature error bit is set if an over or under temperature condition exists
on channel 1. This error is cleared by a read of the DEVSTAT2 register through any
communication interface or on a data transmission that includes the error in the status
field. See Section 11.2.15.2 for details on a method to disable the automatic clearing of
this error in PSI5 mode.
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Table 66.ꢀChannel 1 temperature sensor error (TEMP1_ERR)
TEMP1_ERR
Error condition
0
1
No error detected
Over- or Under-Temperature error condition detected
11.2.2.21 Channel 0 temperature sensor error (TEMP0_ERR)
The channel 0 temperature error bit is set if an over or under temperature condition exists
on channel 0. This error is cleared by a read of the DEVSTAT2 register through any
communication interface or on a data transmission that includes the error in the status
field. See Section 11.2.15.2 for details on a method to disable the automatic clearing of
this error in PSI5 mode.
Table 67.ꢀChannel 0 temperature sensor error (TEMP0_ERR)
TEMP0_ERR
Error condition
0
1
No error detected
Over- or Under-Temperature error condition detected
11.2.2.22 SPI MISO data mismatch error flag (MISO_ERROR)
In SPI mode, the MISO data mismatch flag is set when a MISO Data mismatch fault
occurs as specified in Section 14.5.7. The MISO_ERROR bit is cleared by a read of the
DEVSTAT3 register through any communication interface, or by a status transmission
including the error status through the SPI.
Table 68.ꢀSPI MISO data mismatch error flag (MISO_ERROR)
MISO_ERROR
Error condition
0
1
Normal operation
MISO Data Mismatch
11.2.2.23 Oscillator training error (OSCTRAIN_ERR)
The oscillator training error bit is set if an error detected in either the oscillator
training settings, or the master communication timing. See Section 11.5.2. Once the
error condition is corrected, the OSCTRAIN_ERR bit is cleared after a read of the
OSCTRAIN_ERR bit through any communication interface, or by a status transmission
including the error status through any communication interface.
Table 69.ꢀOscillator training error (OSCTRAIN_ERR)
OSCTRAIN_ERR
Error condition
0
1
No error detected
Oscillator Training Error. See Section 11.5.2
11.2.3 Communication protocol revision register (COMMREV)
The communication protocol revision register is a read-only register which contains the
revision for the communication protocol used.
This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode.
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Table 70.ꢀCommunication protocol revision register (COMMREV)
Location
Bit
Address
$05
Register
7
0
0
0
0
0
6
0
0
0
0
0
5
0
0
0
0
0
4
0
0
0
0
0
3
2
1
0
COMMREV
COMMREV[3:0]
Reset Value for DSI3
Reset Value for PSI5
Reset Value for SPI
Reset Value for I2C
0
0
0
0
0
1
0
1
0
1
0
0
1
0
0
1
Note: The response to a register write of the COMMREV register is a valid response
with the register contents equal to 0x00.
11.2.4 Margin read status register (MREAD_STAT)
The Margin Read Status register is a read-only register which contains the status for the
user enabled OTP margin read test.
This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode.
Table 71.ꢀMargin read status register (MREAD_STAT)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$06
MREAD_
STAT
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
MARGIN_
RD_ACT
MARGIN_
RD_ERR
Reset Value
0
0
0
0
0
0
0
0
Note: The user enabled OTP margin read test is not intended for use in normal
operation. It is intended for use only after user OTP programming during manufacturing.
11.2.4.1 Margin read active status (MARGIN_RD_ACT)
The margin read active status bit is set if a user enabled OTP margin read test is in
process. The status bit is automatically cleared when the OTP margin read test is
complete. See Section 11.2.7.1 for details regarding the user enabled OTP margin read
test.
Table 72.ꢀMargin read active status (MARGIN_RD_ACT)
MARGIN_RD_ACT
Condition
0
1
No Margin Read Test is in Process
Margin Read Test is in Process
11.2.4.2 Margin read error status (MARGIN_RD_ERR)
The margin read error status bit is set if a user enabled OTP margin read test has failed.
The margin read error status bit is cleared on a read of the MREAD_STAT register. The
margin read error status bit has no impact on device operation or performance. See
Section 11.2.7.1 for details regarding the user enabled OTP margin read test.
Table 73.ꢀMargin read error status (MARGIN_RD_ERR)
MARGIN_RD_ERR
Condition
0
1
No Margin Read Test Failure
Margin Read Test Failure
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11.2.5 Temperature register (TEMPERATURE)
The temperature register is a read-only register which provides a temperature value from
the channel 0 temperature sensor. The temperature value is specified in Section 10.5.
Note, the device is only guaranteed to operate within the temperature limits specified in
Section 10. This includes the performance of the temperature register values.
This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode.
Table 74.ꢀTemperature register (TEMPERATURE)
Location
Bit
Address
$0E
Register
7
6
5
4
3
2
1
0
TEMPE
TEMP[7:0]
RATURE
Reset Value
0
0
0
0
0
0
0
0
11.2.6 Device lock register (DEVLOCK_WR)
The device lock register is a user programmed read/write register which contains the
ENDINIT bit and reset control bits.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 75.ꢀDevice lock register (DEVLOCK_WR)
Location
Bit
Address
Register
7
ENDINIT
0
6
5
4
3
2
1
0
$10
DEVLOCK_WR
RESERVED
0
RESERVED
0
RESERVED
0
SUP_ERR_DIS
0
RESERVED
0
RESET[1:0]
Reset Value
0
0
11.2.6.1 End initialization bit (ENDINIT)
The ENDINIT bit is a control bit used to indicate that the user has completed all device
and system level initialization tests. Once the ENDINIT bit is set, writes to all writable
register bits are inhibited except for the DEVLOCK_WR register. Once set, the ENDINIT
bit can only be cleared by a device reset.
When ENDINIT is set, the following occurs:
• An error detection is enabled for all user writable registers. The error detection code is
continuously calculated on the user writable registers and verified against a previously
calculated error detection code.
• The offset cancellation filter is forced to its final stage.
• Self-test is disabled and inhibited.
• Register Writes are inhibited with the exception of the RESET[1:0] bits in the
DEVLOCK_WR register.
In DSI3 mode, when the ENDINIT bit is set, the device is forced to PDCM according to
the device settings and no longer responds to CRM commands.
In PSI5 mode, the ENDINIT bit is automatically set when the device exits Initialization
Phase 3.
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11.2.6.2 Supply error reporting disable bit (SUP_ERR_DIS)
The supply error disable bit allows the user to disable reporting of the supply errors in the
DSI3 PDCM and SPI status fields. See Section 11.2.2.5.
11.2.6.3 Reset control bits (RESET[1:0])
In DSI3 mode, SPI mode, I2C mode or PSI5 mode, a series of three consecutive register
write operations to the reset control bits results in a device reset. To reset the device, the
following register write operations must be performed in consecutive commands and in
the order shown in Table 76 or the device will reset.
Table 76.ꢀReset control bits (RESET[1:0])
Register write to DEVLOCK_WR
Register Write 1
RES_1
RES_0
Effect
0
1
0
0
1
1
No Effect
No Effect
Device RESET
Register Write 2
Register Write 3
The response to a register write returns the new register value, including the values
written to the RESET[1:0] bits. After the third Register Write command, the device
initiates a reset and therefore does not transmit a response to this command or an
Acknowledge in I2C mode. The response to a register read returns '00' for RESET[1:0]
and terminates the reset sequence. The reset control bits are not included in the read/
write array error detection.
11.2.7 Write OTP enable register
The write OTP enable register is a user programmed read/write register that allows the
user to write the contents of the user programmed OTP array mirror registers to the OTP
registers. This register is included in the user read/write array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 77.ꢀWrite OTP enable register
Location
Address
$11
Bit
Register
7
6
5
4
3
2
1
0
WRITE_OTP_EN UOTP_WR_
INIT
MARGIN_RD_
EN
RESERVED
RESERVED
EX_
COMMTYPE
EX_PADDR
UOTP_REGION[1:0]
Reset Value
0
0
0
0
0
0
0
0
11.2.7.1 Margin read enable bit (MARGIN_RD_EN)
The margin read enable bit initiates an OTP margin read test for all user programmable
OTP regions: UF2, UF0, and UF1. The user enabled OTP margin read test is not
intended for use in normal operation. It is intended for use only after user OTP
programming during manufacturing.
The procedure for completing an OTP margin read test is shown in step 1 through step 7:
1. Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT and
MARGIN_RD_ERR bits are both cleared.
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2. Write 0x40 to the WRITE_OTP_EN register to set the MARGIN_RD_EN bit. This
initiates the OTP margin read test which completes the sequence listed in steps a
through i.
a. The UF2 block is read. The ECC is checked for double bit errors and the CRC
is verified. If an ECC error or CRC error exists or if UF2 block is unlocked, the
MARGIN_RD_ERR bit is set and the test is terminated.
b. A margin read low test is run with the read threshold reduced by 25 %. The data
is checked against the expected values in the mirror registers. If a double bit ECC
error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and
the test is terminated.
c. A margin read high test is run with the read threshold increased by 25 %. The data
is checked against the expected values in the mirror registers. If a double bit error
or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test
is terminated.
d. The UF0 block is read. The ECC is checked for double bit errors and the CRC
is verified. If an ECC error or CRC error exists or if UF0 block is unlocked, the
MARGIN_RD_ERR bit is set and the test is terminated.
e. A margin read low test is run with the read threshold reduced by 25 %. The data
is checked against the expected values in the mirror registers. If a double bit ECC
error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and
the test is terminated.
f. A margin read high test is run with the read threshold increased by 25 %. The data
is checked against the expected values in the mirror registers. If a double bit error
or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test
is terminated.
g. The UF1 block is read. The ECC is checked for double bit errors and the CRC
is verified. If an ECC error or CRC error exists or if UF1 block is unlocked, the
MARGIN_RD_ERR bit is set and the test is terminated.
h. A margin read low test is run with the read threshold reduced by 25 %. The data
is checked against the expected values in the mirror registers. If a double bit ECC
error or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and
the test is terminated.
i. A margin read high test is run with the read threshold increased by 25 %. The data
is checked against the expected values in the mirror registers. If a double bit error
or data comparison mismatch occurs, the MARGIN_RD_ERR bit is set and the test
is terminated.
3. Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT bit is set and
the MARGIN_RD_ERR bit is cleared.
4. Delay 1.5 ms minimum.
5. Read the MREAD_STAT register to confirm that the MARGIN_RD_ACT bit is cleared.
Check the state of the MARGIN_RD_ERR bit.
• If the MARGIN_RD_ERR bit is cleared, the margin read test passed.
• If the MARGIN_RD_ERR bit is set, the margin read test failed.
6. When the test is complete, the MARGIN_RD_EN bit is cleared.
7. When the test is complete and the MREAD_STAT register has been read, the
MARGIN_RD_ACT and the MARGIN_RD_ERR bit are cleared.
The user enabled OTP margin read test can only be enabled when the ENDINIT bit is not
set.
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11.2.7.2 Write OTP enable and programming bits
Register writes executed by the user to the user programmed OTP array only update
the mirror register contents for the OTP array, not the actual OTP registers. To copy the
values to the actual OTP registers, a write must be executed to the WRITE_OTP_EN
register with the UOTP_WR_INIT bit set. The state of the UOTP_REGION[1:0], the
EX_COMMTYPE, and the EX_PADDR bits in the command determine which region of
OTP are written as shown in Table 78.
Table 78.ꢀWrite OTP enable and programming bits
EX_
EX_PADDR
UOTP_
UOTP_
OTP write operation
Special
COMMTYPE
REGION[1] REGION[0]
conditions
x
x
0
x
x
0
0
0
1
0
1
0
Write the current contents of the UF0 registers
to OTP
Write the current contents of the UF1 registers
to OTP
Write the current contents of the UF2 registers
to OTP, including the COMMTYPE register and
the PHYSADDR register
0
1
1
1
0
1
1
1
1
0
0
0
Write the current contents of the UF2 registers PHYSADDR =
to OTP, including COMMTYPE and excluding 0x00 after OTP
PHYSADDR.
Write
Write the current contents of the UF2 registers User must
to OTP, excluding COMMTYPE and including not overwrite
PHYSADDR.
COMMTYPE
Write the current contents of the UF2 registers User must
to OTP, excluding COMMTYPE and excluding not overwrite
PHYSADDR.
COMMTYPE
PHYSADDR =
0x00 after OTP
Write
x
x
1
1
Reserved for Future Use
The UF0 and UF1 user OTP regions as well as the NXP programmed F OTP regions
share common mirror registers. For this reason, writes to the OTP for each region must
be completed independently according to the procedure below.
Depending upon the operating mode used, the user needs to write the UF2 values
to OTP either with or without the PHYSADDR register and the COMMTYPE register
being written. If Discovery Mode or switch connected daisy chain mode is used, the
PHYSADDR register must remain un-programmed (0x0000). If a pre-programmed bus
mode is used, the PHYSADDR register must be programmed to a non-zero value. To
support these two user modes, the EX_PADDR bit is used as described in Table 78.
Once a region is written using the OTP Write sequence, the LOCK_Uxx bit in the
appropriate CRC_xxx register is automatically set, locking the array from future writes.
Once a region is locked, an error detection is activated to detect changes to the register
values. Register values in the UF2 region can be over-written using register write
commands, but no new values can be written to the OTP.
The procedure for writing to the user OTP array UF0 and UF1 regions is:
1. Read the appropriate CRC_UFx register and confirm the LOCK_Uxx bit is not set.
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2. Write the desired values to the user array registers for only the region to be written
using the procedures in Section 11.2.10.
• The user must take care to ensure that the proper data is written to each region.
If a register write is executed to a new region, the base address changes to the
new region. The previous data written to the register block remains in the shared
registers and is written to OTP if the Write OTP sequence is completed.
3. Execute a write to the WRITE_OTP_EN register with the appropriate bits set for the
desired region to program.
• Once the WRITE_OTP_EN register write is completed, a CRC is calculated for
the data to be written to the region, the register values are written to OTP and the
region is locked from future writes. The UOTP_WR_INIT bit remains set.
4. Delay tOTP_WRITE_MAX to allow the device to complete the writes to OTP.
5. Verify that the OTP write successfully completed by reading back all of the OTP
registers using Register Read commands as defined in Section 11.2.10.
6. Repeat steps 1 through 4 for all regions to be programmed.
The procedure for writing to the user OTP array UF2 region is:
1. Read the CRC_UF2 register and confirm the LOCK_UF2 bit is not set.
2. Write the desired values to the user array registers.
3. Execute a write to the WRITE_OTP_EN register with region 2 selected and the
EX_COMMTYPE and EX_PADDR bit set as desired.
• Once the WRITE_OTP_EN register write is completed, a CRC is calculated for
the data to be written to the region, the register values are written to OTP and the
region is locked from future writes. The UOTP_WR_INIT bit remains set.
4. Delay tOTP_WRITE_MAX to allow the device to complete the writes to OTP and an
automatic read of the UF2 registers from OTP.
5. Verify that the OTP write successfully completed by reading back all of the OTP
registers using Register Read commands.
11.2.8 Bus switch control register (BUSSW_CTRL)
The bus switch control register is a user programmed read/write register which controls
the state of the bus switch output driver. This register is included in the user read/write
array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 79.ꢀBus switch control register (BUSSW_CTRL)
Location
Bit
Address
Register
BUSSW_CTRL
Reset Value
7
6
5
4
3
2
1
0
$12
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
BUSSW_CTRL[1:0]
0
0
The BUSSW_CTRL bit controls the state of the BUSSW_L pin.
Table 80.ꢀBUSSW_L pin state
BUSSW_CTRL[1] BUSSW_CTRL[0] BUSSW_L Pin State
0
0
High Impedance. An external pullup or pulldown resistor
is required if an external switch is connected
0
1
High Impedance. An external pullup or pulldown resistor
is required if an external switch is connected
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Table 80.ꢀBUSSW_L pin state...continued
BUSSW_CTRL[1] BUSSW_CTRL[0] BUSSW_L Pin State
1
1
0
1
Active Low.
Active High.
Note: In DSI3 and PSI5 DPM modes, the bus switch is activated upon receipt of the
register write command. The bus switch activation may impact the current on the bus and
cause corruption of the register write response.
11.2.9 PSI5 test register (PSI5_TEST)
The PSI5 test register is a user read/write register that contains the PSI5 test control.
This register is included in the user read/write array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 81.ꢀPSI5 test register (PSI5_TEST)
Location
Register
PSI5_TEST
Reset Value
Bit
Address
7
6
5
4
3
2
1
0
$13
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
PSI5_TEST
0
11.2.9.1 PSI5 test bit (PSI5_TEST)
If PSI5 mode is not enabled in the COMMTYPE, the PSI5 test bit enables a single PSI5
command receive and response transmission to allow for the PSI5 transceiver to be
tested in other modes.
When the PSI5_TEST bit is set, the device and system proceed through following
process.
1. The device switches the BUS_I transceiver to PSI5 mode.
2. The system holds the BUS_I node constant for 2 ms minimum to allow the BUS_I
command receiver to capture the average voltage.
3. The system must transmit a sync pulse meeting the specifications in Section 10.
4. The device transmits a response to the sync pulse with the following configuration:
a. The sync pulse is pulled down as configured by the SYNC_PD bit in the
PSI5_CFG register.
b. The response starts in the time slot selected in the PDCM_RSPST0 register.
c. The response bit time is configured in the CHIPTIME register.
d. The response current is configured by the PSI5_ILOW bit in the PSI5_CFG
register.
e. Two start bits are transmitted as specified in Section 13.3.2.
f. 10-bits of data equal to 0x2AA are transmitted.
g. Error checking bits are transmitted as configured by the P_CRC bit in the
PSI5_CFG register.
5. Once the transmission is complete, the PSI5_TEST bit is cleared and the device
returns to the communication mode as defined in the COMMTYPE register.
If the bit is set from DSI3 mode, this process occurs once the device has replied to the
write message, regardless of whether or not the reply attempted was successful.
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If the bit is set from SPI mode, the process occurs once the PSI5_TEST bit is set with no
SPI reply necessary.
If the bit is set from I2C mode, the process occurs once the PSI5_TEST bit is set with no
I2C reply necessary.
If PSI5 mode is enabled in the COMMTYPE register, this bit has no impact on device
operation or performance.
11.2.10 UF region selection registers (UF_REGION_x)
The UF region load register is a user read/write register that contains the control bits for
the UF0 and UF1 regions to be accessed. This register is included in the user read/write
array error detection. The UF region active register is a read-only register that contains
the status bits for the UF0 and UF1 regions to be accessed.
The UF_REGION_W register is readable and writable in DSI3 mode, SPI mode, I2C
mode or PSI5 Programming Mode. The UF_REGION_R register is readable in DSI3
mode, SPI mode, I2C mode or PSI5 Programming Mode.
Table 82.ꢀUF region selection registers (UF_REGION_x)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$14
UF_
REGION_LOAD[3:0]
0
0
0
0
REGION_W
$15
UF_REGION_R
REGION_ACTIVE[3:0]
0
0
0
0
0
0
0
0
Reset Value
1
1
1
0
The user OTP regions UF0, UF1, and F share a block of 16 registers. Prior to reading the
registers via any communication interface, the user must ensure that the desired OTP
registers are loaded into the readable registers. To ensure proper reading of the UF0,
UF1 and F registers, follow this procedure:
1. Write the desired address range to be read to the REGION_LOAD[3:0] bits in the
UF_REGION_W register using one of the communication interfaces available via the
COMMTYPE register.
Table 83.ꢀRegion load bits
REGION_LOAD[3:0]
OTP register addresses loaded into the readable
registers
0
0
0
0
0
0
0
1
Not Applicable
Not Applicable
0010 through 1001
RESERVED
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Address Range $A0 through $AF
Address Range $B0 through $BF
Address Range $C0 through $CF
Address Range $D0 through $DF
Address Range $E0 through $EF
Address Range $F0 through $FF
2. Delay a minimum of tSSN_UF01
.
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3. Optional: Execute a register read of the UF_REGION_R register and confirm the
REGION_ACTIVE[3:0] bits match the values written to the REGION_LOAD[3:0] bits in
the UF_REGION_W register.
Table 84.ꢀRegion active bits
REGION_ACTIVE[3:0]
OTP register addresses loaded into the readable
registers
0
0
0
0
0
0
0
1
Load of OTP registers is in process
The contents of the shared registers has been over-written
by the user
0010 through 1001
Not Applicable
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Address Range $A0 through $AF
Address Range $B0 through $BF
Address Range $C0 through $CF
Address Range $D0 through $DF
Address Range $E0 through $EF
Address Range $F0 through $FF
4. Execute a Register Read of the desired registers from the UF0, UF1, or F register
section. Complete all desired Register Reads of the selected UF Region.
5. Repeat steps 1 through 4 for the next desired UF region to read.
Notes:
• The user must take care to ensure that the desired registers are addressed. For
example, if the REGION_LOAD bits are set to 0xA and the user executes a read
of address $C2, the contents of registers $A2 are transmitted. No error detection is
included other than a read of the REGION_ACTIVE bits.
• For COMMTYPE options with multiple protocol options (COMMTYPE = '000' or '001'),
no error detection is included other than a read of the REGION_ACTIVE bits. The user
must take care to ensure that the REGION_LOAD, bits are not inadvertently changed
by an alternative protocol while executing register reads.
• In DSI3, BDM, writes to registers are inhibited. For this reason, reads of the UF0, UF1,
and F registers will only be possible for the region selected by the REGION_ACTIVE
bits at the time ENDINIT is set.
• In SPI and I2C mode, once the ENDINIT bit is set, writes to registers other than the
RESET[1:0] bits are inhibited. For this reason, reads of the UF0, UF1, and F registers
will only be possible for the region selected by the REGION_ACTIVE bits at the time
ENDINIT is set.
11.2.11 Communication type register (COMMTYPE)
The communication type register is a user programmed read/write register which
contains user-specific configuration information for communication type. This register is
included in the read/write array error detection.
This register is readable and writable in DSI3 mode, SPI mode, and I2C mode. In PSI5
Programming Mode, the value of this register must not be changed or a U_OTP Memory
occurs.
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Table 85.ꢀCommunication type register (COMMTYPE)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$16
COMMTYPE
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
COMMTYPE[2:0]
0
Unprogrammed OTP
Value: FXLS90xxx
0
0
0
1
Programmed OTP
Value: FXLS93xxx
0
0
0
0
0
0
11.2.11.1 Communication type (COMMTYPE[2:0])
The communication type bits select the available protocols for the device as shown in
Table 86.
Table 86.ꢀCommunication type (COMMTYPE[2:0])
COMMTYPE
[2:0]
Available communication protocols
Arming function availability
BUS_I
undervoltage
detection
DSI3[1]
PSI5[2]
32-bit SPI[3]
I2C[4]
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X
X
X
X
Enabled based on ARM_CFG[2:0]
Enabled based on ARM_CFG[2:0]
Enabled based on ARM_CFG[2:0]
Disabled
Disabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Disabled
X
X
X
Enabled based on ARM_CFG[2:0]
Disabled
X
X
X
Disabled
Disabled
[1] See Section 12 "DSI3 protocol"
[2] See Section 13 "PSI5 protocol"
[3] See Section 14 "Standard 32-bit SPI protocol"
[4] See Section 15 "Inter-integrated circuit (I2C) interface"
When writing to this register, care must be taken to prevent from inadvertently disabling
the desired communication mode. Communication mode register value changes which
disable a protocol, including writes to OTP, will not take effect until a device reset to
prevent from disabling a necessary communication method. Table 87 describes how
communication mode register changes are handled.
Table 87.ꢀCOMMTYPEs and effect on device
Original
New
Device effect
COMMTYPE
COMMTYPE
0 (DSI3 / SPI)
1 (PSI5 / SPI) A protocol change does not occur until a device reset (assuming the OTP is
programmed).
0 (DSI3 / SPI) 2, 3, 4, 5 (SPI, A protocol change does not occur until a device reset (assuming the OTP is
DSI3 or PSI5) programmed).
0 (DSI3 / SPI)
6, 7 (I2C)
A protocol change does not occur until a device reset (assuming the OTP is
programmed).
1 (PSI5 / SPI)
5 (PSI5)
A protocol change does not occur until a device reset (assuming the OTP is
programmed).
2, 3, 4, 5 (SPI)
6, 7 (I2C)
Any
Any
No protocol change occurs.
No protocol change occurs.
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Notes:
• In PSI5 / SPI mode (COMMTYPE = 1), SPI transactions are ignored by the device until
PSI5 initialization 3 is complete. SPI Test Mode Entry is not restricted.
• In PSI5 / SPI mode (COMMTYPE = 1), only SPI read register transactions are
available.
• In DSI3 / SPI mode (COMMTYPE = 0) and PSI5 / SPI mode (COMMTYPE = 1),
registers accesses by protocol are completed in the order received. Care must be
taken to prevent from incorrect addressing of the F, UF0, and UF1 registers.
• In SPI only mode and in I2C only mode, the BUS_I undervoltage detection is disabled
to allow for 3.3 V system operation. the VBUF undervoltage detection replaces the
BUS_I undervoltage detection.
• If the COMMTYPE register is pre-programmed in OTP to a specific communication
type, the user must prevent writes to this register when writing the UF2 register to OTP.
If a pre-programmed COMMTYPE register is over-written and then written to OTP, the
UF2 CRC verification will fail.
11.2.12 Physical address register (PHYSADDR)
The physical address register is a user programmed OTP register which contains the
physical address of the slave for use in DSI3. This register is included in the read/write
array error detection. If the physical address stored in the OTP array is zero, the address
is assigned either during Discovery Mode or during Command and Response Mode.
If the physical address stored in the OTP array is non-zero, the device ignores Discovery
Mode and uses the programmed physical address for Command and Response Mode.
The physical address register value can be changed by a Command and Response
Mode register write command. However, if the UF2 region is locked, the value will always
be reset to the OTP array value after a reset.
In SPI mode, I2C mode and PSI5 mode, the PHYSADDR register is readable and
writable, but has no impact on device operation or performance.
Table 88.ꢀPhysical address register (PHYSADDR)
Location
Bit
Address Register
7
6
5
4
3
2
1
0
$18
PHYS
ADDR
0
0
0
0
PADDR[3:0]
Unprogrammed
OTP Value
0
0
0
0
0
0
0
0
11.2.13 Source identification registers (SOURCEID_x)
The source identification registers are user programmed read/write registers which
contain the source identification information used for DSI3 PDCM, PSI5 mode, and SPI
Mode. These registers are included in the read/write array error detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 89.ꢀSource identification registers (SOURCEID_x)
Location
Bit
Address
Register
SOURCEID_0
7
6
5
4
3
2
1
0
$1A
SID0_EN
PDCMFORMAT[2:0]
SOURCEID_0[3:0]
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Table 89.ꢀSource identification registers (SOURCEID_x)...continued
Location
Bit
Address
Register
7
0
1
6
0
1
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
Unprogrammed OTP Value
FXLS93xxx
Unprogrammed
Default PSI5 Mode
$1B
Unprogrammed OTP Value
$1C SOURCEID_2
SOURCEID_1
SID1_EN
RESERVED
RESERVED
RESERVED
SOURCEID_1[3:0]
0
0
0
0
0
0
0
0
SID2_EN
RESERVED
RESERVED
RESERVED
SOURCEID_2[3:0]
Unprogrammed OTP Value
FXLS93xxx
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unprogrammed
Default PSI5 Mode
$1D
SOURCEID_3
SID3_EN
0
RESERVED
0
RESERVED
0
RESERVED
0
SOURCEID_3[3:0]
Unprogrammed OTP Value
0
0
0
0
11.2.13.1 Data source enable bits (SIDx_EN)
The SIDx_EN bits enable the data source for the associated source identification as
described in Section 11.2.13.3.
11.2.13.2 PDCM format control bits (PDCMFORMAT[2:0])
In DSI3 mode, the PDCM format control bits set the PDCM field sizes as shown in
Table 90. See Section 12.4.2 for PDCM response format details.
Table 90.ꢀPDCM format control bits (PDCMFORMAT[2:0])
PDCMFORMAT[2:0]
Source ID field
size (Bits)
Keep alive
counter field
size (Bits)
Status field size
(Bits)
Data field size
(Bits)
Total
including CRC
(Bits)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
4
0
4
0
0
0
4
2
2
0
0
2
0
0
0
4
4
4
4
0
0
4
4
10
10
12
12
10
16
16
16
24
28
24
28
20
24
28
32
In PSI5 mode, the PDCM format control bits set the PSI5 response format as shown
in Table 91. See Section 13.3.2 for PSI5 response format details. Note: the data field
size applies to all modes except Programming Mode which has a fixed size of 10 bits.
The user must take care to prevent from combining incompatible data field sizes and
transmission times.
Table 91.ꢀPDCM format control bits
PDCMFORMAT[2:0]
Data field size (Bits)
0
1
x
x
x
x
10
16
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In SPI and I2C mode, the PDCMFORMAT bits are readable and writable, but have no
impact on device operation or performance.
11.2.13.3 Source identification (SOURCEID_x)
In SPI mode, the SOURCEID field in the SPI command is compared against the values
in the SOURCEID_x registers. If the SOURCEID field matches one of the values in the
SOURCEID_x registers and the SIDx_EN bit is set for that register, the sensor data
for that SOURCEID is transmitted as shown in Table 92. If more than one enabled
SOURCEID_x register value matches the SOURCEID field in the SPI command a SPI
sensor data request error response is transmitted. If no enabled SOURCEID_X register
value matches the SOURCEID field in the SPI command a SPI sensor data request error
response is transmitted.
Table 92.ꢀSPI source identification (SOURCEID_x)
Source ID
Source ID enable (SIDx_EN) Transmitted data
SOURCEID_0
0
1
0
1
0
1
0
1
SPI Error Response
CH0_SNSDATA0
SPI Error Response
CH0_SNSDATA1
SPI Error Response
CH1_SNSDATA0
SPI Error Response
CH1_SNSDATA1
SOURCEID_1
SOURCEID_2
SOURCEID_3
In DSI3 mode, if the SIDx_EN bit in the SOURCEID_x register is set, the associated
SOURCEID value is transmitted in the SOURCEID field of PDCM mode using the
associated transmission time shown in Table 93.
Table 93.ꢀDSI3 source identification (SOURCEID_x)
Source ID
Source ID enable Transmission time[1]
(SIDx_EN)
Transmitted data[2]
SOURCEID_0
0
1
0
1
0
1
0
1
NA
NA
PDCM_RSPST0
NA
CH0_SNSDATA0
NA
SOURCEID_1
SOURCEID_2
SOURCEID_3
PDCM_RSPST1
NA
CH0_SNSDATA1
NA
PDCM_RSPST2
NA
CH1_SNSDATA0
NA
PDCM_RSPST3
CH1_SNSDATA1
[1] See Section 11.2.18.1 "Periodic data collection mode response start time (PDCM_RSPSTx[12:0])"
[2] See Section 11.2.25.2 "Channel data type 0 selection bits (CHxDATATYPE0)" and See Section 11.2.25.3 "Channel data
type 1 selection bits (CHxDATATYPE1)"
In PSI5 mode, the SOURCEID_x register SIDx_EN bit values control data transmissions
as shown in Table 94. The SOURCEID_x bits have no effect in PSI5 mode.
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Table 94.ꢀPSI5 source identification (SOURCEID_x)
Source ID
Source
ID enable
(SIDx_EN)
Asynchronous mode
Synchronous mode
Daisy chain mode
Dual transmission mode
Transmission Transmission
Transmission
Transmitted
data[2]
Transmission
time
Transmitted
data
Transmission
Transmitted
data
time data
time[1]
time
SOURCEID_
0
0
1
tASYNC
CH0_SNSDATA0
NA
NA
See
CH0_SNSDATA0
PDCM_
RSPST0
CH1_
SNSDATA0,
Section 13.8
PDCM_RSPST0
CH0_SNSDATA0
CH0_SNSDATA0
See
Section 13.7
SOURCEID_
1
0
1
0
1
0
1
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
CH1_SNSDATA0
NA
NA
NA
NA
NA
NA
NA
PDCM_RSPST1
NA
CH0_SNSDATA1
NA
SOURCEID_
2
See
Section 13.8
PDCM_RSPST2
NA
CH1_SNSDATA0
NA
SOURCEID_
3
NA
PDCM_RSPST3
CH1_SNSDATA1
[1] See Section 11.2.18.1 "Periodic data collection mode response start time (PDCM_RSPSTx[12:0])"
[2] See Section 11.2.25.2 "Channel data type 0 selection bits (CHxDATATYPE0)" and Section 11.2.25.3 "Channel data type 1 selection bits
(CHxDATATYPE1)"
In I2C mode, the SOURCEID_x registers are readable and writable. See Section 15.6.3,
for details regarding the effect of the SIDx_EN bits.
11.2.14 Communication timing register (TIMING_CFG)
The communication timing configuration register is a user programmed read/write
register which contains user-specific con-figuration information for protocol timing. This
register is included in the read/write array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 95.ꢀCommunication timing register (TIMING_CFG)
Location
Address
$22
Bit
Register
7
6
5
4
3
2
1
0
TIMING_CFG
PDCM_PER[2:0]
OSCTRAIN_
SEL
CK_CAL_RST
CRM_PER[1:0]
CK_CAL_EN
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
11.2.14.1 Periodic data collection mode period (PDCM_PER[3:0])
The periodic data collection mode period selection bits set the data collection mode
period to be used by the DSI3, SPI, PSI5, or I2C master as shown in Table 96. This value
is only necessary for oscillator training and is only used if the CK_CAL_EN bit is set in
the TIMING_CFG register.
Table 96.ꢀPeriodic data collection mode period (PDCM_PER[3:0])
PDCM_PER[2] PDCM_PER[1] PDCM_PER[0]
Periodic data collection mode period
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
100 µs
125 µs
250 µs
333 µs
500 µs
800 µs
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Table 96.ꢀPeriodic data collection mode period (PDCM_PER[3:0])...continued
PDCM_PER[2] PDCM_PER[1] PDCM_PER[0]
Periodic data collection mode period
1
1
1
1
0
1
1000 µs
2000 µs
In DSI3 mode, PDCM, and BDM commands are decoded and responded to regardless
of the value of this register as long as the general PDCM timing parameters specified in
Section 10.11 are met. See Section 11.5.1 for details regarding oscillator training.
In PSI5 synchronous mode, sync pulses are decoded and responded to regardless of the
value of this register as long as the general timing parameters specified in Section 10.12
are met. See Section 11.5.1 for details regarding oscillator training.
In PSI5 asynchronous mode, oscillator training is not applicable.
In PSI5 Programming Mode, oscillator training is not applicable.
In PSI5 Daisy Chain command phase, oscillator training is not applicable.
In SPI mode, sensor data requests are decoded and responded to regardless of the
value of this register as long as the general timing parameters specified in Section 10.13
are met. See Section 11.5.1 for details regarding oscillator training.
In I2C mode, sensor data register reads are decoded and responded to regardless of the
value of this register as long as the general timing parameters specified in Section 10.14
are met. See Section 11.5.1 for details regarding oscillator training.
11.2.14.2 Oscillator training protocol selection bit (OSCTRAIN_SEL)
The oscillator training selection bit selects the protocol to use for oscillator training for the
COMMTYPE values that enable multiple protocols as shown in Table 97.
Table 97.ꢀOscillator training protocol selection bit (OSCTRAIN_SEL)
COMMTYPE
OSCTRAIN_SEL
Protocol to use for oscillator training
0
0
1
0
1
x
x
x
x
x
x
DSI3
SPI
1
PSI5
SPI
2
3
4
5
6
7
SPI
DSI3
SPI
PSI5
I2C
I2C
11.2.14.3 Clock calibration value reset (CK_CAL_RST)
The clock calibration reset bit controls the state of the oscillator training when the
CK_CAL_EN bit is cleared as described in the table in Section 11.2.14.5. See
Section 11.5.1 for details regarding oscillator training.
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11.2.14.4 Command and response mode period (CRM_PER[1:0])
In DSI3 mode, the command and response mode period bits set the period for command
and response mode commands in increments of the periodic data collection mode period
(PDCM_PER). This value is only necessary for DSI3 oscillator training and is only used
if the CK_CAL_EN bit is set in the TIMING_CFG register. command and response mode
commands will be decoded and responded to regardless of the value of this register
as long as the general command and response mode timing parameters specified in
Section 10.11 are met. See Section 11.5.1 for details regarding oscillator training.
In SPI and I2C mode, the CRM_PER[1:0] bits are readable and writable, but have no
impact on device operation or performance.
In PSI5 mode, the CRM_PER[1:0] bits are readable and writable, but have no impact on
device operation or performance.
Table 98.ꢀCommand and response mode period (CRM_PER[1:0])
CRM_PER[1]
CRM_PER[0]
Command and response mode period
(Multiples of the periodic data collection mode period)
0
0
1
1
0
1
0
1
1
2
4
8
11.2.14.5 Clock calibration enable (CK_CAL_EN)
The clock calibration enable bit enables oscillator training over the DSI3, PSI5, SPI, or
I2C communication interface. See Section 11.5.1 for details regarding oscillator training.
Table 99.ꢀClock calibration enable (CK_CAL_EN)
CK_CAL_EN CK_CAL_RST Oscillator training
0
0
1
0
1
x
The oscillator value is maintained at the last trained value prior
to clearing the CK_CAL_RST bit.
The oscillator value is reset to the untrained value with a
tolerance specified in Section 10.20.
Oscillator is trained as specified in Section 11.5.1
11.2.15 Chip time and bit time register (CHIPTIME)
The chip time and bit time register is a user programmed read/write register which
contains user-specific configuration information. This register is included in the read/write
array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 100.ꢀChip time and bit time register (CHIPTIME)
Location
Register
CHIPTIME
Bit
Address
7
6
5
4
3
2
1
0
$23
ST_RPT[1:0]
PSI5_
SS_EN
CHIPTIME[3:0]
ERRLATCH
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
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Table 100.ꢀChip time and bit time register (CHIPTIME)...continued
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
FXLS93xxx
0
0
0
0
1
0
0
0
Unprogrammed
Default PSI5 Mode
11.2.15.1 PSI5 self-test repetition bits (ST_RPT[1:0])
In PSI5 mode, the PSI5 self-test repetition bits set the maximum number of PSI5 self-test
repetitions that the device will run before setting the ST_ERROR bit. See Section 6.6.2.5
for details regarding the PSI5 startup self-test.
Table 101.ꢀPSI5 self-test repetition bits (ST_RPT[1:0])
ST_RPT[1]
ST_RPT[0]
Maximum PSI5 self-test repetitions
0
0
1
1
0
1
0
1
8
1
4
2
11.2.15.2 PSI5 error latching enable bit (PSI5_ERRLATCH)
In PSI5 mode, the PSI5 error latching enable bit allows for users to disable the automatic
error clearing mechanism for internal faults. When this bit is set, internal errors are
latched until reset. See Section 13.9.4 and Section 13.9.5 for details regarding internal
error handling.
Table 102.ꢀPSI5 error latching enable bit (PSI5_ERRLATCH)
PSI5_
PSI5 error handling
ERRLATCH
0
1
Error handling is as specified in Section 11.2.2 and Section 13.9.4
Automatic error clearing is disabled and internal errors are latched until reset as
specified in Section 13.9.5
11.2.15.3 Simultaneous sampling enable (SS_EN)
In DSI3 mode, the simultaneous sampling enable bit selects between one of two data
latency methods. See Section 12.4.7 for details regarding sample timing.
Table 103.ꢀDSI3 simultaneous sampling enable (SS_EN)
SS_EN
Data latency
0
Synchronous Sampling Mode: Latency relative to transmission start time (PDCM_
RSPST)
1
Simultaneous Sampling Mode: Latency relative to the start of the Periodic Data
Collection Mode command (falling edge)
In PSI5 mode, the simultaneous sampling enable bit selects between one of two data
latency methods to accommodate synchronized sampling or simultaneous sampling.
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Table 104.ꢀPSI5 simultaneous sampling enable (SS_EN)
SS_EN Data latency
0
1
Synchronous Sampling Mode (Latency relative to Time Slot)
Simultaneous Sampling Mode (Latency relative to sync pulse)
In SPI mode, the simultaneous sampling enable bit selects between one of two data
latency methods.
Table 105.ꢀSPI simultaneous sampling enable (SS_EN)
SS_EN
Data latency
0
Synchronous sampling mode: The data for all sources is latent relative to the
falling edge of slave select for the response to the Sensor Data Request for the
corresponding SOURCEID.
1
Simultaneous sampling mode: The data for all sources is latent relative to the falling
edge of slave select for the response to the Sensor Data Request for SOURCEID_0.
If SOURCEID_0 is disabled, then the data for all SOURCEIDs is latent relative to the
falling edge of slave select for the response to the Sensor Data Request for lowest
enabled SOURCEID register address.
Note: If multiple SOURCEIDs are enabled, sensor data for the higher SOURCEID
register addresses only changes on a sensor data request for the lowest enabled
SOURCEID register address. If continuous sensor data requests occur without
sensor data requests for the lowest SOURCEID register address, sensor data
will not be updated. Care must be taken by the user to ensure proper data
transmissions.
In I2C mode, the simultaneous sampling enable bit is readable and writable but has no
impact on device operation or performance.
11.2.15.4 Chip time (CHIPTIME)
In DSI3 mode, the CHIPTIME bits set the chip time for Periodic Data Collection Mode
as described in Table 106. The chip time for Command and Response Mode and
Background Diagnostic Mode is always set to 5 µs with slew control enabled.
In PSI5 mode, the CHIPTIME bits set the bit time for the PSI5 response data as
described in Table 106.
Table 106.ꢀChip time (CHIPTIME)
CHIPTIME[3]
CHIPTIME[2]
CHIPTIME[1]
CHIPTIME[0]
PSI5
Baud rate
189 kHz
189 kHz
189 kHz
189 kHz
189 kHz
189 kHz
189 kHz
189 kHz
125 kHz
125 kHz
125 kHz
125 kHz
125 kHz
DSI3
Period time
5.3 µs
5.3 µs
5.3 µs
5.3 µs
5.3 µs
5.3 µs
5.3 µs
5.3 µs
8.0 µs
8.0 µs
8.0 µs
8.0 µs
8.0 µs
Slew control
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Chip time
1.0 µs
2.0 µs
2.5 µs
2.6 µs
2.6 µs
2.7 µs
2.8 µs
2.9 µs
3.0 µs
3.1 µs
3.2 µs
3.3 µs
3.5 µs
Chip rate
1000 kHz
500.0 kHz
400.0 kHz
384.6 kHz
384.6 kHz
370.3 kHz
357.1 kHz
344.8 kHz
333.3 kHz
322.6 kHz
312.5 kHz
303.0 kHz
294.1 kHz
Slew control
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
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Table 106.ꢀChip time (CHIPTIME)...continued
CHIPTIME[3]
CHIPTIME[2]
CHIPTIME[1]
CHIPTIME[0]
PSI5
DSI3
Period time
8.0 µs
Baud rate
125 kHz
125 kHz
125 kHz
Slew control
Enabled
Chip time
4.0 µs
Chip rate
250.0 kHz
222.2 kHz
200.0 kHz
Slew control
Enabled
1
1
1
1
1
1
0
1
1
1
0
1
8.0 µs
Enabled
4.5 µs
Enabled
8.0 µs
Enabled
5.0 µs
Enabled
In SPI and I2C mode, the CHIPTIME bits are readable and writable but have no impact
on device operation or performance.
11.2.16 Timing configuration #2 register (TIMING_CFG2)
The timing configuration #2 register is a user programmed read/write register which
contains user-specific timing configuration information. This register is included in the
read/write array error detection. See Section 12.4 for details regarding Background
Diagnostic Mode.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 107.ꢀTiming configuration #2 register (TIMING_CFG2)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$24
TIMING_CFG2
PSI5_
OSCTRAIN_ERRCNT[2:0]
CAPTEST_OFF
RESERVED
BDM_
BDM_EN
INIT2_D19
FRAGSIZE
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
11.2.16.1 PSI5 initialization phase 2 D19 and D20 change bit (PSI5_INIT2_D19)
The PSI5 initialization phase 2 D19 and D20 change bit provides the option to change
the data transmitted in PSI5 Initialization Phase 2 nibbles D19 and D20 as shown in
Table 108.
Table 108.ꢀPSI5 initialization phase 2 D19 and D20 change bit (PSI5_INIT2_D19)
PSI5_INIT2_
D19
Initialization phase 2 data
Reference
D19
D20
0
1
SN4[7:4]
SN4[3:0]
Section 11.2.42, Section 13.4.2.1
USERDATA_6[7:4] USERDATA_E[7:4] Section 11.2.45.1, Section 13.4.2.1
In DSI3 mode, SPI mode, and I2C mode, the PSI5_INIT2_D19 bit is readable and
writable, but has no impact on device operation or performance.
11.2.16.2 Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])
The oscillator training error counter bits use the number of 4 ms periods used to
determine the error detection time for oscillator training as shown in Table 109. See
Section 11.5.2 for details regarding oscillator training error detection.
Table 109.ꢀOscillator training error counter (OSCTRAIN_ERRCNT[2:0])
OSCTRAIN_ERRCNT[2:0]
4 ms periods counted
before the OSCTRAIN
error flag is set
Minimum time for
error detection
(ms)
0
0
0
64
256
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Table 109.ꢀOscillator training error counter (OSCTRAIN_ERRCNT[2:0])...continued
OSCTRAIN_ERRCNT[2:0]
4 ms periods counted
before the OSCTRAIN
error flag is set
Minimum time for
error detection
(ms)
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
2
4
8
4
16
8
32
16
32
64
64
128
256
11.2.16.3 Capacitor test disable bit (CAPTEST_OFF)
The capacitor test disable bit provides the option to disable the VBUF capacitor test in
DSI3 mode as shown in Table 110.
Table 110.ꢀCapacitor test disable bit (CAPTEST_OFF)
CAPTEST_OFF Capacitor test status
0
1
Capacitor test is operational as specified in Section 11.4.1
Capacitor test will not run
If a capacitor error is present, the VBUFUV_ERR bit is set in the DEVSTAT1 register as
specified in Section 11.4.1. The presence of the VBUFUV_ERR will prevent the user from
writing to the TIMING_CFG2 register to disable the capacitor test unless and until the
capacitor error recovers.
In SPI and I2C mode, the CAPTEST_OFF bit is readable and writable, but has no impact
on device operation or performance.
In PSI5 mode, the CAPTEST_OFF bit is readable and writable, but has no impact on
device operation or performance.
11.2.16.4 Background diagnostic mode fragment size (BDM_FRAGSIZE)
The background diagnostic mode fragment size bit sets the number of background
diagnostic command bits and response chips to be sent per Periodic Data Collection
Mode sampling period.
Table 111.ꢀBackground diagnostic mode fragment size (BDM_FRAGSIZE)
BDM_
FRAGSIZE
BDM command fragment size
(Bits)
BDM response fragment size
(Chips)
0
1
2
4
3
6
In SPI and I2C mode, the BDM_FRAGSIZE bit is readable and writable, but has no
impact on device operation or performance.
In PSI5 mode, the BDM_FRAGSIZE bit is readable and writable, but has no impact on
device operation or performance.
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11.2.16.5 Background diagnostic mode enable (BDM_EN)
The background diagnostic mode enable bit enables background diagnostic mode as
described in Table 112. See Section 12.4 for details regarding background diagnostic
mode.
Table 112.ꢀBackground diagnostic mode enable (BDM_EN)
BDM_EN
Background diagnostic mode
0
1
Disabled
Enabled
In SPI and I2C mode, the BDM_EN bit is readable and writable, but has no impact on
device operation or performance.
In PSI5 mode, the BDM_EN bit is readable and writable, but has no impact on device
operation or performance.
11.2.17 PSI5 configuration register (PSI5_CFG)
The PSI5 configuration register is a user programmable OTP register that contains PSI5
specific configuration information. This register is included in the read/write array error
detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
programming mode.
Table 113.ꢀPSI5 configuration register (PSI5_CFG)
Location
Register
PSI5_CFG
Bit
Address
7
6
5
4
3
2
1
0
$25
SYNC_PD
DAISY_CHAIN
PSI5_ILOW
DUALTRANS
EMSG_EXT
P_CRC
INIT2_EXT
ASYNC
Unprogrammed OTP Value
FXLS93xxx
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Unprogrammed
Default PSI5 Mode
11.2.17.1 Sync pulse pull-down enable bit (SYNC_PD)
In PSI5 mode, the sync pulse pull-down enable bit selects if the Sync pulse pull-down
is enabled once a sync pulse is detected. See Section 11.2.18.1 for more information
regarding the sync pulse pulldown.
Table 114.ꢀSync pulse pull-down enable bit (SYNC_PD)
SYNC_PD
Sync pulse pull-down
Disabled
0
1
Enabled for all PSI5 operating modes
In DSI3 mode, the SYNC_PD bit is readable and writable, but has no impact on device
operation or performance.
In SPI and I2C mode, the SYNC_PD bit is readable and writable, but has no impact on
device operation or performance.
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11.2.17.2 PSI5 daisy chain selection bit (DAISY_CHAIN)
In PSI5 mode, the transmission mode selection bits select the PSI5 transmission mode
as shown in Table 115.
Table 115.ꢀPSI5 daisy chain selection bit (DAISY_CHAIN)
DAISY_ Operating mode
CHAIN
Response (PDCM_ Reference
RSTST0)
0
Normal Mode (Asynchronous or Parallel,
SNSDATA0
Section 13.5
Synchronous)
1
Daisy Chain Mode
SNSDATA0
Section 13.8
In DSI3 mode, the DAISY_CHAIN bit is readable and writable, but has no impact on
device operation or performance.
In SPI and I2C mode, the DAISY_CHAIN bit is readable and writable, but has no impact
on device operation or performance.
11.2.17.3 PSI5 low response current selection bit (PSI5_ILOW)
In PSI5 mode, the PSI5 low response current selection bit selects the low PSI5 response
current specified in Section 10.4 as shown in Table 116.
Table 116.ꢀPSI5 low response current selection bit (PSI5_ILOW)
PSI5_ILOW
PSI5 response current
Normal Response Current
Low Response Current
0
1
In DSI3 mode, the PSI5_ILOW bit is readable and writable, but has no impact on device
operation or performance.
In SPI and I2C mode, the PSI5_ILOW bit is readable and writable, but has no impact on
device operation or performance.
11.2.17.4 Dual transmission mode (DUALTRANS)
In PSI5 mode, the dual transmission mode bit enables dual data transmission as
described in Section 13.7 only if the DAI-SY_CHAIN bit is not set and the ASYNC bit is
not set.
Table 117.ꢀDual transmission mode (DUALTRANS)
DUALT
RANS
SID3_EN SID2_EN SID1_EN SID0_EN
Operating mode
Response
Response
Response
Response
Refer
ence
PDCM_RSPST0 PDCM_RSPST1 PDCM_RSPST2 PDCM_RSPST3
0
1
As specified in
Normal Mode
CH0_
SNSDATA0
CH0_
SNSDATA1
CH1_
SNSDATA0
CH1_
SNSDATA1
Section 13.5,
Section 13.8
Section 11.2.13.3
Asynchronous or Synchronous,
Parallel, Daisy Chain
x
x
x
x
0
0
0
1
No Transmission
None
None
None
None
None
None
None
Section 13.7
Dual Data Transmission
Mode, Single Transmission
CONCATENATE
(CH1_SNSDA-
TA0, CH0_
SNS-DATA0)
x
x
x
x
1
1
0
1
Dual Data Transmission
Mode, Single Transmission
None
CONCATENATE
(CH1_SNSDA-
TA1, CH0_
None
None
None
None
SNS-DATA1)
Dual Data Transmission
CONCATENATE CONCATENATE
Mode, Double Transmission
(CH1_SNSDA-
TA0, CH0_
(CH1_SNSDA-
TA1, CH0_
SNS-DATA0)
SNS-DATA1)
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In DSI3 mode, the DUALTRANS mode is readable and writable, but has no impact on
device operation or performance.
In SPI and I2C mode, the DUALTRANS bits are readable and writable, but has no impact
on device operation or performance.
11.2.17.5 Error message information extension bit (EMSG_EXT)
In PSI5 mode, the error message information extension bit enables or disables additional
PSI5 error message information as shown in Table 118.
Table 118.ꢀError message information extension bit (EMSG_EXT)
EMSG_EXT Description
0
1
All internal Errors map to 0x1F4 (See Section 13.3.4)
Additional PSI5 reserved codes are used for internal error distinction (See
Section 13.3.4)
In DSI3 mode, the EMSG_EXT bit is readable and writable, but has no impact on device
operation or performance.
In SPI and I2C mode, the EMSG_EXT bit is readable and writable, but has no impact on
device operation or performance.
11.2.17.6 PSI5 response message error detection selection bit (P_CRC)
In PSI5 mode, the response message error detection selection bit selects either
even parity, or a 3-bit CRC for error detection of the PSI5 response message. See
Section 11.2.18.1 for details regarding response message error detection.
Table 119.ꢀPSI5 response message error detection selection bit (P_CRC)
P_CRC
Parity or CRC
Parity
0
1
CRC
In DSI3 mode, the P_CRC bit is readable and writable, but has no impact on device
operation or performance.
In SPI and I2C mode, the P_CRC bit is readable and writable, but has no impact on
device operation or performance.
11.2.17.7 Initialization phase 2 data extension bit (INIT2_EXT)
In PSI5 mode, the initialization phase 2 data extension bit enables or disables data
transmission in data fields D33 through D48 of PSI5 initialization phase 2 as shown in
Table 120.
Table 120.ꢀInitialization phase 2 data extension bit (INIT2_EXT)
INIT2_EXT Description
0
1
D33 through D48 are not transmitted
D33 through D48 are transmitted as defined in Section 13.4.2.1
In DSI3 mode, the INIT2_EXT bit is readable and writable, but has no impact on device
operation or performance.
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In SPI and I2C mode, the INIT2_EXT bit is readable and writable, but has no impact on
device operation or performance.
11.2.17.8 Asynchronous mode bit (ASYNC)
In PSI5 mode, the asynchronous mode bit enables asynchronous data transmission as
described in Section 11.2.18.1 only if the DAISY_CHAIN bit is not set.
In DSI3 mode, the ASYNC bit is readable and writable, but has no impact on device
operation or performance.
In SPI and I2C mode, the ASYNC bit is readable and writable, but has no impact on
device operation or performance.
11.2.18 DSI3 and PSI5 start time registers (PDCM_RSPSTx_x)
The DSI3 and PSI5 start time registers are user programmed read/write registers which
contain user-specific configuration information for DSI3 periodic data collection mode
and PSI5 synchronous mode. These registers are included in the read/write array error
detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 121.ꢀDSI3 and PSI5 start time registers (PDCM_RSPSTx_x)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$26
PDCM_
PDCM_RSPST0[7:0]
RSPST0_L
Unprogrammed OTP Value
FXLS93xxx
0
0
0
0
0
1
0
0
0
1
0
1
0
1
0
1
Unprogrammed
Default PSI5 Mode
$27
PDCM_
RSPST0_H
BRC_RSP0[1:0]
BRC_RSP1[1:0]
BRC_RSP2[1:0]
RESERVED
PDCM_RSPST0[12:8]
Unprogrammed OTP Value
FXLS93xxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unprogrammed
Default PSI5 Mode
$28
PDCM_
RSPST1_L
PDCM_RSPST1[7:0]
Unprogrammed OTP Value
FXLS93xxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unprogrammed
Default PSI5 Mode
$29
PDCM_
RSPST1_H
RESERVED
PDCM_RSPST1[12:8]
Unprogrammed OTP Value
FXLS93xxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unprogrammed
Default PSI5 Mode
$2A
PDCM_
RSPST2_L
PDCM_RSPST2[7:0]
Unprogrammed OTP Value
FXLS93xxx
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
Unprogrammed
Default PSI5 Mode
$2B
PDCM_
RSPST2_H
RESERVED
0
PDCM_RSPST2[12:8]
0
Unprogrammed OTP Value
0
0
0
0
0
0
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Table 121.ꢀDSI3 and PSI5 start time registers (PDCM_RSPSTx_x)...continued
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
FXLS93xxx
0
0
0
0
0
0
0
0
Unprogrammed
Default PSI5 Mode
$2C
PDCM_
RSPST3_L
PDCM_RSPST3[7:0]
Unprogrammed OTP Value
FXLS93xxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unprogrammed
Default PSI5 Mode
$2D
PDCM_
BRC_RSP3[1:0]
RESERVED
PDCM_RSPST3[12:8]
RSPST3_H
Unprogrammed OTP Value
FXLS93xxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Unprogrammed
Default PSI5 Mode
11.2.18.1 Periodic data collection mode response start time (PDCM_RSPSTx[12:0])
The periodic data collection mode response start time registers set the DSI3 periodic
data collection mode or PSI5 synchronous mode response start time for the associated
data and SOURCEID. The value is stored in 1.0 µs increments.
Table 122.ꢀPeriodic data collection mode response start time
(PDCM_RSPSTx[12:0])
PDCM_RSPSTx[12:0]
0
Periodic data collection mode response start time
See Table 123
0 < PDCM_RSPSTx[12:0] < 20
20 < PDCM_RSPSTx[12:0]
20.0 µs
PDCM response start = PDCM_RSPST x 1.0 µs
Table 123 shows the relationship of the SOURCEID, the transmitted data, the response
start times, and the default states for each set of registers in DSI3 periodic data collection
mode. Care must be taken to prevent from programming response start times which
cause data contention in the system.
Table 123.ꢀSynchronous mode: Source ID response start time
SOURCEID register
SOURCEID_0
SOURCEID_1
SOURCEID_2
SOURCEID_3
Transmitted data
CH0_SNSDATA0
CH0_SNSDATA1
CH1_SNSDATA0
CH1_SNSDATA1
Start time registers
PDCM_RSPST0[12:0]
PDCM_RSPST1[12:0]
PDCM_RSPST2[12:0]
PDCM_RSPST3[12:0]
Default start (PDCM_RSPSTx[12:0] = 0x00)
Transmit Data with a start time of 20 µs
Transmit Data with a start time of 20 µs
Transmit Data with a start time of 20 µs
Transmit Data with a start time of 20 µs
Table 124 shows the PSI5 data transmission start times based on the values in the
PDCM_RSPSTx registers and the value of the ASYNC bit. Care must be taken to
prevent from programming time slots which violate the PSI5 Version 1.3 specification, or
time slots which will cause data contention.
Table 124.ꢀAsynchronous mode: Source ID response start time
ASYNC bit
SOURCEID
register
Transmitted data
Time slot
start time
Default start (PDCM_
RSPSTx[12:0] = 0x00)
1
SOURCEID_0
CH0_SNSDATA0
Asynchronous
Mode
tASYNC
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Table 124.ꢀAsynchronous mode: Source ID response start time...continued
ASYNC bit
SOURCEID
register
Transmitted data
CH0_SNSDATA0
CH0_SNSDATA1
CH1_SNSDATA0
CH1_SNSDATA1
Time slot
start time
Default start (PDCM_
RSPSTx[12:0] = 0x00)
0
SOURCEID_0
SOURCEID_1
SOURCEID_2
SOURCEID_3
PDCM_
RSPST0[12:0]
Transmit Data with a start time of 20 µs
Transmit Data with a start time of 20 µs
Transmit Data with a start time of 20 µs
Transmit Data with a start time of 20 µs
PDCM_
RSPST1[12:0]
PDCM_
RSPST2[12:0]
PDCM_
RSPST3[12:0]
In SPI and I2C mode, the PDCM_RSPSTx registers are readable and writable, but have
no impact on device operation or performance.
11.2.18.2 Broadcast read command type selection bits (BRC_RSP[1:0])
The broadcast read command type selection bits select the broadcast read command
types that the device responds to for each Source ID as shown in Table 125:
Table 125.ꢀBroadcast read command type selection bits (BRC_RSP[1:0])
BRC_RSP[1]
BRC_RSP[0]
Response
0
0
1
1
0
1
0
1
Respond to all Broadcast Read Commands
Respond to Broadcast Read Command 0 only
Respond to Broadcast Read Command 1 only
Respond to all Broadcast Read Commands
If a device is programmed to respond only to BRC0 or BRC1 commands, it will
synchronize to alternate responses when BDM commands are received.
• If the last command prior to a BDM command is a BRC0, a device programmed to
respond only to BRC0 commands will not respond to the first BDM command and will
then respond to every other BDM command until the next BRC command is received.
• If the last command prior to a BDM command is a BRC0, a device programmed to
respond only to BRC1 commands will respond to the first BDM command, and will then
response to every other BDM command until the next BRC command is received.
• If the last command prior to a BDM command is a BRC1, a device programmed to
respond only to BRC0 commands will respond to the first BDM command, and will then
response to every other BDM command until the next BRC command is received.
• If the last command prior to a BDM command is a BRC1, a device programmed to
respond only to BRC1 commands will not respond to the first BDM command and will
then respond to every other BDM command until the next BRC command is received.
In PSI5 mode, the BRC_RSP[1:0] bits are readable and writable, but have no impact on
device operation or performance.
In SPI and I2C mode, the BRC_RSP[1:0] bits are readable and writable, but have no
impact on device operation or performance.
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11.2.19 DSI3 and PSI5 command blocking time registers (PDCM_CMD_B_x)
The DSI3 and PSI5 command blocking registers are user programmed read/write
registers which contain user-specific con-figuration information for DSI3 mode and PSI5
mode. These registers are included in the read/write array error detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
programming mode.
Table 126.ꢀDSI3 and PSI5 command blocking time registers (PDCM_CMD_B_x)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$38
PDCM_
PDCM_CMD_B[7:0]
CMD_B_L
$39
PDCM_
CMD_B_H
RESERVED
0
RESERVED
0
RESERVED
0
PDCM_CMD_B[12:8]
0
Unprogrammed OTP Value
0
0
0
0
In DSI3 mode, the DSI3 periodic data collection mode command blocking time bits
set the periodic data collection mode command blocking time in 1.0 µs increments,
with zero as the default value of 450 µs. For proper communication, the command
blocking time must exceed the completion of the last source response transmission. See
Section 12.1.1 for details regarding the command receiver and command blocking.
Care must be taken to prevent from programming command blocking times which
prevent proper command decoding in the system and to ensure proper sampling of the
VHIGH voltage. As shown in Section 12.1.1, Figure 63, the VHIGH voltage is initially
captured at the end of the command blocking time and then filtered. The user must
ensure that the command blocking end time is set for a time when no command or
response transmissions are occurring to provide the most stable BUS_I voltage.
Table 127.ꢀDSI3 mode: Command blocking time bits
PDCM_CMD_B[12:0] Sync pulse blocking time
0
450 µs
Non-Zero
Sync Pulse Blocking Time = PDCM_CMD_B x 1 µs
In PSI5 mode, the command blocking time bits set the PSI5 sync pulse blocking time in
1.0 µs increments, with zero as the default value of 450 µs. See Section 13.2.1 for details
regarding the PSI5 sync pulse receiver and command blocking.
Care must be taken to prevent from programming command blocking times which
prevent proper sync pulse decoding in the system and to ensure proper sampling of the
PSI5 voltage.
Table 128.ꢀPSI5 mode: Command blocking time bits
PDCM_CMD_B[12:0] Sync pulse blocking time
0, 1, 2, 3, 4, 5, 6, 7, 8, 9 450 µs
10 - 8191
Sync Pulse Blocking Time = PDCM_CMD_B x 1 µs
In SPI and I2C mode, the PDCM_CMD_B bits are readable and writable, but have no
impact on device operation or performance.
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11.2.20 SPI configuration control register
In SPI mode, the SPI configuration control register is a user programmed read/write
register which contains the SPI protocol configuration information. This register is
included in the read/write array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
programming mode.
Table 129.ꢀSPI configuration control register
Location
Register
SPI_CFG
Bit
Address
7
6
DATASIZE
0
5
4
3
2
1
0
$3D
SPI_STATUS
0
SPI_CRC_LEN[1:0]
SPICRCSEED[3:0]
Unprogrammed OTP Value
0
0
0
0
0
0
11.2.20.1 SPI status reporting selection bit (SPI_STATUS)
The SPI status reporting bit controls the reporting of the SPI basic status as shown in
Table 130. See Section 14.5.
Table 130.ꢀSPI status reporting selection bit (SPI_STATUS)
SPI_STATUS
SPI basic status reporting
0
1
As documented in Section 14.5.1
As documented in Section 14.5.2
In DSI3 mode, the SPI_STATUS bit is readable and writable, but has no impact on device
operation or performance.
In PSI5 mode, the SPI_STATUS bit is readable and writable, but has no impact on device
operation or performance.
In I2C mode, the SPI_STATUS bit is readable and writable, but has no impact on device
operation or performance.
11.2.20.2 SPI data field size bit (DATASIZE)
The SPI data field size bit controls the size of the SPI data field as shown in Table 131.
See Section 11.6.4.9.
Table 131.ꢀSPI data field size bit (DATASIZE)
DATASIZE
SPI data field size
12-bits
0
1
16-bits
In DSI3 mode, the DATASIZE bit is readable and writable, but has no impact on device
operation or performance.
In PSI5 mode, the DATASIZE bit is readable and writable, but has no impact on device
operation or performance.
In I2C mode, the DATASIZE bit is readable and writable, but has no impact on device
operation or performance.
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11.2.20.3 SPI CRC length and seed bits (SPI_CRC_LEN[1:0], SPICRCSEED[3:0])
The SPI_CRC_LEN[1:0] bits select the CRC length for SPI mode as shown in Table 132.
The SPI CRC seed bits contain the seed used for the SPI Mode. The default SPI CRC is
an 8-bit. When the SPI_CRC_LEN[1:0] bits are set to a non-zero value using a register
write command, the SPI CRC changes as defined in the table. The new polynomial value
is enabled for both MISO and MOSI on the next SPI mode command.
The default seed (SPICRCSEED[3:0] = 0x0) is 0xFF for an 8-bit CRC. When the value
is changed to a non-zero value using a register write command, the SPI CRC seed
changes to the value programmed as shown in the table. The new seed value is enabled
for both MISO and MOSI on the next SPI mode command.
Table 132.ꢀSPI CRC length and seed bits (SPI_CRC_LEN[1:0], SPICRCSEED[3:0])
SPI_CRC_
LEN[1:0]
SPICR
CSEED
CRC polynomial
CRC seed
0
0
0
x8 + x5 + x3 + x2 + x + 1
1111, 1111
Non-Zero
1111,
SPICRCSEED[3:0]
0
1
1
1
0
1
0
x4 + 1
1010
SPICRCSEED[3:0]
111
Non-Zero
0
x3 + x + 1
x3 + x + 1
Non-Zero
0
SPICRCSEED[2:0]
111
Non-Zero
SPICRCSEED[2:0]
In PSI5 mode, the SPI CRC bits are readable and writable, but have no impact on device
operation or performance.
In DSI3 mode, the SPI CRC bits are readable and writable, but have no impact on device
operation or performance.
In I2C mode, the SPI CRC bits are readable and writable, but have no impact on device
operation or performance.
11.2.21 Who Am I register
The Who Am I register is a user programmed read/write register which contains the
unique product identifier for I2C mode. The register is readable in all modes. This register
is included in the read/write array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 133.ꢀWho Am I register
Location
Bit
Address Register
7
6
5
4
3
2
1
0
$3E
WHO_
AM_I
WHO_AM_I[7:0]
Unprogrammed
OTP Value
0
0
0
0
0
0
0
0
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Table 133.ꢀWho Am I register...continued
Location
Bit
Address Register
7
6
5
4
3
2
1
0
Unprogrammed
Read Value
1
1
0
0
0
1
0
0
The default register value is 0x00. If the register value is 0x00, a value of 0xC4 is
transmitted in response to a read command. For all other register values, the actual
register value is transmitted in response to a read command.
Table 134.ꢀWHO_AM_I bits
WHO_AM_I Register Value (HEX)
0X00
Response to a register read command
0xC4
0X01 Through 0xFF
Actual register value
11.2.22 I2C slave address register
The I2C slave address register is a user programmed read/write register which contains
the unique I2C slave address. The register is readable in all modes. This register is
included in the read/write array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 135.ꢀI2C slave address register
Location
Register
I2C_ADDRESS
Bit
Address
7
6
5
4
3
2
1
0
$3F
I2C_ADDRESS[7:0]
Unprogrammed OTP Value
Unprogrammed Read Value
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
The default register value is 0x00. If the register value is 0x00, the I2C slave address is
0x60 and a value of 0x60 is transmitted in response to a read command. For all other
register values, the I2C slave address is the lower 7 bits of the actual register value and
the actual register value is transmitted in response to a read command.
Table 136.ꢀI2C_ADDRESS bits
I2C_ADDRESS
register value (HEX)
Response to a register
read command
I2C slave address
0x00, 0x80
0x60
0x60
0x01 Through 0x7F,
0x81 Through 0xFF
Actual Register Value
I2C_ADDRESS[6:0]
11.2.23 Channel 0 and Channel 1 user configuration #1 registers (CH0_CFG_U1,
CH1_CFG_U1)
The Channel 0 and Channel 1 user configuration #1 registers are user programmable
read/write registers which contain channel-specific configuration information. These
registers are included in the read/write array error detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
programming mode.
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Table 137.ꢀChannel 0 and Channel 1 user configuration #1 registers (CH0_CFG_U1, CH1_CFG_U1)
Location
Bit
Address
$40
Register
7
6
5
4
3
2
1
0
CH0_CFG_U1
CH1_CFG_U1
LPF[3:0]
LPF[3:0]
SAMPLERATE[1:0]
SAMPLERATE[1:0]
USER_SNS_SHIFT[1:0]
USER_SNS_SHIFT[1:0]
$48
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
11.2.23.1 Low-pass filter and sample rate selection bits (LPF[3:0], SAMPLERATE[1:0])
The low-pass filter selection bits and sample rate bits select the low-pass filter for the
associated channel. See Section 11.6.4.4 for details regarding the low-pass filter.
Table 138.ꢀLow-pass filter and sample rate selection bits (LPF[3:0], SAMPLERATE[1:0])
LPF[3]
LPF[2]
LPF[1]
LPF[0]
Low-pass filter type
SAMPLERATE = 10
32 µs
SAMPLERATE = 00, 01
16 µs
SAMPLERATE = 11
64 µs
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
400 Hz, 4-Pole
400 Hz, 3-Pole
400 Hz, 4-Pole
400 Hz, 3-Pole
325 Hz, 3-Pole
370 Hz, 2-Pole
180 Hz, 2-Pole
100 Hz, 2-Pole
1500 Hz, 4-Pole
500 Hz, 3-Pole
800 Hz, 4-Pole
1200 Hz, 4-Pole
120 Hz, 3-Pole
20 kHz, 2-Pole
120 Hz, 2-Pole
50 Hz, 4-Pole
200 Hz, 4-Pole
200 Hz, 3-Pole
200 Hz, 4-Pole
200 Hz, 3-Pole
162.5 Hz, 3-Pole
185 Hz, 2-Pole
90 Hz, 2-Pole
50 Hz, 2-Pole
750 Hz, 4-Pole
250 Hz, 3-Pole
400 Hz, 4-Pole
600 Hz, 4-Pole
60 Hz, 3-Pole
10 kHz, 2-Pole
60 Hz, 2-Pole
25 Hz, 4-Pole
100 Hz, 4-Pole
100 Hz, 3-Pole
100 Hz, 4-Pole
100 Hz, 3-Pole
81.25 Hz, 3-Pole
92.5 Hz, 2-Pole
45 Hz, 2-Pole
25 Hz, 2-Pole
375 Hz, 4-Pole
125 Hz, 3-Pole
200 Hz, 4-Pole
300 Hz, 4-Pole
30 Hz, 3-Pole
5 kHz, 2-Pole
30 Hz, 2-Pole
12.5 Hz, 4-Pole
Changes to these register bits reset the DSP data path. The contents of the SNSDATA_x
registers are not guaranteed until the DSP has completed initialization as specified in
Section 10.20. Reads of the SNSDATA_x registers and Sensor Data requests should be
prevented during this time.
11.2.23.2 User sensitivity shift selection bits (U_SNS_SHIFT[1:0])
The user sensitivity selection bits are used along with the user sensitivity multiplier bits to
scale the output sensitivity of the device. See Section 11.2.24.1 for details.
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11.2.24 Channel 0 and Channel 1 user configuration #2 registers (CH0_CFG_U2,
CH1_CFG_U2)
The Channel 0 and Channel 1 user configuration #2 registers are user programmable
read/write registers which contain channel-specific configuration information. The
registers are included in the read/write array error detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
programming mode.
Table 139.ꢀChannel 0 and Channel 1 user configuration #2 registers (CH0_CFG_U2, CH1_CFG_U2)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$41
CH0_CFG_U2
CH1_CFG_U2
U_SNS_
MULT[7]
U_SNS_
MULT[6]
U_SNS_
MULT[5]
U_SNS_
MULT[4]
U_SNS_
MULT[3]
U_SNS_
MULT[2]
U_SNS_
MULT[1]
U_SNS_
MULT[0]
$49
U_SNS_
MULT[7]
U_SNS_
MULT[6]
U_SNS_
MULT[5]
U_SNS_
MULT[4]
U_SNS_
MULT[3]
U_SNS_
MULT[2]
U_SNS_
MULT[1]
U_SNS_
MULT[0]
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
11.2.24.1 User sensitivity multiplier bits (U_SNS_MULT[7:0])
The user sensitivity multiplier bits are used along with the user sensitivity shift bits to
scale the output sensitivity of the device. Equation 1 describes the scaling:
(1)
Where:
TrimSensitivity
= The default trimmed sensitivity of the device, as specified in
Section 10.6
SensitivityMultiplier
= The unsigned multiplier value contained in the U_SNS_MULT[7:0] bits
SensitivityShiftFactor = The Shift Factor selected by the U_SNS_SHIFT[1:0] bits as described
in Table 140
Table 140.ꢀSensitivity shift factors
Device Type
U_SNS_SHIFT[1]
U_SNS_SHIFT[0]
Sensitivity
shift factor
Normal Range
Normal Range
Normal Range
Normal Range
0
0
1
1
0
1
0
1
0.25
0.50
1
2
Table 141 shows some example user shift and multiplier values for typical full scale
ranges (± 2047, 12 bit):
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Table 141.ꢀExample user shift and multiplier configuration for typical scale range
Device
type
Desired
range
Desired
NXP trim
User sensitivity
shift factor
User multiplier value
Actual
Actual
Actual
Actual
sensitivity
(12 bit,
LSB/g)
sensitivity
sensitivity
sensitivity
sensitivity
(g)
(12 bit,
LSB/g)
16 bit register 10 bit Sensor 12 bit Sensor 16 bit Sensor
Chx_SNS-
DATAx LSB/g)
U_SNS_
Shift
U_SNS_-
Multiplier
value
data request, data request, data request,
SHIFT (HEX)
MULT (HEX)
Factor
LSB/g
LSB/g
LSB/g
(Dec)
255
182
127
255
182
153
127
51
Low g
1.50
1.75
2.00
3.00
3.50
3.75
4.00
5.00
5.98
6.00
7.50
8.00
10.00
12.00
15.00
20.00
23.95
15.5
16
1364.6667
1169.7143
1023.5000
682.3333
584.8571
545.8667
511.7500
409.4000
341.8343
341.1667
272.9333
255.8750
204.7000
170.5833
136.4667
102.3500
85.4586
131.7246
127.9375
102.3500
81.8800
58.4857
40.9400
34.1167
33.0161
32.7520
27.2933
24.0000
20.4700
19.5000
18.2000
16.3760
16.0000
13.6467
40.9400
34.1167
33.0161
32.7520
20.4700
19.5000
18.2000
16.3760
16.0000
13.6467
10.9465
8.1880
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
341.8343
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
33.0161
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
10.9465
0x3
0x3
0x3
0x2
0x2
0x2
0x2
0x2
0x2
0x1
0x1
0x1
0x1
0x0
0x0
0x0
0x0
0x3
0x3
0x3
0x3
0x2
0x2
0x2
0x2
0x1
0x1
0x1
0x1
0x1
0x1
0x0
0x0
0x0
0x3
0x3
0x3
0x3
0x2
0x2
0x2
0x2
0x2
0x2
0x2
0x1
0x1
0x0
2
2
0xFF
0xB6
0x7F
0xFF
0xB6
0x99
0x7F
0x33
0x00
0xFF
0x99
0x7F
0x33
0xFF
0x99
0x33
0x00
0xFF
0xF0
0x8D
0x3D
0xC5
0x3D
0x09
0x00
0xFC
0xA7
0x74
0x3D
0x2E
0x1A
0xFC
0xF0
0xA7
0xDF
0x8F
0x82
0x7F
0xDF
0xC8
0xAA
0x7F
0x76
0x3F
0x00
0x7F
0x32
0xFF
2729.333
2339.429
2045.665
1364.667
1169.714
1092.267
1022.832
819.8682
683.6686
682.3334
546.1338
511.4162
409.9342
341.1666
273.0668
204.9670
170.9170
263.6130
255.8748
204.8030
163.5328
116.8460
81.7664
68.3536
66.0322
65.5164
54.5540
47.9766
40.8832
38.9486
36.3692
32.7582
31.9844
27.2770
81.9278
68.2446
66.0210
65.5080
40.9638
38.9970
36.4314
32.7540
31.9844
27.2808
21.8930
16.3770
13.0844
10.9252
341.1667
292.4286
255.7081
170.5833
146.2143
136.5334
127.8541
102.4835
85.4586
85.2917
68.2667
63.9270
51.2418
42.6458
34.1333
25.6209
21.3646
32.9516
31.9844
25.6004
20.4416
14.6058
10.2208
8.5442
1364.6667
1169.7143
1022.8324
682.3333
584.8571
546.1337
511.4162
409.9341
341.8343
341.1667
273.0669
255.7081
204.9671
170.5833
136.5334
102.4835
85.4586
131.8065
127.9374
102.4015
81.7664
58.4230
40.8832
34.1768
33.0161
32.7582
27.2770
23.9883
20.4416
19.4743
18.1846
16.3791
15.9922
13.6385
40.9639
34.1223
33.0105
32.7540
20.4819
19.4985
18.2157
16.3770
15.9922
13.6404
10.9465
8.1885
21834.67
18715.43
16365.32
10917.33
9357.714
8738.139
8182.659
6558.946
5469.349
5458.667
4369.070
4091.330
3279.474
2729.333
2184.534
1639.736
1367.338
2108.904
2046.998
1638.424
1308.262
934.7680
654.1312
546.8288
528.2576
524.1312
436.4320
383.8128
327.0656
311.5888
290.9536
262.0656
255.8752
218.2160
655.4224
545.9568
528.1680
524.0640
327.7104
311.9760
291.4512
262.0320
255.8752
218.2464
175.1440
131.0160
104.6752
87.4016
2
1
1
1
1
1
1
0
0.5
0.5
0.5
0.5
0.25
0.25
0.25
0.25
2
255
153
127
51
255
153
51
0
Medium
g
255
240
141
61
2
20
2
25
2
35
1
197
61
50
1
60
1
9
62
1
0
8.2540
62.5
75
0.5
0.5
0.5
0.5
0.5
0.5
0.25
0.25
0.25
2
252
167
116
61
8.1896
6.8193
85.3
100
105
112.5
125
128
150
50
5.9971
5.1104
46
4.8686
26
4.5462
252
240
167
223
143
130
127
223
200
170
127
118
63
4.0948
3.998
3.4096
High g
10.2410
8.5306
60
2
62
2
8.2526
62.5
100
105
112.5
125
128
150
187
250
312.5
375
2
8.1885
1
5.1205
1
4.8746
1
4.5539
1
4.0943
1
3.9981
1
3.4101
1
0
2.7366
0.5
0.5
0.25
127
50
2.0471
6.5504
1.6356
6.5422
5.4587
255
1.3657
5.4626
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Table 141.ꢀExample user shift and multiplier configuration for typical scale range...continued
Device
type
Desired
range
Desired
NXP trim
User sensitivity
shift factor
User multiplier value
Actual
Actual
Actual
Actual
sensitivity
(12 bit,
LSB/g)
sensitivity
sensitivity
sensitivity
sensitivity
(g)
(12 bit,
LSB/g)
16 bit register 10 bit Sensor 12 bit Sensor 16 bit Sensor
Chx_SNS-
DATAx LSB/g)
U_SNS_
Shift
U_SNS_-
MULT (HEX)
Multiplier
value
data request, data request, data request,
SHIFT (HEX)
Factor
LSB/g
LSB/g
LSB/g
(Dec)
500
4.0940
10.9465
0x0
0.25
0x7F
127
8.1884
1.0236
4.0942
65.5072
Note:
Table 141 includes some typical device ranges. Other ranges are possible with the user-selected shift and multiplier values.
Table 142 shows some example user shift and multiplier values for typical PSI5 full scale
ranges (± 480, 10 bit):
Table 142.ꢀExample user shift and multiplier configuration for typical psi5 scale range
Device
type
Desired
range
Desired
sensitivity (10
bit, LSB/g)
NXP trim
NXP trim
User sensitivity shift factor
User multiplier value
Actual
Actual
(10 bit, LSB/g) (16 bit, LSB/g)
sensitivity
sensitivity
U_SNS_
Shift Factor
U_SNS_ Multiplier
(g)
(PSI5 10
bit, LSB/g)
(PSI5 16
bit, LSB/g)
SHIFT (HEX)
MULT (HEX)
value
(Dec)
Medium g
15
20
32.0000
24.0000
16.0000
8.0000
4.0000
8.0000
4.0000
2.0000
1.0000
8.2540
8.2540
8.2540
8.2540
8.2540
2.7366
2.7366
2.7366
2.7366
528.256
528.256
528.256
528.256
528.256
175.142
175.142
175.142
175.142
0x3
0x3
0x2
0x1
0x0
0x3
0x2
0x1
0x0
2
2
0xF0
0x74
0xF0
0xF0
0xF0
0x76
0x76
0x76
0x76
240
116
240
240
240
118
118
118
118
31.9844
23.9883
15.9922
7.9961
3.9980
7.9961
3.9980
1.9990
0.9995
2047.00
1535.25
1023.50
511.500
255.875
511.749
255.874
127.937
63.9686
30
1
60
0.5
0.25
2
120
60
High g
120
240
480
1
0.5
0.25
Note:
Table 142 includes some typical device ranges. Other ranges are possible with the user-selected shift and multiplier values.
11.2.25 Channel 0 and Channel 1 user configuration #3 registers (CH0_CFG_U3,
CH1_CFG_U3)
The Channel 0 and Channel 1 user configuration #3 registers are user programmable
read/write registers which contain channel-specific configuration information. The
registers are included in the read/write array error detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 143.ꢀChannel 0 and Channel 1 user configuration #3 registers (CH0_CFG_U3, CH1_CFG_U3)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$42
CH0_CFG_U3
CH1_CFG_U3
UNSIGN
EDDATA
DATATYPE0[1:0]
DATATYPE1[2:0]
DATATYPE1[2:0]
0
MOVEAVG[1:0]
MOVEAVG[1:0]
$4A
UNSIGN
EDDATA
DATATYPE0[1:0]
Unprogrammed OTP Value
0
0
0
0
0
0
0
11.2.25.1 Unsigned data select bit (UNSIGNEDDATA)
The unsigned data selection bit selects signed or unsigned data for the register and
sensor data transmissions as shown in Table 144.
Table 144.ꢀUnsigned data select bit (UNSIGNEDDATA)
UNSIGN
EDDATA
Register values
CHx_SNSDATA0 CHx_SNSDATA1
Channel Sensor Data
DATATYPE transmissions
Sensor data (DSI, SPI) Sensor data (PSI5)
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Table 144.ꢀUnsigned data select bit (UNSIGNEDDATA)...continued
UNSIGN
EDDATA
Register values
DATATYPE transmissions
CHx_SNSDATA0
CHx_SNSDATA1
Signed Data
Sensor data (DSI, SPI)
Signed Data
Sensor data (PSI5)
0
1
Signed Data
Signed Data
Unsigned Data
Unsigned Data
Unsigned Data
Temperature Sensor Data
As specified in Section 11.7.2
0
1
11.2.25.2 Channel data type 0 selection bits (CHxDATATYPE0)
The Channel Data Type 0 selection bits select the type of data to be included in the
SNSDATA0_L and SNSDATA0_H registers for each channel.
Table 145.ꢀChannel data type 0 selection bits (CHxDATATYPE0)
CHxDATA
TYPE0[1]
CHxDATA
TYPE0[0]
Data transmitted
Data transmitted
Offset
Moving
Interpo
lation?
canceled?
average?
0
0
CHx Sensor Data Selected by
OC_-FILT[1:0]
Selected by
Selected by
MOVEA
VG[1:0]
MOVEA
VG[1:0]
0
1
1
1
0
1
CHx Sensor Data
No
Temperature Sensor Data (As specified in Section 11.7.2)
11.2.25.3 Channel data type 1 selection bits (CHxDATATYPE1)
The Channel data type 1 selection bits select the type of data to be included in the
SNSDATA1_L and SNSDATA1_H registers for each channel.
Table 146.ꢀChannel data type 1 selection bits (CHxDATATYPE1)
CHxDATA
TYPE1[2]
CHxDATA
TYPE1[1]
CHxDATA
TYPE1[0]
Data transmitted
Data transmitted
Offset
Moving
Interpolation?
canceled?
average?
0
0
0
0
0
1
CHx Sensor Data
Selected by
OC_-FILT[1:0]
Selected by
No
MOVEA
VG[1:0]
CHx Sensor Data
No
Selected by
No
MOVEA
VG[1:0]
0
0
1
1
1
0
0
1
0
Temperature Sensor Data (As specified in Section 11.7.2)
CHx Sensor Data
CHx Sensor Data
Selected by
OC_-FILT[1:0]
No
No
No
1
0
1
No
Selected by
MOVEA
VG[1:0]
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Table 146.ꢀChannel data type 1 selection bits (CHxDATATYPE1)...continued
CHxDATA
TYPE1[2]
CHxDATA
TYPE1[1]
CHxDATA
TYPE1[0]
Data transmitted
Data transmitted
Offset
Moving
Interpolation?
canceled?
average?
1
1
1
1
0
1
Temperature Sensor Data (As specified in Section 11.7.2)
11.2.25.4 Signal chain moving average selection bits (MOVEAVG[1:0])
The signal chain moving average selection bits determine the input sample period to be
used for the signal chain moving average filter.
Table 147.ꢀSignal chain moving average selection bits (MOVEAVG[1:0])
MOVEAVG[1] MOVEAVG[0]
Typical signal
Signal chain
Interpolation
sampling period
moving average
(Dependent on oscillator)
(µs)
0
0
1
1
0
1
0
1
Determined by LPF
Bypassed
Enabled
Disabled
Disabled
Disabled
32
64
8 Sample Moving Average
8 Sample Moving Average
8 Sample Moving Average
128
Changes to these register bits reset the DSP data path. The contents of the SNSDATA_x
registers are not guaranteed until the DSP has completed initialization as specified in
Section 10.20. Reads of the SNSDATA_x registers and Sensor Data requests should be
prevented during this time.
11.2.26 Channel 0 and Channel 1 user configuration #4 registers (CH0_CFG_U4,
CH1_CFG_U4)
The Channel 0 and Channel 1 user configuration #4 registers are user programmable
read/write registers which contain channel-specific configuration information. These
registers are included in the read/write array error detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 148.ꢀChannel 0 and Channel 1 user configuration #4 registers (CH0_CFG_U4, CH1_CFG_U4)
Location
Bit
Address
$43
Register
7
6
5
4
3
2
1
0
CH0_CFG_U4
CH1_CFG_U4
RESET_OC
RESET_OC
0
INVERT
INVERT
0
OC_FILT[1:0]
OC_FILT[1:0]
PCM
PCM
0
ARM_CFG[2:0]
ARM_CFG[2:0]
0
$4B
Unprogrammed OTP Value
0
0
0
0
11.2.26.1 Reset offset cancellation startup bit (RESET_OC)
When the reset offset cancellation startup bit is written to logic 1, the offset cancellation
startup is forced to phase 0 and follows the phase advancement as documented in
Section 11.6.4.6. The RESET_OC bit is cleared when the offset cancellation phase
reaches phase 1.
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11.2.26.2 Signal inversion bit (INVERT)
The signal inversion bit provides the option to invert the polarity of the sensor signals as
shown in Table 149.
Table 149.ꢀSignal inversion bit (INVERT)
INVERT Acceleration Fixed pattern
sensor data self-test
Digital self-test
Analog self-test
Positive Delta from Offset as
Temperature
0
As shown in As specified in
Digital Self-Test
Activation results in Self-Test:
the values specified
in Section 10.8.
Self-Test:
As specified in
Section 11.7.2
Section 8.
specified in Section 10
Section 11.2.27.1
Negative
Delta from Offset inverted
from the specified values
in Section 10.8 (Negative
Values)
1
Inverted
Digital Self-
Positive
Self-Test:
Delta from Offset inverted
from the specified values
in Section 10.8 (Negative
Values)
polarity from
that shown
in Section 8
Test Activation
results in the two's
complement of the
values specified in
Section 10.8.
Negative
Self-Test:
Delta from Offset as
specified in Section 10
11.2.26.3 Offset cancellation filter selection bits (OC_FILT[1:0])
The offset cancellation filter selection bits provide the option to bypass the offset
cancellation filter and the rate limiting for the associated channel. See Section 11.6.4.6
for details regarding offset cancellation.
Table 150.ꢀOffset cancellation filter selection bits (OC_FILT[1:0])
Offset cancellation
OC_FILT[1]
OC_FILT[0]
Offset cancellation IIR filter
rate limiting
0
0
1
1
0
1
0
1
0.04 Hz
0.04 Hz
Enabled
Bypassed
Bypassed
Bypassed
0.005 Hz
Bypassed
11.2.26.4 Arming pin configuration bits (ARM_CFG[2:0]) and PCM range selection bit (PCM)
The ARM configuration bits (ARM_CFG[2:0]) select the mode of operation for the arming
pins.
Table 151.ꢀArming pin configuration bits (ARM_CFG[2:0]) and PCM range selection bit (PCM)
ARM_
CFG[2]
ARM_
CFG[1]
ARM_
CFG[0]
PCM
Operating mode
Output type
High Impedance
Driven Low
Reference
0
0
0
x
Arm/PCM Output
Disabled
0
0
1
0
Arm/PCM Output
Disabled
0
0
0
1
1
0
1
x
PCM Output
Digital Output
Section 11.8
Moving Average
Mode
Open-Drain, Active High with
Pull-down Current
Section 11.9.1
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Table 151.ꢀArming pin configuration bits (ARM_CFG[2:0]) and PCM range selection bit (PCM)...continued
ARM_
ARM_
ARM_
PCM
Operating mode
Output type
Reference
CFG[2]
CFG[1]
CFG[0]
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
x
x
x
x
x
Moving Average
Mode
Open-Drain, Active Low with
Pull-up Current
Section 11.9.1
Section 11.9.2
Section 11.9.2
Section 11.9.3
Section 11.9.3
Count Mode
Open-Drain, Active High with
Pull-down Current
Count Mode
Open-Drain, Active Low with
Pull-up Current
Unfiltered Mode
Unfiltered Mode
Open-Drain, Active High with
Pull-down Current
Open-Drain, Active Low with
Pull-up Current
Note: The arming function is reset on a change to the ARM_CFG bits. This includes the
downsampling state and all history registers.
When the PCM output is enabled, a Pulse Code Modulated signal proportional to the
data selected by the DATATYPE0 selection bits is output on the ARM/PCM pin. See
Section 11.8 for more information regarding the PCM output.
11.2.27 Channel 0 and Channel 1 user configuration #5 register (CH0_CFG_U5,
CH1_CFG_U5)
The Channel 0 and Channel 1 user configuration #5 registers are user programmable
read/write registers which contain channel-specific configuration information. These
registers are included in the read/write array error detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 152.ꢀChannel 0 and Channel 1 user configuration #5 register (CH0_CFG_U5, CH1_CFG_U5)
Location
Bit
Address
$44
Register
7
6
5
4
3
2
1
0
CH0_CFG_U5
CH1_CFG_U5
ST_CTRL[3:0]
ST_CTRL[3:0]
OC_LIMIT[2:0]
OC_LIMIT[2:0]
0
DSP_DIS
DSP_DIS
0
$4C
Unprogrammed OTP Value
0
0
0
0
0
0
11.2.27.1 Self-test control bits (ST_CTRL[3:0])
The self-test control bits select one of the various analog and digital self-test features of
the device as shown in Table 153.
The self-test control bits are writable in DSI3 command and response mode.
The self-test control bits are writable in SPI Mode.
The self-test control bits are writable in I2C Mode.
The self-test control bits are writable in PSI5 programming mode.
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Table 153.ꢀSelf-test control bits (ST_CTRL[3:0])
ST_
ST_
ST_
ST_
Function
16-bit
Effect on
Effect on
CTRL[3] CTRL[2] CTRL[1] CTRL[0]
SNSDATAx
ST_
ST_ACTIVE
Register
value
INCMPLT
bit in Chx_
STAT
bit in Chx_
STAT
signed
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DSP writes to the SNS_DATAx_
X registers as configured in the
ChxDATATYPEx registers.
Sensor Data
No Effect
Clear when
Active
Clear on
Activation
Set When
Active
Clear on
Activation
Set When
Active
Clear on
Activation
Set When
Active
DSP write to registers inhibited.
0x0000
0xAAAA
Clear on
Activation
Set When
Active
Clear on
Activation
Set When
Active
0x5555
Clear on
Activation
Set When
Active
0xFFFF
Clear on
Activation
Set When
Active
Positive Analog Self-test - Low
Negative Analog Self-test - Low
Positive Analog Self-test - High
Negative Analog Self-test - High
Digital Self-test
Sensor Data
Clear on
Activation
Set When
Active
Clear on
Activation
Set When
Active
Clear on
Activation
Set When
Active
Clear on
Activation
Set When
Active
Reference
Clear on
Activation
Set When
Active
Section 10.8
Clear on
Activation
Set When
Active
Clear on
Activation
Set When
Active
Clear on
Activation
Set When
Active
11.2.27.2 Offset cancellation test limit bits (OC_LIMIT[2:0])
The offset cancellation test limit bits set the offset limits for the offset test at the end of
the PSI5 self-test documented in Section 11.6.2.5. The test limits are set as shown in
Table 154.
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Table 154.ꢀOffset cancellation test limit bits (OC_LIMIT[2:0])
OC_LIMIT[2:0]
Post PSI5 self-test offset limits
The post PSI5 self-test offset test is disabled.
± 2 LSB, 10-bit
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
± 4 LSB, 10-bit
± 6 LSB, 10-bit
± 8 LSB, 10-bit
± 10 LSB, 10-bit
± 12 LSB, 10-bit
± 14 LSB, 10-bit
11.2.27.3 DSP disable bit (DSP_DIS)
The DSP disable bit provides the option for the user to disable the clocking to the DSP if
sensor data from the associated channel is not used.
Table 155.ꢀDSP disable bit (DSP_DIS)
DSP_DIS
DSP status
0
1
DSP operational as specified
DSP clocking disabled. Sensor data is readable but will not be updated by the DSP
even when self-test is enabled
Care must be taken to ensure the DSP is not disabled for sources that are enabled.
11.2.28 Channel 0 and Channel 1 arming configuration registers (CH0_ARM_CFG,
CH1_ARM_CFG)
The arming configuration registers contain configuration information for the arming
function. The values in these registers are only relevant if the arming function is operating
in moving average mode, or count mode.
Note: The arming function is reset on a change to the CHx_ARM_CFG bits. This
includes the downsampling state and all history registers.
These registers can be written during initialization but are locked once the ENDINIT bit
is set. Refer to Section 11.2.6. The registers are included in the read/write array error
detection.
Table 156.ꢀChannel 0 and Channel 1 arming configuration registers (CH0_ARM_CFG, CH1_ARM_CFG)
Location
Bit
Address
$45
Register
7
6
5
4
3
2
1
0
CH0_ARM_CFG
CH1_ARM_CFG
ARM_DS[1:0]
ARM_DS[1:0]
ARM_PS[1:0]
ARM_PS[1:0]
ARM_WS_N[1:0]
ARM_WS_N[1:0]
ARM_WS_P[1:0]
ARM_WS_P[1:0]
$4D
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
11.2.28.1 Arming function down sampling selection bits (ARM_DS[1:0])
The arming function down sampling selection bits select the down sample rate for the
arming function. See Section 11.9.4.
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Table 157.ꢀArming function down sampling selection bits (ARM_DS[1:0])
ARM_
DS[1]
ARM_
DS[0]
Down sampling
0
0
1
1
0
1
0
1
Provide every Sensor Data Request sample to the arming function for the relevant channel.
Provide every other Sensor Data Request sample to the arming function for the relevant channel.
Provide every fourth Sensor Data Request sample to the arming function for the relevant channel.
Provide every eighth Sensor Data Request sample to the arming function for the relevant channel.
11.2.28.2 Arming pulse stretch (ARM_PS[1:0])
The ARM_PS[1:0] bits set the programmable pulse stretch time for the arming outputs.
See Section 11.9 for more details regarding the arming function. Pulse stretch times are
derived from the internal oscillator, so the tolerance on this oscillator applies.
Table 158.ꢀArming pulse stretch (ARM_PS[1:0])
ARM_PS[1]
ARM_PS[0]
Pulse stretch time (typical oscillator)
0 ms
0
0
1
1
0
1
0
1
128.000 ms - 130.048 ms
512.000 ms - 514.048 ms
2048.000 ms - 2050.048 ms
11.2.28.3 Arming window size (ARM_WS_N[1:0], A_WS_P[1:0])
The ARM_WS_N[1:0] and ARM_WS_P[1:0] bits have a different function depending on
the state of the ARM_CFG bits in the CHx_CFG_U4 registers. See Section 11.9 for more
details regarding the arming function. If the arming function is set to moving average
mode, the ARM_WS bits set the number of sensor samples used for the arming function
moving aver-age. The number of samples is set independently for each channel and
polarity. If the arming function is set to count mode, the ARM_WS bits set the sample
count limit for the arming function. The sample count limit is set independently for each
channel.
Table 159.ꢀPositive arming window size definitions (moving average mode)
ARM_WS_P[1]
ARM_WS_P[0]
Positive window size
0
0
1
1
0
1
0
1
2
4
8
16
Table 160.ꢀNegative arming window size definitions (moving average mode)
ARM_WS_N[1]
ARM_WS_N[0]
Negative window size
0
0
1
1
0
1
0
1
2
4
8
16
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Table 161.ꢀArming count limit definitions (count mode)
ARM_WS_N[1]
Don't Care
Don't Care
Don't Care
Don't Care
ARM_WS_N[0]
Don't Care
Don't Care
Don't Care
Don't Care
ARM_WS_P[1]
ARM_WS_P[0]
Sample count limit
0
0
1
1
0
1
0
1
1
3
7
15
11.2.29 Arming threshold registers (CHx_ARM_T_P, CHx_ARM_T_N)
The arming threshold registers contain the positive and negative thresholds to be used
by the arming function for each channel. Refer to Section 11.9 for more details regarding
the arming function.
These registers can be written during initialization but are locked once the ENDINIT bit
is set. Refer to Section 11.2.6. The registers are included in the read/write array error
detection.
Table 162.ꢀArming threshold registers (CHx_ARM_T_P, CHx_ARM_T_N)
Location
Bit
Address
$46
Register
7
6
5
4
3
2
1
0
CH0_ARM_T_P
CH0_ARM_T_N
CH1_ARM_T_P
CH1_ARM_T_N
ARM_T_P[7:0]
ARM_T_N[7:0]
ARM_T_P[7:0]
ARM_T_N[7:0]
$47
$4E
$4F
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
The values programmed into the threshold registers are the threshold values used for the
arming function as described in Section 11.9. The threshold registers hold independent
unsigned 8-bit values for each channel and polarity. Each threshold increment is
equivalent to 1 output LSB, 10-bit. Table 163 shows examples of some threshold register
values and the corresponding threshold.
Table 163.ꢀExample threshold register values and corresponding threshold
Device
Range
Sensitivity Arming
Range
of arm
Programmed thresholds
thresh-old
resolution threshold
(12 bit,
LSB/g)
Positive
Negative
(Decimal)
Positive
threshold
Negative
threshold
(g)
(Decimal)
(10 bit,
LSB/g)
(g)
(g)
(g)
125
62
50
25
16
16.3760
33.0161
40.9400
81.8800
127.9375
4.0940
8.2540
62.2863
30.8940
24.9145
12.4573
7.9726
40
12
24
61
61
95
10
15
24
12
7
–3
–3
–6
–3
–3
123
245
245
223
10.2350
20.4700
31.9844
If either the positive or negative threshold for one channel is programmed to 0x00,
comparisons are disabled for only that polarity. The arming function still operates for the
opposite polarity. If both the positive and negative arming thresholds for one channel are
programmed to 0x00, the arming function for the associated channel is disabled and the
output pin is set to high impedance, regardless of the value of the ARM_CFG bits in the
CHx_CFG_U4 register.
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11.2.30 Offset cancellation user configuration register (OC_PHASE_CFG)
The offset cancellation user configuration register is a user programmable read/write
register which contains offset cancellation configuration information. The register is
included in the read/write array error detection.
This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode.
Table 164.ꢀOffset cancellation user configuration register (OC_PHASE_CFG)
Location
Register
OC_PHASE_CFG CH0_OCFINAL CH1_OCFINAL
Bit
Address
7
6
5
4
3
2
1
0
$50
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
RESERVED
0
Unprogrammed OTP Value
0
0
11.2.30.1 Channel 0 and Channel 1 offset cancellation final phase control bit (CH0_OCFINAL,
CH1_OCFINAL)
The channel 0 offset cancellation final phase control bit provides the option for the user to
control the final offset cancellation phase for normal mode as shown in Table 165.
Table 165.ꢀChannel 0 offset cancellation final phase control bit (CH0_OCFINAL,
CH1_OCFINAL)
CH0_
Channel 0 offset cancellation final phase for normal mode
OCFINAL
0
1
Phase 6 (a or b) as specified in the table in Section 11.6.4.6
Phase 5 as specified in the table in Section 11.6.4.6
(Rate Limiting is always bypassed)
The channel 1 offset cancellation final phase control bit provides the option for the user to
control the final offset cancellation phase for normal mode as shown in Table 166.
Table 166.ꢀChannel 1 offset cancellation final phase control bit (CH0_OCFINAL,
CH1_OCFINAL)
CH1_
Channel 1 offset cancellation final phase for normal mode
OCFINAL
0
1
Phase 6 (a or b) as specified in the table in Section 11.6.4.6
Phase 5 as specified in the table in Section 11.6.4.6
(Rate Limiting is always bypassed)
11.2.31 User offset calibration registers (Chx_U_OFFSET_L, Chx_U_OFFSET_H)
The user offset calibration registers contain a user programmable 16-bit signed offset
correction value for the sensor data.
These registers can be written during initialization but are locked once the ENDINIT bit
is set. Refer to Section 11.2.6. The registers are included in the read/write array error
detection.
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Table 167.ꢀUser offset calibration registers (Chx_U_OFFSET_L, Chx_U_OFFSET_H)
Location
Bit
Address
$55
Register
7
6
5
4
3
2
1
0
CH0_U_OFFSET_L
CH0_U_OFFSET_H
CH1_U_OFFSET_L
CH1_U_OFFSET_H
CH0_U_OFFSET[7:0]
CH0_U_OFFSET[15:8]
CH1_U_OFFSET[7:0]
CH1_U_OFFSET[15:8]
$56
$5D
$5E
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
The value programmed into the user offset calibration register is directly added to the
sensor data after the user sensitivity scaling but before the offset cancellation. See
Section 11.6.4.9 for scaling of the CHx_U_OFFSET value. The CHx-_U_OFFSET
register has the same resolution as the sensor value in the SNSDATAx registers. A 1
LSB change in the CHx-_U_OFFSET register will result in a 1 LSB change to the value in
the SNSDATAx registers.
Note: The user offset calibration register range is larger than the full scale range of the
output. The user must take care to ensure that the value stored in this register does not
result in a compressed output range or a railed output.
11.2.32 Channel-specific status register (CH0_STAT, CH1_STAT)
The channel-specific status registers are read-only registers which contain sensor data-
specific status information.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming
mode.
Table 168.ꢀChannel-specific status register (CH0_STAT, CH1_STAT)
Location
Bit
Address
$60
Register
7
6
5
4
3
2
1
0
CH0_STAT
CH1_STAT
SIGNALCLIP
SIGNALCLIP
0
OCPHASE[2:0]
OCPHASE[2:0]
0
ST_INCMPLT
ST_INCMPLT
1
ST_ACTIVE
ST_ACTIVE
0
OFFSET_ERR
OFFSET_ERR
0
ST_ERROR
ST_ERROR
0
$70
Reset Value
0
0
11.2.32.1 Signal clipped status bit (SIGNALCLIP)
In DSI3 mode, SPI mode, and I2C mode, the signal clipped status bit is set if the output
of the sinc filter reaches either the maximum or minimum value. The SIGNALCLIP bit is
cleared on a read of the CHx_STAT register through any communication interface or on a
data transmission that includes the error in the status field.
In PSI5 mode, the SIGNALCLIP bit has no impact on device operation or performance.
11.2.32.2 Offset cancellation phase status (OCPHASE[2:0])
The offset cancellation phase status bits indicate the current phase of the offset
cancellation filter as described in Section 11.6.4.6.
Table 169.ꢀOffset cancellation phase status (OCPHASE[2:0])
OCPHA
SE[2:0]
Offset cancellation startup phase
Offset low-pass filter frequency
(Hz)
000
001
010
Phase 0
Phase 1
Phase 2
163.8
40.96
10.24
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Table 169.ꢀOffset cancellation phase status (OCPHASE[2:0])...continued
OCPHA
SE[2:0]
Offset cancellation startup phase
Offset low-pass filter frequency
(Hz)
2.560
0.640
0.160
0.04
011
100
101
110
111
Phase 3
Phase 4
Phase 5
Phase 6 / Normal Mode
Not Applicable
11.2.32.3 Self-test incomplete (ST_INCMPLT)
The self-test incomplete bit is set after a device reset and is cleared when one of the
analog or digital self-tests modes are enabled in the ST_CTRL register (ST_CTRL[3] =
logic 1 | ST_CTRL[2] = logic 1 | | ST_CTRL[1] = logic 1 | | ST_CTRL[0] = logic 1) or the
PSI5 internal self-test procedure has started.
Table 170.ꢀSelf-test incomplete (ST_INCMPLT)
ST_
Condition
INCMPLT
0
1
An Analog or Digital Self-test has been activated since the last reset
No Analog or Digital Self-test has not been activated since the last reset AND the PSI5 internal self-test
procedure has not completed
11.2.32.4 Self-test active flag (ST_ACTIVE)
The self-test active bit is set if any self-test mode is currently active, including the PSI5
internal self-test or a self-test voltage is applied to the transducer. The self-test active
bit is cleared when no self-test mode is active and no self-test voltage is applied to the
transducer.
ST_ACTIVE = ST_CTRL[3] | ST_CTRL[2] |ST_CTRL[1] | ST_CTRL[0] | (self-test voltage
applied to transducer)
11.2.32.5 Offset error flag (OFFSET_ERR)
The offset error flag is set if the sensor signal reaches the offset limit specified in
Section 10.6. The OFFSET_ERR bit is cleared on a read of the CHx_STAT register
through any communication interface or on a data transmission that includes the error in
the status field. See Section 11.2.15.2 for details on a method to disable the automatic
clearing of this error in PSI5 mode.
Table 171.ꢀOffset error flag (OFFSET_ERR)
OFFSET_ERR
Error condition
0
1
No error detected
Offset error detected
11.2.32.6 Self-test error flag (ST_ERROR)
The self-test error flag is set if the PSI5 startup self-test fails as described in Section
6.6.2.5. This bit can only be cleared by a device reset.
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11.2.33 Device status copy register (DEVSTAT_COPY)
The device status copy register is a read-only register which contains a copy of the
device status information contained in the DEVSTAT register. See Section 11.2.2 for
details regarding the DEVSTAT register contents.
This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming mode.
A read of the DEVSTAT_COPY register has the same effect as a read of the DEVSTAT
register.
Table 172.ꢀDevice status copy register (DEVSTAT_COPY)
Location
Register
DEVSTAT_COPY
Bit
Address
7
6
5
4
3
2
1
0
$61
CH0_ERR
CH1_ERR
COMM_ERR
MEMTEMP_
ERR
SUPPLY_ERR
TESTMODE
DEVRES
DEVINIT
11.2.34 Sensor data #0 registers (CHx_SNSDATA0_L, CHx_SNSDATA0_H)
The sensor data #0 registers are read-only registers which contain the 16-bit sensor
data. The data type for the sensor data #0 registers is selected by the DATATYPE0 bits
in the CHx_CFG_U3 register. See Section 11.2.25.2. See Section 11.6.4.9 for details
regarding the 16-bit sensor data.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode. In I2C mode, the SNSDA-TA0_H register value is latched on a read of the
SNSDATA0_L register value until the SNSDATA0_H register is read. To avoid
data mismatch, it is required that the user always read the registers in sequence,
SNSDATA0_L register first, followed by the SNSDATA0_H register.
Table 173.ꢀSensor data #0 registers (CHx_SNSDATA0_L, CHx_SNSDATA0_H)
Location
Bit
Address
$62
Register
7
6
5
4
3
2
1
0
CH0_SNSDATA0_L
CH0_SNSDATA0_H
CH1_SNSDATA0_L
CH1_SNSDATA0_H
Reset Value
CH0_SNSDATA0[7:0]
CH0_SNSDATA0[15:8]
CH1_SNSDATA0[7:0]
CH1_SNSDATA0[15:8]
$63
$72
$73
0
0
0
0
0
0
0
0
11.2.35 Sensor data #1 registers (CHx_SNSDATA1_L, CHx_SNSDATA1_H)
The sensor data #1 registers are read-only registers which contain the 16-bit sensor
data. The data type for the sensor data #1 registers is selected by the DATATYPE1 bits
in the CHx_CFG_U3 register. See Section 11.2.25.3. See Section 11.6.4.9 for details
regarding the 16-bit sensor data.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming
mode. In I2C mode, the SNSDA-TA1_H register value is latched on a read of the
SNSDATA1_L register value until the SNSDATA1_H register is read. To avoid
data mismatch, it is required that the user always read the registers in sequence,
SNSDATA1_L register first, followed by the SNSDATA1_H register.
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Table 174.ꢀSensor data #1 registers (CHx_SNSDATA1_L, CHx_SNSDATA1_H)
Location
Bit
Address
$64
Register
7
6
5
4
3
2
1
0
CH0_SNSDATA1_L
CH0_SNSDATA1_H
CH1_SNSDATA1_L
CH1_SNSDATA1_H
Reset Value
CH0_SNSDATA1[7:0]
CH0_SNSDATA1[15:8]
CH1_SNSDATA1[7:0]
CH1_SNSDATA1[15:8]
$65
$74
$75
0
0
0
0
0
0
0
0
11.2.36 Channel-specific factory configuration register (CHx_CFG_F)
The channel-specific configuration registers are factory programmable OTP registers
which contain channel specific configuration information. These registers are included in
the factory programmed OTP array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for this register.
Table 175.ꢀChannel-specific factory configuration register (CHx_CFG_F)
Location
Bit
Address Register
7
6
5
4
3
2
1
0
$A0
CH0_
CFG_F
DEV_RANGE[3:0]
RESE
RVED
RESE
RVED
AXIS[1:0]
AXIS[1:0]
$B0
CH1_
CFG_F
DEV_RANGE[3:0]
RESE
RVED
RESE
RVED
11.2.36.1 Range indication bits (RANGE[3:0])
The range indication bits indicate the full scale range of the channel as shown in
Table 176.
Table 176.ꢀRange indication bits (RANGE[3:0])
RANGE[3]
RANGE[2]
RANGE[1]
RANGE[0]
Acceleration range
RESERVED
RESERVED
Medium
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
RESERVED
High
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
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Table 176.ꢀRange indication bits (RANGE[3:0])...continued
RANGE[3]
RANGE[2]
RANGE[1]
RANGE[0]
Acceleration range
RESERVED
1
1
1
1
1
1
0
1
1
1
0
1
RESERVED
RESERVED
11.2.36.2 Axis indication bits (AXIS[1:0])
The axis indication bits indicate the axes of sensitivity for the channel as shown in
Table 177.
Table 177.ꢀAxis indication bits (AXIS[1:0])
AXIS[1]
AXIS[0]
Axis of sensitivity
0
0
1
1
0
1
0
1
X
Y
Z
RESERVED
11.2.37 Self-test deflection storage registers
The self-test deflection registers are factory programmable OTP registers which contain
the nominal self-test values for the various self-tests at 25 °C. These registers are
included in the factory programmed OTP array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for these registers.
Table 178.ꢀSelf-test deflection storage registers
Location
Bit
Address
$A2
$A3
$A4
$A5
$A6
$A7
$A8
$A9
$B2
$B3
$B4
$B5
$B6
$B7
$B8
$B9
Register
7
6
5
4
3
2
1
0
CH0_STL_P_L
CH0_STL_P_H
CH0_STH_P_L
CH0_STH_P_H
CH0_STL_N_L
CH0_STL_N_H
CH0_STH_N_L
CH0_STH_N_H
CH1_STL_P_L
CH1_STL_P_H
CH1_STH_P_L
CH1_STH_P_H
CH1_STL_N_L
CH1_STL_N_H
CH1_STH_N_L
CH1_STH_N_H
CH0_STL_P[7:0]
CH0_STL_P[15:8]
CH0_STH_P[7:0]
CH0_STH_P[15:8]
CH0_STL_N[7:0]
CH0_STL_N[15:8]
CH0_STH_N[7:0]
CH0_STH_N[15:8]
CH1_STL_P[7:0]
CH1_STL_P[15:8]
CH1_STH_P[7:0]
CH1_STH_P[15:8]
CH1_STL_N[7:0]
CH1_STL_N[15:8]
CH1_STH_N[7:0]
CH1_STH_N[15:8]
The self-test values are positive and negative deflection values, measured at the factory,
and factory programmed for each device. The stored value is equal to one half of the
absolute value of the difference be tween the factory measured Chx-_SNSDATA0
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register value with the analog self-test active and the factory measured CHx_SNSDATA0
register value for off-set at nominal temperature (Data is aligned to the 12-bit sensor
data). Both the self-test and offset values are measured with the user scaling set to 1:
U_SNS_SHIFT[1:0] = 0x2 and U_SNS_MULT[7:0] = 0x00.
CH0_STL_P = 0.5 * [CH0_SNSDATA0ST_CTRL=0x8 - CH0_SNSDATA0ST_CTRL=0x0
CH0_STL_N = 0.5 * [CH0_SNSDATA0ST_CTRL=0x0 - CH0_SNSDATA0ST_CTRL=0x9
CH0_STH_P = 0.5 * [CH0_SNSDATA0ST_CTRL=0xA - CH0_SNSDATA0ST_CTRL=0x0
CH0_STH_N = 0.5 * [CH0_SNSDATA0ST_CTRL=0x0 - CH0_SNSDATA0ST_CTRL=0xB
CH1_STL_P = 0.5 * [CH1_SNSDATA0ST_CTRL=0x8 - CH1_SNSDATA0ST_CTRL=0x0
]
]
]
]
]
CH1_STL_N = 0.5 * [CH1_SNSDATA0ST_CTRL=0x0 - CH1_SNSDATA0ST_CTRL=0x9
]
CH1_STH_P = 0.5 * [CH1_SNSDATA0ST_CTRL=0xA - CH1_SNSDATA0ST_CTRL=0x0
]
CH1_STH_N = 0.5 * [CH1_SNSDATA0ST_CTRL=0x0 - CH1_SNSDATA0ST_CTRL=0xB
]
Two self-test values are stored and available for comparison: a high self-test value and a
low self-test value. The self-test value is controlled by the user via the ST_CTRL[3:0] bits
in the CHx_CFG_U5 registers as described in Section 11.2.27.1.
When self-test is activated, the sensor data can be compared to the values in the
appropriate registers. The difference from the measured deflection value, and the
nominal deflection value stored in the register shall not fall outside the self-test accuracy
limits specified in Section 10.7 (ΔSTACC). See Section 11.6.2 for more details on
calculating the self-test limits.
11.2.38 IC type register
The IC type register is a factory programmable OTP register which contains the IC type
as defined in Table 179. This register is included in the factory programmed OTP array
error detection.
Table 179.ꢀIC type register
Location
Bit
Address
Register
ICTYPEID
7
6
5
4
3
2
1
0
$C0
0
0
0
0
0
0
1
1
11.2.39 IC revision register
The IC revision register is a factory programmable OTP register which contains the IC
revision. The upper nibble contains the main IC revision. The lower nibble contains the
sub IC revision. This register is included in the factory programmed OTP array error
detection.
This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming mode
when ENDINIT is not set. See Section 11.2.10 for details on the register read process for
this register.
Table 180.ꢀIC revision register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$C1
ICREVID
ICREVID[7:0]
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11.2.40 IC manufacturer identification register
The IC manufacturer identification register is a factory programmable OTP register
which identifies NXP as the IC manufacturer. This register is included in the factory
programmed OTP array error detection.
This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming Mode
when ENDINIT is not set. See Section 11.2.10 for details on the register read process for
this register.
Table 181.ꢀIC manufacturer identification register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$C2
ICMFGID
0
0
0
0
0
0
1
0
11.2.41 Part number register
The part number registers are factory programmed OTP registers which include the
numeric portion of the device part number. These registers are included in the factory
programmed OTP array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming
Mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for these registers.
Table 182.ꢀPart number register
Location
Bit
Address
$C4
Register
PN0
7
6
5
4
3
2
1
0
PN0[7:0]
PN1[7:0]
$C5
PN1
Table 183.ꢀPart number: Protocol type
PN1[7:4]
Pinout
Protocol type
User Selectable
SPI32
0
Standard
1
2
3
DSI3
PSI5
4
I2C
5 - 7
8
RESERVED
User Selectable
SPI32
Alternative
9
10
DSI3
11
PSI5
12
I2C
13 - 15
RESERVED
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Table 184.ꢀPart number: Axis
PN1[3:0]
Channel 0 axis
Channel 1 axis
0
RESERVED
1
RESERVED
RESERVED
2
3
X
X
Y
Z
4
5
6
RESERVED
RESERVED
7
Y
Z
8 - 15
RESERVED
Table 185.ꢀPart number: Channel 0 range
PN0[7:4]
Channel 0 range
0
RESERVED
RESERVED
Medium g
High g
1
2
3
4 - 15
RESERVED
Table 186.ꢀPart number: Channel 1 range
PN0[3:0]
Channel 1 range
RESERVED
RESERVED
Medium g
0
1
2
3
High g
4 - 15
RESERVED
11.2.42 Device serial number registers
The serial number registers are factory programmed OTP registers which include the
unique serial number of the device. Serial numbers begin at 1 for all produced devices
in each lot and are sequentially assigned. Lot numbers begin at 1 and are sequentially
assigned. No lot will contain more devices than can be uniquely identified by the 14-bit
serial number. Depending on lot size and quantities, all possible lot numbers and serial
numbers may not be assigned. These registers are included in the factory programmed
OTP array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming
mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for these registers.
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Table 187.ꢀDevice serial number registers
Location
Bit
Address
$C6
Register
SN0
7
6
5
4
3
2
1
0
SN[7:0]
SN[15:8]
SN[23:16]
SN[31:24]
$C7
SN1
$C8
SN2
$C9
SN3
$CA
SN4
SN[39:36] = DEVICE_REV[3:0]
SN[35:32]
Table 188 shows an example serial number decoding:
Table 188.ꢀExample serial number decoding
Serial number
Full serial number
Stored Data Format
Serial Number Mapping
Example SN (Hex)
SN4
SN3
SN2
SN1
SN0
Serial Number within a lot
Test ID
1
Lot Number
0
0
0
5
2
0
0
5
0
Example SN (Binary)
Example Device Rev
Example Lot Number
Example Serial Number
00
01
00
00
00
00
00
00
01
01
00
10
00
00
00
00
01
01
00
00
4'b0000 = 0x0 = 0d
4'b00 00 00 00 00 00 01 01 00 10 00 = 0x000148 = 328d
14'b00 00 00 01 01 00 00 = 0x0050 = 80d
11.2.43 ASIC wafer ID registers
The ASIC wafer ID registers are factory programmed OTP registers which include the
wafer number, wafer X, and Y coordinates and the wafer lot number for the device ASIC.
These registers are included in the factory programmed OTP array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming
mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for these registers.
Table 189.ꢀASIC wafer ID registers
Location
Bit
Address
$CB
Register
7
6
5
4
3
2
1
0
ASICWFR#
ASICWFR_X
ASICWFR_Y
ASICWLOT_L
ASICWLOT_H
ASICWFR#[7:0]
$CC
ASICWFR_X[7:0]
ASICWFR_Y[7:0]
ASICWLOT_L[7:0]
ASICWLOT_H[7:0]
$CD
$D0
$D1
11.2.44 Transducer wafer ID registers
The transducer wafer ID registers are factory programmed OTP registers which include
the wafer number, wafer X, and Y coordinates and the wafer lot number for the device
transducers. The upper 3 bits of the TRNSWFR# register include a transducer and
assembly revision counter. These registers are included in the factory programmed OTP
array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming
mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for these registers.
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Table 190.ꢀTransducer wafer ID registers
Location
Bit
Address
$D2
Register
7
6
5
4
3
2
1
0
TRNS1WFR_X
TRNS1WFR_Y
TRNS1LOT_L
TRNS1LOT_H
TRNS1WFR#
TRNS1WFR_X[7:0]
TRNS1WFR_Y[7:0]
TRNS1LOT_L[7:0]
TRNS1LOT_H[7:0]
$D3
$D4
$D5
$DA
TRNS_ASSY_REV[2:0]
TRNS1WFR#[4:0]
11.2.45 User data registers (USERDATA_0 - USERDATA_E)
User data registers are user programmable OTP registers which contain user-specific
information. These registers are included in the user programmed OTP array error
detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
Programming Mode when ENDINIT is not set. See Section 11.2.10 for details on the
register read process for these registers.
Table 191.ꢀUser data registers (USERDATA_0 - USERDATA_E)
Location
Bit
Address
$E0
Register
7
6
5
4
3
2
1
0
USERDATA_0
USERDATA_1
USERDATA_2
USERDATA_3
USERDATA_4
USERDATA_5
USERDATA_6
USERDATA_7
USERDATA_8
USERDATA_9
USERDATA_A
USERDATA_B
USERDATA_C
USERDATA_D
USERDATA_E
USERDATA_0[7:0]
USERDATA_1[7:0]
USERDATA_2[7:0]
USERDATA_3[7:0]
USERDATA_4[7:0]
USERDATA_5[7:0]
USERDATA_6[7:0]
USERDATA_7[7:0]
USERDATA_8[7:0]
USERDATA_9[7:0]
USERDATA_A[7:0]
USERDATA_B[7:0]
USERDATA_C[7:0]
USERDATA_D[7:0]
USERDATA_E[7:0]
$E1
$E2
$E3
$E4
$E5
$E6
$E7
$E8
$E9
$EA
$EB
$EC
$ED
$EE
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
11.2.45.1 PSI5 initialization phase 2 data transmissions of user data
In PSI5 Mode, the values of the user data registers are transmitted in Initialization phase
2 as shown in Table 192. See Section 13.4.2.1 for details on the PSI5 Initialization Phase
2 Transmissions.
Table 192.ꢀPSI5 initialization phase 2 data transmissions of user data
Location
Bit
Address
$E0
Register
7
6
5
4
3
2
1
0
USERDATA_0
USERDATA_1
USERDATA_2
USERDATA_3
USERDATA_4
USERDATA_5
Channel 1 F1: D1
Channel 0 F1: D1
$E1
Channel 0 F3: D5
Channel 0 F4: D7
Channel 0 F5: D9
Channel 0 F6: D11
Channel 0 F7: D13
Channel 0 F3: D4
Channel 0 F4: D6
Channel 0 F5: D8
Channel 0 F6: D10
Channel 0 F7: D12
$E2
$E3
$E4
$E5
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Table 192.ꢀPSI5 initialization phase 2 data transmissions of user data...continued
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$E6
USERDATA_6
USERDATA_7
USERDATA_8
PSI5_INIT2_D19 = 0, Channel 0 F9: D32
Channel 0 F7: D14
PSI5_INIT2_D19 = 1, Ch 0 F9: D32 = Ch 0 F9: D19 = Ch 1 F9: D19
$E7
$E8
Channel 0 F8: D16
Channel 0 F8: D15 = Channel 1 F8: D15
Channel 0 F8: D17 = Channel 1 F8: D17
Channel 0 F8: D16 = Channel 1 F8: D16
Channel 0 F8: D18
Channel 0 F8: D18 = Channel 1 F8: D18
$E9
$EA
$EB
$EC
$ED
$EE
USERDATA_9
USERDATA_A
USERDATA_B
USERDATA_C
USERDATA_D
USERDATA_E
Channel 1 F3: D5
Channel 1 F4: D7
Channel 1 F5: D9
Channel 1 F6: D11
Channel 1 F7: D13
Channel 1 F3: D4
Channel 1 F4: D6
Channel 1 F5: D8
Channel 1 F6: D10
Channel 1 F7: D12
Channel 1 F7: D14
PSI5_INIT2_D19 = 0, Channel 1 F9: D32
PSI5_INIT2_D19 = 1, Ch 1 F9: D32 = Ch 0 F9: D20 = Ch 1 F9: D20
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
11.2.46 User data registers (USERDATA_10 - USERDATA_1E)
User data registers are user programmable OTP registers which contain user-specific
information. These registers are included in the user programmed OTP array error
detection.
These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5
programming mode when ENDINIT is not set. See Section 11.2.10 for details on the
register read process for these registers.
Table 193.ꢀUser data registers (USERDATA_10 - USERDATA_1E)
Location
Bit
Address
$F0
Register
7
6
5
4
3
2
1
0
USERDATA_10
USERDATA_11
USERDATA_12
USERDATA_13
USERDATA_14
USERDATA_15
USERDATA_16
USERDATA_17
USERDATA_18
USERDATA_19
USERDATA_1A
USERDATA_1B
USERDATA_1C
USERDATA_1D
USERDATA_1E
USERDATA_10[7:0]
USERDATA_11[7:0]
USERDATA_12[7:0]
USERDATA_13[7:0]
USERDATA_14[7:0]
USERDATA_15[7:0]
USERDATA_16[7:0]
USERDATA_17[7:0]
USERDATA_18[7:0]
USERDATA_19[7:0]
USERDATA_1A[7:0]
USERDATA_1B[7:0]
USERDATA_1C[7:0]
USERDATA_1D[7:0]
USERDATA_1E[7:0]
$F1
$F2
$F3
$F4
$F5
$F6
$F7
$F8
$F9
$FA
$FB
$FC
$FD
$FE
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
11.2.47 Lock and CRC registers
The lock and CRC registers are automatically programmed OTP registers which include
the lock bit, the block identifier, and the block OTP array CRC use for error detection.
These registers are automatically programmed when the corresponding data array
is programmed to OTP using the Write OTP Enable register as documented in
Section 11.2.7.
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Table 194.ꢀLock and CRC registers
Location
Bit
Address
Register
7
6
0
0
5
4
0
0
3
2
1
0
$5F
CRC_UF2
LOCK_UF2
0
CRC_UF2[3:0]
Unprogrammed OTP Value
0
0
0
0
0
0
$AF
$BF
$CF
$DF
$EF
CRC_F_A
Reset Value
CRC_F_B
Reset Value
CRC_F_C
Reset Value
CRC_F_D
Reset Value
CRC_F_E
LOCK_F_A
REGA_BLOCKID[2:0]
CRC_F_A[3:0]
Varies
1
0
0
0
1
0
0
0
1
0
1
0
0
0
LOCK_F_B
REGB_BLOCKID[2:0]
CRC_F_B[3:0]
Varies
1
1
LOCK_F_C
REGC_BLOCKID[2:0]
CRC_F_C[3:0]
Varies
1
1
LOCK_F_D
REGD_BLOCKID[2:0]
CRC_F_D[3:0]
Varies
1
0
LOCK_F_E
REGE_BLOCKID[2:0]
CRC_F_E[3:0]
Unprogrammed OTP Value
$FF CRC_F_F
Unprogrammed OTP Value
0
0
0
0
0
0
0
0
0
0
LOCK_F_F
0
REGF_BLOCKID[2:0]
0
CRC_F_F[3:0]
Table 195 shows the state of the lock bits, the block identifiers, and the CRC for each
register block before and after programming.
Table 195.ꢀLock bit, block identifier, and CRC states
Register
Lock bit
Block identifier
CRC
block address
bit[7]
bits[6:4]
bits[3:0]
Before
After
Before
After
Before
After
programming
programming
programming
programming
programming
programming
UF2
$Ax
$Bx
$Cx
$Dx
$Ex
$Fx
0
0
0
0
0
0
0
1
1
1
1
1
1
1
000
N/A
N/A
N/A
N/A
000
000
000
001
010
011
100
101
110
0000
Varies
Varies
Varies
Varies
Varies
Varies
Varies
N/A
N/A
N/A
N/A
0000
0000
11.2.48 Reserved registers
A register read command to a reserved register or a register with reserved bits will result
in a valid response. The data for reserved bits may be logic 0 or logic 1.
A register write command to a reserved register or a register with reserved bits will
execute and result in a valid response. The data for the reserved bits may be logic 0 or
logic 1. A write to the reserved bits must always be '0' for normal device operation and
performance.
11.2.49 Invalid register addresses
A register read command to a register address outside the addresses listed in
Section 11.1 will result in a valid response. The data for the registers will be '0x00'.
A register write command to a register address outside the addresses listed in
Section 11.1 will not execute, but will result in a valid response. The data for the registers
will be '0x00'.
A register write command to a read-only register will not execute, but will result in a valid
response. The data for the registers will be the current contents of the register.
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11.3 OTP and read/write register array CRC verification
11.3.1 NXP OTP registers
The following registers are internal OTP registers. These registers are verified by the
OTP ECC as well as an independent 4-bit CRC for each 16 byte block.
Table 196.ꢀMemory type code: NXP OTP register
Memory type codes
F
User readable register with OTP
11.3.2 User OTP only registers
The following registers are user OTP registers. These registers are verified by the OTP
ECC as well as an independent 4-bit CRC for each 16 byte block. The CRC verification
uses a generator polynomial of g(x) = X4 + X3 + 1, with a seed value = '0000'. The bits
are fed into the CRC calculation from right to left (MSB first) and from top to bottom
(lowest address first) in the register map.
Table 197.ꢀMemory type code: User OTP register
Memory type codes
UF0
UF1
One time user programmable OTP region 0
One time user programmable OTP region 1
11.3.3 OTP modifiable registers
The following registers are user read/write registers as well as OTP registers with
writable mirror registers. The OTP registers are verified by the OTP ECC as well as an
independent 4-bit CRC stored in the CRC_UF2 register.
The values read from OTP can be over-written while ENDINIT is not set. Once ENDINIT
is set, the writable registers (all registers in the R/W and UF2 regions with the exception
of the DEVLOCK_WR register) are verified by an additional continuous 4-bit CRC that is
calculated on the entire array. The CRC verification uses a generator polynomial of g(x) =
X4+X3+1, with a seed value = '0000'. The bits are fed into the CRC calculation from right
to left (MSB first) and from top to bottom (lowest address first) in the register map.
Registers verified by the OTP CRC:
Table 198.ꢀMemory type code: CRC verified OTP registers
Memory type codes
UF2
One time user programmable OTP region 3 with modifiable mirror registers
Registers verified by the ENDINIT calculated CRC:
Table 199.ꢀMemory type code: ENDINIT CRC verified OTP registers
Memory type codes
UF2
R/W
One time user programmable OTP region 3 with modifiable mirror registers
User writable register, with the exception of the DEVLOCK_WR register
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11.4 Voltage regulators
The device derives its internal supply voltage from the VCC/BUS_I and VSS pins. The
internal regulators are supplied by a buffer regulator (VBUF) to provide immunity from
EMC and supply dropouts on BUS_I. An external filter capacitor is required for VBUF, as
shown in Section 6.
The voltage regulator module includes voltage monitoring circuitry which holds the
device in reset following power-on until the internal voltages have increased above the
under-voltage detection thresholds. The voltage monitor asserts internal reset when the
external supply or internally regulated voltages fall below the under-voltage detection
thresholds. A reference generator provides a reference voltage for the ΣΔ converter.
BUS_I
V
V
BUF
REF
VOLTAGE
REGULATOR
V
BUF
V
REGA
VOLTAGE
REGULATOR
V
REGA
BIAS
GENERATOR
OSCILLATOR
TRIM
TRIM
V
REF
BANDGAP
REFERENCE
TRIM
C2V
V
REF_MOD
REFERENCE
GENERATOR
Σ
CONVERTER
V
BUF
OTP
ARRAY
V
V
REG
REF
VOLTAGE
REGULATOR
DIGITAL
LOGIC
DSP
BUS_I
COMPARATOR
BUSI_UV_ERR
VBUF_UV_ERR
V
BUF
COMPARATOR
COMPARATOR
COMPARATOR
V
REG
POR
V
REGA
V
REF
aaa-030605
Figure 11.ꢀVoltage regulation and monitoring
11.4.1 VBUF regulator capacitor and capacitor monitor
In DSI3 and PSI5 modes, the buffer regulator requires an external capacitor between the
VBUF pin and the VSS pin. Section 6 shows the recommended types and values for each
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of these capacitors. A monitor circuit is incorporated to ensure predict-able operation if
the connection to the external VBUF capacitor becomes open. If the external capacitor is
not present, the regulator voltage will fall below the threshold specified in Section 10.4
causing the VBUF_ERR bit to be set in the DEVSTAT1 register.
The VBUF capacitor is tested synchronous to the protocol transmissions as shown in the
diagrams in Figure 12, Figure 13, and Figure 14.
11.4.1.1 VBUF capacitance monitor timing, DSI3
t
t
D_CAPTEST
D_CAPTEST
BUS_I
t
t
CAPTST_TIME
CAPTST_TIME
Cap_Test
capacitor present
capacitor open
V
BUF
BUF_UV_f
VBUF_ERR
V
time
aaa-030606
Figure 12.ꢀVBUF capacitor monitor timing, DSI3
11.4.1.2 VBUF capacitance monitor timing, PSI5
t
t
P_CAPTEST
P_CAPTEST
BUS_I
t
t
CAPTST_TIME
CAPTST_TIME
Cap_Test
capacitor present
capacitor open
V
BUF
BUF_UV_f
VBUF_ERR
V
time
aaa-030607
Figure 13.ꢀVBUF capacitor monitor timing, PSI5 synchronous mode
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11.4.1.3 VBUF capacitance monitor timing, PSI5 asynchronous mode
t
t
A_CAPTEST
A_CAPTEST
I
BUS_I
t
t
CAPTST_TIME
CAPTST_TIME
Cap_Test
capacitor present
capacitor open
V
BUF
BUF_UV_f
VBUF_ERR
V
time
aaa-030608
Figure 14.ꢀVBUF capacitor monitor timing, psi5 asynchronous mode
11.4.2 BUS_I, VBUF, VREG, VREGA, undervoltage monitor
A circuit is incorporated to monitor the BUS_I supply voltage and the internally regulated
voltages, VBUF, VREG, and VREGA. If any of the voltages fall below the specified under-
voltage thresholds in Section 10.4, the device reacts as described:
• DSI3
– If any supply falls below the specified threshold during a command transmission in
Command and Response Mode, the command is ignored, and no DSI3 response
transmission occurs. Once the supply returns above the threshold, the device will
resume decoding commands as specified in Section 11.2.2.5.
– If any supply falls below the specified threshold during a response transmission in
Command and Response Mode, the response is terminated. No attempt is made to
resend the response. Once the supply returns above the threshold, the device will
resume decoding commands as specified in Section 11.2.2.5.
– If any supply falls below the specified threshold during a command transmission in
Periodic Data Collection Mode, the command is ignored and no periodic response
occurs during that period. Once the supply returns above the threshold, the device
will resume periodic transmissions in response to commands as specified in
Section 11.2.2.5. Any partially received Background Diagnostic Mode command
is flushed and the device will begin decoding a new Background Diagnostic Mode
command.
– If any supply falls below the specified threshold during a periodic response
transmission in Periodic Data Collection Mode, the response is terminated. No
attempt is made to resend the response. Once the supply returns above the
threshold, the device will resume periodic transmissions in response to commands
as specified in Section 11.2.2.5. Any partially received Background Diagnostic
Mode command is flushed and the device will begin decoding a new Background
Diagnostic Mode command.
– If any supply falls below the specified threshold during a Background Diagnostic
Mode response transmission in Periodic Data Collection Mode, the response is
terminated. No attempt is made to resend the response. Once the supply returns
above the threshold, the device will resume periodic transmissions in response
to commands as specified in Section 11.2.2.5. Any partially received Background
Diagnostic Mode command is flushed and the device will begin decoding a new
Background Diagnostic Mode command.
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• PSI5
– If any supply falls below the specified threshold, all PSI5 transmissions are
terminated for the present sync pulse or asynchronous transmission cycle. Once the
supply returns above the threshold, the device will resume responses as specified in
Section 11.2.2.5.
• SPI
– If any supply falls below the specified threshold, SPI responses are terminated. Once
the supply returns above the threshold, the device will resume command decode and
response transmissions as specified in Section 11.2.2.5.
• I2C
– If any supply falls below the specified threshold, I2C transactions are terminated.
Once the supply returns above the threshold, the device will resume responses as
specified in Section 11.2.2.5.
See Figure 15 for an example of a supply line interruption during a DSI3 or PSI5
response.
BUS_I micro-cut occurs
BUS_I
BUS_I undervoltage detected
V
BUF
V
REG
V
REGA
response terminated
I
BUS_I
POR
time
aaa-030609
Figure 15.ꢀBUS_I micro-cut response (DSI3 or PSI5)
11.5 Internal oscillator
The device includes a factory trimmed oscillator as specified in Section 10.20.
11.5.1 Oscillator training
The device includes a feature to train the oscillator to a tighter accuracy than the factory
trimmed capability assuming the system master has a tighter oscillator accuracy than the
slave factory trimmed capability. This feature can be enabled for all modes: DSI3, PSI5,
SPI, and I2C.
Note: Do not use oscillator training in systems that employ spread spectrum
communication methods to reduce emissions.
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11.5.1.1 DSI3 oscillator training
Oscillator training is enabled if the CK_CAL_EN bit is set in the TIMING_CFG register
and is accomplished by verifying the timing of periodic transmissions from the master
against the values stored in the CRM_PER[1:0] and PDCM_PER[2:0] bits of the user
read/write register array. The master programs the intended Periodic Data Collection
Mode command period into the PDCM_PER[2:0] bits and the intended Command
and Response Mode command period into the CRM_PER[1:0] bits. The device then
calculates the number of transmission periods for every 4 ms (nCRM_PER_4ms_TYP and
nPDCM_PER_4ms_ TYP).
-
In Command and Response Mode, oscillator training is completed over 4 ms periods
if and only if the CK_CAL_EN bit is set and the Command and Response Mode period
is between 500 µs and 4 ms, inclusive. The following procedure is used to train the
oscillator (See Figure 16):
1. The device counts the number of oscillator cycles in nCRM_PER_4ms_TYP periods
(nOSC_4ms).
2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made.
Otherwise, no adjustment is made.
a. If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency
target is decreased by OscTrainRES
b. If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target
is increased by OscTrainRES
.
.
c. The oscillator frequency target value is changed at the end of the command
blocking time for the command ending the nCRM_PER_OSC calculation.
If the CK_CAL_EN bit is cleared after oscillator training has already been initiated,
the state of the oscillator is determined by the state of the CK_CAL_RST bit in the
TIMING_CFG register. If the CK_CAL_RST bit is cleared, the last adjustment value for
the oscillator is maintained. If the CK_CAL_RST bit is set, the oscillator is reset to its
untrained value with the untrained tolerance specified in Section 10.20.
Command
t
CmdBlock_CRM
Response
one CRM period
4 ms = n
CRM_PER_4ms_TYP
oscillator
adjustment
new oscillator
count starts
n
OSC_4ms
time
aaa-030610
Figure 16.ꢀCommand and response mode oscillator training timing diagram
In Periodic Data Collection Mode, oscillator training is completed over 4 ms periods if
the CK_CAL_EN bit is set. The following procedure is used to train the oscillator (See
Figure 17):
1. The device counts the number of oscillator cycles in nPDCM_PER_4ms_TYP periods
(nOSC_4ms).
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2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made.
Otherwise, no adjustment is made.
a. If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency
target is decreased by OscTrainRES
b. If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target
is increased by OscTrainRES
.
.
c. The oscillator frequency target value is changed at the end of the command
blocking time for the command ending the nPDCM_PER_OSC calculation.
Command
t
CmdBlock_PDCM
Response
one PDCM period
4 ms = n
PDCM_PER_4ms_TYP
oscillator
adjustment
new oscillator
count starts
n
OSC_4ms
time
aaa-030611
Figure 17.ꢀPeriodic data collection mode oscillator training timing diagram
11.5.1.2 PSI5 oscillator training
Oscillator training is enabled if the CK_CAL_EN bit is set in the TIMING_CFG register
and is accomplished by verifying the timing of periodic transmissions from the master
against the values stored in the PDCM_PER[2:0] bits of the user read/write register array.
The sync pulse period is pre-programmed into the PDCM_PER[2:0] bits. The device then
calculates the number of transmission periods for every 4 ms (nPSI5_PER_4ms_TYP).
Oscillator training is completed over 4 ms periods if the CK_CAL_EN bit is set. The
following procedure is used to train the oscillator (see Figure 18):
1. The device counts the number of oscillator cycles in nPSI5_PER_4ms_TYP periods
(nOSC_4ms).
2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made.
Otherwise, no adjustment is made.
a. If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency
target is decreased by OscTrainRES
b. If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target
is increased by OscTrainRES
.
.
c. The oscillator frequency target value is changed at the end of the command
blocking time for the command ending the nPDCM_PER_OSC calculation.
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Command
t
PDCM_CMD_B
Response
one PSI5 period
4 ms = n
PDCM_PER_4ms_TYP
oscillator
adjustment
new oscillator
count starts
n
OSC_4ms
time
aaa-030612
Figure 18.ꢀPSI5 oscillator training timing diagram
Notes:
• In order to benefit from the PSI5 oscillator training accuracy improvements, the
oscillator must be trained prior to data transmissions in Initialization phase 2. For this
reason, if oscillator training is enabled in PSI5 mode, the device will not respond to
sync pulses during initialization phase 1, but oscillator training will be enabled tRS_PM
after reset.
11.5.1.3 SPI oscillator training
Oscillator training is enabled if the CK_CAL_EN bit is set in the TIMING_CFG register
and is accomplished by verifying the timing of periodic SOURCEID_0 sensor data
request SPI commands from the master against the value stored in the PDC-M_PER[2:0]
bits of the user read/write register array. The master programs the intended command
period into the PDC-M_PER[2:0] bits. The device then calculates the number of
transmission periods for every 4 ms (nSPI_PER_4ms_TYP).
In SPI Mode, oscillator training is completed over 4 ms periods if the CK_CAL_EN bit is
set. The following procedure is used to train the oscillator:
1. The device counts the number of oscillator cycles in nSPI_PER_4ms_TYP periods
(nOSC_4ms).
2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made.
Otherwise, no adjustment is made.
a. If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency
target is decreased by OscTrainRES
b. If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target
is increased by OscTrainRES
c. The oscillator frequency target value is changed.
.
.
11.5.1.4 I2C oscillator training
Oscillator training is enabled if the CK_CAL_EN bit is set in the TIMING_CFG register
and is accomplished by verifying the timing of periodic I2C reads of the SNSDATA0_L
register from the master against the value stored in the PDCM_PER[2:0] bits of the user
read/write register array. The master programs the intended command period into the
PDCM_PER[2:0] bits. The device then calculates the number of transmission periods for
every 4 ms (nSPI_PER_4ms_TYP).
In I2C mode, oscillator training is completed over 4 ms periods if the CK_CAL_EN bit is
set. The following procedure is used to train the oscillator:
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1. The device counts the number of oscillator cycles in nI2C_PER_4ms_TYP periods
(nOSC_4ms).
2. nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training
window (OscTrainWIN) specified in Section 10.20, an oscillator adjustment is made.
Otherwise, no adjustment is made.
a. If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency
target is decreased by OscTrainRES
b. If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target
is increased by OscTrainRES
c. The oscillator frequency target value is changed.
.
.
11.5.2 Oscillator training error handling
If oscillator training is enabled by the user, but the conditions are not correct to complete
oscillator training, the OSC-TRAIN_ERR bit is set in the DEVSTAT register. The following
conditions will result in the OSCTRAIN_ERR bit being set.
• The CLK_CAL_EN bit in the TIMING_CFG register is set and the measured period
(nOSC_4ms) for any mode is outside the Oscillator Training Window (OscTrainWIN).
• The result of the comparison is filtered with an up and down counter.
• If nOSC_4ms is outside the oscillator training window, the counter is incremented.
• If nOSC_4ms is inside the oscillator training window, the counter is decremented.
• If the counter reaches the OSCTRAIN_ERRCNT setting in the TIMING_CFG2 register,
the OSCTRAIN_ERR bit is set.
• The up and down counter has a maximum value of 127 and a minimum value of 0.
• The Command and Response Mode period established by the PDCM_PER and
CRM_PER settings does not fall within the 500 µs to 4 ms window.
• The Command and Response Mode period established by the PDCM_PER and
CRM_PER settings is not a whole number divisor of 4 ms.
11.6 Inertial sensor signal path
11.6.1 Inertial sensor transducer
The device transducer is an overdamped mass-spring-damper system defined by the
following transfer function:
(2)
Where:
ζ
=
=
Damping Ratio
ωn
Natural Frequency =
f
2∗Π∗ n
See Section 10.19 for transducer parameters.
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11.6.2 Inertial sensor self-test interface
The analog self-test interface applies a voltage to the g-cell, causing deflection of the
proof mass. The resulting sensor data can be compared against the values stored in the
Self-test Deflection Registers (See Section 11.2.37). The self-test interface is controlled
through register write operations to the ST_CTRL[3:0] bits in the CHx_CFG_U5 register
described in Section 11.2.27. A diagram of the self-test interface is shown in Figure 19.
The following signals are all
selected by the ST_CTRL[3:0] bits
SELFTEST ENABLE
- SELFTEST ENABLE
SELFTEST POLARITY
- SELFTEST POLARITY
- High/Low Self Test Select
High/Low Self Test Select
+
STV_HIGH
STV_LOW
SELFTEST
VOLTAGE
TRANSDUCER
GENERATOR
-
ENDINIT
SELFTEST ENABLE
SELFTEST POLARITY
aaa-030613
Figure 19.ꢀSelf-test interface
Two self-test voltages are available for each device range. The self-test voltage is
selected via the ST_CTRL[3:0] bits.
Self-test can be verified via the following methods:
11.6.2.1 Raw self-test deflection verification
In DSI3 mode, SPI mode or I2C mode, the raw self-test deflection can be verified against
raw self-test limits in Section 10.7.
11.6.2.2 Delta self-test deflection verification
In DSI3 mode, SPI mode or I2C mode, the raw self-test deflection can be verified against
the nominal temperature self-test deflection value recorded at the time the device was
produced. The production self-test deflection is stored in the CHx-_STy_z register as
defined in Section 11.2.37. The Delta Self-test Deflection limits can then be determined
by Equation 3 and Equation 4:
(3)
Note: This value is truncated.
(4)
Note: This value is rounded up.
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Where:
ΔSTACC
=
=
The accuracy of the self-test deflection relative to the stored deflection as
specified in Section 10.8.
STDATA
The value stored in the appropriate CHx_STy_z register as defined in
Section 11.2.37.
11.6.2.3 Startup digital self-test
In DSI3 mode, SPI mode or I2C mode, during device initialization (ENDINIT not set),
the user can activate a digital self-test by writing to the ST_CTRL[3:0] bits in the
CHx_CFG_U5 register. The digital self-test inputs a known signal stream into the front
end of the DSP. After a delay defined by the low-pass filter selected, the output sensor
data reaches a fixed value which can be verified by the user. The digital self-test values
are listed in Section 11.2.27.1.
11.6.2.4 Fixed pattern self-test
In DSI3 mode, SPI mode or I2C mode, during device initialization (ENDINIT not set),
the user can activate a fixed pattern self-test by writing to the ST_CTRL[3:0] bits in the
CHx_CFG_U5 register. Fixed pattern self-tests force the DSP output to a set of known
values, enabling the user to verify each bit of the sensor data. The fixed pattern self-test
values are listed in Section 11.2.27.1.
11.6.2.5 PSI5 automatic startup self-test procedure
Figure 20 shows the PSI5 self-test procedure which is run automatically at startup on
each channel if the device is a PSI5 device. The minimum gain settings are used for this
procedure: U_SNS_SHIFT = '00', U_SNS_MULT = 0x00.
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PS15 Internal self-test
Complete Internal Fixed
Capacitor self-test
no
Self-test failed.
SET ST_ERROR
Fixed Cap Test Pass?
yes
Delay t
PSI5ST_START
Exit
Suspend the Offset
Cancellation Filter
ST Disabled
Sample DSP Output
yes
no
Enable Positive self-test
Delay 8.192 ms
Captured 16 Sensor
Readings?
Delay 512 µs
Sample DSP Output
no
Captured 16 Sensor
Readings?
Delay 512 µs
yes
ST+ within
Specification Limits?
no
Calculate ST+ =
Set REPEAT_ST
STPOS
- Offset
AVG
AVG
yes
Disable self-test
Delay 8.192 ms
Sample DSP Output
yes
no
Enable Negative self-test
Delay 8.192 ms
Captured 16 Sensor
Readings?
Delay 512 µs
Sample DSP Output
no
Captured 16 Sensor
Readings?
Delay 512 µs
yes
ST- within
Specification Limits?
no
Calculate ST- =
Set REPEAT_ST
STNEG
- Offset
AVG
AVG
yes
no
yes
REPEAT_ST
Set?
Increment ST_RPT
ST_RPT at max?
yes
no
Self-test failed.
SET ST_ERROR
Disable self-test
Delay 8.192 ms
Sample DSP Output
Exit
yes
Captured 16
Sensor Readings?
no
Enable Digital self-test
Delay 19.5 ms
Delay 512 µs
Sample DSP Output
no
DST
within Specification
Limits?
no
yes
Disable self-test
Reset Offset Cancellation
Increment ST_RPT
ST_RPT at max?
yes
Increment ST_RPT
Delay 106 ms
Self-test failed.
SET ST_ERROR
no
no
OC - within
ST_RPT at max?
yes
Programmed Limits?
Exit
yes
Self-test failed.
SET ST_ERROR
Self-test passed.
Clear ST_ERROR
Exit
Exit
aaa-030615
Figure 20.ꢀPSI5 self-test procedure
If the ST_ERROR flag in the CHx_STAT register is set once this test is complete, the
device will exit PSI5 initialization phase 2 with a self-test error and the self-test error
message are transmitted instead of sensor data. In this case, the ST_ER-ROR bit can
only be cleared by a device reset.
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11.6.3 Inertial sensor ΣΔ converter
A second order sigma delta modulator converts the differential capacitance of the
transducer to a data stream that is input to the DSP. The sigma delta modulator operates
at a frequency of 1 MHz. A simplified block diagram is shown in Figure 6.
first
integrator
second
integrator
1-Bit
quantizer
transducer
V
X
α
1 =
α
C
TOP
BOT
2
-1
Z
-1
Z
C
INT1
+
Y(Z) = {0, 1}
+
-1
-1
1 - Z
1 - Z
C
-
-
ADC
DAC
β
1
β
2
V = 0 V, V
REF
aaa-030616
Figure 21.ꢀΣΔ converter block diagram
11.6.4 Inertial sensor digital signal processor
A digital signal processor (DSP) is used to perform signal filtering and compensation. A
diagram illustrating the signal processing flow within the DSP is shown in Figure 22.
selectable output types
data type 0
data type 1
- F with interpolation
- F without interpolation
- M with interpolation
yes (01)
no
no
no
yes (100)
no
- M without interpolation
- F - K with interpolation
- F - K without interpolation
- M - K with interpolation
- M - K without interpolation
- F - L with interpolation
- F - L without interpolation
- M - L with interpolation
- M - L without interpolation
yes (01)
yes (00)
no
yes (001)
no
yes (000)
no
yes (000)
no
yes (100)
no
no
yes (01)
yes (01)
no
no
yes (01)
yes (000)
∑
OUT
A
SINC
FILTER
IIR
LPF
USER
SENSE
SCALING
B
C
D
E
F
DIGITAL
CLIPPING
TRIM
Q
INTERPOLATION
M
MOVING
AVERAGE
DSP
R
OUT
OUTPUT
SCALING
+
-
P
OFFSET
CANCELLATION
RATE LIMIT
H
J
K
DOWN
SAMPLE
DOWN
SAMPLE
OFFSET
LPF
OFFSET
ARMING
MONITOR
FUNCTION
aaa-030617
Figure 22.ꢀSignal chain diagram
Table 200.ꢀSignal chain diagram legend
Description
Sample Time Data
Sign
Over Signal Signal
range width margin
Typical
block
Reference
width
(µs)
(Bits)
(Bits)
(Bits) (Bits)
(Bits)
NA
NA
11
latency
2.5 µs
22.5 µs
N/A
A
B
C
D
E
ΣΔ
1
1
1
1
1
1
1
NA
NA
2
1
Section 11.6.3
SINC Filter
Trim
16, 32, 64
16, 32, 64
16, 32, 64
16, 32, 64
23
32
32
32
21
18
18
18
Section 11.6.4.1
Section 11.6.4.2
Section 11.6.4.3
Section 11.6.4.4
Digital Clipping
Low-pass filter
2
11
N/A
2
11
Filter
Dependent
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Table 200.ꢀSignal chain diagram legend...continued
Description
Sample Time Data
Sign
Over Signal Signal
range width margin
Typical
block
Reference
width
(µs)
(Bits)
(Bits)
(Bits) (Bits)
(Bits)
latency
F
H
J
User Scaling
16, 32, 64
32, 64, 128
256
32
32
32
16
16
24
1
1
1
1
1
1
2
NA
NA
2
18
31
31
11
11
18
11
N/A
Section 11.6.4.5
Section 11.6.4.7
Section 11.6.4.6
Section 11.6.4.6
Section 11.6.4.6
Section 11.6.4.7
Down Sample
NA
NA
2
N/A
Secondary Down Sample
Offset low-pass filter
Offset Rate Limiting
N/A
K
L
256
N/A
256
2
2
N/A
M Moving Average Filter
32, 64, 128
2
3
Filter
Dependent
P
Offset Subtraction
32, 64, 128
1, 2, 4
24
24
18
1
1
2
2
18
18
3
3
N/A
Section 11.6.4.6
Q Interpolation
tSigChainXX Section 11.6.4.8
N/A Section 11.6.4.9
R
Output Range Selection
1, 2, 4
User Selectable
11.6.4.1 Decimation sinc filter
The output of the ΣΔ modulator is decimated and converted to a parallel value by a third
order Sinc Filter with a decimation ratio of 16.
(5)
aaa-030618
0
magnitude
(dB)
-20
-40
frequency: 64.08691
magnitude: -96.35657
-60
-80
-100
0
200
400
600
800
1000
frequency (kHz)
Figure 23.ꢀSinc filter response 3rd order sinc filter magnitude response
11.6.4.2 Signal trim and compensation
The device includes digital trim to compensate for sensor offset, sensitivity, and non-
linearity over temperature. Equation 6, Equation 7, Equation 8, and Equation 9 are used
for the trim compensation.
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(6)
(7)
(8)
(9)
Table 201.ꢀSignal trim and compensation variable descriptions
Variable Description
name
Range
Variable Resolution
size
(Real)
(Real)
(Bits)
A0
Offset Compensation
–1.0 to +1.0
–1.0 to +1.0
–1.0 to +1.0
–1.0 to +1.0
–1.0 to +1.0
–1.0 to +1.0
–1.0 to +1.0
–1.0 to +1.0
12
12
12
12
12
12
12
12
4.8852e–04
4.8852e–04
4.8852e–04
4.8852e–04
4.8852e–04
4.8852e–04
4.8852e–04
4.8852e–04
B2
Offset Compensation with First Order Temperature Compensation
Offset Compensation with Second Order Temperature Compensation
Sensitivity Compensation
C22
B1
C12
C11
T
Sensitivity Compensation with First Order Temperature Compensation
Linearity Compensation
Temperature Sensor Digital Output Value
T25
TrimIn
Temperature Sensor Output Value stored at the Ambient Test Insertion
Output of the Sinc Filter
TrimOut Output of the Trim Block
11.6.4.3 Digital clipping
The device includes a digital clipping block to maximize the symmetry between the
positive and negative electrical dynamic range of the device. Digital clipping values are
specified in Section 10.9 and Section 10.10.
11.6.4.4 Low-pass filter
Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter.
(10)
The device provides the option for one of several low-pass filters. The filter coefficients
are selected with the LPF[3:0] bits in the CHx_CFG_U1 registers.
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The filter selection options are listed in Section 11.2.23.1. Response parameters for the
low-pass filter are specified in Section 10.18. Filter characteristics for the highest sample
rate are illustrated in Figure 24 through Figure 49.
Table 202.ꢀLPF #0 and LPF #2
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
–3 dB
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
0, 2
0000
or
00 or 01
10
400
16
32
4
839
–19.5
1.59
a0 0.003143225986084408
n11 0.0009951105668343345 d11
n12 0.002003487780064749 d12
n13 0.001008466113720278 d13
1
0010
200
1678
3356
–42.3
–66.0
3.18
6.36
–1.892328151433503
0.8954713774195870
1
n21
n22
n23
0.2516720624825626
0.4999888752940916
0.2483390622233452
d21
d22
d23
11
100
64
–1.918978239761011
0.9229853042218408
Table 203.ꢀLPF #1 and LPF #3
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
–3 dB
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
1, 3
0001
or
00 or 01
10
400
16
32
3
697
–16.6
1.49
a0
0.05189235225042199
n11 0.001629077582099646 d11
n12 0.001630351547919014 d12
1
0011
200
1394
2788
–33.5
–51.5
2.98
5.96
–0.9481076477495780
n13
n21
n22
n23
0
d13
d21
d22
d23
0
0.2500977520825902
0.4999999235890745
0.2499023243303036
1
11
100
64
–1.915847097557409
0.9191065266874253
Table 204.ꢀLPF #4
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
4
0100
00 or 01
10
325
16
32
4
856
–21.4
1.84
a0 0.0424754749983549118
n11 0.0010903775691986084 d11
1
162.5
1712
3424
–38.7
–56.8
3.68
7.36
n12
0.001089394
09255981445
d12
–0.957524538
04016113281
n13
n21
0
d13
d21
0
1
0.249887526
03530883789
11
81.25
5
64
n22
0.499999895
69187164307
d22
–1.931408762
93182373047
n23 0.2501125633716583252 d23
0.933588504
79125976562
Table 205.ꢀLPF #5
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
5
0101
00 or 01
370
16
2
586
–14.1
1.55
a0
0.002209828
58445495367
n11
0.25
d11
1
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Table 205.ꢀLPF #5...continued
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
10
11
185
32
1172
–25.2
3.10
n12
n13
0.499999985
09883880615
d12
d13
–1.918031513
69094848633
0.25
0.920241355
89599609375
n21
n22
n23
1
0
0
d21
d22
d23
1
0
0
92.5
64
2344
–37.2
6.20
Table 206.ꢀLPF #6
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
6
0110
00 or 01
10
180
90
16
32
2
1187
–25.6
3.19
a0
0.000534069
20051202178
n11
n12
0.25
d11
d12
1
2374
4748
–37.5
–49.7
6.38
12.8
0.50
–1.959839582
44323730469
n13
0.25
d13
0.960373640
06042480469
n21
n22
n23
1
0
0
d21
d22
d23
1
0
0
11
45
64
Table 207.ꢀLPF #7
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
7
0111
00 or 01
10
100
50
16
32
2
2167
–35.7
4
a0
0.000166309
83736831695
5.75
n11
n12
0.25
0.5
d11
d12
1
4334
8668
–47.7
11.5
23.0
–1.977621793
74694824219
n13
0.25
d13
0.977788090
70587158203
n21
n22
n23
1
0
0
d21
d22
d23
1
0
0
11
25
64
–60.0
5
Table 208.ꢀLPF #8
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
8
1000
00 or 01
1500
16
32
4
223
–1.26
0.420
a0
0.038343372
95612844088
n11
n12
n13
0.012602858
55167835381
d11
d12
d13
1
10
750
446
–5.70
0.840
0.025205812
95635351826
–1.621822061
87479138748
0.012602841
71453899225
0.660165434
83091971734
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Table 208.ꢀLPF #8...continued
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
n21
n22
n23
0.250000391
85483757809
d21
d22
d23
1
11
375
64
892
–21.7
1.68
0.499998882
29656874739
–1.691365664
38039781524
0.250000725
84865173919
0.741777177
60299266558
Table 209.ꢀLPF #9
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(HZ)
(dB)
(ms)
9
1001
00 or 01
500
16
32
3
558
–12.0
1.18
a0
0.064615703
92887561187
n11
n12
0.002532283
58602412005
d11
d12
1
10
250
1116
2232
–27.9
–45.8
2.36
4.72
0.002533824
55746249506
–0.935384296
07112438813
n13
n21
0.0
d13
d21
0.0
1
0.250076066
29379214302
11
125
64
n22
n23
0.499999953
72560029905
d22
d23
–1.894618878
39771225828
0.249923979
97755622097
0.899684986
54120099278
Table 210.ꢀLPF #A
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
A
1010
00 or 01
800
16
32
4
419
–4.92
0.795
a0
0.011904109
84205714229
n11
n12
n13
n21
n22
n23
0.003841581
86528944052
d11
d12
d13
d21
d22
d23
1
10
400
838
–19.5
–42.3
1.59
3.18
0.007683254
14507123675
–1.790004627
19285069468
0.003841554
98534484614
0.801908737
03490794799
0.250001033
66513437564
1
11
200
64
1676
0.499996183
39874751793
–1.836849434
91757790568
0.250002782
93126343421
0.852215825
91330946599
Table 211.ꢀLPF #B
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
B
1011
00 or 01
1200
16
4
279
–2.00
0.530
a0
0.025461958
27091324651
n11
0.008307694
58672901175
d11
1
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Table 211.ꢀLPF #B...continued
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
10
11
600
32
558
–9.30
1.06
n12
n13
n21
n22
n23
0.016615493
41945577768
d12
d13
d21
d22
d23
–1.692260733
94381204551
0.008307673
73784346147
0.717722692
21472528855
0.250000627
40839573694
1
300
64
1116
–28.8
2.12
0.499998117
78583796995
–1.753850626
39799738093
0.250001254
80314383530
0.787081488
14205258770
Table 212.ꢀLPF #C
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
C
1100
or
00 or 01
120
16
32
3
2325
–46.5
5.00
a0
0.015895001
45947964072
1101
n11
n12
0.000151619
88544501960
d11
d12
1
10
60
4650
9300
–64.5
–82.8
10.0
20.0
0.000152009
54845361584
–0.984104998
54052035928
n13
n21
0.0
d13
d21
0.0
1
0.250321249
94306603760
11
30
64
n22
n23
0.499999175
53953604488
d22
d23
–1.974640453
92631648568
0.249679574
70143059551
0.974944083
36020621508
Table 213.ꢀLPF #D
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(kHz)
(dB)
(ms)
D
1100
or
00 or 01
20
16
32
2
< 50
0
< 0.100
a0
0.462284907
69863128662
1101
n11
n12
n13
1.032979726
79138183594
d11
d12
d13
1
10
10
< 100
< 200
–0.01
–0.04
< 0.200
< 0.400
2.065959453
58276367188
0.723919987
67852783203
1.032979726
79138183594
0.186203718
18542480469
n21
n22
n23
1
0
0
d21
d22
d23
1
0
0
11
5
64
Table 214.ꢀLPF #E
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
E
1110
00 or 01
120
16
2
1804
–32.8
4.85
a0
0.000238952
80210650682
FXLS9xxxx
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Dual channel inertial sensor
Table 214.ꢀLPF #E...continued
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
n11
n12
0.25
0.50
d11
d12
1
10
11
60
30
32
64
3608
–44.7
9.70
–1.973166250
13962188007
n13
0.25
d13
0.973405202
94172827587
n21
n22
n23
1
0
0
d21
d22
d23
1
0
0
7216
–57.0
19.4
Table 215.ꢀLPF #F
Filter LPF[3:0] SAMPLERATE[1:0]
Typical
–3 dB
Sample
time
(µs)
Filter
order
Group
delay
1000 Hz
Step response
Filter coefficients
#
Atten
uation
Activation
to 99 %
(µs)
Frequency
(Hz)
(dB)
(ms)
F
1111
00 or 01
50
16
32
4
6726
–89.7
12.8
a0
0.000051373
22664827693
n11
n12
n13
n21
n22
n23
0.000015041
24143177110
d11
d12
d13
d21
d22
d23
1
10
25
13,452
26,904
–114
–138
25.6
51.2
0.000032261
11162087577
–1.986263192
05697576820
0.000017387
20648386979
0.986314565
28362415614
0.268800639
11477075633
1
11
12.5
64
0.498663181
55607519680
–1.989975680
35769623052
0.232535878
66496652770
0.990040369
88244481510
aaa-030619
10
magnitude
(dB)
0
-10
-20
-30
-40
-50
-60
minimum oscillator
typical oscillator
maximum oscillator
2
3
4
10
10
10
10
frequency (Hz)
Figure 24.ꢀ400 Hz, 4-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030688
1000
delay
(µs)
800
600
400
200
minimum oscillator
typical oscillator
maximum oscillator
0
2
3
4
10
10
10
10
frequency (Hz)
Figure 25.ꢀ400 Hz, 4-pole low-pass filter response signal delay
aaa-030620
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum oscillator
typical oscillator
-50
maximum oscillator
-60
2
3
4
10
10
10
10
frequency (Hz)
Figure 26.ꢀ400 Hz, 3-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030689
1000
delay
(µs)
800
600
400
200
minimum oscillator
typical oscillator
maximum oscillator
0
2
3
4
10
10
10
10
frequency (Hz)
Figure 27.ꢀ400 Hz, 3-pole low-pass filter response signal delay
aaa-030621
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum oscillator
typical oscillator
-50
maximum oscillator
-60
2
3
4
10
10
10
10
frequency (Hz)
Figure 28.ꢀ325 Hz, 3-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030690
1000
delay
(µs)
800
600
400
200
minimum oscillator
typical oscillator
maximum oscillator
0
2
3
4
10
10
10
10
frequency (Hz)
Figure 29.ꢀ325 Hz, 3-pole low-pass filter response signal delay
aaa-030622
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum oscillator
typical oscillator
maximum oscillator
-50
-60
2
3
4
10
10
10
10
frequency (Hz)
Figure 30.ꢀ370 Hz, 2-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030691
1000
delay
(µs)
800
600
400
200
minimum oscillator
typical oscillator
maximum oscillator
0
2
3
4
10
10
10
10
frequency (Hz)
Figure 31.ꢀ370 Hz, 2-pole low-pass filter response signal delay
aaa-030623
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum oscillator
typical oscillator
-50
maximum oscillator
-60
2
3
4
10
10
10
10
frequency (Hz)
Figure 32.ꢀ180 Hz, 2-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030692
4000
delay
(µs)
3000
2000
1000
minimum oscillator
typical oscillator
maximum oscillator
0
2
3
4
10
10
10
10
frequency (Hz)
Figure 33.ꢀ180 Hz, 2-pole low-pass filter response signal delay
aaa-030624
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum oscillator
typical oscillator
-50
maximum oscillator
-60
2
3
4
10
10
10
10
frequency (Hz)
Figure 34.ꢀ100 Hz, 2-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030693
4000
delay
(µs)
3000
2000
1000
minimum oscillator
typical oscillator
maximum oscillator
0
2
3
4
10
10
10
10
frequency (Hz)
Figure 35.ꢀ100 Hz, 2-pole low-pass filter response signal delay
aaa-030625
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum
typical
-50
maximum
-60
2
10
3
4
1
10
10
10
frequency (Hz)
Figure 36.ꢀ1500 Hz, 4-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030890
400
delay
(µs)
300
200
100
minimum
typical
maximum
0
1
2
3
4
10
10
10
10
frequency (Hz)
Figure 37.ꢀ1500 Hz, 4-pole low-pass filter response signal delay
aaa-030626
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum
typical
-50
maximum
-60
2
3
4
1
10
10
10
10
frequency (Hz)
Figure 38.ꢀ500 Hz, 3-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030891
1000
delay
(µs)
800
600
400
200
minimum
typical
maximum
0
1
2
3
4
10
10
10
10
frequency (Hz)
Figure 39.ꢀ500 Hz, 3-pole low-pass filter response signal delay
aaa-030627
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum
typical
-50
maximum
-60
2
10
3
4
1
10
10
10
frequency (Hz)
Figure 40.ꢀ800 Hz, 4-pole low-pass filter response magnitude
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
aaa-030892
1000
delay
(µs)
800
600
400
200
minimum
typical
maximum
0
1
2
3
4
10
10
10
10
frequency (Hz)
Figure 41.ꢀ800 Hz, 4-pole low-pass filter response signal delay
aaa-030628
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum
typical
-50
maximum
-60
2
3
4
1
10
10
10
10
frequency (Hz)
Figure 42.ꢀ1200 Hz, 4-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030893
400
delay
(µs)
300
200
100
minimum
typical
maximum
0
1
2
3
4
10
10
10
10
frequency (Hz)
Figure 43.ꢀ1200 Hz, 4-pole low-pass filter response signal delay
aaa-030629
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum
typical
-50
maximum
-60
2
3
4
1
10
10
10
10
frequency (Hz)
Figure 44.ꢀ120 Hz, 3-pole low-pass filter response magnitude
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
aaa-030894
5000
delay
(µs)
4000
3000
2000
1000
minimum
typical
maximum
0
1
2
3
4
10
10
10
10
frequency (Hz)
Figure 45.ꢀ120 Hz, 3-pole low-pass filter response signal delay
aaa-038941
10
magnitude
(dB)
0
-10
-20
-30
-40
minimum
typical
-50
maximum
-60
2
3
4
1
10
10
10
10
frequency (Hz)
Figure 46.ꢀ120 Hz, 2-pole low-pass filter output magnitude response
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
aaa-038942
5000
delay
(µs)
4000
3000
2000
1000
minimum
typical
maximum
0
1
2
3
4
10
10
10
10
frequency (Hz)
Figure 47.ꢀ120 Hz, 2-pole low-pass filter output magnitude response
aaa-030632
40
magintude
(dB)
0
-40
-80
-120
minimum
typical
maximum
-160
2
3
4
1
10
10
10
10
frequency (Hz)
Figure 48.ꢀ50 Hz, 4-pole low-pass filter response magnitude
FXLS9xxxx
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Dual channel inertial sensor
aaa-030896
10000
delay
(µs)
8000
6000
4000
2000
minimum
typical
maximum
0
2
3
4
10
10
10
10
frequency (Hz)
Figure 49.ꢀ50 Hz, 4-pole low-pass filter response signal delay
11.6.4.5 User sensitivity scaling
The device includes a user controlled sensitivity scaling as described in
Section 11.2.24.1.
11.6.4.6 Offset cancellation
The device provides an optional offset cancellation circuit to remove internal offset error.
A simplified block diagram of the offset cancellation is shown in Figure 50.
rate limit select
HIGH PASS FILTER DATAPATH
OFFSET RATE LIMITED DATAPATH
+
OC_Out
-
OFFSET RATE LIMITING
OFFSET
CANCELLATION
LOW PASS FILTER
INC/DEC
OUT
OC_Input
DOWN
SAMPLE
UP/DOWN
COUNTER
n
0
-1
1 - (d x z
)
1
CLK
0.5 Hz
OFFSET MONITOR
OFFMON
OFFMON
NEG
CHx_OFFSET_ERR
POS
aaa-030633
Figure 50.ꢀOffset cancellation block diagram
The transfer function for the offset low-pass filter is:
(11)
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Dual channel inertial sensor
Response parameters are specified in Section 10 and the offset low-pass filter
coefficients are specified in Table 216.
During startup, multiple phases of the offset low-pass filter are used to allow for fast
convergence of the internal offset error during initialization. The offset rate limiting is also
bypassed regardless of the state of the OC_FILT bits in the CHx_CFG_U4 register. The
low-pass filter details and timing for the startup phases is shown in Table 216.
In normal mode, the offset low-pass filter frequency can be selected and output rate
limiting can be applied to the output of the offset low-pass filter via the OC_FILT bits in
the CHx_CFG_U4 register. Rate limiting can only be enabled if the 0.04 Hz offset LPF is
selected. If rate limiting is enabled, the offset cancellation output is updated by OFFStep
LSB every tRL_Rate seconds.
The offset cancellation circuit output value is frozen when analog or digital self-test is
active (ST_CTRL = 0x8 - 0xF) regard-less of the offset cancellation phase. When analog
or digital self-test is deactivated, the offset cancellation output value freeze is extended
for 15 ms before continuing updates.
Table 216.ꢀOffset cancellation phases and times: DSI3, SPI, and I2C modes
Offset LPF
startup phase to start of phase
Time from reset
Sample
Time
Coefficients (24 bit)
LPF corner
frequency (-3 dB)
Time constant (τ)
(ms)
Rate limiting
(ms)
(us)
(Hz)
0
1
0
256
a0
n0
d0
a0
n0
d0
a0
n0
d0
a0
n0
d0
a0
n0
d0
a0
n0
d0
0.234051465988159
163.8
0.9714
3.886
15.54
62.17
248.7
994.7
3979
Bypassed
0.49999988079071
1.0
n1
d1
0.49999988079071
–0.765948414802551
4.096
8.192
24.58
90.11
352.3
1401
1401
256
256
256
256
256
256
1024
0.063805103302002
0.49999988079071
1.0
40.96
10.24
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
n1
d1
0.49999988079071
–0.936194777488708
2
0.0163367986679077
0.49999988079071
1.0
n1
d1
0.49999988079071
–0.983663082122802
3
0.00410926342010498
0.49999988079071
1.0
2.560
n1
d1
0.49999988079071
–0.995890617370605
4
0.00102889537811279
0.49999988079071
1.0
0.6400
0.1600
0.0400
0.005
n1
d1
0.49999988079071
–0.998970985412597
5
0.000257253646850586
0.49999988079071
1.0
n1
d1
0.49999988079071
–0.999742627143859
6a
6b
a0 0.0000643377478321934
Controlled by
OC_FILT[1:0]
n0
d0
a1
0.49999988079071
1.0
n1
d1
0.49999988079071
–0.9999356623
0.000032169
39131789331
32000
Bypassed
n10
d10
0.5
1
n11
d11
0.5
–0.999967830
25562763214
Self-test Active
Output Frozen
FXLS9xxxx
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Dual channel inertial sensor
Table 217.ꢀOffset cancellation phases and times: PSI5 modes
Offset LPF
startup
phase
Time from reset
to start of phase
LPF corner
frequency
(–3 dB)
Time
constant (τ)
Rate limiting
(ms)
(ms)
(Hz)
163.8
40.96
10.24
2.560
0.6400
0.0400
0
1
0
0.9714
3.886
15.54
62.17
248.7
3979
Bypassed
Bypassed
Bypassed
Bypassed
Bypassed
4.096
8.192
24.58
90.11
2
3
4
6a
End of Initialization
Phase 3
Controlled by
OC_FILT[1:0]
6b
End of Initialization
Phase 3
0.005
32000
Bypassed
aaa-030634
10
magintude
(dB)
0
-10
-20
-30
-40
-50
-60
minimum oscillator
typical oscillator
maximum oscillator
-3
-2
-1
10
10
10
1
10
frequency (Hz)
aaa-030897
6000
delay
(ms)
4000
2000
0
minimum oscillator
typical oscillator
maximum oscillator
-3
-2
-1
10
10
10
1
10
frequency (Hz)
Figure 51.ꢀ0.04 Hz offset cancellation low–pass filter characteristics
FXLS9xxxx
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FXLS9xxxx
Dual channel inertial sensor
aaa-030635
40
magintude
(dB)
0
-40
-80
-120
-160
minimum
typical
maximum
-4
-3
-2
-1
2
10
10
10
10
1
10
10
frequency (Hz)
aaa-030698
50
40
30
20
10
0
delay
(s)
minimum
typical
maximum
-4
-3
-2
-1
2
10
10
10
10
10
1
10
frequency (Hz)
Figure 52.ꢀ0.005 Hz offset cancellation low-pass filter characteristics
11.6.4.7 Moving average
The device includes an optional moving average function. See Section 11.2.25.4 for
details regarding the moving aver-age function. If the moving average function is
enabled, interpolation is disabled.
11.6.4.8 Data interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter.
Each result produced by the digital signal processing chain is delayed one sample time.
Transmitted data is interpolated from the 2 previous samples, resulting in a latency of one
sample time, and a maximum signal jitter of 1/16 of the sample time. The device uses the
following functions for calculating the interpolation:
(12)
(13)
An example of the output interpolation is shown in Figure 53.
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Dual channel inertial sensor
aaa-030636
40000
available
output value
(LSB)
30000
20000
10000
0
0
100
200
300
400
500
600
output sample #
DSP output value (LSB)
available output value (LSB)
Figure 53.ꢀOutput interpolation example: Linear interpolation (16 to 1)
11.6.4.9 Output scaling
Table 218 shows the output scaling for each output data type and protocol.
Table 218.ꢀOutput scaling
Data Type
16-bit Register Read
16-bit
PCM
SPI
DSI
PSI5
I2C
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
x
x
x
x
x
16-bit
x
x
x
12-bit
x
x
x
10-bit
x
x
x
x
CHx_U_OFFSET
x
x
Readable Data
Noise Bits
Clipped Bits
Equation 14 is used to convert sensor data readings to acceleration using the variables
specified in Table 219.
Note: The values listed apply for a user gain of 1x (U_SNS_SHIFT = '10' and
U_SNS_MULT = 0x00).
(14)
Where:
Acceleration g
=
=
=
=
The acceleration output in g
SensorDataLSB
SensorDataOFFLSB
SENSEACCEL
The acceleration output in LSB
The acceleration output value at 0 g in LSB
The expected sensitivity in LSB/g
FXLS9xxxx
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Dual channel inertial sensor
Table 219.ꢀSensor data variables
g Range Data reading
type
Typical
SENSEACCEL Minimum sensor
Maximum sensor
data value
data value
SensorDa
taOFFLSB
(LSB/g)
(Signed LSB)
(Signed LSB)
(LSB)
Medium g 16-bit Register Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
66.0322
66.0322
528.258
528.258
33.0161
33.0161
8.25403
8.25403
21.8930
21.8930
175.144
175.144
10.9465
10.9465
2.73663
2.73663
0x8000 (–32768)
0x8001 (–32767)
0x8010 (–32752)
0x8800 (–30720)
0x801 (–2047)
0x801 (–2047)
0x201 (–511)
0x7FFF (+32767)
0x7FFF (+32767)
0x7FFF (+32767)
0x7800 (+30720)
0x7FF (+2047)
0x7FF (+2047)
0x1FF (+511)
16-bit DSI3 PDCM Sensor Data
16-bit SPI Sensor Data
16-bit PSI5 Sensor Data
12-bit DSI3 PDCM Sensor Data
12-bit SPI Sensor Data
10-bit DSI3 PDCM Sensor Data
10-bit PSI5 Sensor Data
16-bit Register Read
0x220 (–480)
0x1E0 (+480)
High g
0x8000 (–32768)
0x8001 (–32767)
0x8010 (–32752)
0x8800 (–30720)
0x801 (–2047)
0x801 (–2047)
0x201 (–511)
0x7FFF (+32767)
0x7FFF (+32767)
0x7FFF (+32767)
0x7800 (+30720)
0x7FF (+2047)
0x7FF (+2047)
0x1FF (+511)
16-bit DSI3 PDCM Sensor Data
16-bit SPI Sensor Data
16-bit PSI5 Sensor Data
12-bit DSI3 PDCM Sensor Data
12-bit SPI Sensor Data
10-bit DSI3 PDCM Sensor Data
10-bit PSI5 Sensor Data
0x220 (–480)
0x1E0 (+480)
11.7 Temperature sensor
11.7.1 Temperature sensor signal chain
The device includes an independent temperature sensor for each channel for signal
compensation. The output of the channel 0 temperature sensor is provided for user
readability. A simplified block diagram is shown in Figure 54. Temperature sensor
parameters are specified in Section 10.5 and Section 10.18.
SINC
FILTER
MOVING
AVERAGE
TEMPERATURE
Σ
CONVERTER
OFFSET
AND
GAIN TRIM
temperature
sensor
to temperature
output
aaa-030637
Figure 54.ꢀTemperature sensor signal chain block diagram
11.7.2 Temperature sensor output scaling equations
Equation 15 is used to convert temperature readings with the variables as specified.
(15)
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Where:
TDEGC
TLSB
=
=
=
=
The temperature output in degrees C
The temperature output in LSB
T0LSB
TSENSE
The expected temperature output in LSB at 0 C
The expected temperature sensitivity in LSB/C
Table 220.ꢀTemperature sensor output scaling equation variables
Data reading
T0LSB
TSENSE
(LSB)
(LSB/C)
8-bit Register Read
68
TSENSE
16-bit Register Read
17408
17408
17408
–1728
1100
1100
276
TSENSE * 256
TSENSE * 256
TSENSE * 256
TSENSE * 64
TSENSE * 16
TSENSE * 16
16-bit DSI3 PDCM Sensor Data
16-bit SPI Sensor Data
16-bit PSI5 Sensor Data
12-bit DSI3 PDCM Sensor Data
12-bit SPI Sensor Data
10-bit DSI3 PDCM Sensor Data
10-bit PSI5 Sensor Data
TSENSE *
TSENSE
4
–27
11.8 PCM output function
The device provides the option for a PCM output function. The PCM output is enabled
if the ARM_CFG bits in the CHx_CF-G_U4 registers are configured for PCM output.
Selecting the PCM output enables the following functions:
• The non-interpolated sensor data output as defined in the DATATYPE0 bits in the
Chx_CFG_U3 register is saturated to 10-bits as shown in Section 11.6.4.9 and
converted to an unsigned value.
• The 10-bit sensor value is input into a summer clocked at 10 MHz.
• The carry from the summer circuit is output to the PCM pin.
A block diagram of the PCM output is shown in Figure 55.
10
DSP [20:11]
out
as defined in DATATYPE0
A
CARRY
10 bit ADDER
SUM
PCM
10
B
D
Q
Q
f
CLK
FF
CLK
10
aaa-030638
Figure 55.ꢀPCM output function block diagram
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11.9 Arming function
When SPI mode is enabled via the COMMTYPE register, the device provides the option
for an arming function with 3 modes of operation. The operation of the arming function is
selected by the state of the ARM_CFG bits in the CHx_CFG_U4 registers.
See Section 14.5 for the operation of the Arming function with exception conditions. Error
conditions do not impact prior arming function responses. If an error occurs after an
arming activation, the corresponding pulse stretch for the existing arming condition will
continue. However, new sensor reads will not update the arming function regardless of
the sensor value.
11.9.1 Arming function: moving average mode
In moving average mode, the arming function runs a moving average on the offset
canceled output of the associated sensor channel DATATYPE0. The number of samples
used for the moving average (k) is programmable via the ARM_WS[1:0] bits in the
CHx_ARM_CFG registers. See Section 11.2.28.3 for register details.
(16)
Where n is the current sample.
The sample rate for each channel is determined by the rate of the SPI sensor data
requests. At the falling edge of SS_B for a sensor data SPI response for SOURCEID_0
(channel 0) or SOURCEID_2 (channel 1), the moving average for the associated channel
is updated with a new sample. See Figure 56. The arming function input data rate can
be down sampled as described in Section 11.9.4. The SPI sensor data sample rate must
meet the minimum time between requests (tACC_REQ_x) specified in Section 10.13.
The moving average output is compared against positive and negative thresholds that
are individually programmed for each channel via the CHx_ARMT_x registers. See
Section 11.2.29 for register details. If the moving average equals or exceeds either
threshold, an arming condition is indicated, the arming pin output is asserted for the
associated channel, and the pulse stretch counter is set as described in Section 11.9.5.
The arming pin output is deasserted only when the pulse stretch counter expires.
Figure 56 shows the arming output operation for different SPI conditions.
ARM_T_P[7:0]
ARM_WS_P[1:0]
OC_out[12:3]
POSITIVE
MOVING AVERAGE
PULSE STRETCH
GATING
I/O
ARM
NEGATIVE
MOVING AVERAGE
ARM_WS_N[1:0]
ARM_T_N[7:0]
ARM_PS[3:0]
aaa-030639
Figure 56.ꢀArming function block diagram - moving average mode
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11.9.2 Arming function: count mode
In count mode, the arming function compares each offset canceled sample against
positive and negative thresholds that are individually programmed for each channel
via the CHx_ARMT_x_x and CHx_ARMT_x_x registers. See Section 11.2.29 for
register details. If the sample equals or exceeds either threshold, a sample counter is
incremented. If the sample does not exceed either threshold, the sample counter is reset
to zero.
The sample rate for each channel is determined by the SPI sensor data sample rate.
At the falling edge of SS_B for a sensor data SPI response for SOURCEID_0 (channel
0) or SOURCEID_2 (channel 1), a new sample for the associated channel is compared
against the thresholds. See Figure 57. The arming function input data rate can be down
sampled as described in Section 11.9.4. The SPI sensor data sample rate must meet the
minimum time between requests (tACC_REQ_x) specified in Section 10.13.
A sample count limit is programmable via the ARM_WS[1:0] bits in the CHx_ARM_CFG
registers. If the sample count reaches the programmable sample count limit, an arming
condition is indicated, the associated arm pin output is asserted, and the pulse stretch
counter is set as described in Section 11.9.5.
The associated arm pin output is deasserted only when the pulse stretch counter expires.
Figure 58 shows the arming output operation for different SPI conditions.
ARM_WS_P[1:0]
ARM_T_P[7:0]
SAMPLE
COUNTER
PULSE
STRETCH
OC_out[12:3]
GATING
I/O
ARM
ARM_T_N[7:0]
ARM_PS[1:0]
aaa-030640
Figure 57.ꢀArming function block diagram - count mode
SCLK
SS_B
MOSI
request SnsData
SnsData resp
request SnsData
SnsData resp
request SnsData
SnsData resp
request SnsData
SnsData resp
MISO
ARM
arming
condition
not present
arming
condition
present
arming
condition
not present
arming
condition
not present
data latched for
arm function and SPI
t
ARM
pulse stretch time
aaa-030641
Figure 58.ꢀArming condition, moving average and count mode
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11.9.3 Arming function: unfiltered mode
At the falling edge of SS_B for a sensor data SPI response for SOURCEID_0 (channel
0) or SOURCEID_2 (channel 1), the most recent available offset canceled sample for
the requested channel is compared against positive and negative thresholds that are
individually programmed for each channel via the CHx_ARM_T_x and CHx_ARM_T_x
registers. See Section 11.2.29 for register details. If the sample equals or exceeds either
threshold, an arming condition is indicated.
Once an arming condition is indicated for the associated channel, the arm pin output for
that channel is asserted when SS_B is asserted and the MISO data includes a sensor
data response for that channel. The pulse stretch function is not applied in Unfiltered
mode.
Figure 59 contains a block diagram of the Arming Function operation in Unfiltered Mode.
Figure 60 shows the Arming output operation under the different SPI request conditions.
ARM_CFG[2]
ARM_CFG[1]
SS_B
ch select
I/O
ARM
ARMING FUNCTION
INTERPOLATED SAMPLE RATE
aaa-030642
Figure 59.ꢀArming function block diagram - unfiltered mode
SCLK
SS_B
MOSI
request SnsData
SnsData resp
request SnsData
SnsData resp
request SnsData
SnsData resp
request SnsData
SnsData resp
MISO
ARM
arming
condition
not present
arming
condition
present
arming
condition
not present
arming
condition
not present
data latched for
arm function and SPI
t
ARM_UF_DLY
aaa-030643
t
ARM_UF_ASSERT
Figure 60.ꢀArming condition, unfiltered mode
11.9.4 Arming function down sampling
The data provided to the arming function can be down sampled using the ARM_DS[1:0]
bits in the CHx_ARM_CFG registers.
The initial value of the counter is zero. At the falling edge of SS_B for a sensor data
SPI response, if the counter value is equal to '00', the arming function is updated with
the new sample as described in Section 11.9.1 or Section 11.9.2. The counter is then
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incremented by one. The counter rolls over to '00' after the maximum value specified in
the ARM_DS[1:0] bits is reached.
11.9.5 Arming pulse stretch function
A pulse stretch function can be applied to the arming outputs in moving average mode, or
count mode.
If the pulse stretch function is not used (ARM_PS[1:0] = '00'), the arming output is
asserted if and only if an arming condition exists for the associated channel after the
most recent evaluated sample. The arming output is deasserted if and only if an arming
condition does not exist for the associated channel after the most recent evaluated
sample.
If the pulse stretch function is used (ARM_PS[1:0] not equal '00'), the arming output is
controlled only by the value of the pulse stretch timer value. If the pulse stretch timer
value is non-zero, the arming output is asserted. If the pulse stretch timer is zero, the
arming output is deasserted. The pulse stretch counter continuously decrements until it
reaches zero. The pulse stretch counter is reset to the programmed pulse stretch value
if and only if an arming condition exists for the associated channel after the most recent
evaluated sample. See Figure 58.
Exception conditions listed in Section 14.5 do not impact prior arming function responses.
If an exception occurs after an arming activation, the corresponding pulse stretch for
the existing arming condition will continue. However, new sensor reads will not reset the
pulse stretch counter regardless of the sensor value.
11.9.6 Arming pin output structure
The arming output pin structure can be set to active high, or active low with the
ARM_CFG bits in the CHx_CFG_U4 registers as described in Section 11.2.26.4. The
active high and active low pin output structures are shown in Figure 61.
open drain, active high
open drain, active low
VCC
VCC
ARM
ARM FUNCTION
GATING
ARM FUNCTION
GATING
ARM
aaa-030644
Figure 61.ꢀArming function - pin output structure
12 DSI3 protocol
The DSI3[2] standard describes two function classes: Signal Function Class and
Power Function Class. The device is a slave conforming to the Signal Function Class
requirements. The device does not support Power Function Class. The following sections
describe the DSI3 Signal Function Class features supported by the device.
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12.1 DSI3 physical layer
12.1.1 Command receiver
The command receive block converts voltage transitions on the BUS_I pin to a digital
pulse train for decoding by the DSI data link layer.
The supply voltage can vary throughout the specified range, so the communication high
voltage (VHIGH) must be sampled and averaged with a low-pass filter. The communication
low voltage is then determined by comparing the supply voltage to the sampled and
averaged VHIGH voltage. Figure 62 shows a block diagram of the command receiver
physical layer.
bus in
DSI3
cmd_block
Vbufa
DSI/PSI
41.66 mV 83.33 mV
DSI3
-
-
+
+
DSI3/PSI5
11 R
command_detect
R
D
2.2 MΩ
2.8 MΩ
count
command
COUNTER
f
OSC
lpf_reset
cmd_start
CONTROL
LOGIC
cmd_valid
Vhigh_sample
command_detect
R
54 pF
aaa-030645
Figure 62.ꢀCommand receiver physical layer
The start of a command is detected when the comparator output (Command_Detect) is
low. The comparator output is input to a counter that is updated at the internal oscillator
frequency. Control logic monitors the counter output and generates the necessary
internal signals for the logic.
Figure 63 shows a timing diagram of the command receiver when a valid command is
received, and Figure 64 shows a timing diagram of the command receiver when a micro-
cut is received during the command window. Voltage values and timing parameters are
specified in Section 10.4 and Section 10.20.
BUS_I
Cmd_Start
t
Cmd_Valid
Cmd_Valid
t
CmdBlock_CRM
t
CmdBlock_ST_CRM
Cmd_Block
VHigh_Samp
time
aaa-030646
Figure 63.ꢀDSI3 command receiver timing diagram: valid command
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BUS_I
Cmd_Start
Cmd_Valid
t
Cmd_Valid
Cmd_Block
VHigh_Samp
time
aaa-030647
Figure 64.ꢀDSI3 command receiver timing diagram: micro-cut
12.1.2 Response transmitter
The response transmitter block converts two digital signals into two supply modulation
current. The response currents are generated such that the rise and fall times are the
same whether the IRESP current is being transmitted or the 2 x IRESP cur-rent is being
transmitted. A diagram of the response transmitter is shown in Figure 63. Current values
and timing parameters are specified in Section 10.4 and Section 10.11.
BUS_I
transmit level `0'
MAGNITUDE
CONTROL
transmit level `1'
SLEW
CONTROL
transmit level `2'
V
SS
aaa-030648
Figure 65.ꢀDSI3 transmitter block diagram
12.1.3 Discovery mode current sense
The current sense circuit is used during discovery mode to determine if any additional
slaves are connected to the BUS_O pin of the device. A diagram of the current sense
circuit is shown in Figure 66. Current values and timing parameters are specified in
Section 10.4 and Section 10.11. Details regarding discovery mode are included in
Section 12.2.3.
I
REF
IDATA
AddrCount
LastDevice
-
-
I
I
>0?
OUT
DISC
+
R
SENSE
BUS_O
Disc_Compare
I
CCQ
amp
I
sample
CCQ
CCQ
CONTROL
LOGIC
I
SAMPLE AND HOLD
Disc_Command_Rcvd
aaa-030649
Figure 66.ꢀDiscovery mode current sense circuit block diagram
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V
HIGH
V
LOW
t
t
DISC_ICCQ_Samp
DISC_Dly
I
_SAMPLE
Activation
CCQ
t
DISC_Idle_RSP
t
DISC_Ramp_RSP
t
START_DISC_RSP
I
RESP
t
t
IDISC_Samp_Dly
IDISC_Samp
Disc_Compare
t
IDISC_CMD_BLK
CmdBlock_DISC
time
aaa-030650
Figure 67.ꢀDSI3 discovery mode sensing timing diagram
12.2 Address assignment
The device supports all three address assignment methods described in the DSI3[2]
standard as described in Section 12.2.1, Section 12.2.2, and Section 12.2.3.
12.2.1 Address assignment method for parallel connected slaves
Devices connected in parallel must have pre-programmed addresses by storing a
non-zero value into the PADDR[3:0] bits of the PHYSADDR OTP register. If a non-
zero value is stored in this OTP register, The device does not participate in any other
address assignment method and waits for Command and Response Mode for further
configuration. See Section 12.3 for details regarding Command and Response Mode.
12.2.2 Address assignment method for bus switch connected daisy chain devices
A device connected in daisy chain by a bus switch may have either a pre-programmed
address as described in Section 12.2.1, or an un-programmed address.
If the address is pre-programmed, the device does not participate in any other
address assignment method and waits for Command and Response Mode for further
configuration information, including activating the bus switch to connect the next device
on the bus. See Section 12.3 for details regarding Command and Response Mode.
If the address is un-programmed, once power is applied, the device is the only device
on the segment which requires an address assignment. The device will accept a
Command and Response Mode register write command addressed to Address $0 (global
command), which writes the PADDR[3:0] bits to a non-zero value. Once a physical
address is assigned to the device, Command and Response Mode is used with the
assigned physical address for further configuration.
On power up, the device bus switch output defaults to deactivated.
12.2.3 DSI3 discovery mode: Address assignment method for resistor connected
daisy chain devices
A device connected in daisy chain via a resistor has an un-programmed address and
uses Discovery Mode to obtain its physical address (PADDR[3:0]).
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The master device must initiate Discovery Mode automatically after power is applied
to the bus segment by sending a sequence of Discovery Commands. Discovery mode
timing is defined in Section 10.11. If the ENDINIT bit is not set and the PADDR[3:0] field
is set to '0000', the device will detect a Discovery Command tSTART_DISC after a power-on
reset and for intervals of tPER_Disc until Discovery Mode has ended (the maximum value
of tSTART_DISC).
Discovery Mode follows the sequence listed here. Figure 68 shows a timing diagram of
the Discover Protocol for a 4 device segment.
1. The master powers up the bus segment to a known state.
2. The master transmits the Discovery Command.
3. After a predetermined delay (tSTART_DISC_RSP), all devices without a physical address
activate a current ramp to the 2x response current at a ramp rate of iDISC_RAMP
.
4. Each device monitors the current through its sense resistor (ΔiSENSE).
a. If the current is above iRESP, the device disables its response current, increments
its physical address counter, and waits for the next Discovery Command.
b. If the current is low (ΔiSENSE less than iRESP), the device continues to ramp its
response current to 2* iRESP in time tDISC_RAMP_RSP and maintains the current at 2*
iRESP for time tDISC_IDLE_RSP
.
c. After time tDISC_IDLE_RSP, if a device has not detected a current through its current
sense resistor of iRESP, the device accepts physical address '1' and disables its
response current.
5. After a pre-defined period (tPER_DISC), the master transmits another Discovery
Command.
6. Steps 3 and 4 are repeated, with the device accepting the address in its address
assignment counter if the sense current is low.
7. The master repeats step 5 until it has transmitted Discovery Commands for all the
devices it expects on the bus.
8. Device initialization can now begin using Command and Response Mode.
Once the Discovery Mode is complete, a physical address is assigned to the device, and
Command and Response Mode is used with the assigned physical address for further
configuration.
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0
0
0
0
Voltage
t
DISC_Bittime
V
LOW
t
PER_DISC
current sensed,
at master
t
START_DISC_RSP
2*I
= i
DISC_Peak
RESP
4*I
4*I
q
q
slave 1 accepts addr `0100'
2*I
current
transmitted
slave 1
RESP
t
+ t
DISC_Idle_RSP
DISC_Ramp_RSP
current sensed,
slave 1
2*I
2*I
RESP
3*I
3*I
q
q
current
transmitted
slave 2
2*I
RESP
slave 2 accepts addr `0011'
t
DISC_Ramp_RSP
current sensed,
slave 2
RESP
2*I
2*I
q
q
current
transmitted
slave 3
2*I
RESP
slave 3 accepts addr `0010'
current sensed,
slave 3
2*I
2*I
RESP
RESP
I
RESP
I
I
q
q
current
transmitted
slave 4
slave 4 accepts addr `0001'
current sensed,
slave 4
0
aaa-030652
Figure 68.ꢀDSI3 discovery mode timing diagram
12.3 DSI3 command and response mode
DSI3 command and response mode is the main communication method used for
initialization of the device.
12.3.1 DSI3 command and response mode command reception
Command and response mode data packets are exchanged between a single master
and a single slave. The primary purpose of command and response transactions are to
read from and write to registers within the device memory structure.
An example command and response mode command is shown in Figure 69. The
command consists of 32 bits of data broken up into multiple fields as described in
Section 12.3.1.2.
BUS_I
PA
[3]
PA CMD
[0] [3]
CMD ED
[0] [7]
ED RD
[0] [7]
RD CRC
[0] [7]
CRC
[0]
PA[3:0]
CMD[3:0]
ED[7:0]
RD[7:0]
CRC[7:0]
aaa-030653
Figure 69.ꢀCommand and response mode example command
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Table 221.ꢀCommand and response mode example command descriptions
Physical address
Command
Extended data
Register data
Error checking
PA3 PA2 PA1 PA0
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
E7
E6
E5
E4
E3
E2
E1
E0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
1
0
12.3.1.1 Bit encoding
Figure 70 shows the bit encoding used for Command and Response Mode Commands
from the Master device.
0
0
0
1
1
0
1
1
V
HIGH
V
LOW
aaa-030654
Figure 70.ꢀCommand and response mode command bit encoding
12.3.1.2 Command message format
The command and response mode command format is shown in Table 222.
Table 222.ꢀCommand and response mode - command format
Physical address
Command
Extended data
Register data
CRC
PA[3:0]
CMD[3:0]
ED[7:0]
RD[7:0]
CRC[7:0]
Table 223.ꢀCommand and response mode - field definitions
Field
Length Definition
(Bits)
PA[3:0]
4
Physical Address. The physical address must match the value in the PADDR[3:0] of the PHYSADDR
register
CMD[3:0]
ED[7:0]
4
8
8
8
Command (see Section 12.3.4)
Extended Data (see Section 12.3.4)
Register Data (see Section 12.3.4)
Error Checking (see Section 12.3.1.3)
RD[7:0]
CRC[7:0]
12.3.1.3 Error checking
The device calculates an 8-bit CRC on the entire 32-bits of each command. Message
data is entered into the CRC calculator MSB first, consistent with the transmission
order of the message. If the calculated CRC does not match the transmitted CRC, the
command is ignored and the device does not respond.
The CRC decoding procedure is:
1. A seed value is preset into the least significant bits of the shift register.
2. Using a serial CRC calculation method, the receiver rotates the received message
and CRC into the least significant bits of the shift register in the order received (MSB
first).
3. When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
4. If the shift register contains all zeros, the CRC is correct.
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5. If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed for Command and Response Mode are shown in
Table 224 .
Table 224.ꢀCommand and response mode command CRC
Mode
Default polynomial
Non-direct seed
Command and Response Mode
x8 + x5 + x3 + x2 + x + 1
1111 1111
Some example CRC calculations are shown in Table 225 .
Table 225.ꢀCommand and response mode - CRC calculation examples
Physical address
Command
0x08
Extended data
0x11
Register data
0x86
Non-direct seed
0xFF
8-bit CRC
0xB0
0x01
0x02
0x03
0x04
0x01
0x25
0xFF
0xFF
0x38
0x0F
0x1A
0x41
0xFF
0x2C
0x01
0x01
0x01
0xFF
0xD4
12.3.2 DSI3 command and response mode response transmission
An example command and response mode response is shown in Figure 71. The
response consists of 32 bits of data broken up into multiple fields as described in
Section 12.3.2.2.
st
1
symbol
response
current
aaa-030655
Figure 71.ꢀCommand and response mode response example
Table 226.ꢀCommand and response mode response example
Physical address
Command
Extended data
Register data
Error checking
PA3 PA2 PA1 PA0 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0
0
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
1
0
12.3.2.1 Symbol encoding
The device response to a Command and Response Mode Command uses multi-level
source coding where data nibbles are first encoded into symbols and then the symbols
are encoded into current levels. The symbols are assembled from three consecutive
three-level current pulses called chips. Within a symbol there are 3 consecutive chips
that can assume one of three discrete current levels as described in Section 10.5: iq, iq +
iRESP, and iq + 2 x iRESP. Figure 72 shows the chip trans-missions and an example of a 3
symbol (9 chip), 12-bit data packet.
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response data bit encoding
symbol
1
1
0
2
0
2
2
1
2
+2*I
+I
RESP
RESP
I
q_all
st nd rd
1
2
3
0 mA
chips
each symbol encodes four data bits
aaa-030656
Figure 72.ꢀResponse symbol encoding
Of the 27 possible combinations for three consecutive tri-level chips, the combinations
that begin with the null current level (iq) are discarded. Of the remaining 18 symbols,
the two symbols that contain the same value for all three chips are also dis-carded.
The remaining 16 symbols all begin with a non-null current level and have at least one
transition. These characteristics guarantee that any response packet has a transition at
the beginning of a packet and at least one transition in every symbol. Each 3-chip symbol
encodes the information of 4-bits. Table 227 shows the symbol encoding used by the
device.
Table 227.ꢀSymbol mapping
Encoded data (4 Bits)
Binary HEX
0000
Symbol transmitted
1st Chip
2nd Chip
3rd Chip
0
1
2
1
2
1
2
1
2
2
2
1
2
1
2
1
1
1
0
0
0
1
1
0
2
1
2
2
2
0
0
0
1
2
2
0
2
2
1
0
0
2
1
0
0
1
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1
2
3
4
5
6
7
8
9
A
B
C
D
E
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Table 227.ꢀSymbol mapping...continued
Encoded data (4 Bits)
Binary HEX
1111
Symbol transmitted
2nd Chip
1st Chip
3rd Chip
F
1
2
1
Where:
0 = iq
1 = iRESP
2 = 2 x iRESP
12.3.2.2 Response message format
The command and response mode response format is shown in Table 228.
Table 228.ꢀCommand and response mode - response format
Physical address
Command
Register + 1 data
Register data
CRC
PA[3:0]
CMD[3:0]
RD1[7:0]
RD[7:0]
CRC[7:0]
Table 229.ꢀCommand and response mode - field definitions
Field
Length (Bits)
Definition
PA[3:0]
4
Physical Address
Matches the value in the PADDR[3:0] of the PHYSADDR register
CMD[3:0]
ED[7:0]
4
8
An echo of the received command
The data contained in the register addressed by RA[7:1] + 1 (High Byte, see
Section 12.3.4)
RD[7:0]
8
8
The data contained in the register addressed by RA[7:1] + 0 (Low Byte, see
Section 12.3.4)
CRC[7:0]
Error Checking (see Section 12.3.2.3)
12.3.2.3 Error checking
The device calculates a CRC on the entire 32-bits of each response. Message data is
entered into the CRC calculator MSB first, consistent with the transmission order of the
message.
The CRC Encoding procedure is:
1. A seed value is preset into the least significant bits of the shift register.
2. Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
3. Following the transmitted message, the transmitter feeds eight zeros into the shift
register, to match the length of the CRC.
4. When the last zero is fed into the input adder, the shift register contains the CRC.
5. The CRC is transmitted.
The CRC polynomial and seed for Command and Response Mode are shown in
Table 230.
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Table 230.ꢀCommand and response mode response CRC
Mode
Default polynomial
x8 + x5 + x3 + x2 + x + 1
Non-direct seed
Command and Response Mode
1111 1111
Some example CRC calculations are shown in Table 225.
12.3.3 DSI3 command and response mode timing
A timing diagram for command and response mode is shown in Figure 73. Timing
parameters are specified in Section 10.11.
CMD_Start
st
nd
32 bit
1
bit
BUS_I
t
ACT_RESP
t
CMD_BitTime
t
POR_DSI
t
START_CRM
V
BUS_I_UV_F + VHYST
t
PER_CRM
st
th
8
1
symbol
symbol
t
CHIP_CRM
I
+ 2 x I
q
RESP
RESP
response
current
I
+ I
q
I
q
t
t
SLEW2_RESP
aaa-030657
SLEW1_RESP
Figure 73.ꢀCommand and response mode timing diagram
12.3.4 DSI3 command and response mode command summary
Table 231.ꢀDSI3 command and response mode command summary
Command
Data
C3 C2 C1 C0 Hex Description
D15
D14
D13
D12
D11
D10
D9
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
$D
$E
$F
Register Read
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register Write
Reserved
Reserved
Enter PDCM
Reserved
Reserved
Reserved
Reserved
RA[7] RA[6] RA[5] RA[4] RA[3] RA[2] RA[1]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
RA[7] RA[6] RA[5] RA[4] RA[3] RA[2] RA[1] RA[0] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
12.3.4.1 Register read command
The device supports the Register Read command as a device address specific command
only. If the PA[3:0] field in the command matches the value in the PADDR[3:0] bits of
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the PHYSADDR register and a valid CRC is calculated, the device responds to the
command.
The device ignores the Register Read command if the command is sent to any other
physical address, including the DSI Global Device Address of '0000'.
The Register Read command uses the byte address definitions shown in Section 11.1.
The Register Read response includes the register contents at the time the Register Read
command decode is complete. Readable registers along with their byte addresses are
shown in Section 11.1. If an attempt is made to read a register that is not readable, the
device will respond with all zero data.
Table 232.ꢀRegister read command format
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
PA[3] PA[2] PA[1] PA[0]
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
RA[7] RA[6] RA[5] RA[4] RA[3] RA[2] RA[1]
x
0
0
0
0
0
0
0
0
8 bits
Table 233.ꢀRegister read command format description
Bit field
Definition
PA[3:0]
DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits
in the PHYSADDR register. Otherwise, the command is ignored.
C[3:0]
Register Read Command = '0000'
RA[7:1]
RA[7:1] contains the upper 7 bits of the byte address for the register to be read.
Table 234.ꢀRegister read command: response format
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
PA[3] PA[2] PA[1] PA[0]
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
RD[15] RD[14] RD[13] RD[12] RD[11] RD[10] RD[9] RD[8] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] 8 bits
Table 235.ꢀRegister read command: response format description
Bit field
PA[3:0]
C[3:0]
Definition
DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.
Register Read Command = '0000'
RD[15:8]
RD[7:0]
The data contained in the register addressed by RA[7:1] + 1 (High Byte)
The data contained in the register addressed by RA[7:1] + 0 (Low Byte)
A register read command to a register address outside the addresses listed in
Section 11.1 will result in a valid response. The data for the registers will be '0x0000'.
12.3.4.2 Register write command
The device supports the Register Write command as a device address specific
command. If the PA[3:0] field in the command matches the value in the PADDR[3:0] bits
of the PHYSADDR register, the device will execute the register write and respond to the
command.
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The device ignores the Register Write command if the command is sent to any other
physical address, including the DSI Global Device Address of '0000', with one exception
as explained in Section 12.3.4.3.
The Register Write command uses the byte address definitions shown in Section 11.1.
Writable registers along with their Byte addresses are shown in Section 11.1.
Table 236.ꢀRegister write command format
Address
Command
Data
CRC
PA3
PA2
PA[2]
PA1
PA0
C3
C2
C1
C0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PA[3]
PA[1]
PA[0]
1
0
0
0
RA[7] RA[6] RA[5] RA[4] RA[3] RA[2] RA[1] RA[0] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] 8 bits
Table 237.ꢀRegister write command format description
Bit field
Definition
PA[3:0]
DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits
in the PHYSADDR register. Otherwise, the command is ignored.
C[3:0]
Register Write Command = 1000'
RA[7:0]
RD[7:0]
RA[7:0] contains the byte address of the register to be read.
RD[7:0] contains the data to be written to the register addressed by RA[7:0].
Table 238.ꢀRegister write command: response format
Address
Command
Data
CRC
PA3
PA2
PA[2]
PA1
PA0
C3
C2
C1
C0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PA[3]
PA[1]
PA[0]
1
0
0
0
RD[15] RD[14] RD[13] RD[12] RD[11] RD[10] RD[9] RD[8] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] 8 bits
Table 239.ꢀRegister write command: response format description
Bit field
PA[3:0]
C[3:0]
Definition
DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.
Register Write Command = '1000'
RD[15:8]
The data contained in the register addressed by RA[7:1] + 1 (High Byte) (after the register write is
executed)
RD[7:0]
The data contained in the register addressed by RA[7:1] + 0 (Low Byte) (after the register write is
executed)
A register write command to a register address outside the addresses listed in
Section 11.1 will not execute, but will result in a valid response. The data for the registers
will be '0x0000'.
A register write command to a read-only register will not execute, but will result in a valid
response. The data for the registers will be the current contents of the register.
12.3.4.3 Global register write command to the PHYSADDR register
The device supports the Register Write command as a global address under the
following conditions:
1. The Register Write command is written to the PHYSADDR register.
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2. The PADDR[3:0] bits of the PHYSADDR register are equal to '0000' prior to the
register write being executed.
If these conditions are met, the device will execute the register write and respond to the
command.
Table 240.ꢀGlobal register write command format
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
RD[3] RD[2] RD[1] RD[0] 8 bits
Table 241.ꢀGlobal register write command format description
Bit field
PA[3:0]
C[3:0]
Definition
The DSI Global address of '0000'.
Register Write Command = '1000'
RA[7:0]
RD[3:0]
RA[7:0] must be set to the PHYSADDR register address.
RD[3:0] contains the new physical address for the device.
Table 242.ꢀGlobal register write command: response format
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
PA[3] PA[2] PA[1] PA[0]
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
RD[15] RD[14] RD[13] RD[12] RD[11] RD[10] RD[9] RD[8] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] 8 bits
Table 243.ꢀGlobal register write command: response format description
Bit field
PA[3:0]
C[3:0]
Definition
The new DSI physical address programmed to the PADDR[3:0] bits in the PHYSADDR register.
Register Write Command = '1000'
RD[15:8]
RD[7:0]
The data contained in register after PHYSADDR
The data contained in the PHYSADDR register after the register write is executed.
12.3.4.4 Enter periodic data collection mode command
The device supports an Enter PDCM command as a device address specific command
and as a Global Command.
If the PA[3:0] field in the command matches the value in the PADDR[3:0] bits of the
PHYSADDR register, the device will set the ENDINIT bit in the DEVLOCK_WR register,
enter Periodic Data Collection Mode, and respond to the command as shown in
Table 247. If the PA[3:0] field in the command matches the Global address of '0000',
the device will set the ENDINIT bit in the DEVLOCK_RW register and enter Periodic
Data Collection Mode regardless of the value of the PADDR[3:0] bits in the PHYSADDR
register (this includes PADDR = 0x0). No response is transmitted for a global command.
The device ignores the Enter PDCM command if the command is sent to any other
physical address.
The various DSI3 communication modes are controlled by the PDCM enable command
and the BDM_EN bit in the TIMING_CFG2 register as shown in Table 244.
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Table 244.ꢀPDCM enable command and BDM_EN bit status
PDCM
BDM_EN
Command and
Periodic Data
Background
Enabled?
Response Mode
Collection Mode
Diagnostic Mode
No
No
0
1
0
1
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Disabled
Disabled
Disabled
Enabled
Yes
Yes
Once the ENDINIT bit is set, the registers listed in Section 11.3.3 are locked and the
user array read/write register array verification is enabled. The ENDINIT bit can only be
cleared by a device reset.
Table 245.ꢀEnter periodic data collection mode command format
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
PA[3] PA[2] PA[1] PA[0]
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8 bits
Table 246.ꢀEnter periodic data collection mode command format description
Bit field
Definition
PA[3:0]
DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits
in the PHYSADDR register or the Global Address of '0000'. Otherwise, the command is ignored.
C[3:0]
Enter PDCM Command = '1011'
Table 247.ꢀEnter periodic data collection mode command: response format
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
PA[3] PA[2] PA[1] PA[0]
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
0
0
0
0
Ch[3] Ch[2] Ch[1] Ch[0]
0
0
0
0
0
0
0
0
8 bits
Table 248.ꢀEnter periodic data collection mode command: response format description
Bit field
PA[3:0]
Ch[3:0]
C[3:0]
Definition
DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.
CHIPTIME[3:0] in the CHIPTIME register
Enter Periodic Data Collection Mode Command = '1011'
12.3.4.5 Reserved commands
If the PA[3:0] field in the command matches the value in the PADDR[3:0] bits of the
PHYSADDR register and a valid CRC is calculated, the device will respond to reserved
commands. The physical address and command will be echoed and the correct CRC are
transmitted. The data included in the response is undefined.
Table 249.ꢀReserved commands
Address
Command
Data
CRC
PA3
PA[3]
PA[3]
PA2
PA1
PA[1]
PA[1]
PA0
PA[0]
PA[0]
C3
0
C2
0
C1
0
C0
1
D15
D14
D13
D12
D11
D10
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
PA[2]
PA[2]
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
8 bits
0
0
1
0
x
x
x
x
x
x
x
x
x
x
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Table 249.ꢀReserved commands...continued
Address
Command
Data
CRC
PA3
PA2
PA1
PA0
C3
0
C2
0
C1
1
C0
1
D15
x
D14
x
D13
x
D12
x
D11
x
D10
x
D9
x
D8
x
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
x
PA[3]
PA[3]
PA[3]
PA[3]
PA[3]
PA[3]
PA[3]
PA[3]
PA[3]
PA[3]
PA[3]
PA[2]
PA[2]
PA[2]
PA[2]
PA[2]
PA[2]
PA[2]
PA[2]
PA[2]
PA[2]
PA[2]
PA[1]
PA[1]
PA[1]
PA[1]
PA[1]
PA[1]
PA[1]
PA[1]
PA[1]
PA[1]
PA[1]
PA[0]
PA[0]
PA[0]
PA[0]
PA[0]
PA[0]
PA[0]
PA[0]
PA[0]
PA[0]
PA[0]
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
8 bits
0
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Table 250.ꢀReserved commands description
Bit field
Definition
PA[3:0]
DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits
in the PHYSADDR register. Otherwise, the command is ignored.
C[3:0]
x
Invalid Commands
Don't Care
Table 251.ꢀReserved command response format
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
C3
C2 C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PA[3] PA[2] PA[1] PA[0] C[3] C[2] C[1] C[0]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8 bits
Table 252.ꢀReserved command response format description
Bit field
PA[3:0]
C[3:0]
Definition
DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.
Reserved Command Echo
12.4 DSI3 periodic data collection mode and background diagnostic mode
When the ENDINIT bit in the DEVLOCK_WR register is set, periodic data collection
mode is enabled and the optional background diagnostic mode is enabled.
12.4.1 DSI3 periodic data collection mode and background diagnostic mode
command reception
When periodic data collection mode is enabled, the device will decode the DSI3
broadcast read command as well as background diagnostic mode command fragments
as described below.
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12.4.1.1 Bit encoding
The Command Bit encoding for Periodic Data Collection Mode and Background
Diagnostic Mode is the same as the bit encoding for Command and Response Mode, as
described in Section 12.3.1.1.
12.4.1.2 Command message format
The command message format for Periodic Data Collection Mode and Background
Diagnostic Mode is the same as the command message format for Command and
Response Mode, as described in Section 12.3.1.2.
If Background Diagnostic Mode is disabled, then the device responds with the Periodic
Data Collection Mode response only if the command is the single bit Broadcast Read
Command. A Broadcast Read Command may be either a '1' or a '0'. Figure 74 shows the
Broadcast Read Commands supported by the device.
BRC 0
BRC 1
V
HIGH
V
LOW
aaa-030658
Figure 74.ꢀBackground diagnostic mode command bit encoding
If Background Diagnostic Mode is enabled:
• Background Diagnostic Mode commands are transmitted and decoded in 2- or 4-bit
fragments depending on the state of the BDM_FRAGSIZE bit in the TIMING_CFG2
register.
• The device responds with the Periodic Data Collection Mode response if and only if the
command is a Broadcast Read Command or a command fragment.
• A Broadcast Read Command or any command length other than 2 or 4 bits resets the
Background Diagnostic Mode command decode.
• The device responds with a Background Diagnostic Mode response only when a full
32-bit command is received and the decoded command is a valid Command and
Response Mode command.
See Section 12.4.4 for additional details on Background Diagnostic Mode timing.
12.4.1.3 Error checking
The error checking for Background Diagnostic Mode commands is the same as the error
checking for Command and Response Mode, and described in Section 12.3.1.3.
No error checking is employed for the Broadcast Read Commands.
12.4.2 DSI3 periodic data collection mode response transmission
When periodic data collection mode is enabled and the device receives either a
broadcast read or background diagnostic command, the device will respond with periodic
data as shown in Figure 75 and described in the following sections.
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BUS_I
slave A
slave B
slave C
Response
Current
t
PDCM_RSPST[12:0], slave A
START_PDCM,
t
PDCM_RSPST[12:0], slave B
START_PDCM,
PDCM_RSPST[12:0] on slave C device
t
PER_PDCM
CmdBlock_PDCM
t
t
command blocking time is independently
programmed in each slave.
CmdBlock_ST_PDCM
Command
Block
aaa-030659
Figure 75.ꢀPeriodic data mode response transmission
12.4.2.1 Symbol encoding
The symbol encoding used for Periodic Data Collection Mode Responses is the same as
for Command and Response Mode responses, and described in Section 12.3.2.1.
12.4.2.2 Response message format
The Periodic Data Collection Mode response format is shown in Table 253 and
Table 254. Field sizes are defined by the PDCMFORMAT[2:0] bits in the SOURCEID_x
register in Section 11.2.13.
Table 253.ꢀPeriodic data collection mode response format
Source ID
Keep alive counter
Status
Sensor data
CRC
SOURCEID
KAC
S
D
CRC[7:0]
• If enabled in the PDCMFORMAT[2:0] bits, the SOURCEID field includes the value
stored in the SOURCEID_x[3:0] bits of the SOURCEID_x register.
• If enabled in the PDCMFORMAT[2:0] bits, the Keep Alive Counter field is a 2-bit rolling
message counter that is independently incremented for each SOURCEID. The initial
value of the counter is '00'.
• If enabled, the status field is transmitted as listed in Table 254. See Section 12.7 for
details on exception handling.
• The Sensor Data field includes the sensor data as selected by the DATATYPEx bits for
the SOURCEID.
• The CRC field includes an 8-bit CRC as defined in Section 12.4.2.3.
Table 254.ꢀPeriodic data collection mode status field definition
s[3:0]
Description
DEVSTAT state
SUP_ER-R_DIS state
Error Sensor data field value
priority
STATUS field size = 4
STATUS field size = 0
0
0
0
0
0
0
0
1
Normal Mode
N/A
N/A
N/A
N/A
16
15
Sensor Data
Sensor Data
Normal Mode, User
Array Not Locked
The Sensor Data Field Error Code is transmitted for
a minimum of one transmission
(UF2 region has not
been locked)
0
0
1
0
Self-test Incomplete or
Self-test Active or Self-
test Error Present
Bit set in
CHx_STAT:
N/A
14
Sensor Data
The Sensor Data Field Error Code is transmitted for
a minimum of one transmission
ST_INCMPLT
or ST_ACTIVE
or ST_ERROR
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Table 254.ꢀPeriodic data collection mode status field definition...continued
s[3:0]
Description
DEVSTAT state
SUP_ER-R_DIS state
Error Sensor data field value
priority
STATUS field size = 4
STATUS field size = 0
0
0
0
1
1
0
1
0
Oscillator Training Error
Offset Error
Bit set in
DEVSTAT3
N/A
N/A
13
12
Sensor Data
The Sensor Data Field Error Code is transmitted for
a minimum of one transmission
Bit set in
CHx_STAT:
Sensor Data
The Sensor Data Field Error Code is transmitted for
a minimum of one transmission
SIGNALCLIP or
OFFSET_ERR
0
1
0
1
Temperature Error
Bit set in
DEVSTAT2
N/A
N/A
N/A
11
9.10
8
Sensor Data
Sensor Data
The Sensor Data Field Error Code is transmitted for
a minimum of one transmission
0110 to 0111 RESERVED
N/A
The Sensor Data Field Error Code is transmitted for
a minimum of one transmission
1
0
0
0
User OTP Memory Error U_OTP_ERR set
The Sensor Data Field Error Code is transmitted for a minimum of one
transmission
in DEVSTAT2
(UF2)
1
1
1
1
0
0
0
1
0
1
1
0
1
0
1
0
User R/W Memory Error
(UF2)
U_RW_ERR set
in DEVSTAT2
N/A
N/A
N/A
0
7
6
5
4
The Sensor Data Field Error Code is transmitted for a minimum of one
transmission
NXP OTP Memory Error
Test Mode Active
Supply Error
F_OTP_ERR set
in DEVSTAT2
The Sensor Data Field Error Code is transmitted for a minimum of one
transmission
TESTMODE bit
set in DEVSTAT
The Sensor Data Field Error Code is transmitted for a minimum of one
transmission
Bit set in
No Response until the supply monitor timer expires
DEVSTAT1
The Sensor Data Field Error Code is transmitted for a minimum of one
transmission
(See Section 11.2.2.5)
1
No Response until the supply monitor timer expires
(See Section 11.2.2.5)
1
1
0
1
Reset Error
DEVRES Set
N/A
N/A
N/A
3
The Sensor Data Field Error Code is transmitted for a minimum of one
transmission
1110 to 1111 RESERVED
1, 2
The Sensor Data Field Error Code is transmitted for a minimum of one
transmission
12.4.2.3 Error checking
The device calculates a CRC on the entire response. Message data is entered into the
CRC calculator MSB first, consistent with the transmission order of the message.
The CRC Encoding procedure is:
1. A seed value is preset into the least significant bits of the shift register.
2. Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
3. Following the transmitted message, the transmitter feeds eight zeros into the shift
register, to match the length of the CRC.
4. When the last zero is fed into the input adder, the shift register contains the CRC.
5. The CRC is transmitted.
The CRC polynomial and seed for periodic data collection mode are shown in Table 255.
Table 255.ꢀPeriodic data collection mode response CRC
Mode
Default polynomial
Non-direct seed
Periodic Data Collection Mode
x8 + x5 + x3 + x2 + x + 1
0000, SOURCEID_x[3:0]
Some example CRC calculations are shown in Table 256.
Table 256.ꢀPeriodic data collection mode - CRC calculation examples
Source
identification
(4 Bits)
Keep alive
counter (2 Bits)
Status (4 Bits)
Sensor data
(10 Bits)
Non-direct seed
8-bit CRC
0x1
0x3
0x0
0x1FF
0x01
0xD6
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Table 256.ꢀPeriodic data collection mode - CRC calculation examples...continued
Source
identification
(4 Bits)
Keep alive
counter (2 Bits)
Status (4 Bits)
Sensor data
(10 Bits)
Non-direct seed
8-bit CRC
0x2
0x3
0x4
0x2
0x1
0x0
0x0
0x0
0x0
0x1FE
0x20D
0x1EA
0x02
0x03
0x04
0x70
0xB0
0x5F
12.4.3 DSI3 periodic data collection mode timing
A timing diagram for periodic data collection mode is shown in Figure 76. Timing
parameters are specified in Section 10.11.
CMD_Start
BUS_I
t
CMD_BitTime
t
PER_PDCM
t
PDCM_RSPT[12;0]
START_PDCM,
st
1
symbol
th
24
symbol
t
CHIP_PDCM
I
+ 2 x I
q
RESP
RESP
response
current
I
+ I
q
I
q
t
t
SLEW2_RESP
aaa-030660
SLEW1_RESP
Figure 76.ꢀPeriodic data collection mode timing diagram
12.4.4 Background diagnostic mode response transmission
12.4.4.1 Symbol encoding
The Background Diagnostic Mode response symbol encoding is the same as the symbol
encoding used for Command and Response Mode responses and is described in
Section 12.3.2.1.
12.4.4.2 Response message format
The Background Diagnostic Mode response message format is the same as the format
used for Command and Response Mode responses and is described in Section 12.3.2.2.
• If a complete 32-bit command is received and decoded to a valid Command and
Response Mode command, the device provides a Background Diagnostic Mode
response.
• Responses are initiated by the master transmitting 1-bit Broadcast Read Commands
following a completed Background Diagnostic Mode command transmission.
• Responses are transmitted in one or two symbol fragments (depending on the state
of the BDM_FRAGSIZE bit) following the 1-bit Broadcast Read Command, using the
same timing window within the frame that the Background Diagnostic Mode Command
used.
• Responses are transmitted if and only if Broadcast Read Commands are received.
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• Four or eight consecutive Broadcast Read Commands are required following a
valid Background Diagnostic Mode command to complete a response transmission
(depending on the state of the BDM_FRAGSIZE bit).
• If any command other than the Broadcast Read Command is received, no response
is transmitted and the remainder of the Broadcast Read Command response is
terminated.
• The data to be transmitted in the response is latched just before the first symbol of the
background diagnostic mode response.
See Figure 77 for Background Diagnostic Mode timing.
12.4.4.3 Error checking
The error checking for Background Diagnostic Mode responses is the same as used for
Command and Response Mode, and described in Section 12.3.1.3.
12.4.5 DSI3 background diagnostic mode timing
An example timing diagram for background diagnostic mode is shown in Figure 77. In
this example, BDM_FRAGSIZE is set to '1' (4 bits). Timing parameters are specified in
Section 10.11.
CMD_start
PA[3:0]
CMD[3:0]
t
PDCM_RSPST[12:0]
START_PDCM,
ED[7:3]
CRC[3:0]
broadcast read
0
broadcast read
1
BDM response data latched
t
START_BDM
1-2-1
1-2-0
aaa-030661
Figure 77.ꢀBackground diagnostic mode timing diagram
12.4.6 DSI3 periodic data collection mode and background diagnostic mode
command summary
When periodic data collection mode is enabled, the background diagnostic mode
supports the register read command as described in the command and response mode
command summary, Section 12.3.4.1. The register write command is not supported in
background diagnostic mode.
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12.4.7 DSI3 PDCM data transmission modes
12.4.7.1 Simultaneous sampling mode (SS_EN = 1)
0
100
200
300
400
500
600
700
800
900
1000
Time (µs)
t
+ t
LAT_INTERP
LAT_DSI
t
PDCM_RSPSTx
interpolated
samples
broadcast read
command
response
transmission
transmitted
data value
aaa-030662
Figure 78.ꢀSimultaneous sampling mode
12.4.7.2 Synchronous sampling mode with minimum latency (SS_EN = 0)
0
100
t
200
300
400
500
600
700
800
900
1000
Time (µs)
t
+ t
LAT_DSI
LAT_INTERP
PDCM_RSPSTx
interpolated
samples
broadcast read
command
response
transmission
transmitted
data value
aaa-030663
Figure 79.ꢀSynchronous sampling mode with minimum latency
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12.5 Initialization timing
offset
cancellation
normal
t
DSP_POR
offset cancellation low pass filter
startup
t
OC_START
periodic
data
POR
internal
delay
user set up and self test control through CRM
collection
read status registers
self test
enter
mode
(DEVSTAT, DEVSTAT2)
initialize signal chain
verification
PDCM
command
initialize communication
discovery
mode
t
START_DISC
t
POR_DSI
POR
aaa-030664
Figure 80.ꢀInitialization timing
12.6 Maximum number of devices on a network
The theoretical maximum number of devices on a DSI3 network is 16: 1 master and
15 slaves. The practical limit for the number of devices on a bus is dependent on the
minimum common capability of the devices on the bus. The capability of the device
is different depending on the bus configuration and operating mode. The impact of
the device capability on the practical limit for the number of devices on the network is
described in this section.
12.6.1 Pre-configured, parallel connected network
The number of devices in a pre-configured, parallel connected network is not directly
limited by the capability of the device. The practical limit is determined by a combination
of the following:
• The capability of the master device, including, but not limited to:
– The bus operating voltage
– The bus supply current
– The bus current limit
– The bit rate
– The response current detection capability (distinguishing response current from
quiescent current)
• The total quiescent current of all slaves on the network.
12.6.2 Bus switch connected daisy chain network
The number of devices in a bus switch connected daisy chain network is not directly
limited by the capability of the device. The practical limit is determined by a combination
of the following:
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• The capability of the master device, including, but not limited to:
– The bus operating voltage
– The bus supply current
– The bus current limit
– The bit rate
– The response current detection capability (distinguishing response current from
quiescent current)
• The total quiescent current of all slaves on the network.
• The current handling capability and resulting voltage drop of the external bus switches
in the network.
12.6.3 Resistor connected daisy chain network using discovery mode
The number of devices in a resistor connected daisy chain network is limited by the
capability of the device. The maximum number of equivalent devices connected to the
BUS_O pin of a device is 3. This is limited by the total quiescent current drawn from the
BUS_O pin during Discovery Mode (IBUS_O_q).
The practical limit is determined by a combination of the above restriction and the
following:
• The capability of the master device, including, but not limited to:
– The bus operating voltage
– The bus supply current
– The bus current limit
– The bit rate
– The response current detection capability (distinguishing response current from
quiescent current)
• The total quiescent current of all slaves on the network.
• The maximum allowed quiescent current drawn from the BUS_O pin of other slaves in
the system.
• The resulting voltage drop of the Discovery Mode resistors in all slaves in the network.
12.7 DSI3 exception handling
Table 257 summarizes the exception conditions detected by the device and the response
for each exception.
Table 257.ꢀException conditions and response
Condition
exception
Description
Device response
PDCM
enabled?
Power-On Reset
VBUS_I Error
N/A
Power Applied
• See Section 12.5
• ST_INCMPLT set, PDCM disabled. The device must be
reinitialized
N/A
VBUS_I < VBUS_I_UV_F
• Response Current Deactivated
• BUSIN_UV_ERR set, PDCM Status set as specified in
Section 12.4.2.2
• The device ignores commands in CRM
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Table 257.ꢀException conditions and response...continued
Condition
exception
Description
Device response
PDCM
enabled?
VBUF Error
N/A
VBUF < VBUF_UV_F
• Response Current Deactivated
• VBUFUV_ERR set, PDCM Status set as specified in
Section 12.4.2.2
• The device ignores commands in CRM
Internal Regulator
Error
N/A
Internal regulator under-
voltage condition
• The device is held in Reset
• No response to DSI commands
• If activated, BUSSW_L is deactivated
• The device must be reinitialized when the internal
regulator returns above the threshold
OTP Error
Detection Fault
N/A
N/A
Error detected in factory
programmed OTP array.
• Periodic Data Collection Mode response data set to
error response
• F_OTP_ERR set, PDCM Status set as specified in
Section 12.4.2.2
(Factory Array)
OTP Error
Detection Fault
Error detected in User
programmed OTP array and
the LOCK_U bit is set.
• Periodic Data Collection Mode response data set to
error response
• U_OTP_ERR set, PDCM Status set as specified in
(User Array)
Section 12.4.2.2
User R/W Array
Error Detection
Fault
No
N/A
N/A
Yes
Error detected in user read
write registers and the
ENDINIT bit is set.
• Periodic Data Collection Mode response data set to
error response
• U_RW_ERR set, PDCM Status set as specified in
Section 12.4.2.2
Self-test
No
ST activated during
initialization
• Internal self-test circuitry enabled
• Self-test Activation Incomplete status cleared
Activated
• Sensor Data Registers (SNSDATAx_x) contain self-test
active data
• ST_ACTIVE set
Yes
ST activated in Periodic Data • Periodic Data Collection Mode sensor response data
Collection Mode
normal
• Self-test Activation ignored
Self-test Never
Activated after
Reset
No
In initialization, before Self-
test
• Normal Responses to Command and Response Mode
Yes
In PDCM, Self-test
incomplete
• Periodic Data Collection Mode sensor response data
normal
• ST_INCMPLT set, PDCM Status set as specified in
Section 12.4.2.2
12.7.1 Daisy chain and discovery mode error handling
Table 258 shows the effect of internal failure modes on the discovery and daisy chain
initialization procedures.
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Table 258.ꢀDSI3 error handling - discovery mode and daisy chain mode
Error condition
Effect on discovery mode
Effect on daisy chain
Supply Error
Discovery Commands Ignored. The device
does not participate in Discovery Mode
Daisy Chain Commands Ignored. The device
will not participate in Daisy Chain
Memory Error
No Effect. The device attempts to participate in No Effect. The device will attempt to participate
Discovery Mode as programmed. in Daisy Chain as programmed.
Temperature Error
No Effect. The device will attempt to participate No Effect. The device will attempt to participate
in Discovery Mode as programmed. in Daisy Chain as programmed.
Communication Error
(Internal)
No Effect. The device participates in Discovery No Effect. The device will participate in Daisy
Mode as programmed.
Chain as programmed.
Offset Error
No Effect. The device will participate in
Discovery Mode as programmed.
No Effect. The device will participate in Daisy
Chain as programmed.
Self-test Incomplete or
Self-test Active
Not Applicable.
Not Applicable.
Device Not Locked
No Effect. The device will participate in
Discovery Mode as programmed.
No Effect. The device will participate in Daisy
Chain as programmed.
13 PSI5 protocol
13.1 Communication interface overview
The communication interface between a master device and this slave device in PSI5
mode is established via a PSI5 compatible 2-wire interface, with parallel or serial (daisy-
chain) connections to the satellite modules. Figure 81 shows one possible system
configuration for multiple satellite modules in parallel.
Master Device
Slave Module #1
V
CC
V
CC
DISCRETE
COMPONENTS
V
SS
CC_OUT
I
Data
V
V
SS
V
SS_OUT
Slave Module #2
V
CC
V
CC
DISCRETE
COMPONENTS
V
SS
CC_OUT
I
Data
V
V
SS
V
SS_OUT
aaa-030665
Figure 81.ꢀPSI5 satellite interface diagram
13.2 Data transmission physical layer
This device uses a two wire interface for both its power supply (VCC), and data
transmission (IDATA). The PSI5 master sup-plies a pre-regulated voltage to this device.
Data transmissions and synchronization control from the PSI5 master to this device are
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accomplished via modulation of the supply voltage. Data transmissions from this device
to the PSI5 master are accomplished via modulation of the current on the power supply
line.
13.2.1 Synchronization pulse
The PSI5 master modulates the supply voltage in the positive direction to provide
synchronization of the satellite sensor data. Upon reception of a synchronization pulse,
this device delays a specified period of time, called a time slot, before transmitting sensor
data. For more details regarding time slots, refer to Section 11.2.18, and Section 10.12.
sync pulses
V
IDLE
SYNC
V
IDLE
ground
IR_PSI5
I
q
+ I
I
q
aaa-030667
Figure 82.ꢀSynchronous communication overview
13.2.1.1 Synchronization pulse detection
The Synchronization (Sync) pulse detection block generates a valid synchronization
pulse signal following the detection of an externally generated Sync pulse. This signal
resets the Sync pulse time reference (tTRIG), and initiates the timers associated with
response messages.
The supply voltage can vary throughout the specified range, so the external Sync pulses
may have different absolute volt-age levels. Thus, the Sync pulse detection threshold
(VCC_SYNC) is dependent not only on the Sync pulse absolute voltage, but also on the
supply voltage. Figure 83 shows a block diagram of the Sync pulse detection circuit.
bus in
DSI3
cmd_block
Vbufa
DSI/PSI
41.66 mV 83.33 mV
DSI3
-
-
+
+
DSI3/PSI5
11 R
command_detect
R
D
2.2 MΩ
2.8 MΩ
count
command
COUNTER
f
OSC
lpf_reset
cmd_start
CONTROL
LOGIC
cmd_valid
Vhigh_sample
command_detect
R
54 pF
aaa-030668
Figure 83.ꢀSynchronization pulse detection circuit
The start of a Sync pulse is detected when the comparator output is set. The comparator
output is input into a counter, and the counter is updated at a fixed frequency. At a fixed
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time after the initial sync pulse detection, the counter is compared against a limit (the
minimum value of tSYNC). If the counter is above the limit, a valid sync pulse is detected.
If the Sync pulse is valid, the following occur:
1. The valid Sync pulse detection signal is set.
2. The detection counter is reset and disabled for tSYNC_OFF (referenced from tTRIG).
tSYNC_OFF can be programmed by the user via the PDCM_CMD_B_x registers. See
Section 11.2.19 for details on the programmable option, and Section 10.12 for timing
specifications for each option.
3. The Sync pulse detection low-pass filter is reset for a specified time (tSYNC_LPF_RESET).
If the Sync pulse is invalid, all timers are reset, and the detector becomes sensitive within
2 µs.
The output of the comparator is monitored at the SampCLK frequency. Once the
comparator output goes high, all of the internal timers are started, so that the tTRIG jitter is
minimized.
sync pulse
V
SYNC_COMP
sync_LPF_reset
sync off
sync_pulse_PD
Response
t
A_SYNC_DLY
t
PD_DLY
t
PD_ON
t
SYNC_LPF_RST_ST
t
TRIG
t
SYNC_LPF_RST
t
SYNC_OFF_xxx
t
TIMESLOTx
aaa-030669
Figure 84.ꢀSynchronization pulse detection timing
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t
t
S-S
RS
t
SYNC
V
SYNC
V
IDLE
V
SYNC
V
CC
GND
aaa-030670
Figure 85.ꢀSync pulse characteristics
13.2.1.2 Synchronization pulse pulldown function
The device includes an optional Sync pulse pulldown function for systems in which
the master device does not include an active pull-down function. The device uses the
modulation current pulldown circuit, which sinks IR_PSI5 additional current from the BUS_I
pin. The pulldown current is activated after tPD_DLY (referenced to tTRIG), and is activated
for tPD_ON
.
The Sync pulse pulldown function is disabled in Programming Mode, in Initialization
Phase 1, and in Daisy Chain Mode until the Run Command is received.
13.3 Data transmission data link layer
13.3.1 Bit encoding
The device outputs data by modulation of the VCC current using Manchester Encoding.
Data is stored in a transition occur-ring in the middle of the bit time. The signal idles at
the normal quiescent supply current. A logic low is defined as an increase in current at
the middle of a bit time. A logic high is defined as a decrease in current at the middle of a
bit time. There is always a transition in the middle of the bit time. If consecutive "1" or "0"
data are transmitted, a transition occurs at the start of a bit time.
`0'
`1'
I
current
R_PSI5
idle current
t
BIT
consecutive
`0'data bits
consecutive
`1' data bits
aaa-030671
Figure 86.ꢀManchester data bit encoding
13.3.2 PSI5 data transmission
PSI5 data transmission frames are composed of two start bits, a 10-bit data word, and
error detection bit(s). Data words are transmitted least significant bit (LSB) first. A typical
Manchester-encoded transmission frame is illustrated in Figure 87.
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data bit
SB1
`0'
SB0
`0'
D0
`1'
D1
`1'
D2
`1'
D3
`0'
D4
`0'
D5
`1'
D6
`1'
D7
`1'
D8
`1'
D9
`0'
PAR
`1'
SB1
I
R_PSI5
bit value
t
BIT
t
= t
BIT
* (2+DATASIZE+(P_CRC?3:1))
TRAN
t
aaa-030672
FRAME
Figure 87.ꢀExample Manchester encoded data transfer - PSI5-x10x
13.3.2.1 PSI5-x10P transmission mode
The device can be configured to transmit 10-bit data with parity by setting the
PDCMFORMAT bits in the SOURCEID_x registers and the P_CRC bit in the PSI5_CFG
register.
Table 259.ꢀPSI5-x10P transmission mode
Start Bits
S2 S1
Sensor data (See Section 11.6.4.9)
D2 D3 D4 D5 D6 D7
Parity
D0
D1
D8
D9
P
13.3.2.2 PSI5-x10C transmission mode
The device can be configured to transmit 10-bit data with 3-bit CRC by setting the
PDCMFORMAT bits in the SOURCEID_x registers and the P_CRC bit in the PSI5_CFG
register.
Table 260.ꢀPSI5-x10C transmission mode
Start bits
S2 S1
Sensor data (See Section 11.6.4.9)
D2 D3 D4 D5 D6 D7
CRC
D0
D1
D8
D9
C2
C1
C0
13.3.2.3 PSI5-x16P transmission mode
The device can be configured to transmit 16-bit data with parity by setting the
PDCMFORMAT bits in the SOURCEID_x registers and the P_CRC bit in the PSI5_CFG
register. In 16-bit mode, the 10-bit initialization data is transmitted in the upper 10-bits of
the data packet and the lower 6-bits are all zeros.
Table 261.ꢀPSI5-x16P transmission mode
Start bits
S2 S1
Init Data
Sensor data (See Section 11.6.4.9)
Parity
D0
0
D1
0
D2
0
D3
0
D4
0
D5
0
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
P
P
10-bit Initialization Data as specified in Section 13.4.2.1
13.3.2.4 PSI5-x16C transmission mode
The device can be configured to transmit 16-bit data with 3-bit CRC by setting the
PDCMFORMAT bits in the SOURCEID_x registers and the P_CRC bit in the PSI5_CFG
register. In 16-bit mode, the 10-bit initialization data is transmitted in the upper 10-bits of
the data packet and the lower 6-bits are all zeros.
Table 262.ꢀPSI5-x16C transmission mode
Start bits Sensor data (See Section 11.6.4.9)
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C2 C1 C0
CRC
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Table 262.ꢀPSI5-x16C transmission mode...continued
Start bits
Sensor data (See Section 11.6.4.9)
10-bit Initialization Data as specified in Section 13.4.2.1
CRC
Init Data
0
0
0
0
0
0
C2 C1 C0
13.3.3 Error detection
Error detection of the transmitted data is accomplished via either a parity bit, or a 3-bit
CRC. The type of error detection used is selected by the P_CRC bit in the PSI5_CFG
register.
13.3.3.1 Parity error detection
When parity error detection is selected, even parity is employed. The number of logic '1'
bits in the transmitted message must be an even number.
13.3.3.2 3-bit CRC error detection
When CRC error detection is selected, a 3-bit CRC is appended to each response
message. The 3-bit CRC uses a generator polynomial of g(x) = X3+X+1, with a non-direct
seed value = '111'. Message data from the transmitted message is read into the CRC
calculator LSB first, and the data is augmented with '000'. Start bits are not used in the
CRC calculation. Table 263 shows some example CRC calculation values for 10-bit data
transmissions.
Table 263.ꢀPSI5 3-bit CRC calculation examples
Data transmitted
CRC
C1
1
HEX
0x000
0x0CC
0x151
0x1E0
0x1F4
0x220
0x275
0x333
0x3FF
D9
0
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
C2
1
C0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
13.3.4 PSI5 data field and data range values
Table 264 shows the details for each data range. The PSI5 data field size is defined by
the PDCMFORMAT bits in the SOURCEID_x registers as described in Section 11.2.13.2.
Table 264.ꢀPSI5 data values
16-bit data values
10-bit data value
Binary Hex
Description
Description
(EMSG_EXT = 1 in PSI5_CFG)
(EMSG_EXT = 0 in
PSI5_CFG)
Dec
Hex
Dec
+32704
+32640
7FC0
7F80
+511
+510
1FF Reserved
1FE
Reserved
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Table 264.ꢀPSI5 data values...continued
16-bit data values
10-bit data value
Binary
Description
(EMSG_EXT = 1 in PSI5_CFG)
Description
(EMSG_EXT = 0 in
PSI5_CFG)
Dec
Hex
Dec
Hex
+32576
+32512
+32448
+32384
+32320
+32256
+32192
+32128
+32064
+32000
7F40
7F00
7EC0
7E80
7E40
7E00
7DC0
7D80
7D40
7D00
+509
+508
+507
+506
+505
+504
+503
+502
+501
+500
1FD
1FC
1FB
1FA
1F9
1F8
1F7
1F6
1F5
1F4 Reserved
Sensor Defect
Error
+31936
+31872
+31808
+31744
+31680
7CC0
7C80
7C40
7C00
7BC0
+499
+498
+497
+496
+495
1F3 Reserved
Reserved
1F2
1F1
1F0
1EF Communication Error (OSCTRAIN_ERR Reserved (Error
bit)
Mapped to 0x1F4)
+31616
+31552
7B80
7B40
+494
+493
1EE Test Mode Enabled (TESTMODE bit set)
1ED Offset Error (CH0 or CH1 OFFSET_
ERR bit set)
+31488
+31424
+31360
7B00
7AC0
7A80
+492
+491
+490
1EC Temperature Error (TEMP0_ERR or
TEMP1_ERR bit set)
1EB Memory Error (F_OTP_ERR, U_OTP_
ERR or U_RW_ERR set)
1EA Sensor Self-test Error (CH0 or CH1 ST_ Sensor Self-test
ERROR bit set)
Error
+31296
+31232
+31168
+31104
7A40
7A00
79C0
7980
+489
+488
+487
+486
1E9 Reserved
Reserved
Sensor Busy
Sensor Ready
1E8 Sensor Busy
1E7 Sensor Ready
1E6 Sensor Ready, but Unlocked
Sensor Ready, but
Unlocked
+31040
+30976
+30912
NA
7940
7900
78C0
NA
+485
+484
+483
+482
1E5 Reserved
Reserved
1E4
1E3
1E2 Bidirectional Communication: RC "Error" Bidirectional
Communication:
RC "Error"
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Table 264.ꢀPSI5 data values...continued
16-bit data values
10-bit data value
Binary Hex
Description
(EMSG_EXT = 1 in PSI5_CFG)
Description
(EMSG_EXT = 0 in
PSI5_CFG)
Dec
Hex
Dec
NA
NA
+481
1E1 Bidirectional Communication: RC "OK"
1E0 Maximum positive sensor value
Bidirectional
Communication:
RC "OK"
+30720
7800
+480
Maximum positive
sensor value
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
Positive sensor values
Positive sensor
values
+129 to +192 0081 to 00C0
+3
+2
+1
0
003
002
001
+65 to +128
+1 to +64
0
0041 to 0080
0001 to 0040
0000
000 Zero
Zero
–1 to –64
FFFF to FFC0
–1
–2
–3
3FF Negative sensor values
Negative sensor
values
–65 to –128 FFBF to FF80
–129 to –192 FF7F to FF40
3FE
3FD
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
–30720
8800
–480
220 Maximum negative sensor value
Maximum negative
sensor value
–30784
87C0
–481 1000011111 21F Initialization Data Codes
10-bit Status Data Nibble 1 - 16 (0000 - 1111) (Dx)
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
–31744
–31808
8400
83C0
–496 1000010000 210
–497 1000001111 20F Initialization Data IDs
Block ID 1 - 16 (10-bit Mode) (IDx)
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
∙
–32767
8000
–512 1000000000 200
13.4 Initialization
Following power-up, the device proceeds through an initialization process which is
divided into 3 phases:
• Initialization Phase 1: No Data transmissions occur
• Initialization Phase 2: Sensor self-test and transmission of configuration information
• Initialization Phase 3: Transmission of the "Sensor Busy" and / or "Sensor Ready" /
"Sensor Defect" messages
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Once initialization is completed the device begins normal mode operation, which
continues as long as the supply voltage remains within the specified limits.
In asynchronous mode, initialization data is transmitted for Source ID 0 only.
In synchronous mode, the initialization data is transmitted independently for each
channel.
In daisy chain mode, initialization data is transmitted in the Source ID 0 and Source ID 2
time slot as defined by the sensor address as documented in Section 13.8.
In Dual Transmission mode, initialization data is transmitted for both Source ID 0 and
Source ID 2 in the Source ID 0 timeslot as documented in Section 13.7.
sync pulses ignored or
program mode entry
normal mode
sync pulses
V
IDLE
SYNC
V
IDLE
ground
I
+ I
R_PSI5
q
I
q
POR
init 2
normal mode
init 1
init 3
aaa-030673
Figure 88.ꢀPSI5 sensor 10-bit initialization
During PSI5 initialization, the device completes an internal initialization process
consisting of the following:
• Power-on reset
• Device Initialization
• Program mode entry verification
• Offset cancellation low-pass filter initialization
• Self-test
Figure 89 shows the timing for internal and external initialization in synchronous mode.
Figure 90 shows the timing for internal and external initialization in asynchronous mode.
Timing parameters are specified in Section 10.12.
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external
PSI5 initialization
phase 1
PSI5 initialization
phase 2
PSI5 initialization
phase 3
PSI5
normal mode
t
PSI5Delay_Before_MasterSync_Pulses
t
t
t
PSI5_INIT1
PSI5_INIT2
PSI5_INIT3
sync. pulses ignored
self test
repeat
offset cancellation LPF init
self test
(if necessary)
ST_RPT * t
ST
t
t
PSI5ST_START
ST
programming mode entry
no
PM
entry
1) Min. 31 sync pulses
2) PME command
otherwise
sync
pulses
ignored
sync pulses ignored
PM
entry
t
t
RS_PM
PME
programming
mode
aaa-030674
Figure 89.ꢀPSI5 initialization timing, synchronous mode
PSI5 initialization
phase 1
PSI5 initialization
phase 2
PSI5 initialization
phase 3
PSI5
normal mode
t
ASYNC
t
t
t
PSI5_INIT1
PSI5_INIT2
PSI5_INIT3
self test
repeat
offset cancellation LPF init
self test
(if necessary)
t
t
ST_RPT * t
PSI5ST_START
ST
ST
programming mode entry
no
PM
entry
1) Min. 31 sync pulses
2) PME command
otherwise
sync
pulses
ignored
sync pulses ignored
PM
entry
t
t
RS_PM
PME
programming
mode
aaa-030675
Figure 90.ꢀPSI5 initialization timing, asynchronous mode
13.4.1 PSI5 initialization phase 1
During PSI5 initialization phase 1, the device begins internal initialization and self-checks,
but transmits no data. Initialization begins with this sequence, shown in Figure 89:
1. Internal delay to ensure analog circuitry has stabilized (tPOR_PSI5
2. Offset cancellation low-pass filter initialization begins (tPSI5ST_START
3. Monitor for the Programming Mode Entry Sequence (tPME
4. If the Programming Mode Entry Sequence is not detected, the device enters
)
)
)
Initialization Phase 2 (tPSI5_INIT2
)
13.4.2 PSI5 initialization phase 2
During PSI5 initialization phase 2, the device continues its internal selfchecks and
transmits the PSI5 initialization phase 2 data. Initialization data is transmitted using
the initialization data codes and IDs specified in Table 264, and in the order shown in
Table 265.
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Table 265.ꢀPSI5 initialization phase 2 data transmission order
D1
D2
...
...
...
D32
ID11
D11
ID12
D12
...
ID1k
D1k
ID21
D21
ID22
D22
...
ID2k
D2k
ID321 D321 ID322 D322
Repeat k times
...
ID32k D32k
Repeat k times
Repeat k times
The Initialization phase 2 time is calculated using Equation 17.
(17)
Where:
TransNibble
=
ꢀ
# of Transmissions per Data Nibble
2: 1 for ID, and 1 for Data
ꢀ
k
=
=
=
The repetition rate for the data fields
32 data fields or 48 data fields (if INIT2_EXT is set)
Sync Pulse Period
Data Fields
tS-S
13.4.2.1 PSI5 initialization phase 2 data transmissions
In PSI5 initialization phase 2, the device transmits a sequence of sensor specific
configuration and serial number information. The transmission data is in conformance
with the PSI5[5] specification, and AKLV27[3]. Unique data content is transmitted for each
channel. The data content and transmission format is shown in Table 267 and Table 268.
Table 266 shows the phase 2 timing for different operating modes. Times are calculated
using the equation in Section 13.4.2.
Table 266.ꢀInitialization phase 2 time
Operating mode
Repetition rate (k)
# of transmissions
Nominal phase 2 time
116.7 ms
Asynchronous Mode (228 µs)
Synchronous Mode (500 µs)
8
4
512
256
128.0 ms
Table 267.ꢀChannel 0 PSI5 initialization phase 2 data
PSI5
PSI5
Page
PSI5 nibble address
Register address
PSI5 description
Value
field ID #
nibble ID #
address
F1
F2
D1
0
0000
USERDATA_0[3:0]
NA
User Specific Data
User
D2, D3
0001, 0010
Number of Data Blocks: 32: INIT2_EXT = 0, 48:
INIT2_EXT = 1
0010 0000
or
0011 0000
F3
F4
F5
D4, D5
D6, D7
D8
0011, 0100
0101, 0110
0111
USERDATA_1[3:0], USERDATA_1[7:4]
USERDATA_2[3:0], USERDATA_2[7:4]
USERDATA_3[3:0]
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User
User
User
User
User
User
User
User
User
User
User
User
User
D9
1000
USERDATA_3[7:4]
F6
F7
D10
D11
1001
USERDATA_4[3:0]
1010
USERDATA_4[7:4]
D12
D13
D14
D15
D16
D17
D18
1011
USERDATA_5[3:0]
1100
USERDATA_5[7:4]
1101
USERDATA_6[3:0]
F8
1110
USERDATA_7[3:0]
1111
USERDATA_7[7:4]
1
0000
USERDATA_8[3:0]
0001
USERDATA_8[7:4]
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Dual channel inertial sensor
Table 267.ꢀChannel 0 PSI5 initialization phase 2 data...continued
PSI5
PSI5
Page
PSI5 nibble address
Register address
PSI5 description
Value
field ID #
nibble ID #
address
F9
D19
D20
0010
0011
SN4[7:4] or USERDATA_6[7:4]
SN4[3:0] or USERDATA_E[7:4]
Data determined by PSI5_INIT2_D19 in
TIMING_CFG2 register
User
User
Data determined by PSI5_INIT2_D19 in
TIMING_CFG2 register
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
SN3[7:4]
SN3[3:0]
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Part Number
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
User
SN2[7:4]
SN2[3:0]
SN1[7:4]
SN1[3:0]
SN0[7:4]
SN0[3:0]
PN1[3:0]
PN0[7:4]
Device Part Number
PN0[3:0]
Device Part Number
USERDATA_6[7:4]
CH0_STAVG_P[7:4]
CH0_STAVG_P[3:0]
CH0_STOFFSET_P[7:4]
User Specific Data
F10
2
Channel 0 Positive Self-test, High Nibble
Channel 0 Positive Self-test, Low Nibble
Varies
Varies
Channel 0 Post Positive Self-test Offset, High
Nibble
Varies
D36
0011
CH0_STOFFSET_P[3:0]
Channel 0 Post Positive Self-test Offset, Low
Nibble
Varies
D37
D38
D39
0100
0101
0110
CH0_STAVG_N[7:4]
CH0_STAVG_N[3:0]
Channel 0 Negative Self-test, High Nibble
Channel 0 Negative Self-test, Low Nibble
Varies
Varies
Varies
CH0_STOFFSET_N[7:4]
Channel 0 Post Negative Self-test Offset, High
Nibble
D40
0111
CH0_STOFFSET_N[3:0]
Channel 0 Post Negative Self-test Offset, Low
Nibble
Varies
D41
D42
D43
1000
1001
1010
CH1_STAVG_P[7:4]
CH1_STAVG_P[3:0]
Channel 1 Positive Self-test, High Nibble
Channel 1 Positive Self-test, Low Nibble
Varies
Varies
Varies
CH1_STOFFSET_P[7:4]
Channel 1 Post Positive Self-test Offset, High
Nibble
D44
1011
CH1_STOFFSET_P[3:0]
Channel 1 Post Positive Self-test Offset, Low
Nibble
Varies
D45
D46
D47
1100
1101
1110
CH1_STAVG_N[7:4]
CH1_STAVG_N[3:0]
Channel 1 Negative Self-test, High Nibble
Channel 1 Negative Self-test, Low Nibble
Varies
Varies
Varies
CH1_STOFFSET_N[7:4]
Channel 1 Post Negative Self-test Offset, High
Nibble
D48
1111
CH1_STOFFSET_N[3:0]
Channel 1 Post Negative Self-test Offset, Low
Nibble
Varies
Table 268.ꢀChannel 1 PSI5 Initialization Phase 2 Data
PSI5
PSI5
Page
PSI5 nibble address
Register address
Description
Value
field ID #
nibble ID #
address
F1
F2
D1
0
0000
USERDATA_0[7:4]
NA
User Specific Data
User
D2, D3
0001, 0010
Number of Data Blocks: 32: INIT2_EXT = 0, 48:
INIT2_EXT = 1
0010 0000
or
0011 0000
F3
F4
F5
D4, D5
D6, D7
D8
0011, 0100
0101, 0110
0111
USERDATA_9[3:0], USERDATA_9[7:4]
USERDATA_A[3:0], USERDATA_A[7:4]
USERDATA_B[3:0]
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User
User
User
User
User
User
D9
1000
USERDATA_B[7:4]
F6
D10
1001
USERDATA_C[3:0]
D11
1010
USERDATA_C[7:4]
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Table 268.ꢀChannel 1 PSI5 Initialization Phase 2 Data...continued
PSI5
PSI5
Page
PSI5 nibble address
Register address
Description
Value
field ID #
nibble ID #
address
F7
D12
D13
D14
D15
D16
D17
D18
D19
1011
1100
1101
1110
1111
0000
0001
0010
USERDATA_D[3:0]
USERDATA_D[7:4]
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User Specific Data
User
User
User
User
User
User
User
USERDATA_E[3:0]
F8
USERDATA_7[3:0]
USERDATA_7[7:4]
1
USERDATA_8[3:0]
USERDATA_8[7:4]
F9
SN4[7:4] or USERDATA_6[7:4]
Data determined by PSI5_INIT2_D19 in
TIMING_CFG2 register
User
D20
0011
SN4[3:0] or USERDATA_E[7:4]
Data determined by PSI5_INIT2_D19 in
TIMING_CFG2 register
User
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
SN3[7:4]
SN3[3:0]
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Serial Number
Device Part Number
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
User
SN2[7:4]
SN2[3:0]
SN1[7:4]
SN1[3:0]
SN0[7:4]
SN0[3:0]
PN1[3:0]
PN0[7:4]
Device Part Number
PN0[3:0]
Device Part Number
USERDATA_E[7:4]
CH0_STAVG_P[7:4]
CH0_STAVG_P[3:0]
CH0_STOFFSET_P[7:4]
User Specific Data
F10
2
Channel 0 Positive Self-test, High Nibble
Channel 0 Positive Self-test, Low Nibble
Varies
Varies
Channel 0 Post Positive Self-test Offset, High
Nibble
Varies
D36
0011
CH0_STOFFSET_P[3:0]
Channel 0 Post Positive Self-test Offset, Low
Nibble
Varies
D37
D38
D39
0100
0101
0110
CH0_STAVG_N[7:4]
CH0_STAVG_N[3:0]
Channel 0 Negative Self-test, High Nibble
Channel 0 Negative Self-test, Low Nibble
Varies
Varies
Varies
CH0_STOFFSET_N[7:4]
Channel 0 Post Negative Self-test Offset, High
Nibble
D40
0111
CH0_STOFFSET_N[3:0]
Channel 0 Post Negative Self-test Offset, Low
Nibble
Varies
D41
D42
D43
1000
1001
1010
CH1_STAVG_P[7:4]
CH1_STAVG_P[3:0]
Channel 1 Positive Self-test, High Nibble
Channel 1 Positive Self-test, Low Nibble
Varies
Varies
Varies
CH1_STOFFSET_P[7:4]
Channel 1 Post Positive Self-test Offset, High
Nibble
D44
1011
CH1_STOFFSET_P[3:0]
Channel 1 Post Positive Self-test Offset, Low
Nibble
Varies
D45
D46
D47
1100
1101
1110
CH1_STAVG_N[7:4]
CH1_STAVG_N[3:0]
Channel 1 Negative Self-test, High Nibble
Channel 1 Negative Self-test, Low Nibble
Varies
Varies
Varies
CH1_STOFFSET_N[7:4]
Channel 1 Post Negative Self-test Offset, High
Nibble
D48
1111
CH1_STOFFSET_N[3:0]
Channel 1 Post Negative Self-test Offset, Low
Nibble
Varies
Note: Offset and self-test data in Field ID #10 is only transmitted if the internal self-
test for the associated channel has completed and has passed before F10, D33 is to be
transmitted. This can only occur if the internal self-test sequence passes the first time.
If F10, D33 is to be transmitted before the internal self-test has completed for a specific
channel, the latest self-test, and offset values are transmitted.
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Note: If self-test has completed all retries and has failed before F10, D33 is to be
transmitted, F10, D33 - D48 will include self-test data from the last failed attempt.
Note: In PSI5 asynchronous mode, self-test will not be complete prior to the
transmission of the F10. Setting the INIT2_EXT bit will result in invalid self-test data in
D33 and D34 (0x0 values).
Note: Constant values are transmitted for all fields marked as "RESERVED"
13.4.3 Internal self-test
Once Initialization Phase 1 completes, the device begins its internal self-test as
described in Section 11.6.2.5. If self-test fails, the device repeats self-test up to ST_RPT
times.
13.4.4 Initialization phase 3
During PSI5 initialization phase 3, the device completes its internal self-checks, and
transmits a combination of "Sensor Busy" or "Sensor Ready" messages as defined in
Table 264. The number of "Sensor Busy" messages transmitted in initialization phase
3 varies depending on the mode of operation, and the number of self-test repetitions.
Self-test is repeated on failure up to ST_RPT times to provide immunity to misuse
inputs during initialization. Self-test terminates successfully after one successful self-test
sequence.
Once internal self-test is completed, the device transmits 2 "Sensor Ready" commands.
Note: Self-test repeats are handled independently for each channel. However, both
channels will exit initialization phase 3 simultaneously. If only one channel is repeating
self-tests, both channels transmit "Sensor Busy" commands until either self-test has
passed on both channels or the total number of repeats have completed.
The ENDINIT bit is automatically set when the device exits Initialization Phase 3.
13.5 Normal mode
13.5.1 Asynchronous mode
The device can be programmed to respond in asynchronous mode as specified in
Section 11.2.18.1.
In asynchronous mode, the device transmits data at a fixed rate (tASYNC) and will not
respond to normal sync pulses. However, during initialization phase 1, the device will
monitor sync pulses to decode the programming mode entry command and allow entry
into programming mode.
13.5.2 Simultaneous sampling mode
The device can be programmed to respond in simultaneous sampling mode by
programming the SS_EN bit to "Simultaneous Sampling Mode".
In simultaneous sampling mode, the most recent interpolated sensor data sample
is latched at tTRIG (rising edge of Sync Pulse) and transmitted starting at the time
programmed in the PDCM_RSPSTx registers, relative to tTRIG
.
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Dual channel inertial sensor
0
100
200
300
400
500
600
700
800
900
1000
Time (µs)
t
+ t
LAT_INTERP
LAT_DSI
t
PDCM_RSPSTx
aaa-030676
Figure 91.ꢀSimultaneous sampling mode
13.5.3 Synchronous sampling mode with minimum latency
The device can be programmed to respond in synchronous sampling mode with
minimum latency by programming the SS_EN bit to "Synchronous Sampling Mode".
In synchronous sampling mode, the most recent interpolated sensor data sample is
latched at the time programmed in the PDCM_RSPSTx registers, relative to tTRIG (rising
edge of Sync pulse). The data is transmitted starting at the time programmed in the
PDCM_RSPSTx registers, relative to tTRIG
.
0
100
t
200
300
400
500
600
700
800
900
1000
Time (µs)
t
+ t
LAT_PSI5
LAT_INTERP
PDCM_RSPSTx
aaa-030677
Figure 92.ꢀSynchronous sampling mode with minimum latency
13.6 PSI5 default mode (un-programmed PSI5 device)
Un-programmed FXLS93xxx PSI5 devices include a default PSI5 transmission mode.
The devices will respond to PSI5 sync pulses and transmit data in PSI5-P16C-500/2L
mode with the minimum user gain and the default 400 Hz, 4-Pole low-pass filter.
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Table 269 shows the default PSI5 response transmission, Table 270 shows the PSI5
timing parameters, and Table 271 and Table 272 show the sensor data configuration
details for each channel.
The default settings apply until the UF2 user OTP memory is written and the UF2 block is
locked.
500 µs
Ch1 Response
47 µs
Ch0 Response
Ch0 Response
244 µs
aaa-038810
Figure 93.ꢀ PSI5 default mode transmission
Table 269.ꢀDefault PSI5-P16C transmission mode
Start bits Sensor data (See Section 11.6.4.9)
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C2 C1 C0
Init Data 10-bit Initialization Data as specified in Section 13.4.2.1 C2 C1 C0
CRC
0
0
0
0
0
0
Table 270.ꢀDefault PSI5-P16C transmission mode timing parameters
Parameter
Default typical value
Default register bit values
Ch0 Time Slot
Ch1 Time Slot
Data Size
47 µs
$27, $26: $PDCM_RSPST0 = 0x002F
$2B, $2A: $PDCM_RSPST1 = 0x00F4
$1A: SOURCEID_0[6:4] = 3'b100
$25: PSI5_CFG[2] = 1'b1
244 µs
16-bit
Error Checking
Baud Rate
3-bit CRC
Low Baud Rate: 125 kB/s, Bit Time = 8.0 µs
$23: CHIPTIME[3:0] = 3'b1000
Table 271.ꢀDefault PSI5-P16C transmission mode, High g sensor data configuration
Parameter
Value
Default register bit values
Sensor Data Range
Sensor Data Sensitivity
Sensor data low-pass filter
702.6 g
$40, $48: CHx_CFG_U1[1:0] = 2'b00
$41, $49: CHx_CFG_U2[7:0] = 0x00
$40, $48: CHx_CFG_U1[7:4] = 4'b0000
$43, $4B: CHx_CFG_U4[5:4] = 2'b00
43.79 LSB/g
400 Hz, 4-Pole LPF
Sensor data offset cancellation 0.04 Hz, 1-Pole HPF with Rate Limiting
Enabled
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Table 272.ꢀDefault PSI5-P16C transmission mode, Medium g sensor data configuration
Parameter
Value
Default register bit values
Sensor data range
Sensor data sensitivity
Sensor data low-pass filter
232.6 g
$40, $48: CHx_CFG_U1[1:0] = 2'b00
$41, $49: CHx_CFG_U2[7:0] = 0x00
$40, $48: CHx_CFG_U1[7:4] = 4'b0000
$43, $4B: CHx_CFG_U4[5:4] = 2'b00
132.06 LSB/g
400 Hz, 4-Pole LPF
Sensor data offset cancellation 0.04 Hz, 1-Pole HPF with Rate Limiting
Enabled
13.7 Dual transmission mode
The device can be programmed to transmit both channel 0 and channel 1 data in one
data packet if the DUALTRANS bit is set in the PSI5_CFG register. In dual transmission
mode, the source identification settings specified in Section 11.2.17.4 determine the data
transmitted as shown in Table 273 through Table 276.
Table 273.ꢀDual transmission mode 10-bit transmission data with parity
SID1_EN SID0_EN Response start time
Response format
No Transmission
No Transmission
0
0
PDCM_RSTST0
PDCM_RSTST1
PDCM_RSTST0
0
1
Start Bits
CH1_SNSDATA0
CH0_SNSDATA0
Parity
P
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
PDCM_RSTST1
PDCM_RSTST0
PDCM_RSTST1
No Transmission
No Transmission
1
1
0
1
Start Bits
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Start Bits CH1_SNSDATA0 CH0_SNSDATA0
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
Start Bits CH1_SNSDATA1 CH0_SNSDATA1
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
CH1_SNSDATA1
CH0_SNSDATA1
Parity
P
PDCM_RSTST0
PDCM_RSTST1
Parity
P
Parity
P
Table 274.ꢀDual transmission mode 10-bit transmission data with CRC
SID1_EN SID0_EN Response start time
Response format
0
0
PDCM_RSTST0
PDCM_RSTST1
PDCM_RSTST0
No Transmission
No Transmission
0
1
Start Bits
CH1_SNSDATA0
CH0_SNSDATA0
CRC
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 C2 C1 C0
PDCM_RSTST1
PDCM_RSTST0
PDCM_RSTST1
No Transmission
No Transmission
1
1
0
1
Start Bits
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 C2 C1 C0
Start Bits CH1_SNSDATA0 CH0_SNSDATA0 CRC
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 C2 C1 C0
Start Bits CH1_SNSDATA1 CH0_SNSDATA1 CRC
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 C2 C1 C0
CH1_SNSDATA1
CH0_SNSDATA1
CRC
PDCM_RSTST0
PDCM_RSTST1
Table 275.ꢀDual transmission mode 16-bit transmission data with parity
SID1_EN SID0_EN Response start time
Response format
0
0
PDCM_RSTST0
PDCM_RSTST1
No Transmission
No Transmission
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Table 275.ꢀDual transmission mode 16-bit transmission data with parity...continued
SID1_EN SID0_EN Response start time
Response format
0
1
1
1
0
1
PDCM_RSTST0
Start
CH1_SNSDATA0
CH0_SNSDATA0
P
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 P
PDCM_RSTST1
PDCM_RSTST0
PDCM_RSTST1
No Transmission
No Transmission
Start
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 P
Start CH1_SNSDATA0 CH0_SNSDATA0
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 P
Start CH1_SNSDATA1 CH0_SNSDATA1
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15 P
CH1_SNSDATA1
CH0_SNSDATA1
P
PDCM_RSTST0
PDCM_RSTST1
P
P
Table 276.ꢀDual transmission mode 16-bit transmission data with CRC
SID1_EN SID0_EN Response start
time
Response format
0
0
0
1
PDCM_RSTST0
PDCM_RSTST1
PDCM_RSTST0
No Transmission
No Transmission
Start
CH1_SNSDATA0
CH0_SNSDATA0
CRC
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11D12D13D14D15D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11D12D13D14D15C2 C1 C0
PDCM_RSTST1
PDCM_RSTST0
PDCM_RSTST1
No Transmission
No Transmission
1
1
0
1
Start
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11D12D13D14D15D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11D12D13D14D15C2 C1 C0
Start CH1_SNSDATA0 CH0_SNSDATA0 CRC
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11D12D13D14D15D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11D12D13D14D15C2 C1 C0
Start CH1_SNSDATA1 CH0_SNSDATA1 CRC
S2 S1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11D12D13D14D15D0 D1 D2 D3 D4 D5 D6 D7 D8 D9D10D11D12D13D14D15C2 C1 C0
CH1_SNSDATA1
CH0_SNSDATA1
CRC
PDCM_RSTST0
PDCM_RSTST1
13.8 Daisy chain mode
The device can be programmed to operate in daisy chain mode by setting the
DAISY_CHAIN bit in the PSI5_CFG register. Daisy chain mode can be programmed to
operate in either "Simultaneous Sampling Mode", or "Synchronous Sampling Mode" by
setting the SS_EN bit to the desired operating mode. In simultaneous sampling mode,
the most recent interpolated sensor data sample is latched at tTRIG (rising edge of Sync
Pulse). In synchronous sampling mode, the most recent interpolated sensor data sample
is latched at the transmission time associated with the programmed sensor address,
relative to tTRIG (rising edge of Sync pulse).
When programmed to operate in daisy chain mode, the device follows the procedure:
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1. After a power on delay of tRS_PM, the device waits for a PSI5 "Set Address" command
defined in Table 278 and Table 279.
a. The Set Address command must be preceded by at least 31 and no more than
60 consecutive sync pulses. All other commands must be preceded by either 31
consecutive sync pulses or 5 consecutive missing sync pulses.
b. The Daisy Chain Programming command and response formats are defined in
Section 13.10.2 using a sync pulse period of ts-s_DC. The response settings are
defined in Table 292, with the exception of the time slot.
c. The response to the PSI5 Set Address command and all other valid commands
uses the Source ID 0, address-based time slot specified in Table 280.
d. If a framing error or CRC error is detected on a received command, the device
does not respond.
2. After receiving a valid address and completing the response, the device will decode
and respond to all Table 278 commands sent to the sensor address it is set to. All
responses are transmitted in the address-based time slot specified in Table 280.
3. When the "Run Mode" command is received, the device responds to the command
using the address-based time slot(s) specified in Table 280. The device then ignores
all commands and proceeds through Initialization Phase 2 and Initialization Phase 3
in response to sync pulses. The following response format is used, regardless of the
state of the relevant bits in the Device Configuration Registers:
Table 277.ꢀDaisy chain: Run mode configuration
Parameter
Time Slot
Reference
Value
Section 11.2.18.1
Section 11.2.13.2
Section 11.2.17.6
Section 11.2.15.4
Address-based time slot(s) specified in Table 280
Data size controlled by the PDCMFORMAT bits
Even Parity
Data Size
Error Checking
Baud Rate
Baud Rate controlled by the CHIPTIME bits
• Upon completion of Initialization Phase 3, the ENDINIT bit is set, the device enters
normal mode and responds to all sync pulses with sensor data according to
Table 278,Table 279, and Table 280.
Table 278.ꢀDaisy chain programming commands and responses
CMD
type
SAdr
A1
0
FC
Command
Response (OK)
A2
0
A0
0
F2 F1 F0
RC
OK
OK
OK
OK
OK
RD1
SAdr
Short
Short
Short
Short
Short
A2 A1 A0 Set Sensor Address (Daisy Chain)
1
1
1
0
0
1
0
0
1
0
0
1
Broadcast Message - "Run Mode"
Activate Low Side Bus Switch
Deactivate Low Side Bus Switch
0x000
0x000
0x111
SAdr
SAdr = 1, 2, 3, 4, 5, 6
SAdr = 1, 2, 3, 4, 5, 6
SAdr = 1, 2, 3, 4, 5, 6
A2 A1 A0 Set Sensor Address (Daisy Chain)
Table 279.ꢀDaisy chain programming response code definitions
Response code
RC = OK
Definition
Value
0x1E1
0x1E2
Command Message Received Properly.
Error during transmission of Command Message.
RC = Error
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Table 279.ꢀDaisy chain programming response code definitions...continued
Response code
Definition
Value
SAdr
Programmed Sensor Address, prepended with logic zeros.
Varies
Table 280.ꢀValid daisy chain addresses
Sensor address (SAdr) Description
Time slot source ID 0
Time slot source ID 2
A2
0
A1
0
A0
0
Un-programmed sensor N/A
N/A
0
0
1
Sensor Address 1
Sensor Address 2
Sensor Address 3
Sensor Address 4
Sensor Address 5
Sensor Address 6
N/A
tTIMESLOT_DC0
tTIMESLOT_DC1_L
tTIMESLOT_DC2_L
tTIMESLOT_DC1_H
tTIMESLOT_DC2_H
tTIMESLOT_DC3_H
N/A
tTIMESLOT_DC1_L
tTIMESLOT_DC2_L
tTIMESLOT_DC0
tTIMESLOT_DC2_H
tTIMESLOT_DC3_H
tTIMESLOT_DC0
N/A
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Note: Writes to Sensor Address 7 are ignored.
Note: If a successful programming mode entry command is received prior to a set
address, daisy chain mode is disabled.
13.9 Error handling
13.9.1 Daisy chain error handling
Table 281 shows the effect of internal failure modes on the daisy chain initialization
procedure.
Table 281.ꢀDaisy chain error handling
Error condition
Supply Error
Effect on daisy chain
Daisy chain commands ignored. The device will not participate in daisy chain.
No effect. The device will participate in Daisy Chain as programmed.
Daisy chain commands ignored. The device will not participate in daisy chain.
No effect. The device will participate in daisy chain as programmed.
No effect. The device will participate in daisy chain as programmed.
No effect. The device will participate in daisy chain as programmed.
No effect. The device will participate in daisy chain as programmed.
No effect. The device will participate in daisy chain as programmed.
Communication Error
Test Mode Enabled
Offset Error
Temperature Error
Memory Error
Self-test Error
Device Not Locked
13.9.2 Initialization phase 2 error handling
Table 282 shows the effect of internal failure modes on the initialization phase 2
transmissions. Some errors occurring in initialization phase 2 will prevent entry into
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initialization phase 3. Once the error is no longer present, the device will complete
initialization phase 2 as necessary and then transition to initialization phase 3.
Table 282.ꢀInitialization phase 2 error handling
Error condition
Supply Error
Effect on initialization phase 2
Temporary, Sync Pulses Ignored
Communication Error
Test Mode Enabled
Offset Error
No Effect
No Effect
No Effect
Temperature Error
Memory Error
No Effect. The device will attempt to transmit Initialization Phase 2 data.
No Effect. The device will attempt to transmit Initialization Phase 2 data.
Self-test Error
No Effect
No Effect
Device Not Locked
13.9.3 Initialization phase 3 error handling
Table 283 shows the effect of internal failure modes on the initialization phase 3
procedures. Some errors occurring in initialization phase 3 will prevent entry into run
mode until the error is no longer present. Once the error is no longer present, one or
more Sensor Ready commands are transmitted before entering Run Mode.
Table 283.ꢀInitialization phase 3 error handling
Error condition
Supply Error
Effect on initialization phase 3
Temporary, Sync Pulses Ignored
Communication Error
Test Mode Enabled
Offset Error
No Effect
No Effect
No Effect
Temperature Error
Memory Error
No Effect. The device will attempt to transmit Initialization Phase 3 data.
No Effect. The device will attempt to transmit Initialization Phase 3 data.
No Effect
Self-test Error
Device Not Locked
Sensor Ready replaced with Sensor Ready, but Not Locked Transmission (UF2 Region is
un-programmed)
13.9.4 Normal mode error handling with internal error automatic clearing
Section 13.9.4.1 and Section 13.9.4.2 summarize the error reporting if the
PSI5_ERRLATCH bit is not set. A single error transmission clears the device status
allowing for temporary error conditions to be cleared once the error condition is removed.
13.9.4.1 Standard error reporting
Table 284 summarizes the error reporting in normal mode if the PSI5 error extension
option is disabled.
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Table 284.ꢀStandard error reporting
Error condition
Supply Error
Error code Error response
NA
Temporary (Normal transmissions continue once condition is removed)
Communication Error
Test Mode Enabled
Offset Error
Temporary (Normal transmissions continue once condition is removed)
Temporary (Normal transmissions continue once condition is removed)
Temporary (Normal transmissions continue once condition is removed)[1]
Temporary (Normal transmissions continue once condition is removed)
Latched until reset
0x1F4
Temperature Error
Memory Error
Self-test Error
0x1EA
NA
Latched until reset[2]
Device Not Locked
NA
[1] An offset error on either channel results in an offset error response from both channels.
[2] A self-test error on either channel results in a self-test error response from both channels.
13.9.4.2 PSI5 error extension option
If the PSI5 error extension option is enabled, additional error reporting is available as
shown in Table 285.
Table 285.ꢀPSI5 error extension option
Error condition
Supply Error
Error code Error response
NA
Temporary (Normal transmissions continue once condition is removed)
Communication Error
Test Mode Enabled
Offset Error
0x1EF
0x1EE
0x1ED
0x1EC
0x1EB
0x1EA
NA
Temporary (Normal transmissions continue once condition is removed)
Temporary (Normal transmissions continue once condition is removed)
Temporary (Normal transmissions continue once condition is removed)[1]
Temporary (Normal transmissions continue once condition is removed)
Latched until reset
Temperature Error
Memory Error
Self-test Error
Latched until reset[2]
Device Not Locked
NA
[1] An offset error on either channel results in an offset error response from both channels.
[2] A self-test error on either channel results in a self-test error response from both channels.
13.9.5 Normal mode error handling with internal error latching
Section 13.9.5.1 and Section 13.9.5.2 summarize the error reporting if the
PSI5_ERRLATCH bit is set. Internal errors are latched until reset.
13.9.5.1 Standard error reporting
Table 286 summarizes the error reporting in normal mode if the PSI5 Error Extension
option is disabled.
Table 286.ꢀStandard error reporting
Error condition
Supply Error
Error code Error response
NA
Temporary (Normal transmissions continue once condition is removed)
Temporary (Normal transmissions continue once condition is removed)
Communication Error
0x1F4
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Table 286.ꢀStandard error reporting...continued
Error condition
Test Mode Enabled
Offset Error
Error code Error response
Latched until reset
Latched until reset.[1]
Latched until reset
Latched until reset
Latched until reset.[2]
NA
Temperature Error
Memory Error
Self-test Error
0x1EA
NA
Device Not Locked
[1] An offset error on either channel results in an offset error response from both channels.
[2] A self-test error on either channel results in a self-test error response from both channels.
13.9.5.2 PSI5 error extension option
If the PSI5 error extension option is enabled, additional error reporting is available as
shown in Table 287.
Table 287.ꢀPSI5 error extension option
Error condition
Supply Error
Error code Error response
NA
Temporary (Normal transmissions continue once condition is removed)
Communication Error
Test Mode Enabled
Offset Error
0x1EF
0x1EE
0x1ED
0x1EC
0x1EB
0x1EA
NA
Temporary (Normal transmissions continue once condition is removed)
Latched until reset
Latched until reset.[1]
Latched until reset
Latched until reset
Latched until reset.[2]
NA
Temperature Error
Memory Error
Self-test Error
Device Not Locked
[1] An offset error on either channel results in an offset error response from both channels.
[2] A self-test error on either channel results in a self-test error response from both channels.
13.10 PSI5 programming mode
PSI5 Programming mode is a synchronous communication mode that allows for
bidirectional communication with the device. Programming mode is intended for factory
programming of the OTP array and reading of diagnostic information. It is not intended
for use in normal operation.
13.10.1 PSI5 programming mode entry
The device enters programming mode if and only if the following sequence occurs:
1. At least 31 sync pulses are detected, directly preceding the Programming Mode Entry
Short Command during the Programming Mode Entry Window shown in Figure 89.
• The window timing is defined in Section 10.12 (tPME).
• The Sync pulses and Programming Mode Entry command must be received with a
sync pulse period of tS-S_PM
If the Programming Mode entry requirement is not met:
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1. Programming Mode Entry is blocked until the device is reset.
2. The device proceeds with PSI5 Initialization Phase 2, and PSI5 Initialization Phase 3.
3. The device enters normal mode, and responds as programmed to normal sync
pulses.
If the Programming Mode entry requirement is met:
1. Normal transmissions to sync pulses are terminated.
2. The device will detect commands if the start condition is met as described in
Section 13.10.2.2.
3. The device responds only to valid PSI5 Short and XLong Commands addressed to
Sensor Address '001', as defined in Section 13.10.3.
13.10.2 PSI5 programming mode - data link layer
13.10.2.1 PSI5 programming mode - command bit encoding
Commands messages are transmitted via the modulation of the supply voltage. The
presence of a sync pulse is a logic '1' and the absence of a sync pulse is a logic '0'. Sync
pulses are expected at a rate of tS-S_PM
.
13.10.2.2 PSI5 programming mode - command message format
Once programming mode is enabled, command message data frames consist of a start
condition, 3 Start Bits (S[2:0]), a 3-bit sensor address (SAdr[2:0]), a 3-bit function code
(FC[2:0]), an optional register address (RAdr[7:0]), an optional data field (D[7:0]), and a
3-bit CRC (C[2:0]. The start condition consists of one of the following:
1. A minimum of 5 consecutive logic '0's (with no sync bits)
2. A minimum of 31 consecutive logic '1's (this includes logic '1's transmitted for the
previous response)
The command message format is shown in Table 289.
Table 288.ꢀProgramming mode via PSI5 command data format
Start bits
Sensor Addr
Function code
Register address
Data
CRC
C1
0
S2
S1
S0
SA0
SA1
SA2
FC0
FC1
FC2
RA0
RA1
RA2
RA3
RA4
RA5
RA6
RA7
D0
D1
D2
D3
D4
D5
D6
D7
C2
0
C0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
CRC
Data to be written to register (optional)
Register Address (optional)
Function Codes (See Section 13.10.3)
Sensor Address - Fixed at 001
Start Bit Sequence = 010
Table 289.ꢀProgramming mode via PSI5 command data format - response
Response
RC
RD1
RD0
$3FF
$3FF
$3FF
Bit stuffing is necessary to maintain a synchronized timebase between the command
master and the device. A logic '1' Sync bit is added every fourth bit in the command
message to ensure that there will never be more than 3 logic '0' bits in a row.
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Table 290.ꢀProgramming mode via PSI5 XLONG command data format with sync bits
Start bits
Sensor
address
Function
code
Register address
Data
CRC
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy RA6 RA7 D0 Sy D1 D2 D3 Sy D4 D5 D6 Sy D7 C2 C1 Sy C0
0
1
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
Table 291.ꢀProgramming mode via PSI5 XLONG command data format with sync bits - response
Response
RC
RD1
RD0
$1E2
$3FF
$3FF
Once a command is received and verified, the device expects 2 to 3 consecutive sync
pulses (depending upon the command message lengths described in Table 292). There
is no delay restriction between the command and the first sync pulse for the response.
Once the first sync pulse for the response is received, each successive response sync
pulse must be received within the programming mode sync pulse period specified (tS-
S_PM) or a framing error may occur.
For each of these sync pulses, The device will respond with the following settings:
Table 292.ꢀProgramming mode via PSI5 response message settings
Parameter
Value
Time Slot
tTIMESLOT_DC0
10-bit data
Even Parity
125 kBd
Data Size
Error Checking
Baud Rate
Sync Pulse Pulldown
Disabled
13.10.2.3 Short frame command and response format
Short frames are the simplest type of command message. No data is transmitted in a
short frame command. Only specific instructions are performed in response to short
frame commands. The short frame format is shown in Table 293. Short frame commands
and responses are defined in Section 13.10.3.
The device only supports a short command for programming mode entry.
Table 293.ꢀProgramming mode via PSI5 short command
Start bits
Sensor address
Function code
CRC
C1
0
S2
S1
S0
Sy
SA0
SA1
SA2
Sy
FC0
FC1
FC2
Sy
C2
C0
0
1
0
1
1
0
0
1
0
0
1
1
0
0
Table 294.ꢀResponse format
Response
RC
$1E2
RD1
$3FF
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13.10.2.4 Long frame command and response format
Long frames allow for the transmission of data nibbles for register writes. The device
can provide register data in response to a read or write request. the long frame format is
shown in Table 295. The device does not support the long frame command.
Table 295.ꢀProgramming mode via PSI5 long command
Start Bits
Sensor Address
Function Code
Register Address
Data
CRC
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy D0 D1 D2 Sy D3 C2 C1 Sy C0
0
1
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
1
0
Table 296.ꢀResponse format
Response
RD1
RC
RD0
$1E2
$3FF
$3FF
13.10.2.5 Extra long frame command and response format
Extra long frames allow for the transmission of address and data bytes for register reads
and writes. The device can provide register data in response to a read or write request.
The extra long frame format is shown in Table 297. Extra long frame commands and
responses are defined in Section 13.10.3.
The device supports register read and register write extra long commands.
Table 297.ꢀProgramming mode via PSI5 long command
Start Bits
Sensor
Address
Function
Code
Register Address
Data
CRC
S2 S1 S0 Sy SA0 SA1 SA2 Sy FC0 FC1 FC2 Sy RA0 RA1 RA2 Sy RA3 RA4 RA5 Sy RA6 RA7 D0 Sy D1 D2 D3 Sy D4 D5 D6 Sy D7 C2 C1 Sy C0
0
1
0
1
1
0
0
1
0
1
0
1
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
Table 298.ꢀResponse format
Response
RD1
RC
RD0
$1E2
$3FF
$3FF
13.10.2.6 Command message CRC
Programming mode command error checking is accomplished by a 3-bit CRC. The 3-
bit CRC is calculated using all message bits except start bits and sync bits. The CRC
verification uses a generator polynomial of g(x) = X3+X+1, with a non-direct seed value
= '111'. The message data is provided to the CRC calculator in the order received (LSB
first, SAdr, FC, RAdr, Data), and then augmented with '000'. Table 263 shows some
example CRC calculation values for 10-bit data transmissions.
The calculated CRC is then compared against the received 3-bit CRC (received MSB
first). If a CRC mismatch is detected, the device responds with a CRC Error response as
defined in Section 13.10.4.
13.10.2.7 Command sync pulse blanking time
In programming mode and programming mode entry, the device employs a fixed sync
pulse blanking time of tSYNC_OFF_250 regardless of the state of the PDCM_CMD_B
register value.
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13.10.2.8 Command timeout
In the event that the device does not detect a sync pulse within a 4-bit window time, the
command reception will be terminated and the device will respond to the next sync pulse
with a Short Frame Framing Error response as defined in Section 13.10.4.
13.10.3 PSI5 programming mode command and response summary
Table 299.ꢀProgramming mode via PSI5 commands and responses
CMD type
SAdr
FC
Command
Register Data field
address
Response (OK)
RD1
Response (Error)
FC[2:0]
RC
RD0
RC
RD1
RD0
Short
Short
Short
Short
Long
001
100
101
110
111
010
011
000
001
Invalid Command
N/A
N/A
N/A
N/A
No Response
No Response
No Response
0x0CA
No Response
No Response
No Response
No Response
No Response
No Response
ErrN
Invalid Command
Invalid Command
N/A
N/A
Enter Programming Mode
Invalid Command
N/A
N/A
OK
N/A
N/A
N/A
No Response
No Response
RData
Long
Invalid Command
N/A
N/A
XLong
XLong
Read register located at address RA7:RA0
Write WData to register RA7:RA0
Varies
Varies
Varies
Varies
OK
OK
RData+1
RA7:RA0
Error
Error
0x000
0x000
WData
ErrN
Table 300.ꢀProgramming mode via PSI5 response code definitions
Response code
RC = OK
Definition
Value
0x1E1
0x1E2
Varies
Varies
Varies
Command Message Received Properly
Error during transmission of Command Message
RC = Error
RData
Byte Contents of Register located at address RA7:RA1 with RA0 = 0 (Low Byte)
Byte Contents of Register located at address RA7:RA1 with RA0 = 1 (High Byte)
Byte Contents of Register located at address RA7:RA0
RData + 1
WData
13.10.4 Programming mode via PSI5 error response summary
Table 301.ꢀError response summary
ErrN
Mnemon Description
ic
Supported
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
General
Framing
CRC
General Error
No
Framing Error (4 consecutive zeros) Yes
CRC Error on Received Message
Sensor Address Not Supported
Function Code Not Supported
Yes
Address
FC
No (Invalid Address is ignored)
No (N/A)
Reserved Reserved
No
Reserved Reserved
No
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Table 301.ꢀError response summary...continued
ErrN
Mnemon Description
ic
Supported
1100
1101
1110
1111
ErrN is transmitted in the 4 LSBs of RD1. All other bits in the response data field are set
to '0'.
13.11 PSI5 OTP programming procedure
1. Enter programming mode.
2. Set VCC = VPP
3. Load desired data into the desired registers using PSI5 Write commands.
4. Write the necessary OTP program sequence to the WRITE_OTP_EN register for the
desired OTP region to be written.
5. Delay tPROG_TIME after the completion of the Write OTP program to allow for
completion of the OTP writes.
6. Read the DEVSTAT and DEVSTAT2 registers to confirm that no errors occurred
during the OTP writes.
7. Read back the register values that were written and compare to the desired values to
confirm successful OTP writes.
Refer to the PSI5 OTP Programming Procedure Application Note for further details on
OTP programming.
14 Standard 32-bit SPI protocol
The device includes a standard SPI protocol requiring 32-bit data packets. The device is
a slave device requires that the base clock value be low (CPOL = 0) with data captured
on the rising edge of the clock and data propagated on the falling edge of the clock
(CPHA = 0). The most significant bit is transferred first (MSB first). SPI transfers are
completed through a sequence of two phases. During the first phase, the command is
transmitted from the SPI master to the device. During the second phase, response data
is transmitted from the slave device. MOSI and SCLK transitions are ignored when SS_B
is not asserted.
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SCLK
SS_B
MOSI
phase one: command
phase one: response - previous command
phase two: response
MISO
SCLK
SS_B
MOSI
T1
T2
R1
T3
R2
R3
MISO
aaa-030678
Figure 94.ꢀStandard 32-bit SPI protocol timing diagram
14.1 SPI command format
Table 302.ꢀSPI command format
MSB
LSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Register Access Command
Command
C[3:0]
Fixed Bits:
Must = 0x0
Register Address
RA[7:1]
Register Data
RD[7:0]
8-bit CRC
CRC[7:0]
0
0
0
0
0
0
RA[0]
Sensor Data Command
Command
C[3:0]
Fixed Bits: Must = 0x00000
8-bit CRC
CRC[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14.2 SPI response format
Table 303.ꢀSPI response format
MSB
LSB
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Response to Register Request
Command
Basic
Unused
Data = 0x0
Register Data: Contents of RA[7:1] High Byte
Register Data: Contents of RA[7:1] Low Byte
8-bit CRC
CRC[7:0]
Status
C[0] C[3] C[2] C[1]
ST[1:0]
0
0
RD[15:8]
RD[7:0]
Response to Sensor Data Request
Sensor Data
Command
Basic
Detail
8-bit CRC
CRC[7:0]
Status
Status
C[0] C[3] C[2] C[1]
ST[1:0]
SD[11:0]
Optional SD resolution
Error Response to Register Request
SF[1:0]
Command
Basic
Unused
Data = 0x0
Register Data: Contents of RA[7:1] High Byte
Register Data: Contents of RA[7:1] Low Byte
8-bit CRC
CRC[7:0]
Status
0
0
0
0
1
1
0
0
RD[15:8]
RD[7:0]
Error Response to Sensor Data Request With Sensor Data
Sensor Data
Command
Basic
Detail
8-bit CRC
Status
Status
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Table 303.ꢀSPI response format...continued
MSB
LSB
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C[0] C[3] C[2] C[1]
1
1
SD[11:0]
Optional SD resolution
SF[1:0]
CRC[7:0]
Error Response to Sensor Data Request Without Sensor Data
Unused Data = 0x0000
Command
Basic
Status
x
x
Detail
8-bit CRC
CRC[7:0]
Status
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SF[1:0]
14.3 Command summary
Table 304.ꢀCommand summary
C[3:0] Command type
Data source
Reference
SOURCEID[2:0] = C[3:1]
0
0
0
0
Unused Command (Reserved for Error
Response)
Not Applicable
Not Applicable
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Sensor Data Request
Reserved Command
Sensor Data Request
Reserved Command
Sensor Data Request
Reserved Command
Sensor Data Request
Register Write Request
Sensor Data Request
Reserved Command
Sensor Data Request
Register Read Request
Sensor Data Request
Reserved Command
Sensor Data Request
SOURCEID[3:0] = 0x0
Not Applicable
Section 14.3.3
Not Applicable
Section 14.3.3
Not Applicable
Section 14.3.3
Not Applicable
Section 14.3.3
Section 14.3.2
Section 14.3.3
Not Applicable
Section 14.3.3
Section 14.3.1
Section 14.3.3
Not Applicable
Section 14.3.3
SOURCEID[3:0] = 0x1
Not Applicable
SOURCEID[3:0] = 0x2
Not Applicable
SOURCEID[3:0] = 0x3
Not Applicable
SOURCEID[3:0] = 0x4
Not Applicable
SOURCEID[3:0] = 0x5
Not Applicable
SOURCEID[3:0] = 0x6
Not Applicable
SOURCEID[3:0] = 0x7
14.3.1 Register read command
The device supports a Register Read command. The Register Read command uses the
upper 7 bits of the addresses defined in Section 11.1 to address two 8-bit registers in the
register map. The response to the command includes the con-tents of RA[7:1] high byte
(RA[0] = 1) in the upper byte and the contents of RA[7:1] low byte (RA[0] = 0) in the lower
byte.
The response to a register read command is shown in Section 14.3.1.2. The response is
transmitted on the next SPI message if and only if all of the following conditions are met:
• No SPI Error is detected (See Section 14.5.6)
• No MISO Error is detected (See Section 14.5.7)
If the conditions are met, the device responds to the register read request as shown in
Section 14.3.1.2. Otherwise, the device responds with the Error Response as defined in
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Section 14.5.4. The Register Read response includes the register contents at the rising
edge of SS_B for the Register Read command.
14.3.1.1 Register read command message format
Table 305.ꢀRegister read command message format
MSB
LSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Command C[3:0]
Fixed Bits:
Must = 0x0
Register Address
Register Data
8-bit CRC
1
1
0
0
0
0
0
0
RA[7:1]
RA[0]
0
0
0
0
0
0
0
0
CRC[7:0]
Table 306.ꢀRegister read command message format description
Bit field
C[3:0]
Definition
Register Read Command = '1100'
RA[7:1]
CRC[7:0]
RA[7:1] contains the word address of the register to be read.
CRC. See Section 14.4
14.3.1.2 Register read response message format
Table 307.ꢀRegister read response message format
MSB
LSB
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Command C[0], [3:1]
Basic
Unused
Data
= 0x0
Register Data: Contents
of RA[7:1] High Byte
Register Data: Contents
of RA[7:1] Low Byte
8-bit CRC
Status
0
1
1
0
0
0
RD[15:8]
RD[7:0]
CRC[7:0]
Table 308.ꢀRegister read response message format description
Bit field
C[0], [3:1]
ST[1:0]
Definition
Register Read Command = '0110'
Status. See Section 14.5.1
RD[15:8]
RD[7:0]
The contents of the register addressed by RA[7:1] High Byte (RA[0] = 1)
The contents of the register addressed by RA[7:1] Low Byte (RA[0] = 0)
CRC. See Section 14.4
CRC[7:0]
14.3.2 Register write command
The device supports a Register Write command. The Register Write command writes
the value specified in RD[7:0] to the register addressed by RA[7:0]. The response to the
command includes the new contents of RA[7:1] high byte (RA[0] = 1) in the upper byte
and the contents of RA[7:1] low byte (RA[0] = 0) in the lower byte.
The response to a register write command is shown in Section 14.3.2.2. The register
write is executed and a response is transmitted on the next SPI message if and only if all
of the following conditions are met:
• No SPI Error is detected (See Section 14.5.6)
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• The ENDINIT bit is cleared
– This applies to all registers with the exception of the RESET[1:0] bits in the
DEVLOCK_WR register
If the conditions are met, the register write is executed and the device responds to the
register write request as shown in Section 14.3.2.2. Otherwise, no register is written and
the device responds with the Error Response as defined in Section 14.2. The register
is not written until the transfer during which the register write was requested has been
completed.
A register write command to a read-only register will not execute, but will result in a valid
response.
14.3.2.1 Register write command message format
Table 309.ꢀRegister write command message format
MSB
LSB
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Command C[3:0]
Fixed Bits:
Must = 0x0
Register Address
Register Data
8-bit CRC
1
0
0
0
0
0
0
0
RA[7:1]
RA[0]
RD[7:0]
CRC[7:0]
Table 310.ꢀRegister write command message format description
Bit field
C[3:0]
Definition
Register Write Command = '1000'
RA[7:0]
RD[7:0]
CRC[7:0]
RA[7:1] contains the byte address of the register to be written.
RD[7:0] contains the data byte to be written to address RA[7:0]
CRC. See Section 14.4
14.3.2.2 Register write response message format
Table 311.ꢀRegister write response message format
MSB
LSB
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Command C[0], [3:1]
Basic
Unused
Data
= 0x0
Register Data: Contents
of RA[7:1] High Byte
Register Data: Contents
of RA[7:1] Low Byte
8-bit CRC
Status
0
1
0
0
ST[1:0]
0
0
RD[15:8]
RD[7:0]
CRC[7:0]
Table 312.ꢀRegister write response message format description
Bit field
C[0], [3:1]
ST[1:0]
Definition
Register Write Command = '0100'
Status. See Section 14.5.1
RD[15:8]
RD[7:0]
The contents of the register addressed by RA[7:1] High Byte (RA[0] = 1)
The contents of the register addressed by RA[7:1] Low Byte (RA[0] = 0)
CRC. See Section 14.4
CRC[7:0]
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14.3.3 Sensor data request commands
The device supports standard sensor data request commands. The sensor data request
command format is described in Section 14.3.3.1. The response to a sensor data request
is shown in Section 14.3.3.2. The response is transmitted on the next SPI message
subject to the error handling conditions specified in Section 14.5. The sensor data
included in the response is the sensor data at the falling edge of SS_B for the Sensor
Data Request response.
14.3.3.1 Sensor data request command message format
Table 313.ꢀSensor data request command message format
MSB
LSB
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11
10
9
8
7
6
5
4
3
2
1
Command
C[3:0]
Fixed Bits: Must = 0x00000
8-bit CRC
CRC[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 314.ꢀSensor data request command message format description
Bit field
Definition
C[0]
Sensor Data Request Command = '1'
C[3:1] = SOURCEID[2:0]
CRC[7:0]
Source Identification code for the requested sensor data. See Section 11.2.13.
CRC. See Section 14.4
14.3.3.2 Sensor data request response message format
Table 315.ꢀSensor data request response message format
MSB
LSB
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Command C[0], [3:1]
Basic
Sensor Data
Detail
8-bit CRC
Status
Status
1
C[3] C[2] C[1] ST[1:0]
SD[11:0]
Optional SD
resolution
SF[1:0]
CRC[7:0]
Table 316.ꢀSensor data request response message format description
Bit field
Definition
C[0]
Sensor Data Request Command = '1'
C[3:1] = SOURCEID[2:0]
ST[1:0]
Source Identification code for the requested sensor data. See Section 11.2.13.
Basic Status. See Section 14.5.1
SD[11:0]
Sensor Data. See Section 11.6.4.9
Optional SD Resolution
SF[1:0]
Optional for 16-bit Sensor Data. See Section 11.6.4.9
Detailed Status. See Section 14.5.3
CRC[7:0]
CRC. See Section 14.4
14.3.4 Reserved commands
The device responds to reserved commands on the next SPI message subject to the
error handling conditions specified in Section 14.5.
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14.3.4.1 Reserved command message format
MSB
LSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
x
x
x
x
x
x
x
8
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
Command
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8-bit CRC
CRC[7:0]
CRC[7:0]
CRC[7:0]
CRC[7:0]
CRC[7:0]
CRC[7:0]
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
1
1
0
0
0
0
0
0
Bit field
Definition
Reserved Command
CRC. See Section 14.4
C[3:0]
CRC[7:0]
14.3.4.2 Reserved command response message format
Table 317.ꢀReserved command response message format
MSB
LSB
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Command Echo
Data
8-bit CRC
CRC[7:0]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Table 318.ꢀReserved command response message format description
Bit field
Definition
Command Echo
Data
Reserved Command Echo - Undefined
Response Data - Undefined
CRC. See Section 14.4
CRC[7:0]
14.4 Error checking
14.4.1 Default 8-bit CRC
14.4.1.1 Command error checking
The device calculates an 8-bit CRC on the entire 32-bits of each command. Message
data is entered into the CRC calculator MSB first, consistent with the transmission
order of the message. If the calculated CRC does not match the transmitted CRC, the
command is ignored and the device responds with the SPI Error response.
The CRC decoding procedure is:
1. A seed value is preset into the least significant bits of the shift register.
2. Using a serial CRC calculation method, the receiver rotates the received message
and CRC into the least significant bits of the shift register in the order received (MSB
first).
3. When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
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4. If the shift register contains all zeros, the CRC is correct.
5. If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed are shown in Table 319.
Table 319.ꢀSPI command message CRC
SPICRCSEED[3:0]
0000
Default polynomial
Default non-direct seed
1111 1111
x8 + x5 + x3 + x2 + x + 1
x8 + x5 + x3 + x2 + x + 1
Non-Zero
1111 SPICRCSEED[3:0]
Some example CRC calculations are shown in Table 321.
14.4.1.2 Response error checking
The device calculates a CRC on the entire 32-bits of each response. Message data is
entered into the CRC calculator MSB first, consistent with the transmission order of the
message.
The CRC Encoding procedure is:
1. A seed value is preset into the least significant bits of the shift register.
2. Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
3. Following the transmitted message, the transmitter feeds eight zeros into the shift
register, to match the length of the CRC.
4. When the last zero is fed into the input adder, the shift register contains the CRC.
5. The CRC is transmitted.
The CRC polynomial and seed are shown in Table 320.
Table 320.ꢀSPI CRC polynomial and seed
SPICRCSEED[3:0]
0000
Default polynomial
Default non-direct seed
1111 1111
x8 + x5 + x3 + x2 + x + 1
x8 + x5 + x3 + x2 + x + 1
Non-Zero
1111 SPICRCSEED[3:0]
Some example CRC calculations are shown in Table 321.
Table 321.ꢀSPI 8-bit CRC calculation examples
Polynomial
Seed
Bits[31:28]
Command
0x8
Bits[27:24]
0x0
Bits[23:16]
Bits[15:8]
Bits[7:0]
Register address Register data
8-bit CRC
0xBD
0x57
x8 + x5 + x3 + x2 + x + 1
x8 + x5 + x3 + x2 + x + 1
x8 + x5 + x3 + x2 + x + 1
x8 + x5 + x3 + x2 + x + 1
x8 + x5 + x3 + x2 + x + 1
x8 + x5 + x3 + x2 + x + 1
x8 + x5 + x3 + x2 + x + 1
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0x0
22
1F
22
1F
FF
3E
FF
C1
C1
00
C1
5A
00
5A
0x4
0x0
0xC
0x0
0x66
0x6
0x0
0xB8
0x4
0x0
0xE5
0xC
0x0
0x13
0x6
0x0
0x0A
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14.4.2 Selectable 4-bit CRC
The user can select a 4-bit CRC instead of the default 8-bit CRC for the SPI by
programming the SPI_CFG register as described in Section 11.2.20.
14.4.2.1 SPI command format with 4-bit CRC
Table 322.ꢀSPI command format with 4-bit CRC
MSB
LSB
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
0
0
6
5
4
0
0
3
2
1
Register Access Command
Command
C[3:0]
Fixed Bits:
Must = 0x0
Register Address
RA[7:1]
Register Data
RD[7:0]
Fixed Bits:
Must = 0x0
4-bit CRC
CRC[3:0]
0
0
0
0
0
0
0
0
RA[0]
0
0
Sensor Data Command
Command
C[3:0]
Fixed Bits: Must = 0x00000
Fixed Bits:
Must = 0x0
4-bit CRC
CRC[3:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14.4.2.2 SPI response format with 4-bit CRC
Table 323.ꢀSPI response format with 4-bit CRC
MSB
LSB
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Response to Register Request
Command
Basic
Unused
Data
= 0x0
Register Data: Contents
of RA[7:1] High Byte
Register Data: Contents
of RA[7:1] Low Byte
Unused Data = 0x0
4-bit CRC
CRC[3:0]
Status
C[0] C[3] C[2] C[1] ST[1:0]
0
0
RD[15:8]
RD[7:0]
0
0
0
0
Response to Sensor Data Request
Sensor Data
Command
Basic
Detail
KAC
4-bit CRC
CRC[3:0]
Status
Status
C[0] C[3] C[2] C[1] ST[1:0]
SD[11:0]
Optional SD
resolution
SF[1:0]
KAC[3:0]
Error Response to Register Request
Command
Basic
Unused
Data
= 0x0
Register Data: Contents
of RA[7:1] High Byte
Register Data: Contents
of RA[7:1] Low Byte
Unused Data = 0x0
4-bit CRC
CRC[3:0]
Status
0
0
0
0
1
1
0
0
RD[15:8]
RD[7:0]
0
0
0
0
Error Response to Sensor Data Request With Sensor Data
Sensor Data
Command
Basic
Detail
KAC
4-bit CRC
CRC[3:0]
Status
Status
C[0] C[3] C[2] C[1]
Command
1
1
SD[11:0]
Optional SD
resolution
SF[1:0]
KAC[3:0]
Error Response to Sensor Data Request Without Sensor Data
Unused Data = 0x0000
Basic
x
x
Detail
Unused Data = 0x0
4-bit CRC
CRC[3:0]
Status
Status
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SF[1:0]
0
0
0
0
14.4.2.3 Command error checking with 4-bit CRC
The device calculates a 4-bit CRC on the entire 32-bits of each command. Message data
is entered into the CRC calculator MSB first, consistent with the transmission order of the
message. If the calculated CRC does not match the transmitted CRC, the command is
ignored and the device responds with the SPI Error response.
The CRC decoding procedure is:
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1. A seed value determined by the SPICRCSEED[3:0] value in the SPI_CFG register is
preset into the least significant bits of the shift register.
2. Using a serial CRC calculation method, the receiver rotates the received message
and CRC into the least significant bits of the shift register in the order received (MSB
first).
3. When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
4. If the shift register contains all zeros, the CRC is correct.
5. If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed are shown in Table 324.
Table 324.ꢀSPI command message CRC, 4 bit
Default polynomial
Non-direct seed
x4 + 1
SPICRCSEED[3:0]
14.4.2.4 Response error checking with 4-bit CRC
The device calculates a CRC on the entire 32-bits of each response. Message data is
entered into the CRC calculator MSB first, consistent with the transmission order of the
message.
The CRC Encoding procedure is:
1. A seed value determined by the SPICRCSEED[3:0] value is preset into the least
significant bits of the shift register.
2. Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
3. Following the transmitted message, the transmitter feeds four zeros into the shift
register, to match the length of the CRC.
4. When the last zero is fed into the input adder, the shift register contains the CRC.
5. The CRC is transmitted.
The CRC polynomial and seed are shown in Table 325.
Table 325.ꢀSPI response message CRC, 4-bit
Default polynomial
Non-direct seed
x4 + 1
SPICRCSEED[3:0]
14.4.2.5 Message counter (KAC) with 4-bit CRC
If the 4-bit CRC is enabled, a 4-bit message counter field (KAC) is added to the Sensor
Data Request Response. The message counter field is a 4-bit rolling message counter
that is independently incremented for each SOURCEID. The initial value of the counter is
'0001'.
14.4.2.6 Example 4-bit CRC calculations
Some example CRC calculations for 32-bit SPI commands are shown in Table 326.
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Table 326.ꢀSPI 4-bit CRC calculation examples
Polynomial
Seed
Bits[31:28]
Command
0x8
Bits[27:24]
0x0
Bits[23:16]
Bits[15:8]
Bits[7:4]
0x0
Bits[3:0]
4-bit CRC
0xF
Register address Register data
x4 + 1
x4 + 1
x4 + 1
x4 + 1
x4 + 1
x4 + 1
x4 + 1
1010
1010
1010
1010
1010
1010
1010
0x0
22
1F
22
1F
FF
3E
FF
C1
C1
00
C1
5A
00
5A
0x0
0x4
0x0
0x0
0xD
0xC
0x0
0x0
0x6
0x6
0x0
0x0
0xF
0x4
0x0
0x0
0x1
0xC
0x0
0x0
0xB
0x6
0x0
0x0
0x3
14.4.3 Selectable 3-bit CRC
The user can select a 3-bit CRC instead of the default 8-bit CRC for the SPI by
programming the SPI_CFG register as described in Section 11.2.20.
14.4.3.1 SPI command format with 3-bit CRC
Table 327.ꢀSPI command format with 3-bit CRC
MSB
LSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Register Access Command
Command
C[3:0]
Fixed Bits:
Must = 0x0
Register Address
RA[7:1]
Register Data
RD[7:0]
Fixed Bits: Must = 0x00
3-bit CRC
CRC[2:0]
0
0
0
0
0
0
RA[0]
0
0
0
0
0
Sensor Data Command
Command
C[3:0]
Fixed Bits: Must = 0x00000
Fixed Bits: Must = 0x00
3-bit CRC
CRC[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14.4.3.2 SPI response format with 3-bit CRC
Table 328.ꢀSPI response format with 3-bit CRC
MSB
LSB
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Response to Register Request
Command
Basic
Unused
Data
= 0x0
Register Data: Contents
of RA[7:1] High Byte
Register Data: Contents
of RA[7:1] Low Byte
Unused Data = 0x00
3-bit CRC
CRC[2:0]
Status
C[0] C[3] C[2] C[1] ST[1:0]
0
0
RD[15:8]
RD[7:0]
0
0
0
0
0
Response to Sensor Data Request
Sensor Data
Command
Basic
Detail
KAC
1
1
3-bit CRC
CRC[2:0]
Status
Status
C[0] C[3] C[2] C[1] ST[1:0]
SD[11:0]
Optional SD
resolution
SF[1:0]
KAC[3:0]
Error Response to Register Request
Command
Basic
Unused
Data
= 0x0
Register Data: Contents
of RA[7:1] High Byte
Register Data: Contents
of RA[7:1] Low Byte
Unused Data = 0x00
3-bit CRC
CRC[2:0]
Status
0
0
0
0
1
1
0
0
RD[15:8]
RD[7:0]
0
0
0
0
0
Error Response to Sensor Data Request With Sensor Data
Sensor Data
Command
Basic
Detail
KAC
1
1
3-bit CRC
CRC[2:0]
Status
Status
C[0] C[3] C[2] C[1]
1
1
SD[11:0]
Optional SD
resolution
SF[1:0]
KAC[3:0]
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Table 328.ꢀSPI response format with 3-bit CRC...continued
MSB
LSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Error Response to Sensor Data Request Without Sensor Data
Command
Basic
x
x
Unused Data = 0x0000
Detail
Unused Data = 0x00
3-bit CRC
CRC[2:0]
Status
Status
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SF[1:0]
0
0
0
0
0
14.4.3.3 Command error checking with 3-bit CRC
The device calculates a 3-bit CRC on the entire 32-bits of each command. Message data
is entered into the CRC calculator MSB first, consistent with the transmission order of the
message. If the calculated CRC does not match the transmitted CRC, the command is
ignored and the device responds with the SPI Error response.
The CRC decoding procedure is:
1. A seed value determined by the SPICRCSEED[2:0] value in the SPI_CFG register is
preset into the least significant bits of the shift register.
2. Using a serial CRC calculation method, the receiver rotates the received message
and CRC into the least significant bits of the shift register in the order received (MSB
first).
3. When the calculation on the last bit of the CRC is rotated into the shift register, the
shift register contains the CRC check result.
4. If the shift register contains all zeros, the CRC is correct.
5. If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial and seed are shown in Table 329.
Table 329.ꢀSPI command message CRC, 3 bit
Default polynomial
Non-direct seed
x3 + x + 1
SPICRCSEED[2:0]
Some example CRC calculations are shown in Table 263.
14.4.3.4 Response error checking with 3-bit CRC
The device calculates a CRC on the entire 32-bits of each response. Message data is
entered into the CRC calculator MSB first, consistent with the transmission order of the
message.
The CRC encoding procedure is:
1. A seed value determined by the SPICRCSEED[2:0] value is preset into the least
significant bits of the shift register.
2. Using a serial CRC calculation method, the transmitter rotates the transmitted
message into the least significant bits of the shift register, MSB first.
3. Following the transmitted message, the transmitter feeds three zeros into the shift
register, to match the length of the CRC.
4. When the last zero is fed into the input adder, the shift register contains the CRC.
5. The CRC is transmitted.
The CRC polynomial and seed are shown in Table 330.
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Table 330.ꢀSPI response message CRC, 3-bit
Default polynomial
x3 + x + 1
Non-direct seed
SPICRCSEED[2:0]
14.4.3.5 Message (KAC) with 3-bit CRC
If the 3-bit CRC is enabled, a 4-bit message counter field (KAC) is added to the Sensor
Data Request Response. The message counter field is a 4-bit rolling message counter
that is independently incremented for each SOURCEID. The initial value of the counter is
'0001'.
14.4.3.6 Example 3-bit CRC calculations
Some example CRC calculations for 32-bit SPI commands are shown in Table 331.
Table 331.ꢀSPI 3-bit CRC calculation examples
Polynomial
Seed
Bits[31:28]
Bits[27:24]
Bits[23:16]
Bits[15:8]
Bits[7:3]
Bits[2:0]
Command
(Hex)
0x0
Register address Register data
0b00000
(Binary)
3-bit CRC
(Binary)
(Hex)
(Hex)
22
(Hex)
C1
C1
00
x3 + x + 1
x3 + x + 1
x3 + x + 1
x3 + x + 1
x3 + x + 1
x3 + x + 1
x3 + x + 1
111
111
111
111
111
111
111
0x8
0x4
0xC
0x6
0x4
0xC
0x6
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0b00000
0b00000
0b00000
0b00000
0b00000
0b00000
0b00000
0b100
0b010
0b001
0b000
0b000
0b101
0b010
1F
22
1F
C1
5A
FF
3E
FF
00
5A
14.5 Exception handling
14.5.1 Standard basic status reporting field
All responses include a basic status field (ST[1:0]) that includes the general status of the
device and transmitted data as described in Table 332 and Table 333. The contents of
the basic status field is a representation of the device status at the rising edge of SS_B
for the previous SPI command.
14.5.1.1 Basic status field for responses to register commands
Table 332.ꢀBasic status field for responses to register commands
ST[1:0]
Status
Description
Priority
0
0
1
0
1
Device in Initialization
Normal Mode
Self-test
ENDINIT Not Set
3
4
2
1
0
1
1
ENDINIT Set
ST_CTRL[3:0] not equal to '0000' for any channel
See Figure 95
Internal Error Present
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14.5.1.2 Basic status field for responses to sensor data request commands
Table 333.ꢀBasic status field for responses to sensor data request commands
ST[1:0] Status
Description
SF[1:0]
Sensor data field Priority
0
0
1
0
1
0
Device in Initialization
Normal Mode
Self-test
ENDINIT Not Set
ENDINIT Set
0
0
0
0
0
0
Sensor Data
Sensor Data
Sensor Data
3
4
2
ST_CTRL[3:0] not equal
to '0000' for the associated
channel
1
1
Internal Error Present
See Section 14.5.3
See Section 14.5.3 See Section 14.5.3
1
14.5.2 Alternative basic status reporting field
If the SPI_STATUS bit is set in the SPI_CFG register, the basic status reporting is as
shown in Table 334.
Table 334.ꢀAlternative basic status reporting field
ST[1:0] Status
Description
SF[1:0]
Sensor data field Priority
0
0
1
0
1
0
Device in Initialization
Normal Mode
Self-test
ENDINIT Not Set
ENDINIT Set
0
0
0
0
0
0
Sensor Data
Sensor Data
Sensor Data
3
4
2
ST_CTRL[3:0] not equal
to '0000' for the associated
channel for dual axis
1
1
Internal Error Present
See Section 14.5.4
See Section 14.5.4 See Section 14.5.4
1
Figure 95 shows the internal device status mapping by register and the basic status field
contents by response type.
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BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CH0_ERR
CH1_ERR
COMM_ERR
MEMTEMP_ERR
SUPPLY_ERR
TESTMODE
DEVRES
DEVINIT
BIT 7
BIT 6
CH0_ERR
CH1_ERR
Device in Test Mode
CHx_STAT
Device Reset Occured
BIT 7
BIT 6
BIT 5
OC_PHASE
N/A
BIT 4
BIT 3
ST_INC
00, 01
00, 01
BIT 2
ST_ACT
10
BIT 1
OFF_ERR
00, 01
11
BIT 0
ST_ERR
00, 01
SIGCLIP
Basic Status, Register Command
00, 01
11
DSP in initialization Data not Valid
00, 01
Basic Status, Sensor Data Command
N/A
10
BIT 5
COMM_ERR
DEVSTAT3
BIT 7
BIT 6
BIT 5
RSVD
N/A
BIT 4
RSVD
BIT 3
RSVD
N/A
BIT 2
RSVD
N/A
BIT 1
BIT 0
RSVD
N/A
MISO_ERR OSC TRAIN
RSVD
N/A
Basic Status, Register Command
11
11
00, 01
11
N/A
N/A
N/A
N/A
Basic Status, Sensor Data Command
N/A
N/A
N/A
BIT 4
MEMTEMP_ERR
DEVSTAT2
BIT 7
BIT 6
U_OTP_E
00, 01
11
BIT 5
BIT 4
U_W_ACT
00, 01
BIT 3
TEMP1
00, 01
11
BIT 2
TEMP0
00, 01
11
BIT 1
RSVD
N/A
BIT 0
RSVD
N/A
F_OTP_E
00, 01
11
U_RW_E
00, 01
11
Basic Status, Register Command
N/A
N/A
Basic Status, Sensor Data Command
11
BIT 3
SUPPLY_ERR
DEVSTAT1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
INTREG
11
BIT 1
INTREGF
BIT 0
VBUFUV
BUSINUV
VBUFOV
RSVD
N/A
INTREGA
CONT_ERR
Basic Status, Register Command
11
11
11
11
11
11
11
11
11
11
11
11
Basic Status, Sensor Data Command
N/A
11
aaa-030679
Figure 95.ꢀInternal status mapping and SPI basic status content
14.5.3 Standard detailed status field reporting
The response to sensor data requests includes a detailed status field (SF[1:0]). If the
Basic Status indicates an internal error, the contents of the detailed status field provide
additional information regarding the error status. The contents of the detailed status field
is a representation of the device status at the rising edge of SS_B for the previous SPI
command.
Table 335.ꢀSPI error response status field definition
ST[1:0]
SF[1:0] Status sources
DEVSTAT state
SUPERR_
DIS state
Error
priority
Command echo
field (Source ID)
Sensor data request commands
Sensor data field value
PCM
Oscillator Training Error
Bit set in DEVSTAT3
Bit set in CHx_STAT:
N/A
N/A
11
10
C[0], C[3:1]
C[0], C[3:1]
Sensor Data
Sensor Data
No Effect
No Effect
Offset Error
1
1
0
0
SIGNALCLIP or OFF-
SET_ERR
Temperature Error
Bit set in DEVSTAT2
N/A
N/A
9
8
C[0], C[3:1]
0x0
Sensor Data
No Effect
No Effect
User OTP Memory Error
(UF0 or UF1)
U_OTP_ERR set in
DEVSTAT2
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
User R/W Memory Error
(UF2)
U_RW_ERR set in
DEVSTAT2
N/A
N/A
7
6
0x0
0x0
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
No Effect
No Effect
1
1
0
1
NXP OTP Memory Error
F_OTP_ERR set in
DEVSTAT2
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
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Table 335.ꢀSPI error response status field definition...continued
ST[1:0]
SF[1:0] Status sources
DEVSTAT state
SUPERR_
DIS state
Error
priority
Command echo
field (Source ID)
Sensor data request commands
PCM
Sensor data field value
Test Mode Active
Supply Error
TESTMODE bit set in
DEVSTAT
N/A
0
5
4
0x0
0x0
All zero response
No Effect
Disabled
Bit set in DEVSTAT1
All zero response until the supply monitor
timer expires
An Error Code is transmitted for a minimum of
one transmission
(See Section 11.2.2.5)
1
1
1
0
1
4
0x0
All zero response until the supply monitor
timer expires
(See Section 11.2.2.5)
Reset Error
MISO Error
SPI Error
DEVRES set
Bit set in DEVSTAT3
N/A
N/A
N/A
N/A
3
2
1
0x0
0x0
0x0
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
No Effect
No Effect
No Effect
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
1
1
1
1
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
14.5.4 Alternative detailed status field reporting
The response to sensor data requests includes a detailed status field (SF[1:0]). If the
Basic Status indicates an internal error, the contents of the detailed status field provide
additional information regarding the error status. The contents of the detailed status field
is a representation of the device status at the rising edge of SS_B for the previous SPI
command.
If the SPI_STATUS bit is set in the SPI_CFG register, the basic status reporting is shown
in Table 336.
Table 336.ꢀAlternate SPI error response status field definition
ST[1:0]
SF[1:0] Status sources
DEVSTAT state
SUPERR_
DIS state
Error
priority
Command echo
field (Source ID)
Sensor data request commands
Sensor data field value
PCM
Oscillator Training Error
Bit set in DEVSTAT3
N/A
N/A
11
10
C[0], C[3:1]
C[0], C[3:1]
Sensor Data
Sensor Data
No Effect
No Effect
Offset Error
Bit set in CHx_STAT:
OFFSET_ERR
1
1
0
0
Temperature Error
Bit set in DEVSTAT2
N/A
N/A
9
8
C[0], C[3:1]
0x0
Sensor Data
No Effect
No Effect
User OTP Memory Error
(UF0 or UF1)
U_OTP_ERR set in
DEVSTAT2
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
User R/W Memory Error
(UF2)
U_RW_ERR set in
DEVSTAT2
N/A
N/A
7
6
0x0
0x0
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
No Effect
No Effect
1
1
0
1
NXP OTP Memory Error
F_OTP_ERR set in
DEVSTAT2
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
Test Mode Active
Supply Error
TESTMODE bit set in
DEVSTAT
N/A
0
5
4
0x0
0x0
All zero response
No Effect
Disabled
Bit set in DEVSTAT1
All zero response until the supply monitor
timer expires
An Error Code is transmitted for a minimum of
one transmission
(See Section 11.2.2.5)
1
1
1
0
1
4
3
0x0
0x0
All zero response until the supply monitor
timer expires
(See Section 11.2.2.5)
Reset Error
DEVRES set
N/A
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
No Effect
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Table 336.ꢀAlternate SPI error response status field definition...continued
ST[1:0]
SF[1:0] Status sources
DEVSTAT state
SUPERR_
DIS state
Error
priority
Command echo
field (Source ID)
Sensor data request commands
PCM
Sensor data field value
MISO Error
Bit set in DEVSTAT3
N/A
N/A
2
1
0x0
0x0
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
No Effect
1
1
1
1
SPI Error
N/A
The Sensor Data Field Error Code
is transmitted for a minimum of one
transmission
No Effect
14.5.5 Error responses
Table 337.ꢀError responses
MSB
LSB
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Error Response to Register Request
Command
Basic
Unused
Data
= 0x0
Register Data: Contents
of RA[7:1] High Byte
Register Data: Contents
of RA[7:1] Low Byte
8-bit CRC
CRC[7:0]
Status
0
0
0
0
1
1
0
0
RD[15:8]
RD[7:0]
Error Response to Sensor Data Request With Sensor Data
Sensor Data
Command
Basic
Detail
8-bit CRC
CRC[7:0]
Status
Status
C[0] C[3] C[2] C[1]
Command
1
1
SD[11:0]
Optional SD
resolution
SF[1:0]
Error Response to Sensor Data Request Without Sensor Data
Unused Data = 0x0000
Basic
x
x
Detail
8-bit CRC
CRC[7:0]
Status
Status
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SF[1:0]
Table 338.ꢀError response description
Bit field
C[3:0]
Definition
Command bits: all 0s or a command echo
Sensor Data or the Sensor Data Field Error Code.
SD[11:0]
• For unsigned data, the Sensor Data Field Error Code is 0x000
• For signed data, the Sensor Data Field Error Code is 0x800
See Section 14.5.3 for Sensor Data Request commands.
For all other commands, all bits are '0'.
SF[3:0]
Status. See Section 14.5.3
14.5.6 SPI error
The following external SPI conditions result in a SPI error:
• SCLK is high when SS_B is asserted
• The number of SCLK rising edges detected while SS_B is asserted is not equal to 0 or
32
• SCLK is high when SS_B is deasserted
• A command message CRC error is detected (MOSI)
• A Sensor Data Request is received for a SOURCEID that is not enabled
• A Register Write command to any register other than the DEVLOCK_WR register is
received while ENDINIT is set.
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If a SPI error is detected, the device responds with the Error Response as described
in Section 14.5.4 with the Detailed Status Field set to "SPI Error" as defined in
Section 14.5.3.
14.5.7 SPI data output verification error
The device includes a function to verify the integrity of the data output to the MISO pin.
The function compares the data transmitted on the MISO pin to the data intended to be
transmitted. If any one bit doesn't match, a SPI MISO Mismatch Fault is detected and the
MISO_ERR flag in the DEVSTAT3 register is set.
If a valid sensor data request message is received during the SPI transfer with the
MISO mismatch failure, the request is ignored and the device responds with the Error
Response as described in Section 14.5.4 with the Detailed Status Field set to "SPI Error"
as defined in Section 14.5.3. during the subsequent SPI message.
If a valid register write request message is received during the SPI transfer with the
MISO mismatch failure, the register write is completed as requested, but the device
responds with the Error Response as described in Section 14.5.4 with the Detailed
Status Field set to "SPI Error" as defined in Section 14.5.3. during the subsequent SPI
message.
If a valid register read request message is received during the SPI transfer with the MISO
mismatch failure, the register read is ignored and the device responds with the Error
Response as described in Section 14.5.4 with the Detailed Status Field set to "SPI Error"
as defined in Section 14.5.3. during the subsequent SPI message.
SPI data out shift register
data out buffer
MISO
D
Q
D
Q
R
MISO ERR
D
Q
SCLK
R
aaa-030680
Figure 96.ꢀSPI data output verification
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14.6 SPI timing diagram
DSP Out
t
LAT
SS_B
t
t
SCLKR
SCLK
t
SSN
t
LEAD
t
SCLKH
t
t
SSCLK
SCLKF
SCLK
t
SCLKL
t
LAG
t
CLKSS
t
ACCESS
t
t
t
HOLD_OUT
DISABLE
VALID
MISO
t
t
SETUP
HOLD_IN
MOSI
aaa-030681
Figure 97.ꢀSPI timing diagram
15 Inter-integrated circuit (I2C) interface
The device includes an interface compliant to the NXP I2C bus specification UM10204[1].
The device operates in slave mode and includes support for Standard Mode, Fast Mode,
and Fast Mode Plus although the maximum practical operating frequency for I2C in a
given system implementation depends on several factors including the pull-up resistor
values and the total bus capacitance.
15.1 I2C bit transmissions
The state of SDA when SCL is high determines the bit value being transmitted. SDA
must be stable when SCL is high and change when SCL is low as shown in Figure 99.
After the START signal has been transmitted by the master, the bus is considered busy.
Timing for the start condition is specified in Section 10.14.
SDA
SCL
SDA stable
SDA = `1'
SDA stable
SDA = `0'
SDA
changes
aaa-030682
Figure 98.ꢀI2C bit transmissions
15.2 I2C start condition
A bus operation is always started with a start condition (START) from the master.
A START is defined as a high to low transition on SDA while SCL is high as shown
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in Figure 99. After the START signal has been transmitted by the master, the bus is
considered busy. Timing for the start condition is specified in Section 10.14.
A start condition (START) and a repeat START condition (rSTART) are identical.
SDA
SCL
START
aaa-030683
Figure 99.ꢀI2C start condition
15.3 I2C byte transmissions
Data transfers are completed in byte increments. The number of bytes that can be
transmitted per transfer is unrestricted. Each byte must be followed by an Acknowledge
bit (Section 15.4) from the receiver. Data is transferred with the Most Significant Bit
(MSB) first (Figure 100). The master generates all clock pulses, including the ninth clock
for the Acknowledge bit. Timing for the byte transmissions is specified in Section 10.14.
All functions for this device are completed within the Acknowledge clock pulse. Clock
Stretching is not used.
SDA
SCL
START
ACK
ACK
STOP
from slave
from receiver
aaa-030684
Figure 100.ꢀI2C byte transmissions
15.4 I2C acknowledge and not acknowledge transmissions
Each byte must be followed by an Acknowledge bit (ACK) from the receiver. For an ACK,
the transmitter releases SDA during the acknowledge clock pulse and the receiver pulls
SDA low during the high portion of the clock pulse. Set-up and hold times as specified in
Section 10.14 must also be taken into account.
For a Not Acknowledge bit (NACK), SDA remains high during the entire acknowledge
clock pulse. Five conditions lead to a NACK:
1. No receiver is present on the bus with the transmitted address.
2. The addressed receiver is unable to receive or transmit because it is performing some
real-time function and is not ready to start communication with the master.
3. The receiver receives unrecognized data or commands.
4. The receiver cannot receive any more data bytes.
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5. The master-receiver signals the end of the transfer to the slave transmitter.
Following a Not Acknowledge bit, the master can transmit either a STOP to terminate the
transfer, or a repeated START to initiate a new transfer.
An example ACK and NACK are shown in Figure 101.
SDA
SCL
ACK
NACK
9th clock pulse
9th clock pulse
aaa-030685
Figure 101.ꢀI2C acknowledge and not acknowledge transmission
15.5 I2C stop condition
A bus operation is always terminated with a stop condition (STOP) from the master.
A STOP is defined as a Low to high transition on SDA while SCL is high as shown in
Figure 102. After the STOP has been transmitted by the master, the bus is considered
free. Timing for the stop condition is specified in Section 10.14.
SDA
SCL
STOP
aaa-030686
Figure 102.ꢀI2C stop condition
15.6 I2C register transfers
15.6.1 Register write transfers
The device supports I2C register write data transfers. Register write data transfers are
constructed as follows:
1. The master transmits a START condition
2. The master transmits the 7-bit slave address
3. The master transmits a '0' for the Read/Write Bit to indicate a Write operation
4. The slave transmits an ACK
5. The master transmits the register address to be written
6. The slave transmits an ACK
7. The master transmits the data byte to be written to the register address
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8. The slave transmits an ACK
9. The master transmits a STOP condition
S
Slave address
W
A
Register address
A
REGISTER DATA
A
P
ꢀ
Master transmission
Slave transmission
The device automatically increments the register address allowing for multiple register
writes to be completed in one trans-action. In this case, the register write data transfers
are constructed as follows:
1. The master transmits a START condition
2. The master transmits the 7-bit slave address
3. The master transmits a '0' for the Read/Write Bit to indicate a Write operation
4. The slave transmits an ACK
5. The master transmits the register address to be written
6. The slave transmits an ACK
7. The master transmits the data byte to be written to the register address
8. The slave transmits an ACK
9. The master transmits the data byte to be written to the register address +1
10.The slave transmits an ACK
11.Repeat step 9 and step 10 until all registers are written
12.The master transmits a STOP condition
15.6.2 Register read transfers
The device supports I2C register read data transfers. Register read data transfers are
constructed as follows:
1. The master transmits a START condition
2. The master transmits the 7-bit slave address
3. The master transmits a '0' for the Read/Write Bit to indicate a Write operation
4. The slave transmits an ACK
5. The master transmits the register address to be read
6. The slave transmits an ACK
7. The master transmits a repeat START condition
8. The master transmits the 7-bit slave address
9. The master transmits a '1' for the Read/Write Bit to indicate a Read operation
10.The slave transmits an ACK
11.The slave transmits the data from the register addressed
12.The master transmits a NACK
13.The master transmits a STOP condition
S
Slave address
W
A
Register address
A
rSTART
Slave address
R
A
Register data
N
P
ꢀ
Master transmission
Slave transmission
The device automatically increments the register address allowing for multiple register
reads to be completed in one trans-action. In this case, the register read data transfers
are constructed as follows:
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1. The master transmits a START condition
2. The master transmits the 7-bit slave address
3. The master transmits a '0' for the Read/Write Bit to indicate a Write operation
4. The slave transmits an ACK
5. The master transmits the register address to be read
6. The slave transmits an ACK
7. The master transmits a repeat START condition
8. The master transmits the 7-bit slave address
9. The master transmits a '1' for the Read/Write Bit to indicate a Read operation
10.The slave transmits an ACK
11.The slave transmits the data from the register addressed
12.The master transmits an ACK
13.The slave transmits the data byte from register address +1
14.Repeat step 12 and step 13 until all registers are read
15.The master transmits a NACK
16.The master transmits a STOP condition
15.6.3 Sensor data register read wrap around options
The device includes automatic sensor data register read wrap around features to
optimize the number of I2C transactions necessary for continuous reads of sensor data.
15.6.3.1 Single channel register read wrap around
Depending on the state of the SIDx_EN bits in the channel 0 and channel 1
SOURCEID_0 and SOURCEID_1 registers, the register address automatically wraps
back to the DEVSTAT_COPY register as shown in .
Table 339.ꢀDual channel register read wrap around
Ch1
Ch1
Ch0
Ch0
Address increment and wrap around effect
Optimized register
read sequence
SID1_EN SID0_EN
SID1_EN SID0_EN
0
0
0
0
0
0
0
1
Address wraps around from $FF to $00
None
Address wraps from $63 (CH0_SNSDATA0_H) DEVSTAT_COPY,
to $61 (DEVSTAT_COPY)
CH0_SNSDATA0_L,
CH0_SNSDATA0_H
0
0
0
1
1
x
x
x
Address wraps from $65 (CH0_SNSDATA1_H) DEVSTAT_COPY,
to $61 (DEVSTAT_COPY)
CH0_SNSDATA0_L,
CH0_SNSDATA0_H,
CH0_SNSDATA1_L,
CH0_SNSDATA1_H
Address jumps from $65 (CH0_SNSDATA1_H) DEVSTAT_COPY,
to $72 (CH1_SNSDATA0_L)
Address wraps from $73 (CH1_SNSDATA1_H) CH0_SNSDATA0_H,
CH0_SNSDATA0_L,
to $61 (DEVSTAT_COPY)
CH0_SNSDATA1_L,
CH0_SNSDATA1_H,
CH1_SNSDATA0_L,
CH1_SNSDATA0_H
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Table 339.ꢀDual channel register read wrap around...continued
Ch1
Ch1
Ch0
Ch0
Address increment and wrap around effect
Optimized register
read sequence
SID1_EN SID0_EN
SID1_EN SID0_EN
1
x
x
x
Address jumps from $65 (CH0_SNSDATA1_H) DEVSTAT_COPY,
to $72 (CH1_SNSDATA0_L)
CH0_SNSDATA0_L,
Address wraps from $75 (CH1_SNSDATA1_H) CH0_SNSDATA0_H,
to $61 (DEVSTAT_COPY)
CH0_SNSDATA1_L,
CH0_SNSDATA1_H,
CH1_SNSDATA0_L,
CH1_SNSDATA0_H,
CH1_SNSDATA1_L,
CH1_SNSDATA1_H
15.7 I2C timing diagram
t
t
SRISE
t
SFALL
SETUP
70 %
30 %
70 %
30 %
. . .
cont
SDA
SCL
t
VALID
t
SCLH
t
t
HOLD
t
SRISE
SFALL
70 %
30 %
70 %
30 %
70 %
30 %
70 %
30 %
. . .
cont
t
SCLL
th
t
9
clock
STARTHOLD
t
SCL
S
st
1
clock cycle
t
FREE
. . .
SDA
t
STARTSETUP
t
VALID
t
t
STOPSETUP
STARTHOLD
t
REJ
70 %
30 %
. . .
SCL
Sr
P
S
th
9
clock
aaa-030687
Figure 103.ꢀI2C timing diagram
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16 Package outline
Figure 104.ꢀPackage outline for LQFN16 (SOT1688-1(SC))
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Figure 105.ꢀPackage outline detail for LQFN16 (SOT1688-1(SC))
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Figure 106.ꢀPackage outline notes for LQFN16 (SOT1688-1(SC))
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Figure 107.ꢀPackage outline for LQFN16 (SOT1688-1(DD))
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Figure 108.ꢀPackage outline detail for LQFN16 (SOT1688-1(DD))
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Figure 109.ꢀPackage outline notes for LQFN16 (SOT1688-1(DD))
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17 Soldering
Figure 110.ꢀReflow soldering footprint part 1 for HLQFN16 (SOT1688-1(SC))
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Figure 111.ꢀReflow soldering footprint part 2 for HLQFN16 (SOT1688-1(SC))
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Figure 112.ꢀReflow soldering footprint part 3 for HLQFN16 (SOT1688-1(SC))
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Figure 113.ꢀReflow soldering footprint part 4 for HLQFN16 (SOT1688-1(SC))
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Figure 114.ꢀReflow soldering footprint part 5 for HLQFN16 (SOT1688-1(SC))
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Figure 115.ꢀReflow soldering footprint part 1 for HLQFN16 (SOT1688-1(DD))
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Figure 116.ꢀReflow soldering footprint part 2 for HLQFN16 (SOT1688-1(DD))
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Figure 117.ꢀReflow soldering footprint part 3 for HLQFN16 (SOT1688-1(DD))
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Figure 118.ꢀReflow soldering footprint part 4 for HLQFN16 (SOT1688-1(DD))
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Figure 119.ꢀReflow soldering footprint part 5 for HLQFN16 (SOT1688-1(DD))
18 References
[1] UM10204 - I2C-bus specification and user manual, Revision 6
https://www.nxp.com/docs/en/user-guide/UM10204.pdf
[2] DSI3 Standard Revision 1.0, Dated February 16, 2011
https://www.dsiconsortium.org/downloads/DSI3_%20Bus_Standard_r1.00.pdf
[3]p AKLV27 V1.40, Revision 1.20
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[4] AEC - Q100 - Rev-H, September 11, 2014 - Failure Mechanism Based Stress Test Qualification for Integrated Circuits
http://www.aecouncil.com/Documents/AEC_Q100_Rev_H_Base_Document.pdf
AECQ100, Revision H, AEC-Q006
http://www.aecouncil.com/Documents/AEC_Q100_Rev_H_Base_Document.pdf
[5] PSI5 Technical Specification Version 2.1, Dated October 8, 2012
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19 Revision history
Table 340.ꢀRevision history
Document ID
FXLS9xxxx v.6
Modifications
Release date
20210208
Data sheet status
Change notice
Supersedes
Product data sheet
—
FXLS9xxxx v.5.15
• This data sheet has been formatted to comply with the identity guidelines of NXP Semiconductors,
N.V.
• FXLS9xxxx, v.6, Dual Channel Inertial Sensor, supercedes and replaces FXLS9xxxx, v.5.15, Dual
Channel Inertial Sensor.
• Global changes:
– Performed minor grammatical and typographic revisions throughout.
– Updated all images to comply with NXP image standards.
FXLS9xxxx v.5.15
20201208
Product data sheet
—
FXLS9xxxx v.5.14
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20 Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Product [short] data sheet
Qualification
Production
This document contains data from the preliminary specification.
This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
20.2 Definitions
Applications — Applications that are described herein for any of these
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Characteristics sections of this document is not warranted. Constant or
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Right to make changes — NXP Semiconductors reserves the right to
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to result in personal injury, death or severe property or environmental
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applications and therefore such inclusion and/or use is at the customer's own
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Notice: All referenced brands, product names, service names and
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Tables
Tab. 1.
Tab. 2.
Tab. 3.
Ordering information ..........................................2
Ordering options ................................................2
DSI3 discovery mode external component
recommendations ..............................................4
PSI5 parallel or universal mode external
component recommendations ........................... 5
PSI5 daisy chain mode external component
recommendations ..............................................6
SPI external component recommendations .......8
I2C external component recommendations .......8
Dual axis device orientation ............................ 10
Device pinout: SPI or I2C mode ......................11
Tab. 38. Dynamic electrical characteristics - signal
chain, low-pass filter ....................................... 32
Tab. 39. Dynamic electrical characteristics - signal
chain ................................................................34
Tab. 40. Dynamic electrical characteristics - analog
self-test response time ....................................35
Tab. 41. Dynamic electrical characteristics - digital
self-test response time ....................................36
Tab. 42. Dynamic electrical characteristics -
transducer ........................................................37
Tab. 43. Dynamic electrical characteristics - supply
and support circuitry ........................................37
Tab. 44. User accessible data - general device
information .......................................................38
Tab. 45. User accessible data - communication
information .......................................................39
Tab. 46. User accessible data - sensor specific
information .......................................................40
Tab. 47. User accessible data - sensor specific
information .......................................................41
Tab. 48. User accessible data - traceability
information .......................................................42
Tab. 49. Rolling counter register (COUNT) ................... 43
Tab. 50. Device status registers (DEVSTATx) ...............44
Tab. 51. Supply error flag (SUPPLY_ERR) ................... 45
Tab. 52. Test mode (TESTMODE) ................................ 45
Tab. 53. Device reset (DEVRES) ..................................45
Tab. 54. Device initialization (DEVINIT) ........................ 46
Tab. 55. VBUF under-voltage error (VBUFUV_ERR) ....46
Tab. 56. BUS IN under-voltage error (BUSINUV_
ERR) ................................................................46
Tab. 57. VBUF over-voltage error (VBUFOV_ERR) ......46
Tab. 58. Internal analog regulator voltage out of
range error (INTREGA_ERR) ..........................47
Tab. 59. Internal digital regulator voltage out of
range error (INTREG_ERR) ............................47
Tab. 60. Internal OTP regulator voltage out of range
error (INTREGF_ERR) ....................................47
Tab. 61. Continuity monitor error (CONT_ERR) ............47
Tab. 62. NXP OTP array error (F_OTP_ERR) .............. 48
Tab. 63. User OTP array error (U_OTP_ERR) ..............48
Tab. 64. User read/write array error (U_RW_ERR) .......48
Tab. 65. User OTP write in process status bit (U_
W_ACTIVE) .....................................................48
Tab. 66. Channel 1 temperature sensor error
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10. Device pinout: DSI3 or PSI5 mode pinout ....... 12
Tab. 11. Test notes legend ............................................13
Tab. 12. Maximum ratings .............................................14
Tab. 13. Operating range - DSI / PSI5 ..........................14
Tab. 14. Operating range - SPI / I2C ............................ 15
Tab. 15. Electrical characteristics - supply and I/O ........15
Tab. 16. Electrical characteristics - temperature
sensor signal chain ......................................... 16
Tab. 17. Electrical characteristics - inertial sensor
signal chain: High g ........................................ 17
Tab. 18. High g adjusted offset specification limits ........18
Tab. 19. PSI5, High g offset cancellation limits ............. 19
Tab. 20. Lateral, High g, SPI/DSI3 12-bit noise
specification .....................................................19
Tab. 21. Z-Axis, High g, SPI/DSI3 12-bit noise
specification .....................................................20
Tab. 22. Lateral, High g, PSI5 10-bit noise
specification .....................................................20
Tab. 23. Z-Axis, High g, PSI5 10-bit noise
specification .....................................................20
Tab. 24. Electrical characteristics - inertial sensor
signal chain: Medium g ................................... 21
Tab. 25. Medium g, SPI/DSI3 12-bit offset
specification .....................................................22
Tab. 26. Medium g, PSI5 10-bit offset specification .......23
Tab. 27. Lateral, Medium g, SPI/DSI3 12-bit noise
specification .....................................................23
Tab. 28. Z-axis, Medium g, SPI/DSI3 12-bit noise
specification .....................................................24
Tab. 29. Lateral, Medium g, PSI5 10-bit noise
specifications ...................................................24
Tab. 30. Z-axis, Medium g, PSI5 10-bit noise
specification .....................................................24
Tab. 31. Electrical characteristics - inertial sensor
self-test ............................................................24
Tab. 32. Electrical characteristics - lateral inertial
sensor overload ...............................................26
Tab. 33. Electrical characteristics - Z-axis inertial
sensor overload ...............................................26
Tab. 34. Dynamic electrical characteristics - DSI3 ........ 27
Tab. 35. Dynamic electrical characteristics - PSI5 ........ 28
Tab. 36. Dynamic electrical characteristics - SPI .......... 30
Tab. 37. Dynamic electrical characteristics - I2C ...........31
(TEMP1_ERR) .................................................49
Tab. 67. Channel 0 temperature sensor error
(TEMP0_ERR) .................................................49
Tab. 68. SPI MISO data mismatch error flag (MISO_
ERROR) .......................................................... 49
Tab. 69. Oscillator training error (OSCTRAIN_ERR) .....49
Tab. 70. Communication protocol revision register
(COMMREV) ................................................... 50
Tab. 71. Margin read status register (MREAD_
STAT) ...............................................................50
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Dual channel inertial sensor
Tab. 72. Margin read active status (MARGIN_RD_
ACT) ................................................................ 50
Tab. 73. Margin read error status (MARGIN_RD_
ERR) ................................................................50
Tab. 74. Temperature register (TEMPERATURE) ......... 51
Tab. 75. Device lock register (DEVLOCK_WR) .............51
Tab. 76. Reset control bits (RESET[1:0]) ...................... 52
Tab. 77. Write OTP enable register ...............................52
Tab. 78. Write OTP enable and programming bits ........ 54
Tab. 79. Bus switch control register (BUSSW_
CTRL) ..............................................................55
Tab. 80. BUSSW_L pin state ........................................ 55
Tab. 81. PSI5 test register (PSI5_TEST) ...................... 56
Tab. 82. UF region selection registers (UF_
REGION_x) ..................................................... 57
Tab. 83. Region load bits .............................................. 57
Tab. 84. Region active bits ............................................58
Tab. 85. Communication type register
(COMMTYPE) ................................................. 59
Tab. 86. Communication type (COMMTYPE[2:0]) .........59
Tab. 87. COMMTYPEs and effect on device .................59
Tab. 88. Physical address register (PHYSADDR) ......... 60
Tab. 89. Source identification registers
Tab. 112. Background diagnostic mode enable
(BDM_EN) ....................................................... 70
Tab. 113. PSI5 configuration register (PSI5_CFG) ......... 70
Tab. 114. Sync pulse pull-down enable bit (SYNC_
PD) .................................................................. 70
Tab. 115. PSI5 daisy chain selection bit (DAISY_
CHAIN) ............................................................ 71
Tab. 116. PSI5 low response current selection bit
(PSI5_ILOW) ................................................... 71
Tab. 117. Dual transmission mode (DUALTRANS) ......... 71
Tab. 118. Error message information extension bit
(EMSG_EXT) ...................................................72
Tab. 119. PSI5 response message error detection
selection bit (P_CRC) ......................................72
Tab. 120. Initialization phase 2 data extension bit
(INIT2_EXT) .................................................... 72
Tab. 121. DSI3 and PSI5 start time registers (PDCM_
RSPSTx_x) ......................................................73
Tab. 122. Periodic data collection mode response
start time (PDCM_RSPSTx[12:0]) ...................74
Tab. 123. Synchronous mode: Source ID response
start time ......................................................... 74
Tab. 124. Asynchronous mode: Source ID response
start time ......................................................... 74
Tab. 125. Broadcast read command type selection
bits (BRC_RSP[1:0]) ....................................... 75
Tab. 126. DSI3 and PSI5 command blocking time
registers (PDCM_CMD_B_x) .......................... 76
Tab. 127. DSI3 mode: Command blocking time bits ....... 76
Tab. 128. PSI5 mode: Command blocking time bits ........76
Tab. 129. SPI configuration control register .................... 77
Tab. 130. SPI status reporting selection bit (SPI_
STATUS) ..........................................................77
Tab. 131. SPI data field size bit (DATASIZE) .................. 77
Tab. 132. SPI CRC length and seed bits (SPI_CRC_
LEN[1:0], SPICRCSEED[3:0]) .........................78
Tab. 133. Who Am I register ...........................................78
Tab. 134. WHO_AM_I bits .............................................. 79
Tab. 135. I2C slave address register .............................. 79
Tab. 136. I2C_ADDRESS bits .........................................79
Tab. 137. Channel 0 and Channel 1 user
(SOURCEID_x) ............................................... 60
Tab. 90. PDCM format control bits
(PDCMFORMAT[2:0]) ......................................61
Tab. 91. PDCM format control bits ................................61
Tab. 92. SPI source identification (SOURCEID_x) ........62
Tab. 93. DSI3 source identification (SOURCEID_x) ......62
Tab. 94. PSI5 source identification (SOURCEID_x) ......63
Tab. 95. Communication timing register (TIMING_
CFG) ................................................................63
Tab. 96. Periodic data collection mode period
(PDCM_PER[3:0]) ........................................... 63
Tab. 97. Oscillator training protocol selection bit
(OSCTRAIN_SEL) ...........................................64
Tab. 98. Command and response mode period
(CRM_PER[1:0]) ..............................................65
Tab. 99. Clock calibration enable (CK_CAL_EN) ..........65
Tab. 100. Chip time and bit time register (CHIPTIME) .... 65
Tab. 101. PSI5 self-test repetition bits (ST_RPT[1:0]) .....66
Tab. 102. PSI5 error latching enable bit (PSI5_
configuration #1 registers (CH0_CFG_U1,
ERRLATCH) .................................................... 66
Tab. 103. DSI3 simultaneous sampling enable (SS_
EN) .................................................................. 66
Tab. 104. PSI5 simultaneous sampling enable (SS_
EN) .................................................................. 67
Tab. 105. SPI simultaneous sampling enable (SS_
EN) .................................................................. 67
Tab. 106. Chip time (CHIPTIME) .................................... 67
Tab. 107. Timing configuration #2 register (TIMING_
CFG2) ..............................................................68
Tab. 108. PSI5 initialization phase 2 D19 and D20
change bit (PSI5_INIT2_D19) ......................... 68
Tab. 109. Oscillator training error counter
CH1_CFG_U1) ................................................80
Tab. 138. Low-pass filter and sample rate selection
bits (LPF[3:0], SAMPLERATE[1:0]) .................80
Tab. 139. Channel 0 and Channel 1 user
configuration #2 registers (CH0_CFG_U2,
CH1_CFG_U2) ................................................81
Tab. 140. Sensitivity shift factors .....................................81
Tab. 141. Example user shift and multiplier
configuration for typical scale range ................82
Tab. 142. Example user shift and multiplier
configuration for typical psi5 scale range ........ 83
Tab. 143. Channel 0 and Channel 1 user
configuration #3 registers (CH0_CFG_U3,
(OSCTRAIN_ERRCNT[2:0]) ............................68
Tab. 110. Capacitor test disable bit (CAPTEST_OFF) .... 69
Tab. 111. Background diagnostic mode fragment size
(BDM_FRAGSIZE) .......................................... 69
CH1_CFG_U3) ................................................83
Tab. 144. Unsigned data select bit
(UNSIGNEDDATA) .......................................... 83
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Dual channel inertial sensor
Tab. 145. Channel data type 0 selection bits
(CHxDATATYPE0) ...........................................84
Tab. 146. Channel data type 1 selection bits
(CHxDATATYPE1) ...........................................84
Tab. 147. Signal chain moving average selection bits
(MOVEAVG[1:0]) ............................................. 85
Tab. 148. Channel 0 and Channel 1 user
Tab. 175. Channel-specific factory configuration
register (CHx_CFG_F) .................................... 96
Tab. 176. Range indication bits (RANGE[3:0]) ................96
Tab. 177. Axis indication bits (AXIS[1:0]) ........................ 97
Tab. 178. Self-test deflection storage registers ............... 97
Tab. 179. IC type register ................................................98
Tab. 180. IC revision register ..........................................98
Tab. 181. IC manufacturer identification register .............99
Tab. 182. Part number register ....................................... 99
Tab. 183. Part number: Protocol type ............................. 99
Tab. 184. Part number: Axis ......................................... 100
Tab. 185. Part number: Channel 0 range ......................100
Tab. 186. Part number: Channel 1 range ......................100
Tab. 187. Device serial number registers ......................101
Tab. 188. Example serial number decoding ..................101
Tab. 189. ASIC wafer ID registers ................................ 101
Tab. 190. Transducer wafer ID registers .......................102
Tab. 191. User data registers (USERDATA_0 -
configuration #4 registers (CH0_CFG_U4,
CH1_CFG_U4) ................................................85
Tab. 149. Signal inversion bit (INVERT) ......................... 86
Tab. 150. Offset cancellation filter selection bits (OC_
FILT[1:0]) ......................................................... 86
Tab. 151. Arming pin configuration bits (ARM_
CFG[2:0]) and PCM range selection bit
(PCM) .............................................................. 86
Tab. 152. Channel 0 and Channel 1 user
configuration #5 register (CH0_CFG_U5,
CH1_CFG_U5) ................................................87
Tab. 153. Self-test control bits (ST_CTRL[3:0]) ...............88
Tab. 154. Offset cancellation test limit bits (OC_
LIMIT[2:0]) ....................................................... 89
Tab. 155. DSP disable bit (DSP_DIS) .............................89
Tab. 156. Channel 0 and Channel 1 arming
USERDATA_E) ..............................................102
Tab. 192. PSI5 initialization phase 2 data
transmissions of user data ............................ 102
Tab. 193. User data registers (USERDATA_10 -
USERDATA_1E) ............................................103
configuration registers (CH0_ARM_CFG,
Tab. 194. Lock and CRC registers ................................104
Tab. 195. Lock bit, block identifier, and CRC states ...... 104
Tab. 196. Memory type code: NXP OTP register .......... 105
Tab. 197. Memory type code: User OTP register ..........105
Tab. 198. Memory type code: CRC verified OTP
registers .........................................................105
Tab. 199. Memory type code: ENDINIT CRC verified
OTP registers ................................................105
CH1_ARM_CFG) .............................................89
Tab. 157. Arming function down sampling selection
bits (ARM_DS[1:0]) ......................................... 90
Tab. 158. Arming pulse stretch (ARM_PS[1:0]) ...............90
Tab. 159. Positive arming window size definitions
(moving average mode) .................................. 90
Tab. 160. Negative arming window size definitions
(moving average mode) .................................. 90
Tab. 161. Arming count limit definitions (count mode) .....91
Tab. 162. Arming threshold registers (CHx_ARM_T_
P, CHx_ARM_T_N) ......................................... 91
Tab. 163. Example threshold register values and
corresponding threshold ..................................91
Tab. 164. Offset cancellation user configuration
register (OC_PHASE_CFG) ............................92
Tab. 165. Channel 0 offset cancellation final
phase control bit (CH0_OCFINAL, CH1_
OCFINAL) ........................................................92
Tab. 166. Channel 1 offset cancellation final
phase control bit (CH0_OCFINAL, CH1_
OCFINAL) ........................................................92
Tab. 167. User offset calibration registers (Chx_U_
OFFSET_L, Chx_U_OFFSET_H) ................... 93
Tab. 168. Channel-specific status register (CH0_
STAT, CH1_STAT) ...........................................93
Tab. 169. Offset cancellation phase status
Tab. 200. Signal chain diagram legend .........................117
Tab. 201. Signal trim and compensation variable
descriptions ................................................... 119
Tab. 202. LPF #0 and LPF #2 ...................................... 120
Tab. 203. LPF #1 and LPF #3 ...................................... 120
Tab. 204. LPF #4 ...........................................................120
Tab. 205. LPF #5 ...........................................................120
Tab. 206. LPF #6 ...........................................................121
Tab. 207. LPF #7 ...........................................................121
Tab. 208. LPF #8 ...........................................................121
Tab. 209. LPF #9 ...........................................................122
Tab. 210. LPF #A .......................................................... 122
Tab. 211. LPF #B .......................................................... 122
Tab. 212. LPF #C ..........................................................123
Tab. 213. LPF #D ..........................................................123
Tab. 214. LPF #E .......................................................... 123
Tab. 215. LPF #F .......................................................... 124
Tab. 216. Offset cancellation phases and times:
DSI3, SPI, and I2C modes ............................138
(OCPHASE[2:0]) ..............................................93
Tab. 170. Self-test incomplete (ST_INCMPLT) ............... 94
Tab. 171. Offset error flag (OFFSET_ERR) .................... 94
Tab. 172. Device status copy register (DEVSTAT_
COPY) ............................................................. 95
Tab. 173. Sensor data #0 registers (CHx_
Tab. 217. Offset cancellation phases and times: PSI5
modes ............................................................139
Tab. 218. Output scaling ............................................... 141
Tab. 219. Sensor data variables ................................... 142
Tab. 220. Temperature sensor output scaling
equation variables ......................................... 143
SNSDATA0_L, CHx_SNSDATA0_H) ...............95
Tab. 174. Sensor data #1 registers (CHx_
Tab. 221. Command and response mode example
command descriptions .................................. 153
SNSDATA1_L, CHx_SNSDATA1_H) ...............96
FXLS9xxxx
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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
Tab. 222. Command and response mode - command
format ............................................................ 153
Tab. 223. Command and response mode - field
definitions ...................................................... 153
Tab. 224. Command and response mode command
CRC ...............................................................154
Tab. 225. Command and response mode - CRC
calculation examples .....................................154
Tab. 226. Command and response mode response
example .........................................................154
Tab. 227. Symbol mapping ........................................... 155
Tab. 228. Command and response mode - response
format ............................................................ 156
Tab. 229. Command and response mode - field
definitions ...................................................... 156
Tab. 230. Command and response mode response
CRC ...............................................................157
Tab. 231. DSI3 command and response mode
command summary .......................................157
Tab. 232. Register read command format .....................158
Tab. 233. Register read command format description ...158
Tab. 234. Register read command: response format .... 158
Tab. 235. Register read command: response format
description ..................................................... 158
Tab. 236. Register write command format .................... 159
Tab. 237. Register write command format description .. 159
Tab. 238. Register write command: response format ....159
Tab. 239. Register write command: response format
description ..................................................... 159
Tab. 240. Global register write command format ...........160
Tab. 241. Global register write command format
description ..................................................... 160
Tab. 242. Global register write command: response
format ............................................................ 160
Tab. 243. Global register write command: response
format description ..........................................160
Tab. 244. PDCM enable command and BDM_EN bit
status .............................................................161
Tab. 245. Enter periodic data collection mode
command format ........................................... 161
Tab. 246. Enter periodic data collection mode
command format description .........................161
Tab. 247. Enter periodic data collection mode
command: response format ...........................161
Tab. 248. Enter periodic data collection mode
command: response format description ........ 161
Tab. 249. Reserved commands .................................... 161
Tab. 250. Reserved commands description .................. 162
Tab. 251. Reserved command response format ........... 162
Tab. 252. Reserved command response format
description ..................................................... 162
Tab. 253. Periodic data collection mode response
format ............................................................ 164
Tab. 254. Periodic data collection mode status field
definition ........................................................ 164
Tab. 255. Periodic data collection mode response
CRC ...............................................................165
Tab. 256. Periodic data collection mode - CRC
calculation examples .....................................165
Tab. 257. Exception conditions and response ...............170
Tab. 258. DSI3 error handling - discovery mode and
daisy chain mode ..........................................172
Tab. 259. PSI5-x10P transmission mode ......................176
Tab. 260. PSI5-x10C transmission mode ......................176
Tab. 261. PSI5-x16P transmission mode ......................176
Tab. 262. PSI5-x16C transmission mode ......................176
Tab. 263. PSI5 3-bit CRC calculation examples ............177
Tab. 264. PSI5 data values ...........................................177
Tab. 265. PSI5 initialization phase 2 data
transmission order .........................................182
Tab. 266. Initialization phase 2 time ..............................182
Tab. 267. Channel 0 PSI5 initialization phase 2 data .... 182
Tab. 268. Channel 1 PSI5 Initialization Phase 2 Data ...183
Tab. 269. Default PSI5-P16C transmission mode ......... 187
Tab. 270. Default PSI5-P16C transmission mode
timing parameters ..........................................187
Tab. 271. Default PSI5-P16C transmission mode,
High g sensor data configuration .................. 187
Tab. 272. Default PSI5-P16C transmission mode,
Medium g sensor data configuration ............. 188
Tab. 273. Dual transmission mode 10-bit
transmission data with parity .........................188
Tab. 274. Dual transmission mode 10-bit
transmission data with CRC ..........................188
Tab. 275. Dual transmission mode 16-bit
transmission data with parity .........................188
Tab. 276. Dual transmission mode 16-bit
transmission data with CRC ..........................189
Tab. 277. Daisy chain: Run mode configuration ............190
Tab. 278. Daisy chain programming commands and
responses ......................................................190
Tab. 279. Daisy chain programming response code
definitions ...................................................... 190
Tab. 280. Valid daisy chain addresses ..........................191
Tab. 281. Daisy chain error handling ............................ 191
Tab. 282. Initialization phase 2 error handling ...............192
Tab. 283. Initialization phase 3 error handling ...............192
Tab. 284. Standard error reporting ................................193
Tab. 285. PSI5 error extension option ...........................193
Tab. 286. Standard error reporting ................................193
Tab. 287. PSI5 error extension option ...........................194
Tab. 288. Programming mode via PSI5 command
data format ....................................................195
Tab. 289. Programming mode via PSI5 command
data format - response ..................................195
Tab. 290. Programming mode via PSI5 XLONG
command data format with sync bits .............196
Tab. 291. Programming mode via PSI5 XLONG
command data format with sync bits -
response ........................................................196
Tab. 292. Programming mode via PSI5 response
message settings .......................................... 196
Tab. 293. Programming mode via PSI5 short
command .......................................................196
Tab. 294. Response format ...........................................196
Tab. 295. Programming mode via PSI5 long
command .......................................................197
Tab. 296. Response format ...........................................197
FXLS9xxxx
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NXP Semiconductors
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Dual channel inertial sensor
Tab. 297. Programming mode via PSI5 long
Tab. 317. Reserved command response message
command .......................................................197
Tab. 298. Response format ...........................................197
Tab. 299. Programming mode via PSI5 commands
and responses ...............................................198
Tab. 300. Programming mode via PSI5 response
code definitions ............................................. 198
Tab. 301. Error response summary ...............................198
Tab. 302. SPI command format .................................... 200
Tab. 303. SPI response format ..................................... 200
Tab. 304. Command summary ......................................201
Tab. 305. Register read command message format ......202
Tab. 306. Register read command message format
description ..................................................... 202
Tab. 307. Register read response message format .......202
Tab. 308. Register read response message format
description ..................................................... 202
Tab. 309. Register write command message format ..... 203
Tab. 310. Register write command message format
description ..................................................... 203
Tab. 311. Register write response message format ...... 203
Tab. 312. Register write response message format
description ..................................................... 203
Tab. 313. Sensor data request command message
format ............................................................ 204
Tab. 314. Sensor data request command message
format description ..........................................204
Tab. 315. Sensor data request response message
format ............................................................ 204
Tab. 316. Sensor data request response message
format description ..........................................204
format ............................................................ 205
Tab. 318. Reserved command response message
format description ..........................................205
Tab. 319. SPI command message CRC ....................... 206
Tab. 320. SPI CRC polynomial and seed ......................206
Tab. 321. SPI 8-bit CRC calculation examples ............. 206
Tab. 322. SPI command format with 4-bit CRC ............ 207
Tab. 323. SPI response format with 4-bit CRC ............. 207
Tab. 324. SPI command message CRC, 4 bit ...............208
Tab. 325. SPI response message CRC, 4-bit ............... 208
Tab. 326. SPI 4-bit CRC calculation examples ............. 209
Tab. 327. SPI command format with 3-bit CRC ............ 209
Tab. 328. SPI response format with 3-bit CRC ............. 209
Tab. 329. SPI command message CRC, 3 bit ...............210
Tab. 330. SPI response message CRC, 3-bit ............... 211
Tab. 331. SPI 3-bit CRC calculation examples ............. 211
Tab. 332. Basic status field for responses to register
commands .....................................................211
Tab. 333. Basic status field for responses to sensor
data request commands ................................212
Tab. 334. Alternative basic status reporting field ...........212
Tab. 335. SPI error response status field definition .......213
Tab. 336. Alternate SPI error response status field
definition ........................................................ 214
Tab. 337. Error responses .............................................215
Tab. 338. Error response description ............................ 215
Tab. 339. Dual channel register read wrap around ....... 221
Tab. 340. Revision history .............................................240
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Part marking ......................................................3
DSI3 discovery mode application diagram ........ 4
PSI5 parallel or universal mode application
diagram ..............................................................5
PSI5 daisy chain mode application diagram ......6
SPI application diagram .................................... 8
I2C application diagram .................................... 8
Dual channel internal block diagram ................. 9
Orientation diagram .........................................10
Device pinout: SPI or I2C mode ......................10
Fig. 20. PSI5 self-test procedure ................................116
Fig. 21. ΣΔ converter block diagram .......................... 117
Fig. 22. Signal chain diagram .....................................117
Fig. 23. Sinc filter response 3rd order sinc filter
magnitude response ......................................118
Fig. 24. 400 Hz, 4-pole low-pass filter response
magnitude ......................................................124
Fig. 25. 400 Hz, 4-pole low-pass filter response
signal delay ................................................... 125
Fig. 26. 400 Hz, 3-pole low-pass filter response
magnitude ......................................................125
Fig. 27. 400 Hz, 3-pole low-pass filter response
signal delay ................................................... 126
Fig. 28. 325 Hz, 3-pole low-pass filter response
magnitude ......................................................126
Fig. 29. 325 Hz, 3-pole low-pass filter response
signal delay ................................................... 127
Fig. 30. 370 Hz, 2-pole low-pass filter response
magnitude ......................................................127
Fig. 31. 370 Hz, 2-pole low-pass filter response
signal delay ................................................... 128
Fig. 32. 180 Hz, 2-pole low-pass filter response
magnitude ......................................................128
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10. Device pinout: DSI3 or PSI5 mode pinout ....... 12
Fig. 11. Voltage regulation and monitoring .................106
Fig. 12. VBUF capacitor monitor timing, DSI3 ............107
Fig. 13. VBUF capacitor monitor timing, PSI5
synchronous mode ........................................107
Fig. 14. VBUF capacitor monitor timing, psi5
asynchronous mode ......................................108
Fig. 15. BUS_I micro-cut response (DSI3 or PSI5) .... 109
Fig. 16. Command and response mode oscillator
training timing diagram ..................................110
Fig. 17. Periodic data collection mode oscillator
training timing diagram ..................................111
Fig. 18. PSI5 oscillator training timing diagram .......... 112
Fig. 19. Self-test interface .......................................... 114
FXLS9xxxx
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NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
Fig. 33. 180 Hz, 2-pole low-pass filter response
signal delay ................................................... 129
Fig. 34. 100 Hz, 2-pole low-pass filter response
magnitude ......................................................129
Fig. 35. 100 Hz, 2-pole low-pass filter response
signal delay ................................................... 130
Fig. 36. 1500 Hz, 4-pole low-pass filter response
magnitude ......................................................130
Fig. 37. 1500 Hz, 4-pole low-pass filter response
signal delay ................................................... 131
Fig. 38. 500 Hz, 3-pole low-pass filter response
magnitude ......................................................131
Fig. 39. 500 Hz, 3-pole low-pass filter response
signal delay ................................................... 132
Fig. 40. 800 Hz, 4-pole low-pass filter response
magnitude ......................................................132
Fig. 41. 800 Hz, 4-pole low-pass filter response
signal delay ................................................... 133
Fig. 42. 1200 Hz, 4-pole low-pass filter response
magnitude ......................................................133
Fig. 43. 1200 Hz, 4-pole low-pass filter response
signal delay ................................................... 134
Fig. 44. 120 Hz, 3-pole low-pass filter response
magnitude ......................................................134
Fig. 45. 120 Hz, 3-pole low-pass filter response
signal delay ................................................... 135
Fig. 46. 120 Hz, 2-pole low-pass filter output
magnitude response ......................................135
Fig. 47. 120 Hz, 2-pole low-pass filter output
magnitude response ......................................136
Fig. 48. 50 Hz, 4-pole low-pass filter response
magnitude ......................................................136
Fig. 49. 50 Hz, 4-pole low-pass filter response
signal delay ................................................... 137
Fig. 50. Offset cancellation block diagram ................. 137
Fig. 51. 0.04 Hz offset cancellation low–pass filter
characteristics ................................................139
Fig. 52. 0.005 Hz offset cancellation low-pass filter
characteristics ................................................140
Fig. 53. Output interpolation example: Linear
interpolation (16 to 1) ....................................141
Fig. 54. Temperature sensor signal chain block
diagram ..........................................................142
Fig. 55. PCM output function block diagram .............. 143
Fig. 56. Arming function block diagram - moving
average mode ............................................... 144
Fig. 57. Arming function block diagram - count
mode ..............................................................145
Fig. 58. Arming condition, moving average and
count mode ................................................... 145
Fig. 59. Arming function block diagram - unfiltered
mode ..............................................................146
Fig. 60. Arming condition, unfiltered mode .................146
Fig. 61. Arming function - pin output structure ........... 147
Fig. 62. Command receiver physical layer ................. 148
Fig. 63. DSI3 command receiver timing diagram:
valid command .............................................. 148
Fig. 64. DSI3 command receiver timing diagram:
micro-cut ........................................................149
Fig. 65. DSI3 transmitter block diagram .....................149
Fig. 66. Discovery mode current sense circuit block
diagram ..........................................................149
Fig. 67. DSI3 discovery mode sensing timing
diagram ..........................................................150
Fig. 68. DSI3 discovery mode timing diagram ............152
Fig. 69. Command and response mode example
command .......................................................152
Fig. 70. Command and response mode command
bit encoding ...................................................153
Fig. 71. Command and response mode response
example .........................................................154
Fig. 72. Response symbol encoding .......................... 155
Fig. 73. Command and response mode timing
diagram ..........................................................157
Fig. 74. Background diagnostic mode command bit
encoding ........................................................163
Fig. 75. Periodic data mode response transmission ...164
Fig. 76. Periodic data collection mode timing
diagram ..........................................................166
Fig. 77. Background diagnostic mode timing
diagram ..........................................................167
Fig. 78. Simultaneous sampling mode ....................... 168
Fig. 79. Synchronous sampling mode with minimum
latency ........................................................... 168
Fig. 80. Initialization timing .........................................169
Fig. 81. PSI5 satellite interface diagram .....................172
Fig. 82. Synchronous communication overview ......... 173
Fig. 83. Synchronization pulse detection circuit ......... 173
Fig. 84. Synchronization pulse detection timing ......... 174
Fig. 85. Sync pulse characteristics .............................175
Fig. 86. Manchester data bit encoding ....................... 175
Fig. 87. Example Manchester encoded data
transfer - PSI5-x10x ...................................... 176
Fig. 88. PSI5 sensor 10-bit initialization ..................... 180
Fig. 89. PSI5 initialization timing, synchronous
mode ..............................................................181
Fig. 90. PSI5 initialization timing, asynchronous
mode ..............................................................181
Fig. 91. Simultaneous sampling mode ....................... 186
Fig. 92. Synchronous sampling mode with minimum
latency ........................................................... 186
Fig. 93. PSI5 default mode transmission ....................187
Fig. 94. Standard 32-bit SPI protocol timing
diagram ..........................................................200
Fig. 95. Internal status mapping and SPI basic
status content ................................................213
Fig. 96. SPI data output verification ........................... 216
Fig. 97. SPI timing diagram ........................................217
Fig. 98. I2C bit transmissions .....................................217
Fig. 99. I2C start condition .........................................218
Fig. 100. I2C byte transmissions ..................................218
Fig. 101. I2C acknowledge and not acknowledge
transmission .................................................. 219
Fig. 102. I2C stop condition ......................................... 219
Fig. 103. I2C timing diagram ........................................222
Fig. 104. Package outline for LQFN16
(SOT1688-1(SC)) .......................................... 223
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Dual channel inertial sensor
Fig. 105. Package outline detail for LQFN16
(SOT1688-1(SC)) .......................................... 224
Fig. 106. Package outline notes for LQFN16
(SOT1688-1(SC)) .......................................... 225
Fig. 107. Package outline for LQFN16
(SOT1688-1(DD)) ..........................................226
Fig. 108. Package outline detail for LQFN16
(SOT1688-1(DD)) ..........................................227
Fig. 109. Package outline notes for LQFN16
(SOT1688-1(DD)) ..........................................228
Fig. 110. Reflow soldering footprint part 1 for
HLQFN16 (SOT1688-1(SC)) .........................229
Fig. 111. Reflow soldering footprint part 2 for
HLQFN16 (SOT1688-1(SC)) .........................230
Fig. 112. Reflow soldering footprint part 3 for
HLQFN16 (SOT1688-1(SC)) .........................231
Fig. 113. Reflow soldering footprint part 4 for
HLQFN16 (SOT1688-1(SC)) .........................232
Fig. 114. Reflow soldering footprint part 5 for
HLQFN16 (SOT1688-1(SC)) .........................233
Fig. 115. Reflow soldering footprint part 1 for
HLQFN16 (SOT1688-1(DD)) .........................234
Fig. 116. Reflow soldering footprint part 2 for
HLQFN16 (SOT1688-1(DD)) .........................235
Fig. 117. Reflow soldering footprint part 3 for
HLQFN16 (SOT1688-1(DD)) .........................236
Fig. 118. Reflow soldering footprint part 4 for
HLQFN16 (SOT1688-1(DD)) .........................237
Fig. 119. Reflow soldering footprint part 5 for
HLQFN16 (SOT1688-1(DD)) .........................238
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FXLS9xxxx
Dual channel inertial sensor
Contents
1
2
3
3.1
3.2
4
4.1
5
General description ............................................ 1
10.20
Dynamic electrical characteristics - supply
and support circuitry ........................................ 37
Functional description ......................................38
User accessible data array ..............................38
User accessible data - general device
information ....................................................... 38
User accessible data - communication
information ....................................................... 39
User accessible data - sensor specific
information ....................................................... 40
User accessible data - sensor specific
information ....................................................... 41
User accessible data - traceability
Features ............................................................... 1
Applications .........................................................2
Automotive .........................................................2
Industrial ............................................................ 2
Ordering information .......................................... 2
Ordering options ................................................ 2
Marking .................................................................3
Application diagrams ..........................................4
DSI3 application diagrams .................................4
DSI3 discovery mode application diagram .........4
PSI5 application diagrams .................................5
PSI5 parallel or universal mode application
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
6
6.1
6.1.1
6.2
6.2.1
diagram ..............................................................5
PSI5 daisy chain mode application diagram ...... 6
SPI application diagram .....................................8
I2C application diagram .....................................8
Block diagram ..................................................... 9
Device orientation diagrams ............................10
Pinning information .......................................... 10
Pinning: SPI or I2C mode ................................10
Pin description: SPI or I2C mode .................... 11
Pinning: DSI3 or PSI5 mode ........................... 12
Pin description: DSI3 or PSI5 mode ................ 12
Electrical characteristics ..................................13
Maximum ratings ............................................. 14
Operating range - DSI / PSI5 .......................... 14
Operating range - SPI / I2C .............................15
Electrical characteristics - supply and I/O ........ 15
Electrical characteristics - temperature
sensor signal chain ..........................................16
Electrical characteristics - inertial sensor
signal chain: High g .........................................17
Electrical characteristics - inertial sensor
signal chain: Medium g ....................................21
Electrical characteristics - inertial sensor
self-test ............................................................ 24
Electrical characteristics - lateral inertial
information ....................................................... 42
Register definitions .......................................... 43
Rolling counter register (COUNT) ....................43
Device status registers (DEVSTATx) ............... 44
6.2.2
6.3
6.4
7
8
9
9.1
9.2
9.3
9.4
10
10.1
10.2
10.3
10.4
10.5
11.2
11.2.1
11.2.2
11.2.2.1 Channel 0 error flag (CH0_ERR) .....................44
11.2.2.2 Channel 1 error flag (CH1_ERR) .....................44
11.2.2.3 Communication error flag (COMM_ERR) ........ 44
11.2.2.4 Memory or temperature error flag
(MEMTEMP_ERR) ...........................................44
11.2.2.5 Supply error flag (SUPPLY_ERR) ................... 44
11.2.2.6 Test mode (TESTMODE) .................................45
11.2.2.7 Device reset (DEVRES) .................................. 45
11.2.2.8 Device initialization (DEVINIT) .........................45
11.2.2.9 VBUF under-voltage error (VBUFUV_ERR) .... 46
11.2.2.10 BUS IN under-voltage error (BUSINUV_
ERR) ................................................................ 46
11.2.2.11 VBUF over-voltage error (VBUFOV_ERR) ...... 46
11.2.2.12 Internal analog regulator voltage out of
range error (INTREGA_ERR) ..........................46
11.2.2.13 Internal digital regulator voltage out of
range error (INTREG_ERR) ............................ 47
11.2.2.14 Internal OTP regulator voltage out of range
error (INTREGF_ERR) .................................... 47
11.2.2.15 Continuity monitor error (CONT_ERR) ............ 47
11.2.2.16 NXP OTP array error (F_OTP_ERR) ...............47
11.2.2.17 User OTP array error (U_OTP_ERR) .............. 48
11.2.2.18 User read/write array error (U_RW_ERR) ....... 48
11.2.2.19 User OTP write in process status bit (U_W_
ACTIVE) ...........................................................48
11.2.2.20 Channel 1 temperature sensor error
10.6
10.7
10.8
10.9
10.10
sensor overload ............................................... 26
Electrical characteristics - Z-axis inertial
sensor overload ............................................... 26
Dynamic electrical characteristics - DSI3 .........27
Dynamic electrical characteristics - PSI5 .........28
Dynamic electrical characteristics - SPI ...........30
Dynamic electrical characteristics - I2C ...........31
Dynamic electrical characteristics - signal
chain, low-pass filter ........................................32
Dynamic electrical characteristics - signal
chain ................................................................ 34
Dynamic electrical characteristics - analog
10.11
10.12
10.13
10.14
10.15
(TEMP1_ERR) .................................................48
11.2.2.21 Channel 0 temperature sensor error
(TEMP0_ERR) .................................................49
11.2.2.22 SPI MISO data mismatch error flag (MISO_
ERROR) ...........................................................49
11.2.2.23 Oscillator training error (OSCTRAIN_ERR) ..... 49
10.16
10.17
10.18
10.19
11.2.3
Communication protocol revision register
(COMMREV) ....................................................49
Margin read status register (MREAD_STAT) ... 50
self-test response time .................................... 35
Dynamic electrical characteristics - digital
self-test response time .................................... 36
Dynamic electrical characteristics -
11.2.4
11.2.4.1 Margin read active status (MARGIN_RD_
ACT) .................................................................50
11.2.4.2 Margin read error status (MARGIN_RD_
ERR) ................................................................ 50
transducer ........................................................37
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Dual channel inertial sensor
11.2.5
11.2.6
Temperature register (TEMPERATURE) ..........51
Device lock register (DEVLOCK_WR) .............51
11.2.17.3 PSI5 low response current selection bit
(PSI5_ILOW) ....................................................71
11.2.17.4 Dual transmission mode (DUALTRANS) ..........71
11.2.17.5 Error message information extension bit
(EMSG_EXT) ...................................................72
11.2.17.6 PSI5 response message error detection
selection bit (P_CRC) ......................................72
11.2.17.7 Initialization phase 2 data extension bit
(INIT2_EXT) .....................................................72
11.2.17.8 Asynchronous mode bit (ASYNC) ................... 73
11.2.18 DSI3 and PSI5 start time registers (PDCM_
RSPSTx_x) ...................................................... 73
11.2.18.1 Periodic data collection mode response
start time (PDCM_RSPSTx[12:0]) ................... 74
11.2.18.2 Broadcast read command type selection
bits (BRC_RSP[1:0]) ........................................75
11.2.19 DSI3 and PSI5 command blocking time
registers (PDCM_CMD_B_x) ...........................76
11.2.20 SPI configuration control register .....................77
11.2.20.1 SPI status reporting selection bit (SPI_
STATUS) .......................................................... 77
11.2.20.2 SPI data field size bit (DATASIZE) ...................77
11.2.20.3 SPI CRC length and seed bits (SPI_CRC_
LEN[1:0], SPICRCSEED[3:0]) ......................... 78
11.2.21 Who Am I register ........................................... 78
11.2.22 I2C slave address register ...............................79
11.2.23 Channel 0 and Channel 1 user
11.2.6.1 End initialization bit (ENDINIT) ........................ 51
11.2.6.2 Supply error reporting disable bit (SUP_
ERR_DIS) ........................................................ 52
11.2.6.3 Reset control bits (RESET[1:0]) .......................52
11.2.7
11.2.7.1 Margin read enable bit (MARGIN_RD_EN) ..... 52
11.2.7.2 Write OTP enable and programming bits .........54
11.2.8
Write OTP enable register ...............................52
Bus switch control register (BUSSW_
CTRL) .............................................................. 55
PSI5 test register (PSI5_TEST) .......................56
11.2.9
11.2.9.1 PSI5 test bit (PSI5_TEST) ...............................56
11.2.10 UF region selection registers (UF_
REGION_x) ......................................................57
11.2.11 Communication type register
(COMMTYPE) ..................................................58
11.2.11.1 Communication type (COMMTYPE[2:0]) ......... 59
11.2.12 Physical address register (PHYSADDR) ......... 60
11.2.13 Source identification registers
(SOURCEID_x) ................................................60
11.2.13.1 Data source enable bits (SIDx_EN) .................61
11.2.13.2 PDCM format control bits
(PDCMFORMAT[2:0]) ...................................... 61
11.2.13.3 Source identification (SOURCEID_x) .............. 62
11.2.14 Communication timing register (TIMING_
CFG) ................................................................ 63
11.2.14.1 Periodic data collection mode period
(PDCM_PER[3:0]) ............................................63
11.2.14.2 Oscillator training protocol selection bit
(OSCTRAIN_SEL) ........................................... 64
11.2.14.3 Clock calibration value reset (CK_CAL_
RST) .................................................................64
11.2.14.4 Command and response mode period
(CRM_PER[1:0]) ..............................................65
11.2.14.5 Clock calibration enable (CK_CAL_EN) .......... 65
11.2.15 Chip time and bit time register (CHIPTIME) .....65
11.2.15.1 PSI5 self-test repetition bits (ST_RPT[1:0]) ..... 66
11.2.15.2 PSI5 error latching enable bit (PSI5_
ERRLATCH) .....................................................66
11.2.15.3 Simultaneous sampling enable (SS_EN) .........66
11.2.15.4 Chip time (CHIPTIME) .....................................67
11.2.16 Timing configuration #2 register (TIMING_
CFG2) .............................................................. 68
11.2.16.1 PSI5 initialization phase 2 D19 and D20
change bit (PSI5_INIT2_D19) ..........................68
11.2.16.2 Oscillator training error counter
(OSCTRAIN_ERRCNT[2:0]) ............................ 68
11.2.16.3 Capacitor test disable bit (CAPTEST_OFF) .....69
11.2.16.4 Background diagnostic mode fragment size
(BDM_FRAGSIZE) ...........................................69
11.2.16.5 Background diagnostic mode enable
(BDM_EN) ........................................................70
11.2.17 PSI5 configuration register (PSI5_CFG) ..........70
11.2.17.1 Sync pulse pull-down enable bit (SYNC_
PD) ...................................................................70
11.2.17.2 PSI5 daisy chain selection bit (DAISY_
CHAIN) .............................................................71
configuration #1 registers (CH0_CFG_U1,
CH1_CFG_U1) ................................................ 79
11.2.23.1 Low-pass filter and sample rate selection
bits (LPF[3:0], SAMPLERATE[1:0]) ................. 80
11.2.23.2 User sensitivity shift selection bits (U_SNS_
SHIFT[1:0]) ...................................................... 80
11.2.24 Channel 0 and Channel 1 user
configuration #2 registers (CH0_CFG_U2,
CH1_CFG_U2) ................................................ 81
11.2.24.1 User sensitivity multiplier bits (U_SNS_
MULT[7:0]) ....................................................... 81
11.2.25 Channel 0 and Channel 1 user
configuration #3 registers (CH0_CFG_U3,
CH1_CFG_U3) ................................................ 83
11.2.25.1 Unsigned data select bit (UNSIGNEDDATA) ... 83
11.2.25.2 Channel data type 0 selection bits
(CHxDATATYPE0) ........................................... 84
11.2.25.3 Channel data type 1 selection bits
(CHxDATATYPE1) ........................................... 84
11.2.25.4 Signal chain moving average selection bits
(MOVEAVG[1:0]) ..............................................85
11.2.26 Channel 0 and Channel 1 user
configuration #4 registers (CH0_CFG_U4,
CH1_CFG_U4) ................................................ 85
11.2.26.1 Reset offset cancellation startup bit
(RESET_OC) ................................................... 85
11.2.26.2 Signal inversion bit (INVERT) ..........................86
11.2.26.3 Offset cancellation filter selection bits (OC_
FILT[1:0]) ..........................................................86
11.2.26.4 Arming pin configuration bits (ARM_
CFG[2:0]) and PCM range selection bit
(PCM) ...............................................................86
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NXP Semiconductors
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Dual channel inertial sensor
11.2.27 Channel 0 and Channel 1 user
11.2.49 Invalid register addresses ..............................104
configuration #5 register (CH0_CFG_U5,
11.3
OTP and read/write register array CRC
CH1_CFG_U5) ................................................ 87
11.2.27.1 Self-test control bits (ST_CTRL[3:0]) ...............87
11.2.27.2 Offset cancellation test limit bits (OC_
LIMIT[2:0]) ........................................................88
11.2.27.3 DSP disable bit (DSP_DIS) ............................. 89
11.2.28 Channel 0 and Channel 1 arming
verification ......................................................105
NXP OTP registers ........................................105
User OTP only registers ................................105
OTP modifiable registers ............................... 105
Voltage regulators ..........................................106
VBUF regulator capacitor and capacitor
11.3.1
11.3.2
11.3.3
11.4
11.4.1
configuration registers (CH0_ARM_CFG,
monitor ...........................................................106
CH1_ARM_CFG) .............................................89
11.2.28.1 Arming function down sampling selection
bits (ARM_DS[1:0]) ..........................................89
11.2.28.2 Arming pulse stretch (ARM_PS[1:0]) ...............90
11.2.28.3 Arming window size (ARM_WS_N[1:0], A_
WS_P[1:0]) .......................................................90
11.2.29 Arming threshold registers (CHx_ARM_T_
P, CHx_ARM_T_N) ..........................................91
11.2.30 Offset cancellation user configuration
register (OC_PHASE_CFG) ............................ 92
11.2.30.1 Channel 0 and Channel 1 offset
11.4.1.1 VBUF capacitance monitor timing, DSI3 ........107
11.4.1.2 VBUF capacitance monitor timing, PSI5 ........107
11.4.1.3 VBUF capacitance monitor timing, PSI5
asynchronous mode ...................................... 108
11.4.2
BUS_I, VBUF, VREG, VREGA,
undervoltage monitor .....................................108
Internal oscillator ............................................109
Oscillator training ...........................................109
11.5
11.5.1
11.5.1.1 DSI3 oscillator training ...................................110
11.5.1.2 PSI5 oscillator training ...................................111
11.5.1.3 SPI oscillator training .....................................112
11.5.1.4 I2C oscillator training .....................................112
cancellation final phase control bit (CH0_
OCFINAL, CH1_OCFINAL) ............................. 92
11.2.31 User offset calibration registers (Chx_U_
OFFSET_L, Chx_U_OFFSET_H) ....................92
11.2.32 Channel-specific status register (CH0_
STAT, CH1_STAT) ........................................... 93
11.2.32.1 Signal clipped status bit (SIGNALCLIP) ...........93
11.2.32.2 Offset cancellation phase status
(OCPHASE[2:0]) ..............................................93
11.2.32.3 Self-test incomplete (ST_INCMPLT) ................94
11.2.32.4 Self-test active flag (ST_ACTIVE) ................... 94
11.2.32.5 Offset error flag (OFFSET_ERR) .....................94
11.2.32.6 Self-test error flag (ST_ERROR) ..................... 94
11.2.33 Device status copy register (DEVSTAT_
COPY) ..............................................................95
11.2.34 Sensor data #0 registers (CHx_
11.5.2
11.6
11.6.1
11.6.2
Oscillator training error handling ....................113
Inertial sensor signal path ..............................113
Inertial sensor transducer .............................. 113
Inertial sensor self-test interface ....................114
11.6.2.1 Raw self-test deflection verification ................114
11.6.2.2 Delta self-test deflection verification .............. 114
11.6.2.3 Startup digital self-test ...................................115
11.6.2.4 Fixed pattern self-test ....................................115
11.6.2.5 PSI5 automatic startup self-test procedure ....115
11.6.3
11.6.4
Inertial sensor ΣΔ converter .......................... 117
Inertial sensor digital signal processor ...........117
11.6.4.1 Decimation sinc filter ..................................... 118
11.6.4.2 Signal trim and compensation ....................... 118
11.6.4.3 Digital clipping ............................................... 119
11.6.4.4 Low-pass filter ............................................... 119
11.6.4.5 User sensitivity scaling .................................. 137
11.6.4.6 Offset cancellation ......................................... 137
11.6.4.7 Moving average ............................................. 140
11.6.4.8 Data interpolation ...........................................140
11.6.4.9 Output scaling ................................................141
SNSDATA0_L, CHx_SNSDATA0_H) ............... 95
11.2.35 Sensor data #1 registers (CHx_
SNSDATA1_L, CHx_SNSDATA1_H) ............... 95
11.2.36 Channel-specific factory configuration
register (CHx_CFG_F) .....................................96
11.2.36.1 Range indication bits (RANGE[3:0]) ................ 96
11.2.36.2 Axis indication bits (AXIS[1:0]) ........................ 97
11.2.37 Self-test deflection storage registers ................97
11.2.38 IC type register ................................................98
11.2.39 IC revision register .......................................... 98
11.2.40 IC manufacturer identification register ............. 99
11.2.41 Part number register ........................................99
11.2.42 Device serial number registers ...................... 100
11.2.43 ASIC wafer ID registers .................................101
11.2.44 Transducer wafer ID registers ....................... 101
11.2.45 User data registers (USERDATA_0 -
11.7
11.7.1
11.7.2
Temperature sensor .......................................142
Temperature sensor signal chain ...................142
Temperature sensor output scaling
equations ....................................................... 142
PCM output function ......................................143
Arming function ..............................................144
Arming function: moving average mode ........ 144
Arming function: count mode .........................145
Arming function: unfiltered mode ...................146
Arming function down sampling .....................146
Arming pulse stretch function ........................ 147
Arming pin output structure ........................... 147
DSI3 protocol ...................................................147
DSI3 physical layer ........................................148
Command receiver ........................................ 148
Response transmitter .....................................149
Discovery mode current sense ...................... 149
Address assignment ...................................... 150
11.8
11.9
11.9.1
11.9.2
11.9.3
11.9.4
11.9.5
11.9.6
12
USERDATA_E) .............................................. 102
11.2.45.1 PSI5 initialization phase 2 data
transmissions of user data .............................102
11.2.46 User data registers (USERDATA_10 -
USERDATA_1E) ............................................ 103
11.2.47 Lock and CRC registers ................................ 103
11.2.48 Reserved registers .........................................104
12.1
12.1.1
12.1.2
12.1.3
12.2
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NXP Semiconductors
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Dual channel inertial sensor
12.2.1
12.2.2
12.2.3
Address assignment method for parallel
12.6.3
Resistor connected daisy chain network
connected slaves ...........................................150
Address assignment method for bus switch
connected daisy chain devices ......................150
DSI3 discovery mode: Address assignment
method for resistor connected daisy chain
devices ...........................................................150
DSI3 command and response mode ............. 152
DSI3 command and response mode
using discovery mode ....................................170
DSI3 exception handling ................................170
Daisy chain and discovery mode error
handling ......................................................... 171
PSI5 protocol ...................................................172
Communication interface overview ................172
Data transmission physical layer ................... 172
Synchronization pulse ....................................173
12.7
12.7.1
13
13.1
13.2
13.2.1
12.3
12.3.1
command reception ....................................... 152
13.2.1.1 Synchronization pulse detection .................... 173
13.2.1.2 Synchronization pulse pulldown function ....... 175
12.3.1.1 Bit encoding ...................................................153
12.3.1.2 Command message format ........................... 153
12.3.1.3 Error checking ............................................... 153
13.3
Data transmission data link layer ...................175
Bit encoding ...................................................175
PSI5 data transmission ..................................175
13.3.1
13.3.2
12.3.2
DSI3 command and response mode
response transmission ...................................154
13.3.2.1 PSI5-x10P transmission mode ...................... 176
13.3.2.2 PSI5-x10C transmission mode ...................... 176
13.3.2.3 PSI5-x16P transmission mode ...................... 176
13.3.2.4 PSI5-x16C transmission mode ...................... 176
12.3.2.1 Symbol encoding ........................................... 154
12.3.2.2 Response message format ............................156
12.3.2.3 Error checking ............................................... 156
12.3.3
12.3.4
DSI3 command and response mode timing ...157
DSI3 command and response mode
command summary ....................................... 157
13.3.3
Error detection ............................................... 177
13.3.3.1 Parity error detection ..................................... 177
13.3.3.2 3-bit CRC error detection .............................. 177
12.3.4.1 Register read command ................................ 157
12.3.4.2 Register write command ................................158
12.3.4.3 Global register write command to the
PHYSADDR register ......................................159
12.3.4.4 Enter periodic data collection mode
13.3.4
13.4
13.4.1
13.4.2
PSI5 data field and data range values ...........177
Initialization .................................................... 179
PSI5 initialization phase 1 ............................. 181
PSI5 initialization phase 2 ............................. 181
13.4.2.1 PSI5 initialization phase 2 data
transmissions .................................................182
13.4.3
13.4.4
13.5
13.5.1
13.5.2
13.5.3
command ....................................................... 160
12.3.4.5 Reserved commands .....................................161
Internal self-test ............................................. 185
Initialization phase 3 ......................................185
Normal mode .................................................185
Asynchronous mode ......................................185
Simultaneous sampling mode ........................185
Synchronous sampling mode with minimum
12.4
DSI3 periodic data collection mode and
background diagnostic mode .........................162
DSI3 periodic data collection mode and
12.4.1
background diagnostic mode command
reception ........................................................ 162
12.4.1.1 Bit encoding ...................................................163
12.4.1.2 Command message format ........................... 163
12.4.1.3 Error checking ............................................... 163
latency ............................................................186
PSI5 default mode (un-programmed PSI5
13.6
device) ........................................................... 186
Dual transmission mode ................................188
Daisy chain mode ..........................................189
Error handling ................................................ 191
Daisy chain error handling .............................191
Initialization phase 2 error handling ...............191
Initialization phase 3 error handling ...............192
Normal mode error handling with internal
12.4.2
DSI3 periodic data collection mode
13.7
13.8
13.9
13.9.1
13.9.2
13.9.3
13.9.4
response transmission ...................................163
12.4.2.1 Symbol encoding ........................................... 164
12.4.2.2 Response message format ............................164
12.4.2.3 Error checking ............................................... 165
12.4.3
12.4.4
DSI3 periodic data collection mode timing .....166
Background diagnostic mode response
transmission ...................................................166
error automatic clearing .................................192
12.4.4.1 Symbol encoding ........................................... 166
12.4.4.2 Response message format ............................166
12.4.4.3 Error checking ............................................... 167
13.9.4.1 Standard error reporting ................................ 192
13.9.4.2 PSI5 error extension option ...........................193
13.9.5
Normal mode error handling with internal
12.4.5
12.4.6
DSI3 background diagnostic mode timing ......167
DSI3 periodic data collection mode and
background diagnostic mode command
error latching ..................................................193
13.9.5.1 Standard error reporting ................................ 193
13.9.5.2 PSI5 error extension option ...........................194
summary ........................................................ 167
DSI3 PDCM data transmission modes .......... 168
12.4.7.1 Simultaneous sampling mode (SS_EN = 1) ...168
12.4.7.2 Synchronous sampling mode with minimum
latency (SS_EN = 0) ......................................168
13.10
PSI5 programming mode ...............................194
12.4.7
13.10.1 PSI5 programming mode entry ......................194
13.10.2 PSI5 programming mode - data link layer ......195
13.10.2.1 PSI5 programming mode - command bit
encoding ........................................................ 195
12.5
12.6
12.6.1
12.6.2
Initialization timing ......................................... 169
Maximum number of devices on a network ....169
Pre-configured, parallel connected network ...169
Bus switch connected daisy chain network ....169
13.10.2.2 PSI5 programming mode - command
message format .............................................195
13.10.2.3 Short frame command and response format ..196
13.10.2.4 Long frame command and response format .. 197
FXLS9xxxx
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
253 / 254
NXP Semiconductors
FXLS9xxxx
Dual channel inertial sensor
13.10.2.5 Extra long frame command and response
format .............................................................197
13.10.2.6 Command message CRC ..............................197
13.10.2.7 Command sync pulse blanking time .............. 197
13.10.2.8 Command timeout ......................................... 198
13.10.3 PSI5 programming mode command and
response summary ........................................ 198
13.10.4 Programming mode via PSI5 error
14.5.5
14.5.6
14.5.7
14.6
15
15.1
15.2
15.3
15.4
Error responses ............................................. 215
SPI error ........................................................ 215
SPI data output verification error ................... 216
SPI timing diagram ........................................ 217
Inter-integrated circuit (I2C) interface ........... 217
I2C bit transmissions ..................................... 217
I2C start condition ......................................... 217
I2C byte transmissions .................................. 218
I2C acknowledge and not acknowledge
response summary ........................................ 198
13.11
14
14.1
14.2
14.3
14.3.1
PSI5 OTP programming procedure ............... 199
Standard 32-bit SPI protocol ..........................199
SPI command format .....................................200
SPI response format ......................................200
Command summary ...................................... 201
Register read command ................................ 201
transmissions .................................................218
I2C stop condition ..........................................219
I2C register transfers .....................................219
Register write transfers ..................................219
Register read transfers ..................................220
Sensor data register read wrap around
15.5
15.6
15.6.1
15.6.2
15.6.3
14.3.1.1 Register read command message format ......202
14.3.1.2 Register read response message format .......202
options ........................................................... 221
15.6.3.1 Single channel register read wrap around ..... 221
14.3.2
Register write command ................................202
15.7
16
17
18
19
I2C timing diagram ........................................ 222
Package outline ...............................................223
Soldering ..........................................................229
References .......................................................238
Revision history .............................................. 240
Legal information ............................................241
14.3.2.1 Register write command message format ......203
14.3.2.2 Register write response message format .......203
14.3.3
14.3.3.1 Sensor data request command message
format .............................................................204
14.3.3.2 Sensor data request response message
format .............................................................204
Sensor data request commands ....................204
20
14.3.4
Reserved commands .....................................204
14.3.4.1 Reserved command message format ............205
14.3.4.2 Reserved command response message
format .............................................................205
14.4
14.4.1
Error checking ............................................... 205
Default 8-bit CRC .......................................... 205
14.4.1.1 Command error checking .............................. 205
14.4.1.2 Response error checking ...............................206
14.4.2
Selectable 4-bit CRC .....................................207
14.4.2.1 SPI command format with 4-bit CRC .............207
14.4.2.2 SPI response format with 4-bit CRC ..............207
14.4.2.3 Command error checking with 4-bit CRC .......207
14.4.2.4 Response error checking with 4-bit CRC .......208
14.4.2.5 Message counter (KAC) with 4-bit CRC ........ 208
14.4.2.6 Example 4-bit CRC calculations .................... 208
14.4.3
Selectable 3-bit CRC .....................................209
14.4.3.1 SPI command format with 3-bit CRC .............209
14.4.3.2 SPI response format with 3-bit CRC ..............209
14.4.3.3 Command error checking with 3-bit CRC .......210
14.4.3.4 Response error checking with 3-bit CRC .......210
14.4.3.5 Message (KAC) with 3-bit CRC .....................211
14.4.3.6 Example 3-bit CRC calculations .................... 211
14.5
14.5.1
Exception handling ........................................ 211
Standard basic status reporting field ............. 211
14.5.1.1 Basic status field for responses to register
commands ..................................................... 211
14.5.1.2 Basic status field for responses to sensor
data request commands ................................212
14.5.2
14.5.3
14.5.4
Alternative basic status reporting field ........... 212
Standard detailed status field reporting ......... 213
Alternative detailed status field reporting ....... 214
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 February 2021
Document identifier: FXLS9xxxx
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