FXPS7115D4_技术文档

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Rev. 3 — 5 December 2019

Product data sheet

1 General description

The FXPS7115D4 high-performance, high-precision barometric absolute pressure (BAP)

sensor consists of a compact capacitive micro-electro-mechanical systems (MEMS)

device coupled with a digital integrated circuit (IC) producing a fully calibrated digital

output.

The sensor is based on NXP's high-precision capacitive pressure cell technology. The

architecture benefits from redundant pressure transducers as an expanded quality

measure. This sensor delivers highly accurate pressure and temperature readings

through either a serial peripheral interface (SPI) or an inter-integrated circuit (I²C)

interface. The FXPS7115D4 uses either a 3.3 V or 5.0 V power supply. Furthermore,

the sensor employs an on-demand digital self-test for the digital IC and the MEMS

transducers.

The sensor operates over a pressure range of 40 kPa to 115 kPa and over a wide

temperature range of −40 ºC to 130 ºC.

The sensor comes in an industry-leading 4 mm x 4 mm x 1.98 mm, restriction of

hazardous substances (RoHS) compliant, high power quad flat no lead (HQFN)

package^[1]suitable for small PCB integration. Its AEC-Q100^[2]compliance, high

accuracy, reliable performance, and high media resistivity make it ideal for use in

automotive, industrial, and consumer applications.

2 Features and benefits

• Absolute pressure range: 40 kPa to 115 kPa

• Operating temperature range: –40 °C to 130 °C

• Pressure transducer and digital signal processor (DSP)

– Digital self-test

• I²C compatible serial interface

– Slave mode operation

– Standard mode, fast mode, and fast-mode plus support

• 32-bit SPI compatible serial interface

– Sensor data transmission commands

– 12-bit data for absolute pressure

– 8-bit data for temperature

– 2-bit basic status and 2-bit detailed status fields

– 3, 4, or 8-bit configurable CRC

• Capacitance to voltage converter with anti-aliasing filter

• Sigma delta ADC plus sinc filter

• 800 Hz or 1000 Hz low-pass filter for absolute pressure

• Lead-free, 16-pin HQFN, 4 mm x 4 mm x 1.98 mm package

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

3 Applications

3.1 Automotive

• Engine management digital BAP

• Small engine control

3.2 Industrial

• Compressed air

• Manufacturing line control

• Gas metering

• Weather stations

3.3 Medical/Consumer

• Blood pressure monitor

• Medicine dispensing systems

• White goods

4 Ordering information

Table 1.ꢀOrdering information

Type number

Package

Name

Description

Version

FXPS7115DI4

FXPS7115DS4

HQFN16

HQFN16, plastic, thermal enhanced quad flat pack; no leads; 16 terminals; 0.8 mm

pitch; 4 mm x 4 mm x 1.98 mm body

SOT1573-1

4.1 Ordering options

Table 2.ꢀOrdering options

Device

Range [kPa]

Packing

Interface

I²C

Temperature range

–40 °C to 130 °C

FXPS7115DI4T1

FXPS7115DS4T1

40 kPa to 115 kPa

Tape and reel

SPI

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

2 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

5 Block diagram

V

CC

V

REG

INTERNAL VOLTAGE

REGULATOR

REGA

V

SS

LOW VOLTAGE

DETECTION

V

REF

REFERENCE

VOLTAGE

OSCILLATOR

LOW VOLTAGE

DETECTION

OTP

ARRAY

CONTROL

LOGIC

SS_B

SCLK/SCL

MOSI

SPI/I2C

MISO/SDA

INT

V

REG

REF

P-CELL 0

P-CELL 1

USER

OFFSET

ADJUST

SINC

FILTER

IIR

LPF

P

ABS

P

Σ

ABS

CONVERTER

C2V

GAIN

AAF

TRIM

COMMON

MODE

ERROR

DETECTION

DSP

aaa-029726

Figure 1.ꢀBlock diagram of FXPS7115D4

6 Pinning information

6.1 Pinning

terminal 1

index area

V

1

2

3

4

12 TEST6

11 MISO

10 MOSI

CC

17

TEST

INT

V

9

SCLK

SS

aaa-029729

Transparent top view

Figure 2.ꢀPin configuration for 16-pin HQFN

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

3 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

6.2 Pin description

Table 3.ꢀPin description

Pin name

Description

3

INT

Interrupt output

The output can be configured to be active low or active high. If unused, NXP

recommends pin 3 be unterminated. Optionally, pin 3 can be tied to V_SS

.

1, 16

V_CC

Power supply

Supply return (ground)

Test pin

4, 15

V_SS

2, 5, 12

TESTx

NXP recommends pins 2, 5, and 12 be unterminated. Optionally, these pins can

be tied to V_SS

6, 7, 14

8

NC

No connect

SS_B

Slave / Device select

In I²C mode, input pin 8 must be connected to V_CCwith an external pull-up

resistor, as shown in the application diagram.

In SPI mode, input pin 8 provides the slave select for the SPI port. An internal

pull-up device is connected to this pin.

9

SCLK/SCL

In I²C mode, input pin 9 provides the serial clock. This pin must be connected to

V_CCwith an external pull-up resistor, as shown in the application diagram.

In SPI mode, input pin 9 provides the serial clock. An internal pull-down device is

connected to this pin.

10

11

MOSI

SPI data in

In SPI mode, pin 10 functions as the serial data input to the SPI port. An internal

pull-down device is connected to this pin.

MISO/SDA

SPI/I²C data out

In I²C mode, pin 11 functions as the serial data input/output. Pin 11 must be

connected to V_CCwith an external pull-up resistor, as shown in the application

diagram.

In SPI mode, pin 11 functions as the serial data output.

13

17

V_CCIO

PAD

I/O supply

Pin 13 must be connected to V_CC, the device supply.

Die attach pad

Pin 17 is the die attach flag, and must be connected to V_SS

.

7 Functional description

7.1 Voltage regulators

The device derives its internal supply voltage from the V_CCand V_SSpins. An external

filter capacitor is required for V_CC, as shown in Figure 25 and Figure 26.

A reference generator provides a reference voltage for the ΣΔ converter.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

4 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

V

CC

V

REGA

V

REGA

REF

BANDGAP

VOLTAGE

REFERENCE

REGULATOR

BIAS

GENERATOR

OSCILLATOR

TRIM

C2V

V

REG_MOD

REFERENCE

GENERATOR

Σ

CONVERTER

OTP

ARRAY

V

CC

V

REG

VOLTAGE

REGULATOR

DIGITAL

LOGIC

V

REF

DSP

V

CC

COMPARATOR

VCC_UV_ERR

V

REG

POR

V

REGA

V

REF

aaa-029736

Figure 3.ꢀVoltage regulation and monitoring

7.1.1 V_CC, V_REG, V_REGA, undervoltage monitor

A circuit is incorporated to monitor the V_CCsupply voltage and the internally regulated

voltages V_REGand V_REGA. If any of the voltages fall below the specified undervoltage

thresholds in Table 101, SPI and I²C transactions are terminated. Once the supply

returns above the threshold, the device resumes responses.

7.2 Internal oscillator

The device includes a factory trimmed oscillator as specified in Table 102.

7.3 Pressure sensor signal path

7.3.1 Transducer

See Table 101 and Table 102 for transducer parameters.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

5 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.3.2 Self-test functions

The device includes analog and digital self-test functions to verify the functionality of the

transducer and the signal chain. The self-test functions are selected by writing to the

ST_CTRL[3:0] bits in the DSP_CFG_U1 register. The ST_CTRL bits select the desired

self-test connection.

Once the ENDINIT bit is set, the ST_CTRL bits are forced to '0000'. Future writes to the

ST_CTRL bits are disabled until a device reset.

7.3.2.1 P_ABScommon mode verification

When the P_ABScommon mode self-test is selected, the ST_ACTIVE bit is set, the

ST_ERROR is cleared, and the device begins an internal measurement of the common

mode signal of the P-cells and compares the result against a predetermined limit. If the

result exceeds the limit, the ST_ERROR bit is set. The P_ABScommon mode self-test

repeats continuously every t_{ST_INIT}when the ST_CTRL bits are set to the specified value.

Once the test is disabled, the ST_ERROR bit updates with the final test result within

t_{ST_INIT}of disabling the test. The ST_ACTIVE bit remains set until the final test result is

reported. Figure 4 is an example of a user-controlled self-test procedure.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

6 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Write ST_CTRL = 0x1

Enable PABS

Common Mode Self Test

Delay < t

from Self Test

ST_INIT

Activation

Write ST_CTRL = 0x0

Disable PABS

Common Mode Self Test

Delay > t

from Self Test

ST_INIT

Activation

Read the DSP_STAT Register

yes

ST_ACTIVE Set?

no

User Determined Options:

1) Repeat Self-Test xx times

2) Set error status and continue

3) Set error status and ignore sensor data

yes

ST_ERROR Set?

no

END

aaa-023443

Figure 4.ꢀUser-controlled P_ABScommon mode self-test flowchart

7.3.2.2 Startup digital self-test verification

Four unique fixed values can be forced at the output of the sinc filter by writing to the

ST_CTRL bits as shown in Table 4. The digital self-test values result in a constant value

at the output of the signal chain. After a specified time period, the SNS_DATAx register

value can be verified against the specified values in the table below. The values listed

below are for the P_ABSsignal. When any of these self-test functions are selected, the

ST_ACTIVE bit is set. These signals can only be selected when the ENDINIT bit is not

set.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

7 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 4.ꢀSelf-test control register

ST_CTRL[3]

ST_CTRL[2]

ST_CTRL[1]

ST_CTRL[0]

Function

SNS_DATAx

register contents

1

0

1

0

1

0

1

Digital self-test #1

Digital self-test #2

Digital self-test #3

Digital self-test #4

8171h

6C95h

807Ah

78ACh

7.3.2.3 Startup sense data fixed value verification

Four unique fixed values can be forced to the SNS_DATAX_x registers by writing to

the ST_CTRL bits as shown in Table 5. When any of these values are selected, the

ST_ACTIVE bit is set. These signals can only be selected when the ENDINIT bit is not

set.

Table 5.ꢀSelf-test control bits for sense data fixed value verification

ST_CTRL[3]

ST_CTRL[2]

ST_CTRL[1]

ST_CTRL[0]

Function

SNS_DATAx

register

contents

0

1

0

1

0

1

0

1

DSP write to SNS_DATAx_

X registers inhibited.

0000h

AAAAh

5555h

FFFFh

DSP write to SNS_DATAx_

X registers inhibited.

DSP write to SNS_DATAx_

X registers inhibited.

DSP write to SNS_DATAx_

X registers inhibited.

7.3.3 ΣΔ converter

A second order sigma delta modulator converts the voltage from the analog front end to a

data stream that is input to the DSP. A simplified block diagram is shown in Figure 5.

1 - bit

quantizer

transducer

first

integrator

second

integrator

V

X

α

1

=

C

TOP

C

INT1

α = 1

2

-1

z

-1

z

Y(Z) = {0,1}

BOT

-1

1 - z

C = C

TOP

- C

BOT

ADC

DAC

β

1

= 1

β = 1

2

V = +V

, 0 V, -V

REF

V = C x V /C

INT1

x

aaa-023446

Figure 5.ꢀΣΔ converter block diagram

The sigma delta modulator operates at a frequency of 1 MHz, with the transfer function in

Equation 1.

(1)

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

8 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.3.4 Digital signal processor (DSP)

A DSP is used to perform signal filtering and compensation. A diagram illustrating the

signal processing flow within the DSP is shown in Figure 6.

USER OFFSET

AND

SINC

FILTER

IIR

LPF

Σ

= Y(Z)

TRIM

P

ABS

OUT

GAIN ADJUST

aaa-029737

Figure 6.ꢀSignal chain diagram

7.3.4.1 Decimation sinc filter

In Equation 2, the output of the ΣΔ modulator is decimated and converted to a parallel

value by two third-order sinc filters; the first with a decimation ratio of 24 and the second

with a decimation ratio of 4.

(2)

aaa-023449

20

magnitude

(dB)

0

-20

-40

-60

-80

minimum

typical

-100

maximum

-120

3

4

5

10

frequency (Hz)

Figure 7.ꢀSinc filter response

7.3.4.2 Signal trim and compensation

The device includes digital trim to compensate for sensor offset, sensitivity, and

nonlinearity over temperature.

7.3.4.3 Low-pass filter

Data from the sinc filter is processed by an infinite impulse response (IIR) low-pass filter

with the transfer function and coefficients shown in Equation 3.

(3)

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

9 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 6.ꢀIIR low pass filter coefficients

Filter

number

Typical –3 dB

frequency

Filter

order

Filter coefficients (24 bit)

Group

delay (μs)

Typical

attenuation @

1000 Hz (dB)

1

800 Hz

4

a₀

0.088642612609670

—

418

4.95

n₁₁

n₁₂

n₁₃

n₂₁

n₂₂

n₂₃

a₀

0.029638050039039

0.087543281056143

0.029695285913601

0.250241278804809

0.499999767379068

0.249758953816089

0.129604264748411

0.043719804402508

0.087543281056143

0.043823599710731

0.250296586927511

0.499999648540934

0.249703764531484

d₁₁

d₁₂

d₁₃

d₂₁

d₂₂

d₂₃

—

1

–1.422792640957290

0.511435253566960

1

–1.503329908017845

0.621996524706640

—

2

1000 Hz

4

333

2.99

n₁₁

n₁₂

n₁₃

n₂₁

n₂₂

n₂₃

d₁₁

d₁₂

d₁₃

d₂₁

d₂₂

d₂₃

1

–1.300502656562698

0.430106921311110

1

–1.379959571988366

0.555046257157745

aaa-029738

0

magnitude

(dB)

-20

-40

-60

-80

minimum

typical

maximum

-100

2

3

4

1

10

frequency (Hz)

Figure 8.ꢀ 800 Hz, 4-pole, low-pass filter response

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

10 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

aaa-029891

1000

delay

(µs)

800

600

400

200

0

minimum

typical

maximum

2

3

4

1

10

frequency (Hz)

Figure 9.ꢀ800 Hz, 4-pole output signal delay

aaa-029739

0

magnitude

(dB)

-20

-40

-60

-80

minimum

typical

maximum

-100

2

3

4

1

10

frequency (Hz)

Figure 10.ꢀ 1000 Hz, 4-pole, low-pass filter response

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

11 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

aaa-029892

1000

delay

(µs)

800

600

400

200

0

minimum

typical

maximum

2

3

4

1

10

frequency (Hz)

Figure 11.ꢀ1000 Hz, 4-pole output signal delay

7.3.4.4 Absolute pressure output data scaling equation

Equation 4 is used to convert absolute pressure readings with the variables as specified

in the tables below. Note, the specified values apply only if the P_CAL_ZERO value is

set to 0000h.

(4)

Where:

PABS_kPa= The absolute pressure output in kPa

PABS_LSB= The absolute pressure output in LSB

PABSOFF_LSB= The internal trimmed absolute pressure output value at 0 kPa in LSB

PABS_SENSE= The trimmed absolute pressure sensitivity in LSB/kPa

Range

Data reading

PABSOff_LSB(LSB)

PABS_SENSE(LSB/kPa)

40 - 115 kPa

12-bit output

–1566.6

25538.8

25538

0

34.98

69.96

16-bit output

Interrupt threshold registers

P-zero calibration registers

7.3.5 Temperature sensor

7.3.5.1 Temperature sensor signal chain

The device includes a temperature sensor for signal compensation and user readability.

Figure 12 shows a simplified block diagram. Temperature sensor parameters are

specified in Table 101 and Table 102.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

12 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

TEMPERATURE

∑

SINC

FILTER

MOVING

AVERAGE

OFFSET

AND

to temperature output

temperature sensor

CONVERTER

GAIN TRIM

aaa-023461

Figure 12.ꢀTemperature sensor signal chain block diagram

7.3.5.2 Temperature sensor output scaling equation

Equation 5 is used to convert temperature readings with the variables specified in

Table 7.

(5)

where:

T_DEGC= The temperature output in degrees C

T_LSB= The temperature output in LSB

T0_LSB= The expected temperature output in LSB at 0 °C

T_SENSE= The expected temperature sensitivity in LSB/°C

Table 7.ꢀTemperature conversion variables

Data reading

T0_LSB(LSB)

T_SENSELSB/C)

8-bit register read

68

1

7.3.6 Common mode error detection signal chain

The device includes a continuous pressure transducer common mode error detection.

A simplified block diagram is shown in Figure 13. The common mode error signal is

compared against the normal absolute pressure signal. If the comparison falls outside

of pre-determined limits, the CM_ERROR bit in the DSP_STAT register is set. Once the

error condition is removed, the CM_ERROR bit is cleared as specified in Section 7.7.16

"DSP_STAT - DSP-specific status register (address 60h)".

common mode

signal from ADC

common mode

error signal

SINC

FILTER

LOW PASS

FILTER

COMPENSATION

aaa-023462

Figure 13.ꢀCommon mode error detection signal chain block diagram

7.4 Inter-integrated circuit (I²C) interface

The device includes an interface compliant to the NXP I²C-bus specification^[3]. The

device operates in slave mode and includes support for standard mode, fast mode, and

fast mode plus, although the maximum practical operating frequency for I²C in a given

system implementation depends on several factors including the pull-up resistor values

and the total bus capacitance.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

13 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.4.1 I²C bit transmissions

The state of SDA when SCL is high determines the bit value being transmitted. SDA

must be stable when SCL is high and change when SCL is low as shown in Figure 14.

After the START signal has been transmitted by the master, the bus is considered busy.

Timing for the start condition is specified in Table 102.

SDA

SCL

SDA stable

SDA = `1'

SDA stable

SDA = `0'

SDA

changes

aaa-029746

Figure 14.ꢀI²C bit transmissions

7.4.2 I²C start condition

A bus operation is always started with a start condition (START) from the master.

A START is defined as a high to low transition on SDA while SCL is high as shown

in Figure 15. After the START signal has been transmitted by the master, the bus is

considered busy. Timing for the start condition is specified in Table 102.

A start condition (START) and a repeat START condition (rSTART) are identical.

SDA

SCL

START

aaa-029747

Figure 15.ꢀI²C start condition

7.4.3 I²C byte transmission

Data transfers are completed in byte increments. The number of bytes that can be

transmitted per transfer is unrestricted. Each byte must be followed by an acknowledge

bit (Section 7.4.4 "I2C acknowledge and not acknowledge transmissions") from the

receiver. Data is transferred with the most significant bit (MSB) first (see Figure 16).

The master generates all clock pulses, including the ninth clock for the acknowledge bit.

Timing for the byte transmissions is specified in Section 7.4.4 "I2C acknowledge and

not acknowledge transmissions". All functions for this device are completed within the

acknowledge clock pulse. Clock stretching is not used.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

14 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

SDA

SCL

START

ACK

STOP

from slave

from receiver

aaa-029748

Figure 16.ꢀI²C byte transmissions

7.4.4 I²C acknowledge and not acknowledge transmissions

Each byte must be followed by an acknowledge bit (ACK) from the receiver. For an ACK,

the transmitter releases SDA during the acknowledge clock pulse and the receiver pulls

SDA low during the high portion of the clock pulse. Set up and hold times as specified in

Table 102 must also be taken into account.

For a not acknowledge bit (NACK), SDA remains high during the entire acknowledge

clock pulse. Five conditions lead to a NACK:

1. No receiver is present on the bus with the transmitted address.

2. The addressed receiver is unable to receive or transmit because it is performing some

real-time function and is not ready to start communication with the master.

3. The receiver receives unrecognized data or commands.

4. The receiver cannot receive any more data bytes.

5. The master-receiver signals the end of the transfer to the slave transmitter.

Following a NACK, the master can transmit either a STOP to terminate the transfer, or a

repeated START to initiate a new transfer.

An example ACK and NACK are shown in Figure 17.

SDA

SCL

ACK

ninth clock pulse

aaa-029749

Figure 17.ꢀI²C acknowledge and not acknowledge transmission

7.4.5 I²C stop condition

A bus operation is always terminated with a stop condition (STOP) from the master.

A STOP is defined as a low to high transition on SDA while SCL is high as shown in

Figure 18. After the STOP has been transmitted by the master, the bus is considered

free. Timing for the stop condition is specified in Table 102.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

15 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

SDA

SCL

STOP

aaa-029750

Figure 18.ꢀI²C stop condition

7.4.6 I²C register transfers

7.4.6.1 Register write transfers

The device supports I²C register write data transfers. Register write data transfers are

constructed as follows:

1. The master transmits a START condition.

2. The master transmits the 7-bit slave address.

3. The master transmits a '0' for the read/write bit to indicate a write operation.

4. The slave transmits an ACK.

5. The master transmits the register address to be written.

6. The slave transmits an ACK.

7. The master transmits the data byte to be written to the register address.

8. The slave transmits an ACK.

9. The master transmits a STOP condition.

S

SLAVE ADDRESS

W

A

REGISTER ADDRESS

A

REGISTER DATA

A

P

Master transmission

Slave transmission

aaa-029920

The device automatically increments the register address allowing for multiple register

writes to be completed in one transaction. In this case, the register write data transfers

are constructed as follows:

1. The master transmits a START condition.

2. The master transmits the 7-bit slave address.

3. The master transmits a '0' for the read/write bit to indicate a write operation.

4. The slave transmits an ACK.

5. The master transmits the register address to be written.

6. The slave transmits an ACK.

7. The master transmits the data byte to be written to the register address.

8. The slave transmits an ACK.

9. The master transmits the data byte to be written to the register address +1.

10.The slave transmits an ACK.

11.Repeat steps 9 and 10 until all registers are written.

12.The master transmits a STOP condition.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

16 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.4.6.2 Register read transfers

The device supports I²C register read data transfers. Register read data transfers are

constructed as follows:

1. The master transmits a START condition.

2. The master transmits the 7-bit slave address.

3. The master transmits a '0' for the read/write bit to indicate a write operation.

4. The slave transmits an ACK.

5. The master transmits the register address to be read.

6. The slave transmits an ACK.

7. The master transmits a repeat START condition.

8. The master transmits the 7-bit slave address.

9. The master transmits a '1' for the read/write bit to indicate a read operation.

10.The slave transmits an ACK.

11.The slave transmits the data from the register addressed.

12.The master transmits a NACK.

13.The master transmits a STOP condition.

S

SLAVE ADDRESS

W

A

REGISTER ADDRESS

A

rSTART

SLAVE ADDRESS

R

A

REGISTER DATA

N

P

Master transmission

Slave transmission

aaa-029919

7.4.6.3 Sensor data register read wrap around

The device includes automatic sensor data register read wrap-around features to

optimize the number of I²C transactions necessary for continuous reads of sensor data.

Depending on the state of the SIDx_EN bits in the SOURCEID_0 and SOURCEID_1

registers, the register address automatically wraps back to the DEVSTAT_COPY register

as shown in Table 8.

Table 8.ꢀSensor data register read wrap-around description

SID1_EN

SID0_EN

Address increment and wrap-around effect

Optimized register-read sequence

None

0

1

Address wraps around from $FF to $00

Address wraps from $63 (SNSDATA0_H) to $61

(DEVSTAT_COPY)

DEVSTAT_COPY, SNSDATA0_L, SNSDATA0_H

1

0

1

Address wraps from $65 (SNSDATA1_H) to $61

(DEVSTAT_COPY)

DEVSTAT_COPY, SNSDATA0_L, SNSDATA0_H,

SNSDATA1_L, SNSDATA1_H

Address wraps from $69 (SNSDATA0_TIME3) to $61

(DEVSTAT_COPY)

DEVSTAT_COPY, SNSDATA0_L, SNSDATA0_H,

SNSDATA1_L, SNSDATA1_H, SNSDATA0_TIME0,

SNSDATA0_TIME1, SNSDATA0_TIME2, SNSDATA0_

TIME3

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

17 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.4.7 I²C timing diagram

t

f

t

r

t

SU;DAT

70 %

30 %

70 %

30 %

SDA

SCL

... cont.

t

VD;DAT

t

r

HD;DAT

f

t

HIGH

70 %

30 %

70 %

30 %

70 %

30 %

70 %

30 %

... cont.

th

9

clock

t

HD;STA

1 / f

1

LOW

SCL

clock cycle

S

st

t

BUF

... SDA

... SCL

t

SU;STA

t

VD;ACK

t

SU;STO

t

SP

HD;STA

70 %

30 %

Sr

P

S

th

9

clock

aaa-029751

Figure 19.ꢀI²C timing diagram

7.5 Standard 32-bit SPI protocol

The device includes a standard SPI protocol requiring 32-bit data packets. The device

is a slave device and requires that the base clock value be low (CPOL = 0) with data

captured on the rising edge of the clock and data propagated on the falling edge of the

clock (CPHA = 0). The most significant bit is transferred first (MSB first). SPI transfers are

completed through a sequence of two phases. During the first phase, the command is

transmitted from the SPI master to the device. During the second phase, response data

is transmitted from the slave device. MOSI and SCLK transitions are ignored when SS_B

is not asserted.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

18 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

SCLK

SS_B

MOSI

phase one: command

phase two response

phase one: response-previous command

MISO

SCLK

SS_B

MOSI

T1

T2

R1

T3

R2

R3

MISO

aaa-023747

Figure 20.ꢀStandard 32 Bit SPI protocol timing diagram

7.5.1 SPI command format

Table 9.ꢀSPI command format

MSB: bit 31; LSB: bit 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

16

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Register access command

Command

Fixed bits:

must = 0h

Register address

Register data

8-bit CRC

C[3:0]

0

RA[7:1]

RA[0]

Sensor data command

Fixed bits: must = 0 0000h

RD[7:0]

CRC[7:0]

Command

8-bit CRC

C[3:0]

0

CRC[7:0]

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

19 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 10.ꢀSPI command bit allocation

C[3:0]

Command type

Data source SOURCEID[2:0] = C[3:1]

Reference

0

Unused Command

Not applicable

(reserved for error response)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Sensor Data Request

reserved Command

Sensor Data Request

reserved Command

Sensor Data Request

reserved Command

Sensor Data Request

Register Write Request

Sensor Data Request

reserved Command

Sensor Data Request

Register Read Request

Sensor Data Request

Reserved Command

Sensor Data Request

SOURCEID = 0h

Not applicable

SOURCEID = 1h

Not applicable

SOURCEID = 2h

Not applicable

SOURCEID = 3h

Not applicable

SOURCEID = 4h

Not applicable

SOURCEID = 5h

Not applicable

SOURCEID = 6h

Not applicable

SOURCEID = 7h

7.5.2 SPI response format

Table 11.ꢀSPI response format

MSB: bit 31; LSB: bit 0

31

30

29

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Response to Register Request

9

8

7

6

5

4

3

2

1

0

Command

Basic Unused

Register data: contents

of RA[7:1] high byte

Register data: contents

of RA[7:1] low byte

8-bit CRC

Status

Data

0h

C[0], [3:1]

ST[1:0]

0

RD[15:8]

RD[7:0]

CRC[7:0]

Response to Sensor Data Request

Sensor Data

Command

Basic

Status

Detail

Status

8-bit CRC

C[0], [3:1]

ST[1:0]

SD[11:0]

0

SF[1:0]

CRC[7:0]

Error Response to Register Request

Unused Data = 0000h

Command

Basic

Status

Detail

Status

8-bit CRC

C[0], [3:1]

1

0

SF[1:0]

CRC[7:0]

Error Response to Sensor Data Request With Sensor Data

Sensor Data

Command

Basic

Status

Detail

Status

8-bit CRC

C[0] C[3] C[2] C[1]

1

SD[11:0]

0

SF[1:0]

CRC[7:0]

Error Response to Sensor Data Request Without Sensor Data

Unused Data = 0000h

Command

Basic

Status

x

Detail

Status

8-bit CRC

0

1

x

0

SF[1:0]

CRC[7:0]

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

20 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.5.3 Command summary

7.5.3.1 Register read command

The device supports a register read command. The register read command uses the

upper 7 bits of the addresses defined in Section 7.6 "User-accessible data array" to

address 8-bit registers in the register map.

The response to a register read command is shown in Section 7.5.3.1.2 "Register read

response message format". The response is transmitted on the next SPI message if and

only if all of the following conditions are met:

• No SPI error is detected (see Section 7.5.5.3 "SPI error" )

• No MISO error is detected (see Section 7.5.5.4 "SPI data output verification error")

If these conditions are met, the device responds to the register read request as shown

in Section 7.5.3.1.2 "Register read response message format". Otherwise, the device

responds with the error response as defined in Section 7.5.5.2 "Error responses". The

register read response includes the register contents at the rising edge of SS_B for the

register read command.

7.5.3.1.1 Register read command message format

Table 12.ꢀRegister read command message format

MSB: bit 31; LSB: bit 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

Register access command

Register address

16

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Command

C[3:0]

Fixed bits:

must = 0h

Register data

8-bit CRC

1

0

RA[7:1]

RA[0]

0

CRC[7:0]

Table 13.ꢀRegister read command message bit field descriptions

Bit field

Definition

C[3:0]

Register read command = '1100'

RA[7:0]

CRC[7:0]

RA[7:1] contains the word address of the register to be read.

Read CRC Section

7.5.3.1.2 Register read response message format

Table 14.ꢀRegister read response message format

MSB: bit 31; LSB: bit 0

31 30 29 28 27

26

25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Register access command

Command

C[0], [3:1]

Basic

Status

Unused

Data 0h

Register data: contents

of RA[7:1] high byte

Register data: contents

of RA[7:1] low byte

8-bit CRC

0

1

0

ST[1:0]

0

RD[15:8]

RD[7:0]

CRC[7:0]

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

21 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 15.ꢀRegister read response message bit field descriptions

Bit field

C[0], [3:1]

ST[1:0]

Definition

Register Read Command = '0110'

Status

RD[15:8]

RD[7:0]

The contents of the register addressed by RA[7:1] high byte (RA[0] = 1)

The contents of the register addressed by RA[7:1] low byte (RA[0] = 0)

8-bit CRC

CRC[7:0]

7.5.3.2 Register write command

The device supports a register write command. The register write command writes the

value specified in RD[7:0] to the register addressed by RA[7:0].

The response to a register write command is shown in Section 7.5.3.2.2 "Register write

response message format". The register write is executed and a response is transmitted

on the next SPI message if and only if all of the following conditions are met:

• No SPI error is detected (see Section 7.5.5.3 "SPI error")

• No MISO error is detected (see Section 7.5.5.4 "SPI data output verification error")

• The ENDINIT bit is cleared

– This applies to all registers with the exception of the RESET[1:0] bits in the

DEVLOCK_WR register

• No invalid register request is detected as described below

If these conditions are met, the register write is executed and the device responds to the

register write request as shown in Section 7.5.3.2.2 "Register write response message

format". Otherwise, no register is written and the device responds with the error response

as defined in Section 7.5.2 "SPI response format". The register is not written until the

transfer during which the register write was requested has been completed.

A register write command to a read-only register will not execute, but will result in a valid

response.

7.5.3.2.1 Register write command message format

Table 16.ꢀRegister write command message format

MSB: bit 31; LSB: bit 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

Register access command

Register address

16

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Command

C[3:0]

Fixed bits:

must = 0h

Register data

8-bit CRC

1

0

RA[7:1]

RA[0]

RD[7:0]

CRC[7:0]

Table 17.ꢀRegister write command message bit field descriptions

Bit field

Definition

C[3:0]

Register write command = '1000'

RA[7:0]

RD[7:0]

CRC[7:0]

RA[7:1] contains the byte address of the register to be written

RD[7:0] contains the data byte to be written to address RA[7:0]

8-bit CRC

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

22 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.5.3.2.2 Register write response message format

Table 18.ꢀRegister write response message format

MSB: bit 31; LSB: bit 0

31 30 29 28 27

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

Register access command

Register data: contents Register data: contents

9

8

7

6

5

4

3

2

1

0

Command

Basic

Unused

Data

0h

8-bit CRC

C[0], [3:1]

Status

of RA[7:1] high byte

of RA[7:1] low byte

0

1

0

ST[1:0]

0

RD[15:8]

RD[7:0]

CRC[7:0]

Table 19.ꢀRegister write response message bit field descriptions

Bit field

C[0], [3:1]

ST[1:0]

Definition

Register Read Command = '0100'

Status

RD[15:8]

RD[7:0]

The contents of the register addressed by RA[7:1] high byte (RA[0] = 1)

The contents of the register addressed by RA[7:1] low byte (RA[0] = 0)

8-bit CRC

CRC[7:0]

7.5.3.3 Sensor data request commands

The device supports standard sensor data request commands. The sensor data request

command format is described in Section 7.5.3.3.1 "Sensor data request command

message format". The response to a sensor data request is shown in Section 7.5.3.3.2

"Sensor data request response message format". The response is transmitted on the

next SPI message subject to the error handling conditions specified in Section 7.5.5

"Exception handling". The sensor data included in the response is the sensor data at the

falling edge of SS_B for the sensor data request response.

7.5.3.3.1 Sensor data request command message format

Table 20.ꢀSensor data request command message format

MSB: bit 31; LSB: bit 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Command

Fixed bits: must = 0 0000h

8-bit CRC

C[3:0]

0

CRC[7:0]

Table 21.ꢀSensor data request command message bit field descriptions

Bit field

Definition

C[0]

Sensor data request command = '1'

Source identification code for the requested sensor data

8-bit CRC

C[3:1] = SOURCEID[2:0]

CRC[7:0]

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

23 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.5.3.3.2 Sensor data request response message format

Table 22.ꢀSensor data request response message format

MSB: bit 31; LSB: bit 0

31 30 29 28 27

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Command

Basic Sensor Data

Detail

8-bit CRC

Status

C[0], [3:1]

ST[1:0]

SD[11:0]

0

SF[1:0]

CRC[7:0]

Table 23.ꢀSensor data request response message bit field descriptions

Bit field

Definition

C[0]

Sensor data request command = '1'

C[3:1] = SOURCEID[2:0]

ST[1:0]

Source identification code for the requested sensor data

Basic Status

Sensor data

Detailed status

8-bit CRC

SD[11:0]

SF[1:0]

CRC[7:0]

7.5.3.4 Reserved commands

The device responds to reserved commands on the next SPI message subject to the

error handling conditions specified in Section 7.5.5 "Exception handling".

7.5.3.4.1 Reserved command message format

Table 24.ꢀReserved command message format

MSB: bit 31; LSB: bit 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

x

8

x

7

6

5

4

3

2

1

0

Command

x

8-bit CRC

CRC[7:0]

0

1

0

1

0

1

0

1

0

1

0

Table 25.ꢀReserved command message bit field descriptions

Bit field

Definition

C[3:0]

Reserved command

8-bit CRC

CRC[7:0]

7.5.3.4.2 Reserved command response message format

Table 26.ꢀReserved command response message format

MSB: bit 15; LSB: bit 0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Command Echo

Data

8-bit CRC

x

CRC[7:0]

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

24 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 27.ꢀReserved command response message bit field descriptions

Bit field

Definition

Command echo

Data

Reserved command echo. Undefined

Response data. Undefined

8-bit CRC

CRC[7:0]

7.5.4 Error checking

7.5.4.1 Default 8-bit CRC

7.5.4.1.1 Command error checking

The device calculates an 8-bit CRC on the entire 32 bits of each command. Message

data is entered into the CRC calculator MSB first, consistent with the transmission

order of the message. If the calculated CRC does not match the transmitted CRC, the

command is ignored and the device responds with the SPI error response.

The CRC decoding procedure is as follows:

1. A seed value is preset into the LSB of the shift register.

2. Using a serial CRC calculation method, the receiver rotates the received message

and CRC into the LSB of the shift register in the order received (MSB first).

3. When the calculation on the last bit of the CRC is rotated into the shift register, the

shift register contains the CRC check result.

4. If the shift register contains all zeros, the CRC is correct.

5. If the shift register contains a value other than zero, the CRC is incorrect.

The CRC polynomial and seed are shown in Table 28.

Table 28.ꢀSPI Command Message CRC

SPICRCSEED[3:0]

Default Polynomial

x⁸+ x⁵+ x³+ x²+ x + 1

Default non-direct Seed

1111 1111

0000

non-zero

1111 SPICRCSEED[3:0]

7.5.4.1.2 Response error checking

The device calculates a CRC on the entire 32 bits of each response. Message data is

entered into the CRC calculator MSB first, consistent with the transmission order of the

message.

The CRC encoding procedure is as follows:

1. A seed value is preset into the LSB of the shift register.

2. Using a serial CRC calculation method, the transmitter rotates the transmitted

message and CRC into the LSB of the shift register (MSB first).

3. Following the transmitted message, the transmitter feeds 8 zeros into the shift

register, to match the length of the CRC.

4. When the last zero is fed into the input adder, the shift register contains the CRC.

5. The CRC is transmitted.

The CRC polynomial and seed are shown in Table 29.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

25 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 29.ꢀSPI Response Message CRC

SPICRCSEED[3:0]

Default Polynomial

x⁸+ x⁵+ x³+ x²+ x + 1

Default non-direct Seed

1111 1111

0000

nonzero

1111 SPICRCSEED[3:0]

7.5.5 Exception handling

7.5.5.1 Basic status field

All responses include a status field (ST[1:0]) that includes the general status of the

device and transmitted data as described below. The contents of the status field is

a representation of the device status at the rising edge of SS_B for the previous SPI

command.

Table 30.ꢀBasic status field for responses to register commands

ST[1:0]

Status

Description

SF[1:0]

Priority

0

Device in Initialization

Device in initialization (ENDINIT not

set)

0

3

0

1

0

Normal Mode

Self-test

Normal mode(ENDINIT set)

0

4

2

Self-test(ST_CTRL[3:0] not equal to

'0000')

1

Internal Error Present

Detailed Status Field

Detailed

1

Status Field

7.5.5.2 Error responses

Table 31.ꢀError responses bit field descriptions

SF[1:0]

Status Sources

DEVSTAT State

Bit set in DEVSTAT3

0

Oscillator training error (OSCTRAIN_ERR)

Offset error (PABS_HIGH or PABS_LOW or CM_ Bit set in DSP_STAT

ERROR)

Bit set in DEVSTAT2

Temperature error

0

1

0

1

User OTP memory error (UF2 or UF1)

User R/W memory error (UF2)

NXP OTP Memory error

U_OTP_ERR set in DEVSTAT2

U_RW_ERR set in DEVSTAT2

F_OTP_ERR set in DEVSTAT2

Test Mode active

Supply error

TESTMODE bit set in DEVSTAT

bit set in DEVSTAT1

DEVRES set

Reset error

MISO error

SPI error

Bit set in DEVSTAT3

N/A

7.5.5.3 SPI error

The following external SPI conditions result in a SPI error:

• SCLK is high when SS_B is asserted

• The number of SCLK rising edges detected while SS_B is asserted is not equal to 16

• SCLK is high when SS_B is deasserted

• CRC error is detected (MOSI)

• A register write command to any register other than the DEVLOCK_WR register is

received while ENDINIT is set

If a SPI error is detected, the device responds with the error response as described

in Section 7.5.5.2 "Error responses" with the detailed status field set to “SPI Error” as

defined in Section 7.5.5.1 "Basic status field".

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

26 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.5.5.4 SPI data output verification error

The device includes a function to verify the integrity of the data output to the MISO pin.

The function compares the data transmitted on the MISO pin to the data intended to be

transmitted. If any one bit does not match, a SPI MISO mismatch fault is detected and

the MISO_ERR flag in the DEVSTAT2 register is set.

If a valid sensor data request message is received during the SPI transfer with the MISO

mismatch failure, the request is ignored and the device responds with the error response

as described in Section 7.5.5.2 "Error responses" with the detailed status field set to

“SPI Error” as defined in Section 7.5.5.1 "Basic status field" during the subsequent SPI

message.

If a valid register write request message is received during the SPI transfer with the

MISO mismatch failure, the register write is completed as requested, but the device

responds with the error response as described in Section 7.5.5.2 "Error responses" with

the detailed status field set to “SPI Error” as defined in Section 7.5.5.1 "Basic status field"

during the subsequent SPI message.

If a valid register read request message is received during the SPI transfer with the MISO

mismatch failure, the register read is ignored and the device responds with the error

response as described in Section 7.5.5.2 "Error responses" with the detailed status field

set to “SPI Error” as defined in Section 7.5.5.1 "Basic status field", during the subsequent

SPI message.

SPI DATA OUT SHIFT REGISTER

DATA OUT BUFFER

MISO

D

Q

D

Q

R

MISO ERR

D

Q

SCLK

R

aaa-023748

Figure 21.ꢀSPI data output verification

7.5.6 SPI timing diagram

DSP Out

t

LAT

SS_B

t

SSN

LEAD

SCLKR

SCLKF

t

SSCLK

t

SCLKH

SCLK

t

CLKSS

SCLKL

LAG

t

ACCESS

t

HOLD_OUT

t

VALID

DISABLE

MISO

t

HOLD_IN

t

SETUP

MOSI

aaa-023749

Figure 22.ꢀSPI timing diagram

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

27 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.6 User-accessible data array

A user-accessible data array allows each device to be customized. The array consists

of a one time programmable (OTP) factory-programmable block, an OTP user-

programmable block, and read-only registers for data and device status. The OTP blocks

incorporate independent data verification.

Table 32.ꢀUser-accessible data — sensor specific information

Address Register

Type^[1]

Bit

7

6

5

4

3

2

1

0

General device information

$00

$01

COUNT

R

COUNT[7:0]

DEVSTAT

DSP_ERR

reserved

COMM_ERR MEMTEMP_

ERR

SUPPLY_

ERR

TESTMODE

DEVRES

DEVINIT

CONT_ERR

reserved

$02

$03

$04

$05

DEVSTAT1

DEVSTAT2

DEVSTAT3

R

VCCUV_

ERR

VCCOV_

ERR

reserved

INTREGA_

ERR

INTREG_

ERR

INTREGF_

ERR

R

F_OTP_ERR

U_OTP_

ERR

U_RW_ERR

U_W_

reserved

TEMP0_

ERR

reserved

ACTIVE

MISO_ERR OSCTRAIN_

ERR

reserved

R

reserved

$06 to

$0D

reserved

$0E

$0F

TEMPERATURE

reserved

R

TEMP[7:0]

reserved

Communication information

$10

DEVLOCK_WR

R/W

ENDINIT

reserved

SUP_

ERR_DIS

reserved

RESET[1:0]

$11 to

$13

reserved

$14

$15

$16

UF_REGION_W R/W

REGION_LOAD[3:0]

REGION_ACTIVE[3:0]

0

UF_REGION_R

COMMTYPE

reserved

R

0

UF2

reserved

COMMTYPE[2:0]

$17 to

$19

reserved

$1A

$1B

SOURCEID_0

SOURCEID_1

reserved

UF2

SID0_EN

SID1_EN

reserved

SOURCEID_0[3:0]

SOURCEID_1[3:0]

$1C to

$21

reserved

$22

TIMING_CFG

reserved

UF2

reserved

OSCTRAIN_

SEL

CK_CAL_

RST

reserved

CK_CAL_EN

$23 to

$3C

reserved

$3D

$3E

$3F

SPI_CFG

UF2

reserved

DATASIZE

SPI_CRC_LEN[1:0]

SPICRCSEED[3:0]

WHO_AM_I

I2C_ADDRESS

WHO_AM_I[7:0]

I2C_ADDRESS[7:0]

Sensor specific information

$40

$41

$42

$43

$44

DSP_CFG_U1

DSP_CFG_U2

DSP_CFG_U3

DSP_CFG_U4

DSP_CFG_U5

UF2

LPF[3:0]

reserved

USER_RANGE[1:0]

reserved

A_OUT

INT_OUT

reserved

ST_CTRL[3:0]

reserved

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

28 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Address Register

Type^[1]

Bit

7

6

5

4

3

2

1

0

$45

INT_CFG

UF2

reserved

INT_PS[1:0]

INT_

reserved

POLARITY

$46

$47

$48

$49

$4A

$4B

$4C

$4D

$4E

P_INT_HI_L

P_INT_HI_H

P_INT_LO_L

P_INT_LO_H

reserved

UF2

P_INT_HI_L[7:0]

P_INT_HI_H[15:8]

P_INT_LO_L[7:0]

P_INT_LO_H[15:8]

reserved

P_CAL_ZERO_L UF2

P_CAL_ZERO_H UF2

P_CAL_ZERO_L[7:0]

P_CAL_ZERO_H[15:8]

reserved

UF2

$4F to

$5E

reserved

$5F

$60

CRC_UF2

F

LOCK_UF2

reserved

0

CRC_UF2[3:0]

ST_ACTIVE CM_ERROR ST_ERROR

DSP_STAT

R

PABS_HIGH PABS_LOW

reserved

ST_

INCMPLT

$61

DEVSTAT_

COPY

R

DSP_ERR

reserved

COMM_ERR MEMTEMP_

ERR

SUPPLY_

ERR

TESTMODE

DEVRES

DEVINT

$62

$63

$64

$65

$66

SNSDATA0_L

SNSDATA0_H

SNSDATA1_L

SNSDATA1_H

R

SNSDATA0_L[7:0]

SNSDATA0_H[15:8]

SNSDATA1_L[7:0]

SNSDATA1_H[15:8]

SNSDATA0_TIME[7:0]

SNSDATA0_

TIME0

$67

$68

$69

$6A

$6B

SNSDATA0_

TIME1

R

SNSDATA0_TIME[15:8]

SNSDATA0_TIME[23:16]

SNSDATA0_TIME[31:24]

SNSDATA0_TIME[39:32]

SNSDATA0_TIME[47:40]

SNSDATA0_

TIME2

SNSDATA0_

TIME3

SNSDATA0_

TIME4

SNSDATA0_

TIME5

$6C

$6D

$6E

$6F

P_MAX_L

P_MAX_H

P_MIN_L

P_MIN_H

reserved

R

P_MAX[7:0]

P_MAX[15:8]

P_MIN[7:0]

P_MIN[15:8]

reserved

$70 to

$77

$78

$79

$7A

$7B

$7C

$7D

FRT0

FRT1

FRT2

FRT3

FRT4

FRT5

reserved

R

FRT[7:0]

FRT[15:8]

FRT[23:16]

FRT[31:24]

FRT[39:32]

FRT[47:40]

reserved

$7E to

$9F

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

29 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Address Register

Type^[1]

Bit

7

6

5

4

3

2

1

0

Sensor Specific Information - User Readable Registers with OTP

$A0

DSP_CFG_F

reserved

F

DEV_RANGE[3:0]

reserved

$A1 to

$AE

reserved

$AF

CRC_F_A

reserved

F

LOCK_F_A

LOCK_F_B

REGA_BLOCKID[2:0]

CRC_F_A[3:0]

$B0 to

$BE

reserved

$BF

CRC_F_B

F

REGB_BLOCKID[2:0]

CRC_F_B[3:0]

Traceability Information

$C0

$C1

$C2

$C3

$C4

$C5

$C6

$C7

$C8

$C9

$CA

$CB

$CC

$CD

$CE

$CF

$D0

$D1

$D2

$D3

$D4

$D5

ICTYPEID

ICREVID

ICMFGID

reserved

PN0

F

ICTYPEID[7:0]

ICREVID[7:0]

ICMFGID[7:0]

reserved

F

PN0[7:0]

PN1

F

PN1[7:0]

SN0

F

SN[7:0]

SN1

F

SN[15:8]

SN2

F

SN[23:16]

SN3

F

SN[31:24]

SN4

F

SN[39:32]

ASICWFR#

ASICWFR_X

ASICWFR_Y

reserved

CRC_F_C

ASICWLOT_L

ASICWLOT_H

reserved

F

ASICWFR#[7:0]

ASICWFR_X[7:0]

ASICWFR_Y[7:0]

reserved

F

LOCK_F_C

REGC_BLOCKID[2:0]

CRC_F_C[3:0]

F

ASICWLOT_L[7:0]

ASICWLOT_H[7:0]

reserved

F

—

F

reserved

$D6 to

$DE

reserved

$DF

$E0

$E1

$E2

$E3

$E4

$E5

$E6

$E7

$E8

$E9

$EA

$EB

CRC_F_D

F

LOCK_F_D

REGD_BLOCKID[2:0]

CRC_F_D[3:0]

USERDATA_0

USERDATA_1

USERDATA_2

USERDATA_3

USERDATA_4

USERDATA_5

USERDATA_6

USERDATA_7

USERDATA_8

USERDATA_9

USERDATA_A

USERDATA_B

UF2

USERDATA_0[7:0]

USERDATA_1[7:0]

USERDATA_2[7:0]

USERDATA_3[7:0]

USERDATA_4[7:0]

USERDATA_5[7:0]

USERDATA_6[7:0]

USERDATA_7[7:0]

USERDATA_8[7:0]

USERDATA_9[7:0]

USERDATA_A[7:0]

USERDATA_B[7:0]

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

30 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Address Register

Type^[1]

Bit

7

6

5

4

3

2

1

0

$EC

$ED

$EE

$EF

$F0

$F1

$F2

$F3

$F4

$F5

$F6

$F7

$F8

$F9

$FA

$FB

$FC

$FD

$FE

$FF

USERDATA_C

UF2

F

USERDATA_C[7:0]

USERDATA_D[7:0]

USERDATA_E[7:0]

USERDATA_D

USERDATA_E

CRC_UF0

LOCK_UF0

REGE_BLOCKID[2:0]

CRC_UF0[3:0]

USERDATA_10

USERDATA_11

USERDATA_12

USERDATA_13

USERDATA_14

USERDATA_15

USERDATA_16

USERDATA_17

USERDATA_18

USERDATA_19

USERDATA_1A

USERDATA_1B

UF1

USERDATA_10[7:0]

USERDATA_11[7:0]

USERDATA_12[7:0]

USERDATA_13[7:0]

USERDATA_14[7:0]

USERDATA_15[7:0]

USERDATA_16[7:0]

USERDATA_17[7:0]

USERDATA_18[7:0]

USERDATA_19[7:0]

USERDATA_1A[7:0]

USERDATA_1B[7:0]

USERDATA_1C[7:0]

USERDATA_1D[7:0]

USERDATA_1E[7:0]

USERDATA_1C UF1

USERDATA_1D UF1

USERDATA_1E

CRC_UF1

UF1

F

LOCK_UF1

REGF_BLOCKID[2:0]

CRC_UF1[3:0]

[1] Memory type codes

R — Readable register with no OTP

F — User readable register with OTP

UF2 — One time user programmable OTP location region 2

7.7 Register information

7.7.1 COUNT - rolling counter register (address 00h)

The count register is a read-only register that provides the current value of a free-running

8-bit counter derived from the primary oscillator. A 10-bit prescaler divides the primary

oscillator frequency by 1000. Thus, the value in the register increases by one count every

100 μs and the counter rolls over every 25.6 ms.

Table 33.ꢀCOUNT - rolling counter register (address 00h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

COUNT[7:0]

0

R

7.7.2 Device status registers

The device status registers are read-only registers that contain device status information.

These registers are readable in SPI or I²C mode.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

31 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.2.1 DEVSTAT - device status register (address 01h)

Table 34.ꢀDEVSTAT - device status register (address 01h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

DSP_ERR

reserved

COMM_ MEMTEMP_ SUPPLY_

TEST

DEVRES

DEVINIT

ERR

MODE

Reset

1

reserved

R

0

x

0

1

Access

R

Table 35.ꢀDEVSTAT - device status register (address 01h) bit description

Bit

Symbol

Description

7

DSP_ERR

The DSP error flag is set if a DSP-specific error is present in the pressure signal DSP:

DSP_ERR = DSP_STAT[PABS_HIGH] | DSP_STAT[PABS_LOW] | DSP_STAT[ST_

INCMPLT] | DSP_STAT[CM_ERROR] | DSP_STAT[ST_ERROR]

5

4

COMM_ERR

The communication error flag is set if any bit in DEVSTAT3 is set:

COMM_ERR = MISO_ERR

MEMTEMP_ERR

The memory error flag is set if any bit in DEVSTAT2 is set:

MEMTEMP_ERR = F_OTP_ERR | U_OTP_ERR | U_RW_ERR | U_W_ACTIVE |

TEMP0_ERR

3

2

SUPPLY_ERR

TESTMODE

The supply error flag is set if any bit in DEVSTAT1 is set:

SUPPLY_ERR = VCCUV_ERR | VCCOV_ER | INTREG_ERR | INTREGA_ERR |

INTREGF_ERR

The test mode bit is set if the device is in test mode. The TESTMODE bit can be cleared by

a test mode operation or by a power cycle.

0 — Test mode is not active

1 — Test mode is active

1

0

DEVRES

DEVINIT

The device reset bit is set following a device reset. This error is cleared by a read of the

DEVSTAT register through any communication interface or on a data transmission that

includes the error in the status field.

0 — Normal operation

1 — Device reset occurred

The device initialization bit is set following a device reset. The bit is cleared once sensor data

is valid for read through one of the device communication interfaces (t_{POR_DataValid}).

0 — Normal operation

1 — Device initialization in process

7.7.2.2 DEVSTAT1 - device status register (address 02h)

Table 36.ꢀDEVSTAT1 - device status register (address 02h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

VCCUV_

ERR

reserved

VCCOV_

ERR

reserved

INTREGA_

ERR

INTREG_

ERR

INTREGF_ CONT_ERR

ERR

Reset

x

0

Access

R

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

32 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 37.ꢀDEVSTAT1 - device status register (address 02h) bit description

Bit

Symbol

Description

7

VCCUV_ERR

The V_CCundervoltage error bit is set if the V_CCvoltage falls below the voltage specified in

Table 101. See Section 7.1 for details on the V_CCundervoltage monitor. This bit is cleared

once sensor data is valid for read through one of the device communication interfaces

(t_{POR_DataValid}).

0 — No error detected

1 — V_CCvoltage low

5

VCCOV_ERR

The V_CCovervoltage error bit is set if the V_CCvoltage rises above the voltage specified in

Table 101. See Section 7.1 for details on the V_CCovervoltage monitor. A common timer is

used for all error bits in the DEVSTAT1 register. If any supply error is present, the timer is

reset to t_{UVOV_RCV}. This bit is cleared once sensor data is valid for read through one of the

device communication interfaces (t_{POR_DataValid}).

0 — No error detected

1 — V_CCvoltage high

3

2

1

0

INTREGA_ERR

INTREG_ERR

INTREGF_ERR

CONT_ERR

The internal analog regulator voltage out-of-range error bit is set if the internal analog

regulator voltage falls outside of expected limits. This bit is cleared once sensor data is valid

for read through one of the device communication interfaces (t_{POR_DataValid}).

0 — No error detected

1 — Internal analog regulator voltage out of range

The internal digital regulator voltage out-of-range error bit is set if the internal digital regulator

voltage falls outside of expected limits. This bit is cleared once sensor data is valid for read

through one of the device communication interfaces (t_{POR_DataValid}).

0 — No error detected

1 — Internal digital regulator voltage out of range

The internal OTP regulator voltage out-of-range error bit is set if the internal OTP regulator

voltage falls outside of expected limits. This bit is cleared once sensor data is valid for read

through one of the device communication interfaces (t_{POR_DataValid}).

0 — No error detected

1 — Internal OTP regulator voltage out of range

The continuity monitor passes a low current through a connection around the perimeter of

the device and monitors the continuity of the connection. The error bit is set if a discontinuity

is detected in the connection. A common timer is used for all error bits in the DEVSTAT1

register. If any supply error is present, the timer is reset to t_{UVOV_RCV.}This bit is cleared

based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in

Section 7.7.4.

0 — No error detected

1 — Error detected in the continuity of the edge seal monitor circuit

7.7.2.3 DEVSTAT2 - device status register (address 03h)

Table 38.ꢀDEVSTAT2 - device status register (address 03h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

F_OTP_

ERR

U_OTP_

ERR

U_RW_ERR

U_W_

ACTIVE

reserved

TEMP0_

ERR

reserved

Reset

0

reserved

R

0

reserved

R

reserved

R

Access

R

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

33 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 39.ꢀDEVSTAT2 - device status register (address 03h) bit description

Bit

Symbol

Description

7

F_OTP_ERR

The NXP factory OTP array error bit is set if a fault is detected in the factory OTP array.

This error is cleared by a read of the DEVSTAT2 register through any communication

interface or on a data transmission that includes the error in the status field.

0 — No error detected

1 — Error detected in the NXP factory OTP array

6

5

U_OTP_ERR

U_RW_ERR

The user OTP array error bit is set if a fault is detected in the user OTP array. This error is

cleared by a read of the DEVSTAT2 register through any communication interface or on a

data transmission that includes the error in the status field.

0 — No error detected

1 — Error detected in the user OTP array

When ENDINIT is set, an error detection is enabled for all user writable registers. The

error detection code is continuously calculated on the user writable registers and verified

against a previously calculated error detection code. If a mismatch is detected in the error

detection, the U_RW_ERR bit is set. This error is cleared by a read of the DEVSTAT2

register through any communication interface or on a data transmission that includes the

error in the status field.

0 — No error detected

1 — Error detected in the user read/write array

4

2

U_W_ACTIVE

TEMP0_ERR

The user OTP write in process status bit is set if a user initiated write to OTP is currently

in process. The U_W_ACTIVE bit is automatically cleared once the write to OTP is

complete.

0 — No OTP write in process

1 — OTP write in process

The temperature error bit is set if an overtemperature or undertemperature condition

exists. This error is cleared by a read of the DEVSTAT2 register through any

communication interface or on a data transmission that includes the error in the status

field.

0 — No error detected

1 — Overtemperature or undertemperature error condition detected

7.7.2.4 DEVSTAT3 - device status register (address 04h)

Table 40.ꢀDEVSTAT3 - device status register (address 04h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol MISO_ERR OSCTRAIN_

reserved

ERR

Reset

0

reserved

R

reserved

R

reserved

R

reserved

R

reserved

R

reserved

R

Access

R

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

34 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 41.ꢀDEVSTAT3 - device status register (address 04h) bit description

Bit

Symbol

Description

7

MISO_ERR

In SPI mode, the MISO data mismatch flag is set when a MISO Data mismatch fault

occurs. The MISO_ERROR bit is cleared by a read of the DEVSTAT3 register through any

communication interface, or by a status transmission including the error status through the

SPI.

0 — No error detected

1 — MISO data mismatch

6

OSCTRAIN_ERR

The oscillator training error bit is set if an error detected in either the oscillator training

settings, or the master communication timing. Once the error condition is corrected, the

OSCTRAIN_ERR bit is cleared after a read of the OSCTRAIN_ERR bit through any

communication interface, or by a status transmission including the error status through any

communication interface.

0 — No error detected

1 — Oscillator training error

7.7.3 TEMPERATURE - temperature register (address 0Eh)

The temperature register is a read-only register that provides a temperature value for the

IC. The temperature value is specified in the temperature sensor signal chain section of

Table 101.

Note: The device is only guaranteed to operate within the temperature limits specified in

Section 10 "Static characteristics ".

Table 42.ꢀTEMPERATURE - temperature register (address 0Eh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

TEMP[7:0]

0

R

7.7.4 DEVLOCK_WR - lock register writes register (address 10h)

The lock register writes register is a read/write register that contains the ENDINIT bit and

reset control bits.

Table 43.ꢀDEVLOCK_WR - lock register writes register (address 10h) bit allocation

Bit

7

ENDINIT

0

6

reserved

0

5

reserved

0

4

reserved

0

3

2

reserved

0

1

0

Symbol

Factory default

Access

SUP_ERR_DIS

RESET[1:0]

0

R/W

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

35 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 44.ꢀDEVLOCK_WR - lock register writes register (address 10h) bit description

Bit

Symbol

Description

7

ENDINIT

The ENDINIT bit is a control bit used to indicate that the user has completed all device and

system level initialization tests. Once the ENDINIT bit is set, writes to all writable register bits

are inhibited except for the DEVLOCK_WR register. Once set, the ENDINIT bit can only be

cleared by a device reset.

When ENDINIT is set, the following occurs:

• An error detection is enabled for all user writable registers. The error detection code is

continuously calculated on the user writable registers and verified against a previously

calculated error detection code.

• Self-test is disabled and inhibited.

• Register writes are inhibited with the exception of the RESET[1:0] bits in the DEVLOCK_WR

register.

3

SUP_ERR_DIS

The supply error disable bit allows the user to disable reporting of the supply errors in the SPI

status fields.

1 to 0 RESET[1:0]

To reset the device, three consecutive register write operations must be performed in the

order shown in Table 45, or the device will not reset.

The response to a register write returns the new register value, including the values written

to the RESET[1:0] bits. After the third register write command, the device initiates a reset

and thus does not transmit an acknowledge. The response to a register read returns '00' for

RESET[1:0] and terminates the reset sequence. The reset control bits are not included in the

read/write array error detection.

Table 45.ꢀDevice reset command sequence

Register write to DEVLOCK_WR

Register write 1

RESET[0]

RESET[1]

Effect

0

1

0

1

No effect

Device RESET

Register write 2

Register write 3

7.7.5 UF_REGION_W, UF_REGION_R - UF region selection registers (address

14h, 15h)

The UF region load register is a user read/write register that contains the control bits for

the UF0 and UF1 regions to be accessed. This register is included in the user read/write

array error detection. The UF region active register is a read-only register that contains

the status bits for the UF0 and UF1 regions to be accessed. This register is included in

the user read/write array error detection.

The UF_REGION_W register is readable and writable in SPI mode or I²C mode. The

UF_REGION_R register is readable in SPI mode or I²C mode.

Table 46.ꢀUF_REGION_W - UF region selection register (address 14h) bit allocation

Bit

7

6

5

4

3

2

0

1

0

Symbol

Factory default

Access

REGION_LOAD[3:0]

0

1

0

R/W

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

36 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 47.ꢀUF_REGION_R - UF region selection register (address 15h) bit allocation

Bit

7

6

5

4

3

2

0

1

0

Symbol

Factory default

Access

REGION_ACTIVE[3:0]

0

1

0

R

The user OTP regions UF0, UF1, and F share a block of 16 registers. Prior to reading the

registers via any communication interface, the user must ensure that the desired OTP

registers are loaded into the readable registers. Below is the necessary procedure to

ensure proper reading of the UF0, UF1, and F registers.

1. Write the desired address range to be read to the REGION_LOAD[3:0] bits in the

UF_REGION_W register using one of the communication interfaces available via the

COMMTYPE register.

Table 48.ꢀREGION_LOAD Bit Definitions

REGION_LOAD[3:0]

OTP register addresses loaded into the readable registers

not applicable

0

1

not applicable

0010 through 1001

reserved

1

0

1

0

1

0

1

0

1

0

1

Address Range $A0 through $AF

Address Range $B0 through $BF

Address Range $C0 through $CF

Address Range $D0 through $DF

Address Range $E0 through $EF

Address Range $F0 through $FF

2. Add a delay (Refer to appropriate Application Note for specific communication

protocol for delay values)

3. Optional: Execute a register read of the UF_REGION_R register and confirm the

REGION_ACTIVE[3:0] bits match the values written to the REGION_LOAD[3:0] bits in

the UF_REGION_W register.

Table 49.ꢀREGION_ACTIVE Bit Definitions

REGION_ACTIVE[3:0]

OTP register addresses loaded into the readable registers

0

1

Load of OTP registers is in process

The contents of the shared registers has been over-written by

the user

0010 through 1001

not applicable

1

0

1

0

1

0

1

0

1

0

1

Address Range $A0 through $AF

Address Range $B0 through $BF

Address Range $C0 through $CF

Address Range $D0 through $DF

Address Range $E0 through $EF

Address Range $F0 through $FF

4. Execute a Register Read of the desired registers from the UF0, UF1 or F register

section. Complete all desired Register Reads of the selected UF Region.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

37 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

5. Repeat steps 1 through 4 for the next desired UF region to read.

Notes:

• The user must take care to ensure that the desired registers are addressed. For

example, if the REGION_LOAD bits are set to Ah and the user executes a read of

address $C2, the contents of registers $A2 will be transmitted. No error detection is

included other than a read of the REGION_ACTIVE bits.

• For COMMTYPE options with multiple protocol options (COMMTYPE = '000' or '001'),

no error detection is included other than a read of the REGION_ACTIVE bits. The user

must take care to ensure that the REGION_LOAD bits are not inadvertently changed

by an alternative protocol while executing register reads.

• In SPI and I²C modes, once the ENDINIT bit is set, writes to registers other than the

RESET[1:0] bits are inhibited. For this reason, reads of the UF0, UF1, and F registers

will only be possible for the region selected by the REGION_ACTIVE bits at the time

ENDINIT is set.

7.7.6 COMMTYPE - communication type register (address 16h)

When writing to this register, care must be taken to prevent from inadvertently disabling

the desired communication mode. Communication mode register value changes, that

disable a protocol, including writes to OTP, will not take effect until a device reset occurs

to prevent disabling a necessary communication method.

Table 50.ꢀCOMMTYPE - communication type register (address 16h) bit allocation

Bit

7

reserved

R/W

6

reserved

R/W

5

reserved

R/W

4

reserved

R/W

3

reserved

R/W

2

1

0

Symbol

Access

Reset

COMMTYPE[2:0]

R/W

0

R/W

0

R/W

0

Table 51.ꢀCOMMTYPE - communication type register (address 16h) bit description

Bit

Symbol

Description

2 to 0

COMMTYPE[2:0}

Communication protocol selection

000

001

010

011

100

101

110

111

32-bit SPI (no internal self-test, debug mode)

32-bit SPI (with startup internal self-test)

32-bit SPI (no internal self-test, debug mode)

reserved

32-bit SPI (no internal self-test, debug mode)

reserved

I²C (pin 3 acts as an Interrupt)

I²C (pin 3 acts as an interrupt)

7.7.7 SOURCEID_x - source identification registers (address 1Ah, 1Bh)

The source identification registers are user programmed read/write registers that contain

the source identification information used in SPI Mode. These registers are included in

the read/write array error detection. These registers are readable and writable in SPI

mode or I²C mode.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

38 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 52.ꢀSOURCEID_0 - source identification register (address 1Ah) bit allocation

Bit

7

SID0_EN

0

6

reserved

0

5

reserved

0

4

reserved

0

3

2

1

0

Symbol

Factory default

Access

SOURCEID_0[3:0]

0

R/W

Table 53.ꢀSOURCEID_1 - source identification register (address 1Bh) bit allocation

Bit

7

SID1_EN

0

6

reserved

0

5

reserved

0

4

reserved

0

3

2

1

0

Symbol

Factory default

Access

SOURCEID_1[3:0]

0

R/W

7.7.8 TIMING_CFG - communication timing register (address 22h)

The communication timing configuration register is a user programmed read/write

register that contains user-specific configuration information for protocol timing. This

register is included in the read/write array error detection. This register is readable and

writable in SPI mode or I²C mode.

Table 54.ꢀTIMING_CFG - communication timing register (address 22h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

reserved

OSCTRAIN_

SEL

CK_CAL_

RST

reserved

CK_CAL_EN

Factory default

Access

0

R/W

7.7.9 SPI Configuration Control Register (SPI_CFG, Address 3Dh)

In SPI mode, the SPI configuration control register is a user programmed read/write

register that contains the SPI protocol configuration information. This register is included

in the read/write array error detection. This register is readable and writable in SPI mode

or I²C mode

Table 55.ꢀSPI_CFG Register (address 3Dh) bit allocation

Bit

7

reserved

0

6

DATASIZE

0

5

4

3

2

1

0

Symbol

Factory default

Access

SPI_CRC_LEN[1:0]

SPICRCSEED[3:0]

0

R/W

7.7.9.1 SPI Data Field Size (DATASIZE)

The SPI data field size bit controls the size of the SPI data field as shown in Table 56.

Table 56.ꢀDATASIZE Bit Definition

DATASIZE

SPI Data Field Size

12-Bits

0

1

16-Bits

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

39 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.9.2 SPI CRC Length and Seed Bits

The SPI_CRC_LEN[1:0] bits select the CRC length for SPI Mode as shown in the table

below. The SPI CRC seed bits contain the seed used for the SPI Mode. The default SPI

CRC is an 8-bit. When the SPI_CRC_LEN[1:0] bits are set to a non-zero value using

a Register Write command, the SPI CRC changes as defined in the table. The new

polynomial value is enabled for both MISO and MOSI on the next SPI Mode command.

The default seed (SPICRCSEED[3:0] = 0h) is FFh for an 8-bit CRC. When the value

is changed to a non-zero value using a Register Write command, the SPI CRC seed

changes to the value programmed as shown in the table. The new seed value is enabled

for both MISO and MOSI on the next SPI Mode command.

Table 57.ꢀSPI CRC Definition

SPI_CRC_LEN[1:0]

SPICRCSEED

CRC Polynomial

x⁸+ x⁵+ x³+ x²+ x + 1

x⁴+ 1

CRC Seed

1111, 1111

0

1

0

1

0

1

0

non-zero

0

0000, SPICRCSEED[3:0]

1010

non-zero

0

x⁴+ 1

SPICRCSEED[3:0]

111

x³+ x + 1

non-zero

0

x³+ x + 1

SPICRCSEED[2:0]

111

x³+ x + 1

non-zero

x³+ x + 1

SPICRCSEED[2:0]

7.7.10 WHO_AM_I - who am I register (address 3Eh)

The WHO_AM_I register is a user programmed read/write register that contains the

unique product identifier. This register is included in the read/write array error detection.

Table 58.ꢀWHO_AM_I - device identification register (address 3Eh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

WHO_AM_I[7:0]

Factory default (stored value)

Factory default (read value)

Access

0

1

0

1

0

1

0

R/W

The default register value is 00h. If the register value is 00h, a value of C4h is transmitted

in response to a read command. For all other register values, the actual register value is

transmitted in response to a read command.

Table 59.ꢀWHO_AM_I register values

WHO_AM_I register value (hex)

Response to a register read command

00h

C4h

01h to FFh

Actual register value

7.7.11 I2C_ADDRESS - I²C slave address register (address 3Fh)

The I²C slave address register is a user programmed read/write register that contains the

unique I²C slave address. The register is readable in all modes. This register is included

in the read/write array error detection.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

40 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 60.ꢀI2C_ADDRESS - I²C slave address register (address 3Fh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

I2C_ADDRESS[7:0]

Factory Default (stored value)

Factory Default (read value)

Access

0

1

0

1

0

R/W

The default register value is 00h. If the register value is 00h, the I²C slave address is

60h and a value of 60h is transmitted in response to a read command. If the register is

written to a value other than 00h, the I²C slave address is the lower seven bits of the

actual register value and the actual register value is transmitted in response to a read

command.

7.7.12 DSP Configuration Registers (DSP_CFG_Ux)

The DSP Configuration registers (DSP_CFG_Ux) are a series of registers that affect the

DSP data path.

There are 5 DSP Configuration registers, however, only DSP_CFG_U1, DSP_CFG_U4

and DSP_CFG_U5 are used when the device is in SPI or I²C mode. The DSP_CFG_U2

and DSP_CFG_U3 registers are for factory use only and are used for internal tests.

7.7.12.1 Self-test control bits

The self-test control bits select one of the various analog and digital self-test features of

the device as shown in the table below. The self-test control bits are not included in the

read/write array error detection.

Table 61.ꢀSelf-Test Control Bits (ST_CTRL[3:0])

ST_

Function

SNS_DATAx_X Contents (16-bit data)

CTRL[3]

CTRL[2]

CTRL[1]

CTRL[0]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal Pressure Signal

16-bit Absolute Pressure Data

reserved

P-Cell Common Mode Verification

reserved

DSP write to SNS_DATAx_X registers inhibited.

reserved

0000h

AAAAh

5555h

FFFFh

reserved

Digital Self-Test 0

Digital Self-Test Output

Digital Self-Test 1

Digital Self-Test 2

Digital Self-Test 3

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

41 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.12.2 DSP_CFG_U1 - DSP user configuration #1 register (address 40h)

The DSP user configuration register #1 is a user programmable read/write register that

contains DSP-specific configuration information. This register is included in the read/write

array error detection.

Changes to this register reset the DSP data path. The contents of the SNSDATA_x

registers are not guaranteed until the DSP has completed initialization as specified in

Table 102. Reads of the SNSDATA_x registers and sensor data requests should be

prevented during this time.

Table 62.ꢀDSP_CFG_U1 - DSP user configuration #1 register (address 40h) bit allocation

Bit

7

6

5

4

3

reserved

0

2

reserved

0

1

0

Symbol

Factory default

Access

LPF[3:0]

USER_RANGE[1]

USER_RANGE[0]

0

R/W

Table 63.ꢀLow-pass filter selection bits (LPF[3:0])

LPF[3]

LPF[2]

LPF[1]

LPF[0]

Low Pass Filter Type

0

1

0

1

0

x

0

1

0

1

0

x

0

1

0

1

0

1

0

x

370 Hz, 2-Pole

400 Hz, 3 Pole

800 Hz, 4-Pole

1000 Hz, 4-Pole

reserved

Table 64.ꢀUser range selection bits (USER_RANGE[1:0])

USER_RANGE[1]

USER_RANGE[0]

Absolute Pressure Range

Notes

0

1

0

1

0

1

reserved

For Internal use Only

7.7.12.3 DSP_CFG_U4 - DSP user configuration #4 register (address 43h)

The DSP user configuration register #4 is a user programmable read/write register that

contains DSP-specific configuration information. This register is included in the read/write

array error detection.

Table 65.ꢀDSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit allocation

Bit

7

reserved

0

6

reserved

0

5

reserved

0

4

reserved

0

3

reserved

0

2

INT_OUT

0

1

reserved

0

reserved

0

Symbol

Reset

Access

R/W

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

42 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 66.ꢀDSP_CFG_U4 - DSP user configuration #4 register (address 43h) bit description

Bit

7 to 4

2

Symbol

reserved

INT_OUT

Description

These bits are reserved.

The interrupt pin configuration bit selects the mode of operation for the interrupt pin.

0 — Open drain, active high with pull-down current

1 — Open drain, active low with pullup current

1 to 0

reserved

These bits are reserved.

7.7.12.4 DSP_CFG_U5 - DSP user configuration #5 register (address 44h)

The DSP user configuration register #5 is a read/write register that contains DSP-specific

configuration information. This register is included in the read/write array error detection.

Table 67.ꢀDSP_CFG_U5 - DSP user configuration #5 register (address 44h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Factory default

Access

ST_CTRL[3:0]

reserved

0

R/W

Table 68.ꢀDSP_CFG_U5 - DSP user configuration #5 register (address 44h) bit description

Bit

Symbol

Description

7 to 4

ST_CTRL[3:0]

The self-test control bits select one of the various analog and digital self-test features of the device as shown in

Table 69. The self-test control bits are not included in the read/write array error detection.

3 to 0

reserved

These bits are reserved.

Table 69.ꢀSelf-test control bits

ST_CTRL[3] ST_CTRL[2] ST_CTRL[1] ST_CTRL[0] Function

SNS_DATAx_X contents

16-bit data

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Normal pressure signal

P-cell common mode verification

reserved

DSP write to SNS_DATAx_X registers inhibited. 0000h

DSP write to SNS_DATAx_X registers inhibited. AAAAh

DSP write to SNS_DATAx_X registers inhibited. 5555h

DSP write to SNS_DATAx_X registers inhibited. FFFFh

reserved

8171h

reserved

Digital self-test 0

Digital self-test 1

Digital self-test 2

Digital self-test 3

6C95h

807Ah

78ACh

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

43 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.13 INT_CFG - interrupt configuration register (address 45h)

The interrupt configuration register contains configuration information for the interrupt

output. This register can be written during initialization but is locked once the ENDINIT bit

is set (see Section 7.7.4 "DEVLOCK_WR - lock register writes register (address 10h)").

The register is included in the read/write array error detection.

Table 70.ꢀINT_CFG - interrupt configuration register (address 45h) bit allocation

Bit

7

6

5

4

3

2

1

reserved

0

Symbol

Reset

Access

reserved

INT_PS[1:0]

INT_POLARITY

0

R/W

Table 71.ꢀINT_CFG - interrupt configuration register (address 45h) bit description

Bit

Symbol

Description

5 to 4

INT_PS[1:0]

The INT_PS[1:0] bits set the programmable pulse stretch time for the interrupt output. Pulse stretch times are derived

from the internal oscillator, so the tolerance on this oscillator applies.

00 — 0 ms

01 —16.000 ms to 16.512 ms

10 — 64.000 ms to 64.512 ms

11 — 256.000 ms to 256.512 ms

If the pulse stretch function is programmed to '00', the interrupt pin is asserted if and only if the interrupt condition exists

after the most recent evaluated sample. The interrupt pin is deasserted if and only if an interrupt condition does not

exist after the most recent evaluated sample.

If the pulse stretch function is programmed to a non-zero value, the interrupt pin is controlled only by the value of the

pulse stretch timer value. If the pulse stretch timer value is non-zero, the interrupt pin is asserted. If the pulse stretch

timer is zero, the interrupt pin is deasserted. The pulse stretch counter continuously decrements until it reaches zero.

The pulse stretch counter is reset to the programmed pulse stretch value if and only if an interrupt condition exists after

the most recent evaluated sample.

3

INT_POLARITY

The interrupt polarity bit controls whether the interrupt is activated for values within or outside of the window selected

by the high and low threshold registers. With this bit and the programmable thresholds, a window comparator can be

programmed for activation either within or outside of a window.

0 — Interrupt activated, if the value is outside the window

1 — Interrupt activated, if the value is inside the window

7.7.14 P_INT_HI, P_INT_LO - interrupt window comparator threshold registers

(address 46h to 49h)

The interrupt threshold registers contain the high and low window comparator thresholds

for pressure to be used to activate and deactivate the interrupt output. These registers

can be written during initialization but are locked once the ENDINIT bit is set (see

Section 7.7.4 "DEVLOCK_WR - lock register writes register (address 10h)"). The register

is included in the read/write array error detection.

Table 72.ꢀP_INT_HI, P_INT_LO - interrupt window comparator threshold registers (address 46h to 49h) bit allocation

Location

Address

46h

Bit

Register

8

7

6

5

4

3

2

1

0

PIN_INT_HI_L

PIN_INT_HI_H

PIN_INT_LO_L

PIN_INT_LO_H

PIN_INT_HI[7:0]

PIN_INT_HI[15:8]

PIN_INT_LO[7:0]

PIN_INT_LO[15:8]

0

47h

48h

49h

Reset

Access

0

R/W

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

44 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

The pressure threshold registers hold independent unsigned 16-bit values for a high and

a low threshold. The window comparator threshold alignment is shown in Section 7.3.4.4

"Absolute pressure output data scaling equation".

If either the high or low threshold is programmed to 0000h, comparisons are disabled for

that threshold only. The interrupt comparison still functions for the opposite threshold.

If both the high and low thresholds are programmed to 0000h, the interrupt output is

disabled.

7.7.15 P_CAL_ZERO - pressure calibration registers (address 4Ch, 4Dh)

The pressure calibration registers contain user programmable values to adjust the offset

of the absolute pressure.

These registers can be written during initialization but are locked once the ENDINIT bit

is set (see Section 7.7.4 "DEVLOCK_WR - lock register writes register (address 10h)").

These registers are included in the read/write array error detection. Changes to these

registers reset the DSP data path. The contents of the SNSDATA_x registers are not

guaranteed until the DSP has completed initialization, as specified in Table 102. Reads

of the SNSDATA_x registers and sensor data requests should be prevented during this

time.

Table 73.ꢀP_CAL_ZERO - pressure calibration registers (address 4Ch, 4Dh) bit allocation

Location

Address

4Ch

Bit

Register

7

6

5

4

3

2

1

0

P_CAL_ZERO_L

P_CAL_ZERO_H

P_CAL_ZERO[7:0]

P_CAL_ZERO[15:8]

4Dh

Reset

0

Access

R/W

The P_CAL_ZERO register value is a signed 16-bit value that is directly added to the

internally calibrated pressure signal value as shown in Equation 6. The equation applies

to the values in the 16-bit SNSDATA registers.

(6)

Where:

PABS_kPa= The absolute pressure output in kPa

PABS_LSB= The internal trimmed absolute pressure output in LSB

PABSOFF_LSB= The internal trimmed absolute pressure output value at 0 kPa in LSB

PABS_SENSE= The trimmed absolute pressure sensitivity in LSB/kPa

UserOffset = The 16-bit signed value programmed into the P_CAL_ZERO register

Note: The pressure calibration registers enable range and resolution options beyond the

specified values of the device. The user must take care to ensure that the value stored in

this register does not result in a compressed output range or a railed output.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

45 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.16 DSP_STAT - DSP-specific status register (address 60h)

The DSP status register is a read-only register that contains sensor data-specific status

information.

Table 74.ꢀDSP_STAT - DSP-specific status register (address 60h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Factory default

Access

reserved

PABS_HIGH

PABS_LOW

reserved

ST_INCMPLT

ST_ACTIVE

CM_ERROR

ST_ERROR

0

1

0

R

Table 75.ꢀDSP_STAT - DSP-specific status register (address 60h) bit description

Bit

Symbol

Description

6

PABS_HIGH

The absolute pressure out-of-range high status bit is set if the absolute pressure exceeds the absolute pressure out-

of-range high limit. The PABS_HIGH bit is cleared on a read of the DSP_STAT register through any communication

interface or on a data transmission that includes the error in the status field.

5

3

PABS_LOW

The absolute pressure out-of-range low status bit is set if the absolute pressure exceeds the absolute pressure out-

of-range low limit. The PABS_LOW bit is cleared on a read of the DSP_STAT register through any communication

interface or on a data transmission that includes the error in the status field.

ST_INCMPLT

The self-test incomplete bit is set after a device reset and is only cleared when one of the analog or digital self-test

modes is enabled in the ST_CTRL register (ST_CTRL[3] = '1' | ST_CTRL[2] = '1' | | ST_CTRL[1] =

'1' | | ST_CTRL[0] = '1').

0 — An analog or digital self-test has been activated since the last reset.

1 — No analog or digital self-test has been activated since the last reset.

2

ST_ACTIVE

The self-test active bit is set if any self-test mode is currently active. The self-test active bit is cleared when no self-test

mode is active.

ST_ACTIVE= ST_CTRL[3] | ST_CTRL[2] | ST_CTRL[1] | ST_CTRL[0]

1

0

CM_ERROR

ST_ERROR

The absolute pressure common mode error status bit is set if the common mode value of the analog front end exceeds

predetermined limits. The CM_ERROR bit is cleared on a read of the DSP_STAT register through any communication

interface or on a data transmission that includes the error in the status field.

The self-test error flag is set if an internal self-test fails as described in Section 7.3.2. This bit can only be cleared by a

device reset.

7.7.17 DEVSTAT_COPY - device status copy register (address 61h)

The device status copy register is a read-only register that contains a copy of the device

status information contained in the DEVSTAT register. See Section 7.7.2.1 "DEVSTAT

- device status register (address 01h)" for details regarding the DEVSTAT register

contents. A read of the DEVSTAT_COPY register has the same effect as a read of the

DEVSTAT register.

Table 76.ꢀDEVSTAT_COPY - device status copy register (address 61h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

DSP_ERR

reserved

COMM_ERR

MEMTEMP_ERR SUPPLY_ERR

TESTMODE

DEVRES

DEVINIT

0

R

7.7.18 SNSDATA0_L, SNSDATA0_H - sensor data #0 registers (address 62h, 63h)

The sensor data #0 registers are read-only registers that contain the 16-bit sensor

data. See Section 7.3.4.4 "Absolute pressure output data scaling equation" for details

regarding the 16-bit sensor data.

The SNSDATA0_H register value is latched on a read of the SNSDATA0_L register

value until the SNSDATA0_H register is read. To avoid data mismatch, the user is

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

46 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

required to always read the registers in sequence, SNSDATA0_L register first, followed

by the SNSDATA0_H register.

Table 77.ꢀSNSDATA0_L, SNSDATA0_H - sensor data #0 registers (addresses 62h, 63h) bit allocation

Location

Address

62h

Bit

Symbol

7

6

5

4

3

2

1

0

SNSDATA0_L

SNSDATA0_H

SNSDATA0_L[7:0]

SNSDATA0_H[15:8]

63h

Factory default

Access

0

R

7.7.19 SNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h)

The sensor data #1 registers are read-only registers that contain the 16-bit sensor

data. See Section 7.3.4.4 "Absolute pressure output data scaling equation" for details

regarding the 16-bit sensor data.

The SNSDATA1_H register value is latched on a read of the SNSDATA1_L register

value until the SNSDATA1_H register is read. To avoid data mismatch, the user is

required to always read the registers in sequence, SNSDATA1_L register first, followed

by the SNSDATA1_H register.

Table 78.ꢀSNSDATA1_L, SNSDATA1_H - sensor data #1 registers (address 64h, 65h) bit allocation

Location

Address

64h

Bit

Symbol

7

6

5

4

3

2

1

0

SNSDATA1_L

SNSDATA1_H

SNSDATA1_L[7:0]

SNSDATA1_H[15:8]

65h

Factory default

Access

0

R

7.7.20 SNSDATA0_TIMEx - time stamp registers (address 66h to 6Bh)

The sensor data 0 time stamp registers are read-only registers that contain a 48-bit time

stamp.

The value of the 48-bit free running timer register is copied to the sensor data 0 time

stamp registers each time sensor data 0 data is latched for transmission. The time stamp

is updated at the start of the sensor data 0 register value transmission for a register read

of the SNSDATA0_L register.

The time stamp register is organized to allow for optimized reading of the time stamp in

I²C automatic sensor data register read wrap-around mode as documented in Table 8.

The sensor data 0 time stamp registers are read-only registers that contain a 48-bit time

stamp.

The value of the 48-bit free running timer register is copied to the sensor data 0 time

stamp registers each time sensor data 0 data is latched for transmission via SPI.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

47 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 79.ꢀSNSDATA0_TIMEx - time stamp register (address 66h to 6Bh) bit allocation

Location

Address

66h

Bit

Symbol

7

6

5

4

3

2

1

0

SNSDATA0_TIME0

SNSDATA0_TIME1

SNSDATA0_TIME2

SNSDATA0_TIME3

SNSDATA0_TIME4

SNSDATA0_TIME5

SNSDATA0_TIME[7:0]

SNSDATA0_TIME[15:8]

SNSDATA0_TIME[23:16]

SNSDATA0_TIME[31:24]

SNSDATA0_TIME[39:32]

SNSDATA0_TIME[47:40]

67h

68h

69h

6Ah

6Bh

Factory default

Access

0

R

7.7.21 P_MAX, P_MIN - maximum and minimum absolute pressure value registers

(address 6Ch to 6Fh)

The minimum and maximum absolute pressure value registers are read-only registers

that contain a sample-by-sample continuously updated minimum and maximum 16-

bit absolute pressure value. The value is reset to 0000h on a write to a DSP_CFG_U1

register that changes the value of the LPF[2:0] or ST_CTRL[3:0].

These registers are readable in SPI mode or I²C mode. In I²C mode the P_xxx_H

register value is latched on a read of the P_xxx_L register value until the P_xxx_H

register is read. To avoid data mismatch, the user is required to always read the registers

in sequence, P_xxx_L register first, followed by the P_xxx_H register.

Table 80.ꢀP_Max and P_Min registers (address 6Ch to 6Fh) bit allocation

Location

Bit

Address

6Ch

Symbol

7

6

5

4

3

2

1

0

P_MAX_L

P_MAX_H

P_MIN_L

P_MIN_H

P_MAX[7:0]

6Dh

P_MAX[15:8]

P_MIN[7:0]

P_MIN[15:8]

6Eh

6Fh

Factory default

Access

0

R

7.7.22 FRT - free running timer registers (addresses 78h to 7Dh)

The free running timer registers are read-only registers that contain a 48-bit free running

timer. The free running timer is clocked by the main oscillator frequency and increments

every 100 ns.

Table 81.ꢀFRT - free running timer registers (addresses 78h to 7Dh) bit allocation

Location

Address

78h

Bit

Symbol

FRT0

FRT1

FRT2

FRT3

FRT4

FRT5

7

6

5

4

3

2

1

0

FRT[7:0]

FRT[15:8]

FRT[23:16]

FRT[31:24]

FRT[39:32]

FRT[47:40]

79h

7Ah

7Bh

7Ch

7Dh

Access

R

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

48 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.23 DSP_CFG_F Register

The DSP configuration register is a factory programmable OTP register that contains

DSP-specific configuration information. This register is included in the factory

programmed OTP array error detection. This register is readable in SPI mode or I²C

mode when ENDINIT is not set.

Table 82.ꢀRange Indication Bits (RANGE[3:0])

RANGE[3]

RANGE[2]

RANGE[1]

RANGE[0]

Absolute Pressure Range (kPa)

Rated Pressure Range

reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

reserved

7.7.24 IC type register (Address C0h)

The IC type register is a factory programmable OTP register that contains the IC type

as defined below. This register is included in the factory programmed OTP array error

detection. This register is readable in SPI mode or I²C mode when ENDINIT is not set.

Table 83.ꢀIC TYPE REGISTER (ICTYPEID address C0h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ICTYPEID[7:0]

0

1

0

R

7.7.25 IC manufacturer revision register (Address C1h)

The IC manufacturer revision register is a factory programmable OTP register that

contains the IC revision. The upper nibble contains the main IC revision. The lower nibble

contains the sub IC revision. This register is included in the factory programmed OTP

array error detection. This register is readable in SPI mode or I²C mode when ENDINIT is

not set.

Table 84.ꢀIC MANUFACTURER REVISION REGISTER (ICREVID address C1h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ICREVID[7:0]

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

49 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.26 IC manufacturer identification register (address C2h)

The IC manufacturer identification register is a factory programmable OTP register

that identifies NXP as the IC manufacturer. This register is included in the factory

programmed OTP array error detection. This register is readable in SPI mode or I²C

mode when ENDINIT is not set.

Table 85.ꢀIC MANUFACTURER IDENTIFICATION REGISTER (ICMFGID address C2h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ICMFGID[7:0]

0

1

0

R

7.7.27 Part number register (address C4h, C5h)

The part number registers are factory programmed OTP registers that include the

numeric portion of the device part number. These registers are included in the factory

programmed OTP array error detection. These registers are readable in SPI mode or I²C

mode when ENDINIT is not set.

Table 86.ꢀPN0 Register (address C4h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

PN0[7:0]

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

Table 87.ꢀPN1 Register (address C5h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

PN1[7:0]

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

7.7.28 Device serial number registers

The serial number registers are factory programmed OTP registers that include the

unique serial number of the device. Serial numbers begin at 1 for all produced devices

in each lot and are sequentially assigned. Lot numbers begin at 1 and are sequentially

assigned. No lot will contain more devices than can be uniquely identified by the 14-bit

serial number. Depending on lot size and quantities, all possible lot numbers and serial

numbers might not be assigned. These registers are included in the factory programmed

OTP array error detection. These registers are readable in SPI mode or I²C mode when

ENDINIT is not set.

Table 88.ꢀSN0 Register (address C6h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

SN[7:0]

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

50 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 89.ꢀSN1 Register (address C7h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

SN[7:0]

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

Table 90.ꢀSN2 Register (address C8h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

Table 91.ꢀSN3 Register (address C9h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

Table 92.ꢀSN4 Register (address CAh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

7.7.29 ASIC wafer ID registers

The ASIC wafer ID registers are factory programmed OTP registers that include the

wafer number, wafer X and Y coordinates and the wafer lot number for the device ASIC.

These registers are included in the factory programmed OTP array error detection. These

registers are readable in SPI mode or I²C mode when ENDINIT is not set.

Table 93.ꢀASICWFR# Register (address CBh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ASICWFR#[7:0]

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

Table 94.ꢀASICWFR_X Register (address CCh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ASICWFR_X[7:0]

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

51 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 95.ꢀASICWFR_Y Register (address CDh) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ASICWFR_Y[7:0]

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

Table 96.ꢀASICWLOT_L Register (address D0h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ASICWLOT_L[7:0]

N/A N/A

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

Table 97.ꢀASICWLOT_H Register (address D1h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

ASICWLOT_H[7:0]

N/A N/A

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

N/A

R

7.7.30 USERDATA_0 to USERDATA_E - user data registers

User data registers are user programmable OTP registers that contain user-specific

information. These registers are included in the user programmed OTP array error

detection. These registers are readable and writable in SPI mode or I²C mode when

ENDINIT is not set.

7.7.31 USERDATA_10 to USERDATA_1E - user data registers

User data registers are user programmable OTP registers that contain user-specific

information. These registers are included in the user programmed OTP array error

detection. These registers are readable and writable in SPI mode or I²C mode when

ENDINIT is not set.

7.7.32 Lock and CRC Registers

The lock and CRC Registers are automatically programmed OTP registers that include

the lock bit, the block identifier, and the block OTP array CRC use for error detection.

These registers are automatically programmed when the corresponding data array is

programmed to OTP using the Write OTP Enable register.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

52 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Table 98.ꢀLock and CRC Register bit definitions

Location

Bit

Address

$5F

Register

7

6

0

5

4

0

3

2

1

0

CRC_UF2

LOCK_UF2

0

CRC_UF2[3:0]

Factory Default

$AF

0

CRC_F_A

CRC_F_B

CRC_F_C

CRC_F_D

CRC_F_E

CRC_F_F

LOCK_F_A

REGA_BLOCKID[2:0]

CRC_F_A[3:0]

varies

Factory Default

$BF

1

0

1

0

1

0

1

0

LOCK_F_B

REGB_BLOCKID[2:0]

CRC_F_B[3:0]

varies

Factory Default

$CF

1

LOCK_F_C

REGC_BLOCKID[2:0]

CRC_F_C[3:0]

varies

Factory Default

$DF

1

LOCK_F_D

REGD_BLOCKID[2:0]

CRC_F_D[3:0]

varies

Factory Default

$EF

1

0

LOCK_F_E

REGE_BLOCKID[2:0]

CRC_F_E[3:0]

Factory Default

$FF

0

LOCK_F_F

0

REGF_BLOCKID[2:0]

0

CRC_F_F[3:0]

Factory Default

7.7.33 Reserved registers

A register read command to a reserved register or a register with reserved bits results in

a valid response. The data for reserved bits may be '0' or '1'.

A register write command to a reserved register or a register with reserved bits executes

and results in a valid response. The data for the reserved bits may be '0' or '1'. A write to

the reserved bits must always be '0' for normal device operation and performance.

7.7.34 Invalid register addresses

A register read command to a register address outside of the addresses listed in

Section 7.6 "User-accessible data array" results in a valid response. The data for the

registers will be '00h'.

A register write command to a register address outside of the addresses listed in

Section 7.6 "User-accessible data array" will not execute, but results in a valid response.

The data for the registers will be '00h'.

A register write command to a read-only register will not execute, but results in a valid

response. The data for the registers is the current content of the registers.

7.8 Read/write register array CRC verification

The writable registers (all registers with the exception of the DEVLOCK_WR register) are

verified by a continuous 4-bit CRC that is calculated on the entire array once ENDINIT is

set. The CRC verification uses a generator polynomial of g(x) = X⁴+ X³+ 1, with a seed

value = '0000'.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

53 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

8 Maximum ratings

Absolute maximum ratings are the limits the device can be exposed to without

permanently damaging it. Absolute maximum ratings are stress ratings only; functional

operation at these ratings is not guaranteed. Exposure to absolute maximum ratings

conditions for extended periods might affect device reliability.

This device contains circuitry to protect against damage due to high static voltage or

electrical fields. NXP advises that normal precautions be taken to avoid application of any

voltages higher than maximum-rated voltages to this high-impedance circuit.

Table 99.ꢀMaximum ratings

Symbol

VCC_MAX

h_DROP

Parameter

Conditions

Min

—

Max

+6.0

1.2

Unit

V

[1]

[2]

Supply Voltage

Drop shock

V_CC, V_CCIO

To concrete, tile or steel surface, 10 drops,

any orientation

—

m

[2]

[2] [3]

[1]

T_stg

Temperature range

Storage

–40

—

+130

+150

150

345

40

°C

T_J

Junction

°C

P_MAX

P_BURST

P_MIN

f_SEAL

θ_JA

Maximum absolute pressure

Continuous (tested at 10 s)

Burst (tested at 100 ms)

Continuous

kPa

N

[1]

—

[1]

Minimum absolute pressure

Pressure sealing force

Thermal resistance

—

[1]

Applied to top face of package

—

10

[4]

—

120

°C/W

ESD and latch-up protection characteristics

[2]

V_ESD

Electrostatic discharge (per

AEC-Q100, Rev H)

Human body model (HBM)

Charge device model (CDM)

–2000

–500

2000

500

V

[2] [5]

[1] Parameter verified by parametric and functional validation.

[2] Parameter verified by qualification testing (Per AEC-Q100 Rev H or per NXP specification).

[3] Functionality verified by modeling, simulation and/or design verification.

[4] Thermal resistance provided with device mounted to a two-layer, 1.6 mm FR-4 PCB as documented in AN1902 with one signal layer and one ground

layer.

[5] CDM tested at ±750 V for corner pins and ±500 V for all other pins.

Caution

This device is sensitive to mechanical shock. Improper handling can cause permanent damage to the part.

Caution

This is an ESD sensitive device. Improper handling can cause permanent damage to the part.

msc896

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

54 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

9 Operating range

Table 100.ꢀElectrical characteristics — supply and I/O

V_{CC_min}≤ (V_CC- V_SS) ≤ V_{CC_max}, T_L≤ T_A≤ T_H, ΔT ≤ 25 °C/min, unless otherwise specified.

Symbol

V_CC

Parameter

Conditions

Min

Max

Units

[1]

Supply voltage

Measured at V_CC

3.10

5.25

V

T_A

Operating temperature range V_CC= 5.0 V, unless otherwise stated.

T_L

T_H

Production tested operating temperature

range

–40

+130

°C

[1]

[2]

T_A

Guaranteed operating temperature range

Supply power on ramp rate

–40

+130

10

°C

V_{CC_RAMP_SPI}

0.00001

V/μs

[1] Parameter tested 100 % at final test.

[2] Parameter verified by parametric and functional validation.

10 Static characteristics

Table 101.ꢀStatic characteristics

V_{CC_min}≤ (V_CC- V_SS) ≤ V_{CC_max}, T_L≤ T_A≤ T_H, ΔT ≤ 25 °C/min, unless otherwise specified.

Symbol

Supply and I/O

I_IH

Parameter

Condition

Min

Typ

Max

Units

[1]

[2]

[1]

[3]

[1]

Input current high

At V_IH; SCLK/SCL

At V_IL; SS_B

10

20

–20

—

70

μA

mA

V

I_IL

Input current low

–70

–5

–10

5

I_{MISO_Lkg}

I_q

MISO output leakage

Quiescent supply current

Low-voltage detection threshold

Input voltage hysteresis

Input high voltage (at V_CC= 3.3 V

Input low voltage

V_CC= 5.0 V

—

8.0

2.84

0.500

—

V_{CC_UV_F}

V_{I_HYST}

V_IH

V_CCfalling

2.64

0.125

2.0

—

2.74

—

SCLK/SCL, SS_B, MOSI

I _Load= –100 μA

V

—

V

V_IL

—

1.0

V_CC

0.1

—

V

V_{INT_OH}

V_{INT_OL}

V_OH

Output high voltage

V_CC– 0.35

—

V

Output low voltage

I _Load= 100 μA

V

Output high voltage

MISO/SDA,

V_CC– 0.2

V

I _Load= –1 mA

Temperature sensor signal chain

T_RANGETemperature measurement range

T₂₅

[3]

–50

83

0

—

93

—

+160

103

°C

Temperature output

At 25 °C

LSB

T_RANGE

Range of output

(8-bit)

Unsigned temperature

255

[4]

T_SENSE

T_ACC

Temperature output sensitivity (8-bit)

Temperature output accuracy (8-bit)

—

1.00

—

LSB/°C

°C

–10

—

+10

+2

T_RMS

Temperature output noise RMS (8-bit) Standard deviation of 50

readings,

—

LSB

f_Samp= 8 kHz

Absolute pressure sensor signal chain

[2]

[5]

P_ABS

Absolute pressure range

Absolute pressure output sensitivity

40

—

115

—

kPa

P_SENS

P_CAL_ZERO = 0h

46.64

LSB/k

Pa

Temperature = –40 °C and

130 °C, V_CC= 5.0 V.

12-bit at 0 Hz, tested at

P_ABS= 100 kPa ± 10 %

and 110 kPa ± 10 %

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

55 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Symbol

Parameter

Condition

Min

Typ

Max

Units

[5] [7]

P_{ACC_LoT1}

Absolute pressure accuracy^[6]

V_CC= 5.0 V

–2.0

—

+2.0

kPa

–40 °C ≤ T_A< –20 °C

P_{ACC_LoT2}

P_{ACC_Typ}

P_{ACC_HiT}

Absolute pressure accuracy^[6]

V_CC= 5.0 V

–1.75

–1.25

–2.0

—

+1.75

+1.25

+2.0

kPa

–20 °C ≤ T_A< 0 °C

V_CC= 5.0 V

0 °C ≤ T_A≤ 85 °C

V_CC= 5.0 V

85 °C < T_A≤ 130 °C

[2]

[3]

P_{ABS_DErr}

P_{ABS_DRng}

PABS_DNL

Absolute pressure output range

Absolute pressure nonlinearity

Digital error response

Digital, 12-bit

—

1

0

—

LSB

—

0

4095

—

Digital error response

—

Absolute pressure DNL,

12-bit monotonic with no

missing codes

—

+1

[3]

[1]

PABS_INL

Absolute pressure nonlinearity

Absolute pressure INL, 12-

bit (least squares BFSL)

—

+20

+8

LSB

PABS_Peak

Absolute pressure noise peak (12-bit)

Temperature = –40 °C and

130 °C, V_CC= 5.0 V.

–8

Maximum deviation from

mean, 50 readings, f_Samp

= 8 kHz, LPF = 800 Hz, 4-

pole

[5]

PABS_RMS

Absolute pressure noise RMS (12-bit)

Absolute pressure offset

Temperature = –40 °C and

130 °C, V_CC= 5.0 V.

—

+2

—

LSB

Standard deviation of 50

readings, f_Samp= 8 kHz,

LPF = 800 Hz, 4-pole

P_{OFF_D12}

At minimum rated

pressure, P_CAL_ZERO =

0h,

299

Temperature = –40 °C and

130 °C, V_CC= 5.0 V,

12-bit

[3]

PSC₃PSC_SPI3

PSC₅PSC_SPI5

Digital power supply coupling

C_VCC= 0.1 μf, 12-bit data

—

2

LSB

1 kHz ≤ f_n≤ 100 MHz, V_CC

= 3.3 V ± 0.1 V

C_VCC= 0.1 μf, 12-bit data

1 kHz ≤ f_n≤ 100 MHz, V_CC

= 5.0 V ± 0.1 V

[1] Parameter verified by pass/fail testing at final test.

[2] Functionality verified by modeling, simulation and/or design verification.

[3] Parameter verified by parametric and functional validation.

[4] Parameter verified by characterization.

[5] Parameter tested at final test.

[6] See Section 13 for accuracy over temperature and life, including nonlinearity, full scale = P_ABSrange.

[7] Parameter does not include lifetime drift. For complete pressure drift over temperature and life, review Section 13.

11 Dynamic characteristics

Table 102.ꢀDynamic characteristics

V_{CC_min}≤ (V_CC– V_SS) ≤ V_{CC_max}, T_L≤ T_A≤ T_H, ΔT ≤ 25 °C/min, unless otherwise specified.

Symbol

Parameter

Condition

Min

Typ

Max

Units

I²C

[1]

t_{SCL_100}

Clock (SCL) period

100 kHz mode

400 kHz mode

1000 kHz mode

—

9.50

2.37

1.00

—

μs

t_{SCLK_400}

t_{SCLK_1000}

(30 % of V_CCto 30 % of V_CC)

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

56 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Symbol

Parameter

Condition

Min

Typ

Max

Units

[1]

t_{SCLH_100}

t_{SCLH_400}

t_{SCLH_1000}

Clock (SCL) high time

100 kHz mode

400 kHz mode

—

4.00

0.60

0.50

—

μs

(70 % of V_CCto 70 % of V_CC

)

1000 kHz mode (not

compliant with UM10204,

rev.6)

[1]

t_{SCLL_100}

t_{SCLL_400}

t_{SCLL_1000}

Clock (SCL) low time

100 kHz mode

400 kHz mode

1000 kHz mode

—

4.70

1.30

0.50

—

μs

(30 % of V_CCto 30 % of V_CC

)

[1]

t_{SRISE_100}

t_{SRISE_400}

t_{SRISE_1000}

Clock (SCL) and data (SDA) rise time

(30 % of V_CCto 70 % of V_CC

100 kHz mode

400 kHz mode

1000 kHz mode

—

1000

300

ns

)

120

[1]

t_{SFALL_100}

t_{SFALL_400}

t_{SFALL_1000}

Clock (SCL) and data (SDA) fall time

—

300

120

ns

100 kHz mode

400 kHz mode

1000 kHz mode

(70 % of V_CCto 30 % of V_CC

)

[1]

t_{SETUP_100}

t_{SETUP_400}

t_{SETUP_1000}

Data input setup time

100 kHz mode

—

250

100

50

—

ns

(SDA = 30/70 % of V_CCto SCL = 30 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{HOLD_100}

t_{HOLD_400}

t_{HOLD_1000}

Data input hold time

100 kHz mode

—

0

900

300

ns

(SCL = 70 % of V_CCto SDA = 30/70 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{STARTSETUP_100}

t_{STARTSETUP_400}

t_{STARTSETUP_1000}

Start condition setup time

100 kHz mode

—

4.70

0.60

0.26

—

μs

(SDA = 30/70 % of V_CCto SCL = 30 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{STARTHOLD_100}

t_{STARTHOLD_400}

t_{STARTHOLD_1000}

Start condition hold time

100 kHz mode

—

4.00

0.60

0.26

—

μs

(SCL = 70 % of V_CCto SDA = 30/70 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{STOPSETUP_100}

t_{STOPSETUP_400}

t_{STOPSETUP_1000}

Stop condition setup time

100 kHz mode

—

4.00

0.60

0.26

—

μs

(SDA = 30/70 % of V_CCto SCL = 30 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{VALID_100}

t_{VALID_400}

t_{VALID_1000}

SCLK low to data valid

100 kHz mode

—

3.45

0.90

0.45

μs

(SCL = 30 % of V_CCto SDA = 30/70 % 400 kHz mode

of V_CC

)

1000 kHz mode

[1]

t_{FREE_100}

t_{FREE_400}

t_{FREE_1000}

Bus free time

100 kHz mode

—

4.00

1.30

0.50

—

μs

(SDA = 70 % of V_CCto SDA = 70 % of 400 kHz mode

V_CC

)

1000 kHz mode

[2]

C_BUS

SPI

Bus capacitive load

—

400

pF

[1]

t_SCLK

Serial interface timing^[3]

Clock (SCLK) period (10 %

—

90

30

10

50

—

25

—

ns

of V_CCto 10 % of V_CC

)

t_SCLKH

t_SCLKL

t_SCLKR

t_SCLKF

t_LEAD

Clock (SCLK) period (90 %

of V_CCto 90 % of V_CC

)

Clock (SCLK) period (10 %

of V_CCto 10 % of V_CC

)

Serial interface timing^[3]

Clock (SCLK) period (10 %

of V_CCto 90 % of V_CC

)

Clock (SCLK) period (90 %

of V_CCto 10 % of V_CC

)

Serial interface timing^[3]

SS_B asserted to SCLK

high (SS_B = 10 % of V_CC

to SCLK = 10 % of V_CC

)

[1]

t_ACCESS

SS_B asserted to SCLK

high (SS_B = 10 % of V_CC

to MISO = 10/90 % of V_CC

—

50

—

ns

)

t_SETUP

SS_B asserted to SCLK

high (MOSI = 10/90 % of

V_CCto SCLK = 10 % of

20

V_CC

)

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

57 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Symbol

Parameter

Condition

Min

Typ

Max

Units

[1]

t_{HOLD_IN}

Serial interface timing^[3]

MOSI data hold time

(SCLK = 90 % of V_CCto

MOSI = 10/90 % of V_CC

—

10

—

ns

)

t_{HOLD_OUT}

MOSI data hold time

(SCLK = 90 % of V_CCto

MISO = 10/90 % of V_CC

0

—

30

—

60

—

1

ns

)

t_VALID

Serial interface timing^[3]

SCLK low to data valid

(SCLK = 10 % of V_CCto

MISO = 10/90 % of V_CC

—

)

t_LAG

SCLK low to SS_B high

(SCLK = 10 % of V_CCto

60

—

SS_B = 90 % of V_CC

)

t_DISABLE

SS_B high to MISO disable

(SS_B = 90 % of V_CCto

MISO = Hi Z)

t_SSN

SS_B high to SS_B low

(SS_B = 90 % of V_CCto

500

50

—

SS_B = 90 % of V_CC

)

t_SLKSS

SCLK low to SS_B low

(SCLK = 10 % of V_CCto

SS_B = 90 % of V_CC

)

t_SSCLK

SS_B high to SCLK high

(SS_B = 90 % of V_CCto

SCLK = 90 % of V_CC

)

t_{LAT_SPI}

Signal chain

t_SigChain

f_c0

Data latency

[4]

P_ABSlow-pass filter

Signal chain sample time

—

48

—

μs

[2] [4]

Cutoff frequency, filter

option #0, 4-pole

800

Hz

[2] [4]

[4]

f_c1

Cutoff frequency, filter

option #1, 4-pole

—

1000

—

Hz

μs

t_SigDelay

Signal delay (sinc filter to output delay,

excluding the P_ABSLPF)

—

128

—

[4]

f_Package

Package resonance frequency

27.1

—

kHz

Supply and support circuitry

[2]

t_{VCC_POR}

Reset recovery (all modes, excluding

V_CCvoltage ramp time)

V_CC= V_CCMINto POR

release

—

1

ms

[4]

[2]

t_{POR_I2C/POR_SPI}

t_{POR_DataValid}

POR to first SPI command

POR to sensor data valid

0.400

—

0.700

ms

6

t_{RANGE_DataValid}

DSP setting change to

sensor data valid

—

[4]

t_{SOFT_RESET_I2C}

Soft reset activation time, command

complete to reset (no ACK follows)

—

700

ns

t_{SOFT_RESET_SPI}

Soft reset activation time, SS_B high to

reset

[4]

t_{CC_POR}

V_CCundervoltage detection delay

—

5

μs

t_{UVOV_RCV}

Undervoltage/overvoltage recovery

delay

100

—

[1] Parameter verified by characterization.

[2] Parameter verified by functional evaluation.

[3] See Section 7.5.6, C_MISO≤ 80 pF, R_MISO≥ 10 kΩ

[4] Functionality verified by modeling, simulation and/or design verification.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

58 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

12 Media compatibility—pressure sensors only

For more information regarding media compatibility information, contact your local sales

representative.

13 Pressure sensor accuracy (drift over temperature and life)

The absolute pressure accuracy is specified in Figure 23 and Figure 24.

Figure 23 shows the absolute pressure drift over the entire specified temperature range.

The absolute pressure drift over temperature is guaranteed by production testing.

Figure 24 shows a multiplying factor that accounts for the life time drift of the pressure

sensor. The results in Figure 24 have been obtained by qualification testing to conform to

the AEC-Q100^[2](Rev-H) standards.

As an example, at room temperature, the worst case drift that the pressure sensor might

have after accounting for lifetime performance is (1 kPa × multiplying factor) = 2 kPa.

Figure 23.ꢀAbsolute pressure accuracy as a function of temperature

Figure 24.ꢀAbsolute pressure accuracy multiplier over life

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

59 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

14 Application information

The FXPS7115D4 sensor can operate in two modes: I²C and SPI. The application

diagrams in Figure 25 and Figure 26 show the modes and their respective biasing and

bypass components.

The sensor can be configured to operate in SPI mode to read the user registers, self-test

and diagnostics information. The application diagram in Figure 26 shows the SPI and the

respective biasing and bypass components.

Note: A gel is used to provide media protection against corrosive elements which

may otherwise damage metal bond wires and/or IC surfaces. Highly pressurized gas

molecules may permeate through the gel and then occupy boundaries between material

surfaces within the sensor package. When decompression occurs, the gas molecules

may collect, form bubbles and possibly result in delamination of the gel from the material

it protects. If a bubble is located on the pressure transducer surface or on the bond wires,

the sensor measurement may shift from its calibrated transfer function. In some cases,

these temporary shifts could be outside the tolerances listed in the data sheet. In rare

cases, the bubble may bend the bond wires and result in a permanent shift.

V

CC

V

CC

V

CC

R1

R2

R3

V

SS

CCIO

INT

FXPS7xxxD4

SCL

C1

V

SDA

SS

aaa-029732

Figure 25.ꢀI²C application diagram of FXPS7115D4

Table 103.ꢀExternal component recommendations for I²C

Name

Type

Description

Purpose

C1

Ceramic

0.1 μF, 10 %, 10 V minimum, X7R

1000 Ω, 5 %, 200 PPM

V_CCpower supply decoupling

I²C selection pin pull-up resistor

Serial clock pull-up resistor

Serial data pull-up resistor

R1

General purpose

R2

R3

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

60 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

V

CC

V

CC

SS_B

MISO

SCLK

V

CCIO

FXPS7xxxD4

C1

MOSI

INT

V

SS

aaa-029733

Figure 26.ꢀSPI application diagram for FXPS7115D4

Table 104.ꢀExternal component recommendations for SPI

Name

Type

Description

Purpose

C1

Ceramic

0.1 μF, 10 %, 10 V minimum, X7R

V_CCpower supply decoupling

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

61 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

15 Package outline

Figure 27.ꢀPackage outline HQFN (SOT1573-1)

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

62 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Figure 28.ꢀPackage outline detail HQFN (SOT1573-1)

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

63 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Figure 29.ꢀPackage outline note HQFN (SOT1573-1)

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

64 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

16 References

[1]

Assembly guidelines for quad flat no-lead (HQFN) and small outline no-lead (SON) packages — NXP

Application Note (AN) 1902, Rev. 8.0 - 6 February 2018, 51 pages,

https://www.nxp.com/docs/en/application-note/AN1902.pdf

[2]

[3]

AEC documents on Automotive Electronics Council Component Technical Committee’s site:

http://www.aecouncil.com/AECDocuments.html

I²C-Bus specification and user manual — NXP User Manual (UM) 10204, Rev. 6 - 4 April 2014, 64 pages,

https://www.nxp.com/docs/en/user-guide/UM10204.pdf

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

65 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

17 Revision history

Table 105.ꢀRevision history

Document ID

FXPS7115D4 v.3

Modifications

Release date

20191205

Data sheet status

Change notice

Supercedes

Product data sheet

-

FXPS7115D4 v.2

• Section 10: updated absolute pressure accuracy specification

• Section 13: updated Figure 23 and Figure 24

FXPS7115D4 v.2

FXPS7115D4 v.1

20190730

20180816

Product data sheet

-

FXPS7115D4 v.1

-

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

66 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

18 Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Definition

Objective [short] data sheet

Development

This document contains data from the objective specification for product

development.

Preliminary [short] data sheet

Product [short] data sheet

Qualification

Production

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple

devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

18.2 Definitions

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes

no representation or warranty that such applications will be suitable

for the specified use without further testing or modification. Customers

are responsible for the design and operation of their applications and

products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications

and products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with

their applications and products. NXP Semiconductors does not accept any

liability related to any default, damage, costs or problem which is based

on any weakness or default in the customer’s applications or products, or

the application or use by customer’s third party customer(s). Customer is

responsible for doing all necessary testing for the customer’s applications

and products using NXP Semiconductors products in order to avoid a

default of the applications and the products or of the application or use by

customer’s third party customer(s). NXP does not accept any liability in this

respect.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences

of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is

intended for quick reference only and should not be relied upon to contain

detailed and full information. For detailed and full information see the

relevant full data sheet, which is available on request via the local NXP

Semiconductors sales office. In case of any inconsistency or conflict with the

short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product

is deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed

to be accurate and reliable. However, NXP Semiconductors does not

give any representations or warranties, expressed or implied, as to the

accuracy or completeness of such information and shall have no liability

for the consequences of use of such information. NXP Semiconductors

takes no responsibility for the content in this document if provided by an

information source outside of NXP Semiconductors. In no event shall NXP

Semiconductors be liable for any indirect, incidental, punitive, special or

consequential damages (including - without limitation - lost profits, lost

savings, business interruption, costs related to the removal or replacement

of any products or rework charges) whether or not such damages are based

on tort (including negligence), warranty, breach of contract or any other

legal theory. Notwithstanding any damages that customer might incur for

any reason whatsoever, NXP Semiconductors’ aggregate and cumulative

liability towards customer for the products described herein shall be limited

in accordance with the Terms and conditions of commercial sale of NXP

Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or

the grant, conveyance or implication of any license under any copyrights,

patents or other industrial or intellectual property rights.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

Right to make changes — NXP Semiconductors reserves the right to

make changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

67 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Customers are responsible for the design and operation of their applications

and products to reduce the effect of these vulnerabilities on customer’s

applications and products, and NXP Semiconductors accepts no liability for

any vulnerability that is discovered. Customers should implement appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

18.4 Trademarks

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Security — While NXP Semiconductors has implemented advanced

security features, all products may be subject to unidentified vulnerabilities.

NXP — is a trademark of NXP B.V.

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

68 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Tables

Tab. 1.

Tab. 2.

Tab. 3.

Tab. 4.

Tab. 5.

Ordering information ..........................................2

Tab. 37. DEVSTAT1 - device status register (address

02h) bit description ..........................................33

Tab. 38. DEVSTAT2 - device status register (address

03h) bit allocation ............................................33

Tab. 39. DEVSTAT2 - device status register (address

03h) bit description ..........................................34

Tab. 40. DEVSTAT3 - device status register (address

04h) bit allocation ............................................34

Tab. 41. DEVSTAT3 - device status register (address

04h) bit description ..........................................35

Ordering options ................................................2

Pin description ...................................................4

Self-test control register .................................... 8

Self-test control bits for sense data fixed

value verification ............................................... 8

IIR low pass filter coefficients ..........................10

Temperature conversion variables .................. 13

Sensor data register read wrap-around

Tab. 6.

Tab. 7.

Tab. 8.

description ....................................................... 17

SPI command format ...................................... 19

Tab. 9.

Tab. 42. TEMPERATURE

(address 0Eh) bit allocation .............................35

Tab. 43. DEVLOCK_WR lock register writes

register (address 10h) bit allocation ................ 35

Tab. 44. DEVLOCK_WR lock register writes

- temperature register

Tab. 10. SPI command bit allocation .............................20

Tab. 11. SPI response format ....................................... 20

Tab. 12. Register read command message format ....... 21

Tab. 13. Register read command message bit field

descriptions ..................................................... 21

Tab. 14. Register read response message format ........ 21

Tab. 15. Register read response message bit field

descriptions ..................................................... 22

Tab. 16. Register write command message format ....... 22

Tab. 17. Register write command message bit field

descriptions ..................................................... 22

Tab. 18. Register write response message format ........ 23

Tab. 19. Register write response message bit field

descriptions ..................................................... 23

Tab. 20. Sensor data request command message

format .............................................................. 23

Tab. 21. Sensor data request command message bit

field descriptions ............................................. 23

Tab. 22. Sensor data request response message

format .............................................................. 24

Tab. 23. Sensor data request response message bit

field descriptions ............................................. 24

Tab. 24. Reserved command message format ..............24

Tab. 25. Reserved command message bit field

descriptions ..................................................... 24

Tab. 26. Reserved command response message

format .............................................................. 24

Tab. 27. Reserved command response message bit

field descriptions ............................................. 25

Tab. 28. SPI Command Message CRC ........................ 25

Tab. 29. SPI Response Message CRC .........................26

Tab. 30. Basic status field for responses to register

commands .......................................................26

Tab. 31. Error responses bit field descriptions .............. 26

Tab. 32. User-accessible data — sensor specific

information .......................................................28

Tab. 33. COUNT - rolling counter register (address

00h) bit allocation ............................................31

Tab. 34. DEVSTAT - device status register (address

01h) bit allocation ............................................32

Tab. 35. DEVSTAT - device status register (address

01h) bit description ..........................................32

Tab. 36. DEVSTAT1 - device status register (address

02h) bit allocation ............................................32

-

register (address 10h) bit description ..............36

Tab. 45. Device reset command sequence ...................36

Tab. 46. UF_REGION_W

register (address 14h) bit allocation ................ 36

Tab. 47. UF_REGION_R UF region selection

- UF region selection

-

register (address 15h) bit allocation ................ 37

Tab. 48. REGION_LOAD Bit Definitions ....................... 37

Tab. 49. REGION_ACTIVE Bit Definitions .................... 37

Tab. 50. COMMTYPE - communication type register

(address 16h) bit allocation .............................38

Tab. 51. COMMTYPE - communication type register

(address 16h) bit description ...........................38

Tab. 52. SOURCEID_0

register (address 1Ah) bit allocation ................39

Tab. 53. SOURCEID_1 source identification

register (address 1Bh) bit allocation ................39

Tab. 54. TIMING_CFG communication timing

-

source identification

-

register (address 22h) bit allocation ................ 39

Tab. 55. SPI_CFG Register (address 3Dh) bit

allocation ......................................................... 39

Tab. 56. DATASIZE Bit Definition ................................. 39

Tab. 57. SPI CRC Definition ......................................... 40

Tab. 58. WHO_AM_I - device identification register

(address 3Eh) bit allocation .............................40

Tab. 59. WHO_AM_I register values .............................40

Tab. 60. I2C_ADDRESS - I2C slave address register

(address 3Fh) bit allocation .............................41

Tab. 61. Self-Test Control Bits (ST_CTRL[3:0]) ............ 41

Tab. 62. DSP_CFG_U1 - DSP user configuration #1

register (address 40h) bit allocation ................ 42

Tab. 63. Low-pass filter selection bits (LPF[3:0]) ...........42

Tab. 64. User range selection bits (USER_

RANGE[1:0]) ....................................................42

Tab. 65. DSP_CFG_U4 - DSP user configuration #4

register (address 43h) bit allocation ................ 42

Tab. 66. DSP_CFG_U4 - DSP user configuration #4

register (address 43h) bit description ..............43

Tab. 67. DSP_CFG_U5 - DSP user configuration #5

register (address 44h) bit allocation ................ 43

Tab. 68. DSP_CFG_U5 - DSP user configuration #5

register (address 44h) bit description ..............43

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

69 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Tab. 69. Self-test control bits ........................................ 43

Tab. 70. INT_CFG - interrupt configuration register

(address 45h) bit allocation .............................44

Tab. 71. INT_CFG - interrupt configuration register

(address 45h) bit description ...........................44

Tab. 72. P_INT_HI, P_INT_LO - interrupt window

comparator threshold registers (address 46h

Tab. 85. IC MANUFACTURER IDENTIFICATION

REGISTER (ICMFGID address C2h) bit

allocation ......................................................... 50

Tab. 86. PN0 Register (address C4h) bit allocation .......50

Tab. 87. PN1 Register (address C5h) bit allocation .......50

Tab. 88. SN0 Register (address C6h) bit allocation .......50

Tab. 89. SN1 Register (address C7h) bit allocation .......51

Tab. 90. SN2 Register (address C8h) bit allocation .......51

Tab. 91. SN3 Register (address C9h) bit allocation .......51

Tab. 92. SN4 Register (address CAh) bit allocation ...... 51

Tab. 93. ASICWFR# Register (address CBh) bit

allocation ......................................................... 51

Tab. 94. ASICWFR_X Register (address CCh) bit

allocation ......................................................... 51

Tab. 95. ASICWFR_Y Register (address CDh) bit

allocation ......................................................... 52

to 49h) bit allocation ........................................44

Tab. 73. P_CAL_ZERO

-

pressure calibration

registers (address 4Ch, 4Dh) bit allocation ......45

Tab. 74. DSP_STAT - DSP-specific status register

(address 60h) bit allocation .............................46

Tab. 75. DSP_STAT - DSP-specific status register

(address 60h) bit description ...........................46

Tab. 76. DEVSTAT_COPY - device status copy

register (address 61h) bit allocation ................ 46

Tab. 77. SNSDATA0_L, SNSDATA0_H - sensor data

#0 registers (addresses 62h, 63h) bit

Tab. 96. ASICWLOT_L Register (address D0h) bit

allocation ......................................................... 52

allocation ......................................................... 47

Tab. 78. SNSDATA1_L, SNSDATA1_H - sensor data

#1 registers (address 64h, 65h) bit allocation ...47

Tab. 79. SNSDATA0_TIMEx - time stamp register

(address 66h to 6Bh) bit allocation ..................48

Tab. 80. P_Max and P_Min registers (address 6Ch to

6Fh) bit allocation ............................................48

Tab. 97. ASICWLOT_H Register (address D1h) bit

allocation ......................................................... 52

Tab. 98. Lock and CRC Register bit definitions .............53

Tab. 99. Maximum ratings .............................................54

Tab. 100. Electrical characteristics — supply and I/O ..... 55

Tab. 101. Static characteristics ....................................... 55

Tab. 102. Dynamic characteristics .................................. 56

Tab. 103. External component recommendations for

I2C ...................................................................60

Tab. 104. External component recommendations for

SPI ...................................................................61

Tab. 105. Revision history ...............................................66

Tab. 81. FRT

-

free running timer registers

(addresses 78h to 7Dh) bit allocation ..............48

Tab. 82. Range Indication Bits (RANGE[3:0]) ............... 49

Tab. 83. IC TYPE REGISTER (ICTYPEID address

C0h) bit allocation ........................................... 49

Tab. 84. IC

MANUFACTURER

REVISION

REGISTER (ICREVID address C1h) bit

allocation ......................................................... 49

Figures

Fig. 1.

Fig. 2.

Fig. 3.

Fig. 4.

Block diagram of FXPS7115D4 ........................ 3

Pin configuration for 16-pin HQFN ....................3

Voltage regulation and monitoring .....................5

User-controlled PABS common mode self-

test flowchart .....................................................7

ΣΔ converter block diagram ..............................8

Signal chain diagram ........................................ 9

Sinc filter response ........................................... 9

800 Hz, 4-pole, low-pass filter response ......... 10

800 Hz, 4-pole output signal delay ..................11

Fig. 16. I2C byte transmissions ....................................15

Fig. 17. I2C acknowledge and not acknowledge

transmission .................................................... 15

Fig. 18. I2C stop condition ........................................... 16

Fig. 19. I2C timing diagram ..........................................18

Fig. 20. Standard 32 Bit SPI protocol timing diagram ... 19

Fig. 21. SPI data output verification ............................. 27

Fig. 22. SPI timing diagram ..........................................27

Fig. 23. Absolute pressure accuracy as a function of

temperature ..................................................... 59

Fig. 5.

Fig. 6.

Fig. 7.

Fig. 8.

Fig. 9.

Fig. 10. 1000 Hz, 4-pole, low-pass filter response ....... 11

Fig. 11. 1000 Hz, 4-pole output signal delay ................12

Fig. 12. Temperature sensor signal chain block

diagram ............................................................13

Fig. 13. Common mode error detection signal chain

block diagram ..................................................13

Fig. 24. Absolute pressure accuracy multiplier over

life ....................................................................59

Fig. 25. I2C application diagram of FXPS7115D4 ........60

Fig. 26. SPI application diagram for FXPS7115D4 .......61

Fig. 27. Package outline HQFN (SOT1573-1) ..............62

Fig. 28. Package outline detail HQFN (SOT1573-1) .... 63

Fig. 29. Package outline note HQFN (SOT1573-1) ......64

Fig. 14. I2C bit transmissions .......................................14

Fig. 15. I2C start condition ...........................................14

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

70 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

Contents

1

2

3

3.1

3.2

3.3

4

4.1

5

6

6.1

6.2

7

7.1

7.1.1

7.2

7.3

7.3.1

7.3.2

7.3.2.1

7.3.2.2

7.3.2.3

7.3.3

7.3.4

7.3.4.1

7.3.4.2

7.3.4.3

7.3.4.4

General description ............................................ 1

7.5.5.1

7.5.5.2

7.5.5.3

7.5.5.4

7.5.6

7.6

Basic status field ............................................. 26

Error responses ............................................... 26

SPI error .......................................................... 26

SPI data output verification error .....................27

SPI timing diagram .......................................... 27

User-accessible data array ..............................28

Register information .........................................31

COUNT - rolling counter register (address

00h) ..................................................................31

Device status registers .................................... 31

DEVSTAT - device status register (address

01h) ..................................................................32

DEVSTAT1 - device status register (address

02h) ..................................................................32

DEVSTAT2 - device status register (address

03h) ..................................................................33

DEVSTAT3 - device status register (address

04h) ..................................................................34

Features and benefits .........................................1

Applications .........................................................2

Automotive .........................................................2

Industrial ............................................................ 2

Medical/Consumer .............................................2

Ordering information .......................................... 2

Ordering options ................................................ 2

Block diagram ..................................................... 3

Pinning information ............................................ 3

Pinning ...............................................................3

Pin description ...................................................4

Functional description ........................................4

Voltage regulators ............................................. 4

VCC, VREG, VREGA, undervoltage monitor .....5

Internal oscillator ............................................... 5

Pressure sensor signal path ..............................5

Transducer .........................................................5

Self-test functions .............................................. 6

PABS common mode verification ...................... 6

Startup digital self-test verification .....................7

Startup sense data fixed value verification ........ 8

ΣΔ converter ......................................................8

Digital signal processor (DSP) ...........................9

Decimation sinc filter ......................................... 9

Signal trim and compensation ........................... 9

Low-pass filter ................................................... 9

Absolute pressure output data scaling

equation ........................................................... 12

Temperature sensor ........................................ 12

Temperature sensor signal chain .................... 12

Temperature sensor output scaling equation ... 13

Common mode error detection signal chain .... 13

Inter-integrated circuit (I2C) interface .............. 13

I2C bit transmissions ....................................... 14

I2C start condition ........................................... 14

I2C byte transmission ......................................14

I2C acknowledge and not acknowledge

transmissions ...................................................15

I2C stop condition ............................................15

I2C register transfers .......................................16

Register write transfers ....................................16

Register read transfers ....................................17

Sensor data register read wrap around ........... 17

I2C timing diagram .......................................... 18

Standard 32-bit SPI protocol ........................... 18

SPI command format .......................................19

SPI response format ........................................20

Command summary ........................................ 21

Register read command .................................. 21

Register write command ..................................22

Sensor data request commands ......................23

Reserved commands .......................................24

Error checking ................................................. 25

Default 8-bit CRC ............................................ 25

Exception handling .......................................... 26

7.7

7.7.1

7.7.2

7.7.2.1

7.7.2.2

7.7.2.3

7.7.2.4

7.7.3

TEMPERATURE

- temperature register

(address 0Eh) ..................................................35

DEVLOCK_WR - lock register writes register

(address 10h) .................................................. 35

7.7.4

7.7.5

UF_REGION_W, UF_REGION_R

-

UF

region selection registers (address 14h, 15h) ...36

COMMTYPE - communication type register

(address 16h) .................................................. 38

7.7.6

7.7.7

SOURCEID_x

registers (address 1Ah, 1Bh) ...........................38

TIMING_CFG communication timing

-

source identification

7.7.8

-

7.3.5

7.3.5.1

7.3.5.2

7.3.6

7.4

7.4.1

7.4.2

7.4.3

7.4.4

register (address 22h) ..................................... 39

SPI Configuration Control Register (SPI_

CFG, Address 3Dh) .........................................39

SPI Data Field Size (DATASIZE) .................... 39

SPI CRC Length and Seed Bits ...................... 40

WHO_AM_I - who am I register (address

3Eh) ................................................................. 40

I2C_ADDRESS - I2C slave address register

(address 3Fh) .................................................. 40

DSP Configuration Registers (DSP_CFG_

Ux) ................................................................... 41

7.7.9

7.7.9.1

7.7.9.2

7.7.10

7.7.11

7.7.12

7.4.5

7.4.6

7.4.6.1

7.4.6.2

7.4.6.3

7.4.7

7.5

7.5.1

7.5.2

7.5.3

7.5.3.1

7.5.3.2

7.5.3.3

7.5.3.4

7.5.4

7.7.12.1 Self-test control bits .........................................41

7.7.12.2 DSP_CFG_U1 - DSP user configuration #1

register (address 40h) ..................................... 42

7.7.12.3 DSP_CFG_U4 - DSP user configuration #4

register (address 43h) ..................................... 42

7.7.12.4 DSP_CFG_U5 - DSP user configuration #5

register (address 44h) ..................................... 43

7.7.13

INT_CFG - interrupt configuration register

(address 45h) .................................................. 44

P_INT_HI, P_INT_LO - interrupt window

comparator threshold registers (address 46h

to 49h) ............................................................. 44

7.7.14

7.7.15

7.7.16

P_CAL_ZERO

-

pressure calibration

registers (address 4Ch, 4Dh) .......................... 45

DSP_STAT - DSP-specific status register

(address 60h) .................................................. 46

7.5.4.1

7.5.5

FXPS7115D4

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 5 December 2019

71 / 72

NXP Semiconductors

FXPS7115D4

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.7.17

7.7.18

7.7.19

7.7.20

7.7.21

DEVSTAT_COPY - device status copy

register (address 61h) ..................................... 46

SNSDATA0_L, SNSDATA0_H - sensor data

#0 registers (address 62h, 63h) .......................46

SNSDATA1_L, SNSDATA1_H - sensor data

#1 registers (address 64h, 65h) .......................47

SNSDATA0_TIMEx - time stamp registers

(address 66h to 6Bh) .......................................47

P_MAX, P_MIN - maximum and minimum

absolute pressure value registers (address

6Ch to 6Fh) ..................................................... 48

7.7.22

FRT

-

free running timer registers

(addresses 78h to 7Dh) ...................................48

DSP_CFG_F Register ..................................... 49

IC type register (Address C0h) ........................49

IC manufacturer revision register (Address

7.7.23

7.7.24

7.7.25

C1h) ................................................................. 49

IC manufacturer identification register

7.7.26

(address C2h) ..................................................50

Part number register (address C4h, C5h) ........50

Device serial number registers ........................ 50

ASIC wafer ID registers ...................................51

USERDATA_0 to USERDATA_E - user data

7.7.27

7.7.28

7.7.29

7.7.30

registers ........................................................... 52

USERDATA_10 to USERDATA_1E - user

7.7.31

data registers ...................................................52

Lock and CRC Registers .................................52

Reserved registers ...........................................53

Invalid register addresses ................................53

Read/write register array CRC verification .......53

Maximum ratings ...............................................54

Operating range ................................................ 55

Static characteristics ........................................55

Dynamic characteristics ...................................56

Media compatibility—pressure sensors

only .....................................................................59

Pressure sensor accuracy (drift over

temperature and life) ........................................ 59

Application information ....................................60

Package outline .................................................62

References .........................................................65

Revision history ................................................ 66

Legal information ..............................................67

7.7.32

7.7.33

7.7.34

7.8

8

9

10

11

12

13

14

15

16

17

18

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section 'Legal information'.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 5 December 2019

Document identifier: FXPS7115D4


型号：	FXPS7115D4
厂家：	NXP
描述：	Digital absolute pressure sensor, 40 kPa to 115 kPa
文件：	总72页 (文件大小：1041K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FXPS7115D4 [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E