HEC4014BD [NXP]
IC 4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register;
| 型号： | HEC4014BD |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, Shift Register 移位寄存器 |
| 文件： | 总6页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4014B
MSI
8-bit static shift register
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4014B
MSI
8-bit static shift register
Operation is synchronous and the device is edge-triggered
on the LOW to HIGH transition of CP. Each register stage
is of a D-type master-slave flip-flop. When PE is HIGH,
data is loaded into the register from P0 to P7 on the LOW
to HIGH transition of CP. When PE is LOW, data is shifted
to the first position from DS, and all the data in the register
is shifted one position to the right on the LOW to HIGH
transition of CP. Schmitt-trigger action in the clock input
makes the circuit highly tolerant to slower clock rise and
fall times
DESCRIPTION
The HEF4014B is a fully synchronous edge-triggered 8-bit
static shift register with eight synchronous parallel inputs
(P0 to P7), a synchronous serial data input (DS), a
synchronous parallel enable input (PE), a LOW to HIGH
edge-triggered clock input (CP) and buffered parallel
outputs from the last three stages (O5 to O7).
Fig.1 Functional diagram.
HEF4014BP(N):
16-lead DIL; plastic
(SOT38-1)
HEF4014BD(F):
HEF4014BT(D):
16-lead DIL; ceramic (cerdip)
(SOT74)
16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category MSI
Fig.2 Pinning diagram.
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4014B
MSI
8-bit static shift register
January 1995
3
Philips Semiconductors
Product specification
HEF4014B
MSI
8-bit static shift register
PINNING
PE
parallel enable input
P0 to P7 parallel data inputs
DS
serial data input
CP
clock input (LOW to HIGH edge-triggered)
O5 to O7 buffered parallel outputs from the last three
stages
FUNCTION TABLES
Serial operation
Parallel operation
INPUTS
INPUTS
DS
OUTPUTS
O6
OUTPUTS
n
CP
PE
O5
O7
n
CP
DS
PE
O5
O6
O7
1
D1
D2
D3
X
L
X
X
X
1
X
H
P5
P6
P7
2
3
6
7
8
L
L
L
L
L
X
X
X
X
X
X
X
no change
X
X
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
D1
D2
D3
X
D1
X
X
X
= positive-going transition
= negative-going transition
X
D2
D1
Dn = either HIGH or LOW
n = number of clock pulse transitions
X
no change
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
5
10
15
900 fi + ∑ (foCL) × VDD
4 300 fi + ∑ (foCL) × VDD
12 000 fi + ∑ (foCL) × VDD
where
2
2
dissipation per
package (P)
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4014B
MSI
8-bit static shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → On
HIGH to LOW
5
130
55
40
115
50
40
60
30
20
60
30
20
10
5
260
110
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
103 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
88 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tPHL
tPLH
tTHL
230
100
80
LOW to HIGH
10
15
5
Output transition times
HIGH to LOW
120
60
10
15
5
40
120
60
LOW to HIGH
10
15
5
tTLH
40
Set-up times
40
PE → CP
10
15
5
tsu
25
15
35
25
25
35
25
25
25
20
15
30
20
15
30
20
15
70
30
24
0
− 5
−5
0
DS → CP
Pn → CP
10
15
5
tsu
−5
−5
0
10
15
5
tsu
Hold times
−5
0
PE → CP
10
15
5
thold
thold
thold
tWCPL
see also waveforms Fig.4
0
15
10
7
DS → CP
Pn → CP
10
15
5
15
10
7
10
15
5
Minimum clock
35
15
12
pulse width; LOW
10
15
Maximum clock
pulse frequency
5
6
15
20
13
30
40
MHz
MHz
MHz
10
15
fmax
January 1995
5
Fig.4 Waveforms showing minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and P to CP. Set-up and hold times
are shown as positive values but may be specified as negative values.
APPLICATION INFORMATION
Some examples of applications for the HEF4014B are:
• Parallel-to-serial converter
• Serial data queueing
• General purpose register
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