HEF4011UBT [NXP]

Quadruple 2-input NAND gate; 四路2输入与非门


型号：	HEF4011UBT
厂家：	NXP
描述：	Quadruple 2-input NAND gate 四路2输入与非门栅极触发器逻辑集成电路光电二极管
文件：	总9页 (文件大小：138K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC

• The IC04 LOCMOS HE4000B Logic

Package Outlines/Information HEF, HEC

HEF4011UB

gates

Quadruple 2-input NAND gate

January 1995

Product speciﬁcation

File under Integrated Circuits, IC04

Philips Semiconductors

Product speciﬁcation

HEF4011UB

gates

Quadruple 2-input NAND gate

DESCRIPTION

The HEF4011UB is a quadruple 2-input NAND gate. This

unbuffered single stage version provides a direct

implementation of the NAND function. The output

impedance and output transition time depends on the input

voltage and input rise and fall times applied.

Fig.2 Pinning diagram.

HEF4011UBP(N):

HEF4011UBD(F):

HEF4011UBT(D):

14-lead DIL; plastic

(SOT27-1)

Fig.1 Functional diagram.

14-lead DIL; ceramic (cerdip)

(SOT73)

14-lead SO; plastic

(SOT108-1)

( ): Package Designator North America

Fig.3 Schematic diagram (one gate). The

splitting-up of the n-transistors provide

identical inputs.

FAMILY DATA, I_DDLIMITS category GATES

See Family Specifications for V_IH/V_ILunbuffered stages

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4011UB

gates

Quadruple 2-input NAND gate

AC CHARACTERISTICS

V_SS= 0 V; T_amb= 25 °C; C_L= 50 pF; input transition times ≤ 20 ns

V_DD

TYPICAL EXTRAPOLATION

FORMULA

SYMBOL

TYP.

MAX.

Propagation delays

I_n→ O_n

HIGH to LOW

120

25 ns + (0,70 ns/pF) C_L

12 ns + (0,27 ns/pF) C_L

10 ns + (0,20 ns/pF) C_L

8 ns + (0,55 ns/pF) C_L

9 ns + (0,23 ns/pF) C_L

9 ns + (0,16 ns/pF) C_L

15 ns + (1,20 ns/pF) C_L

6 ns + (0,48 ns/pF) C_L

4 ns + (0,32 ns/pF) C_L

10 ns + (1,00 ns/pF) C_L

9 ns + (0,42 ns/pF) C_L

6 ns + (0,28 ns/pF) C_L

t_PHL

LOW to HIGH

t_PLH

Output transition

times

150

t_THL

HIGH to LOW

110

LOW to HIGH

t_TLH

Input capacitance

C_IN

V_DD

TYPICAL FORMULA FOR P (µW)

Dynamic power

dissipation per

package (P)

500 f_i+ ∑ (f_oC_L) × V_DD

where

5 000 f_i+ ∑ (f_oC_L) × V_DD

f_i= input freq. (MHz)

25 000 f_i+ ∑ (f_oC_L) × V_DD

f_o= output freq. (MHz)

C_L= load capacitance (pF)

∑ (f_oC_L) = sum of outputs

V_DD= supply voltage (V)

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4011UB

gates

Quadruple 2-input NAND gate

Fig.4 Typical transfer characteristics; one input, the other

input connected to V_DD

V_O;

;

− − − I_D(drain current);

I_O= 0; V_DD= 5 V.

Fig.5 Typical transfer characteristics; one input, the other

input connected to V_DD

V_O;

;

− − − I_D(drain current);

I_O= 0; V_DD= 10 V.

Fig.6 Typical transfer characteristics; one input, the other

input connected to V_DD

V_O;

;

− − − I_D(drain current);

I_O= 0; V_DD= 15 V.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4011UB

gates

Quadruple 2-input NAND gate

Fig.7 Test set-up for measuring forward transconductance g_fs= di_o/dv_iat v_ois constant (see also graph Fig.8).

A : average,

B : average + 2 s,

C : average − 2 s, where ‘s’ is the observed standard deviation.

Fig.8 Typical forward transconductance g_fsas a function of the supply voltage at T_amb= 25 °C.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4011UB

gates

Quadruple 2-input NAND gate

APPLICATION INFORMATION

Some examples of applications for the HEF4011UB are shown below.

Because of the fact that this circuit is unbuffered, it is suitable for use in (partly) analogue circuits.

INH

OSC

In Fig.9 the oscillation frequency is mainly determined by R1C1,

provided R1 << R2 and R2C2 << R1C1.

The function of R2 is to minimize the influence of the forward voltage

across the protection diodes on the frequency; C2 is a stray (parasitic)

capacitance. The period T_pis given by T_p= T₁+ T₂, in which

_DD+ V_ST

2V_DD– V_ST

------------------------------

where

---------------------------

T₁= R1C1 In

and T₂= R1C1 In

V_ST

V_DD– V_ST

_STis the signal threshold level of the gate. The period is fairly

independent of V_DD, V_STand temperature. The duty factor, however, is

influenced by V_ST

Fig.9 (a) Astable relaxation oscillator using two HEF4011UB gates; the diodes may be BAW62; C2 is a parasitic

capacitance.

(b) Waveforms at the points marked A, B, C and D in the circuit diagram.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4011UB

gates

Quadruple 2-input NAND gate

INH

OSC

Fig.10 Example of a crystal oscillator using one HEF4011UB gate.

Fig.12 Test set-up for measuring graph of Fig.11.

Condition: all other inputs connected to

ground.

NOTES

If a gate is just used as an amplifying inverter, there are

two possibilities:

• Connecting the inputs together gives simpler wiring, but

makes the device output not completely symmetrical.

• Connecting one input to V_DDwill give the device a

symmetrical output.

Fig.11 Output voltage as a function of supply

voltage.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4011UB

gates

Quadruple 2-input NAND gate

Fig.13 Voltage gain (V_O/V_I) as a function of supply

voltage.

Fig.14 Supply current as a function of supply

voltage.

Fig.15 Test set-up for measuring graphs of Figs 13

and 14. Condition: all other inputs

connected to ground.

Fig.16 Example of an analogue amplifier with

inhibit using one HEF4011UB gate.

January 1995

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