HEF4013BF [NXP]
Dual D-type flip-flop; 双D型触发器
| 型号： | HEF4013BF |
| 厂家： | 
NXP |
| 描述： | Dual D-type flip-flop |
| 文件： | 总7页 (文件大小：83K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4013B
flip-flops
Dual D-type flip-flop
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4013B
flip-flops
Dual D-type flip-flop
DESCRIPTION
FUNCTION TABLES
INPUTS
The HEF4013B is a dual D-type flip-flop which features
independent set direct (SD), clear direct (CD), clock inputs
(CP) and outputs (O, O). Data is accepted when CP is
LOW and transferred to the output on the positive-going
edge of the clock. The active HIGH asynchronous
clear-direct (CD) and set-direct (SD) are independent and
override the D or CP inputs. The outputs are buffered for
best system performance. Schmitt-trigger action in the
clock input makes the circuit highly tolerant to slower clock
rise and fall times.
OUTPUTS
SD
CD
CP
D
O
O
H
L
L
H
H
X
X
X
X
X
X
H
L
L
H
H
H
H
INPUTS
OUTPUTS
SD
CD
CP
D
On + 1
On + 1
L
L
L
L
H
L
L
H
H
L
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
= positive-going transition
On + 1 = state after clock positive transition
PINNING
D
data inputs
CP
SD
CD
O
clock input (L to H edge-triggered)
asynchronous set-direct input (active HIGH)
asynchronous clear-direct input (active HIGH)
true output
O
complement output
Fig.1 Functional diagram.
HEF4013BP(N):
HEF4013BD(F):
HEF4013BT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
FAMILY DATA, IDD LIMITS category FLIP-FLOPS
Fig.2 Pinning diagram.
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4013B
flip-flops
Dual D-type flip-flop
January 1995
3
Philips Semiconductors
Product specification
HEF4013B
flip-flops
Dual D-type flip-flop
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN.
TYP.
MAX.
Propagation delays
CP → O, O
5
110
45
30
95
40
30
100
40
30
75
35
25
100
40
30
60
30
20
220
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
68 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
73 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
48 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
73 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
33 ns + (0,55 ns/pF) CL
19 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
HIGH to LOW
10
15
5
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
60
190
80
LOW to HIGH
10
15
5
60
SD → O
200
80
HIGH to LOW
10
15
5
60
SD → O
150
70
LOW to HIGH
10
15
5
50
CD → O
200
80
HIGH to LOW
10
15
5
60
CD → O
120
60
LOW to HIGH
10
15
40
Output transition times
HIGH to LOW
5
60
30
20
60
30
20
120
60
ns
ns
ns
ns
ns
ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tTHL
40
120
60
LOW to HIGH
10
15
tTLH
40
January 1995
4
Philips Semiconductors
Product specification
HEF4013B
flip-flops
Dual D-type flip-flop
AC CHARACTERISTI CS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Set-up time
5
40
25
15
20
20
15
60
30
20
50
24
20
50
24
20
15
15
15
40
25
25
7
20
10
5
ns
D → CP
10
15
5
tsu
ns
ns
Hold time
0
ns
D → CP
10
15
5
thold
tWCPL
tWSDH
tWCDH
tRSD
0
ns
0
ns
Minimum clock
30
15
10
25
12
10
25
12
10
−5
0
ns
pulse width; LOW
10
15
5
ns
ns
Minimum SD pulse
width; HIGH
ns
see also waveforms
Figs 4 and 5
10
15
5
ns
ns
Minimum CD pulse
width; HIGH
ns
10
15
5
ns
ns
Recovery time
for SD
ns
10
15
5
ns
0
ns
Recovery time
for CD
25
10
10
14
28
40
ns
10
15
5
tRCD
ns
ns
Maximum clock
pulse frequency
MHz
MHz
MHz
10
15
fmax
14
20
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
850 fi + ∑ (foCL) × VDD
where
2
10
15
3 600 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
9 000 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = total load cap. (pF)
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF4013B
flip-flops
Dual D-type flip-flop
Fig.4 Waveforms showing set-up times, hold times and minimum clock pulse width. Set-up and hold times are
shown as positive values but may be specified as negative values.
Fig.5 Waveforms showing recovery times for SD and CD; minimum SD and CD pulse widths.
January 1995
6
Philips Semiconductors
Product specification
HEF4013B
flip-flops
Dual D-type flip-flop
APPLICATION INFORMATION
Some examples of applications for the HEF4013B are:
• Counters/dividers
• Registers
• Toggle flip-flops
Fig.6 Typical application of the HEF4013B in an n-stage shift register.
Fig.7 Typical application of the HEF4013B in a binary ripple up-counter; divide-by-2n.
Fig.8 Typical application of the HEF4013B in a modified ring counter; divide-by-(n + 1).
7
January 1995
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