HEF40193BT [NXP]
4-bit up/down binary counter; 4位向上/向下二进制计数器
| 型号： | HEF40193BT |
| 厂家： | 
NXP |
| 描述： | 4-bit up/down binary counter |
| 文件： | 总10页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40193B
MSI
4-bit up/down binary counter
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF40193B
MSI
4-bit up/down binary counter
The counter outputs change state on the LOW to HIGH
transition of either clock input. However, for correct
counting, both clock inputs cannot be LOW
DESCRIPTION
The HEF40193B is a 4-bit synchronous up/down
binary counter. The counter has a count-up clock input
(CPU), a count-down clock input (CPD), an asynchronous
parallel load input (PL), four parallel data inputs (P0 to P3),
an asynchronous master reset input (MR), four counter
outputs (O0 to O3), an active LOW terminal count-up
(carry) output (TCU) and an active LOW terminal
count-down (borrow) output (TCD).
simultaneously. The outputs TCU and TCD are normally
HIGH. When the circuit has reached the maximum count
state of ‘15’, the next HIGH to LOW transition of CPU will
cause TCU to go LOW. TCU will stay LOW until CPU goes
HIGH again. Likewise, output TCD will go LOW when the
circuit is in the zero state and CPD goes LOW. When PL is
LOW, the information on P0 to P3 is asynchronously
loaded into the counter. A HIGH on MR resets the counter
independent of all other input conditions. The counter
stages are of a static toggle type flip-flop.
Fig.2 Pinning diagram.
HEF40193BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF40193BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
Fig.1 Functional diagram.
HEF40193BT(D): 16-lead SO; plastic
(SOT109-1)
PINNING
( ): Package Designator North America
PL
parallel load input (active LOW)
parallel data inputs
P0 to P3
CPU
count-up clock pulse input (LOW to HIGH,
edge-triggered)
FAMILY DATA, IDD LIMITS category MSI
See Family Specification
CPD
count-down clock pulse input (LOW to
HIGH, edge-triggered)
MR
master reset input (asynchronous)
TCU
buffered terminal count-up (carry) output
(active LOW)
TCD
buffered terminal count-down
(borrow) output (active LOW)
O0 to O3 buffered counter outputs
January 1995
2
Philips Semiconductors
Product specification
HEF40193B
MSI
4-bit up/down binary counter
Fig.3 Logic diagram (continued on Fig.4).
January 1995
3
Philips Semiconductors
Product specification
HEF40193B
MSI
4-bit up/down binary counter
Fig.4 Logic diagram (continued from Fig.3).
January 1995
4
Philips Semiconductors
Product specification
HEF40193B
MSI
4-bit up/down binary counter
Notes
FUNCTION TABLE
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
MR
PL
CPU
CPD
MODE
H
L
X
L
X
X
X
X
reset (asyn.)
parallel load
= positive-going transition
L
L
H
H
H
count-up
H
count-down
Logic equations for terminal count:
TCU = O0 O1 O2 O3 CPU
TCD = O0 O1 O2 O3 CPD
Fig.5 State diagram.
AC CHARACTERISTICS
SS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
V
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
2
Dynamic power
5
10
15
600 fi + ∑(foCL) × VDD
2700 fi + ∑(foCL) × VDD
7500 fi + ∑(foCL) × VDD
where
dissipation per
package (P)
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
January 1995
5
Philips Semiconductors
Product specification
HEF40193B
MSI
4-bit up/down binary counter
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICAL EXTRAPOLATION
SYMBOL MIN. TYP. MAX.
V
FORMULA
Propagation delays
CPU → On
5
10
15
5
210
85
415 ns
165 ns
120 ns
340 ns
140 ns
100 ns
425 ns
170 ns
125 ns
340 ns
140 ns
100 ns
250 ns
100 ns
70 ns
183 ns + (0,55 ns/pF) CL
74 ns + (0,23 ns/pF) CL
52 ns + (0,16 ns/pF) CL
143 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
183 ns + (0,55 ns/pF) CL
74 ns + (0,23 ns/pF) CL
57 ns + (0,16 ns/pF) CL
143 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
98 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
68 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
113 ns + (0,55 ns/pF) CL
44 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
73 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
168 ns + (0,55 ns/pF) CL
69 ns + (0,23 ns/pF) CL
52 ns + (0,16 ns/pF) CL
118 ns + (0,55 ns/pF) CL
49 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
338 ns + (0,55 ns/pF) CL
119 ns + (0,23 ns/pF) CL
92 ns + (0,16 ns/pF) CL
158 ns + (0,55 ns/pF) CL
64 ns + (0,23 ns/pF) CL
47 ns + (0,16 ns/pF) CL
HIGH to LOW
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
60
170
70
LOW to HIGH
10
15
5
50
CPD → On
210
85
HIGH to LOW
10
15
5
60
170
70
LOW to HIGH
10
15
5
50
CPU → TCU
125
50
HIGH to LOW
10
15
5
35
95
185 ns
80 ns
LOW to HIGH
10
15
5
40
30
60 ns
CPD → TCD
140
55
280 ns
110 ns
80 ns
HIGH to LOW
10
15
5
40
100
40
195 ns
85 ns
LOW to HIGH
10
15
5
30
65 ns
MR → On
195
80
390 ns
160 ns
120 ns
285 ns
115 ns
90 ns
HIGH to LOW
10
15
5
60
MR → TCU
145
60
LOW to HIGH
10
15
5
45
MR → TCD
365
130
100
185
75
730 ns
265 ns
205 ns
360 ns
150 ns
110 ns
HIGH to LOW
10
15
5
PL → On
HIGH to LOW
10
15
55
January 1995
6
Philips Semiconductors
Product specification
HEF40193B
MSI
4-bit up/down binary counter
VDD
V
TYPICAL EXTRAPOLATION
SYMBOL MIN. TYP. MAX.
FORMULA
118 ns + (0,55 ns/pF) CL
49 ns + (0,23 ns/pF) CL
37 ns + (0,16 ns/pF) CL
5
145
60
290 ns
120 ns
90 ns
LOW to HIGH
10
15
tPLH
45
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Output transition
times
HIGH to LOW
5
60
30
20
60
30
20
80
30
25
120 ns
10 ns
9 ns
6 ns
10 ns
9 ns
6 ns
+
+
+
+
+
+
(1,0 ns/pF) CL
10
15
5
tTHL
60 ns
40 ns
120 ns
60 ns
40 ns
ns
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
LOW to HIGH
10
15
5
tTLH
Set-up time
160
60
Pn → PL
10
15
5
tsu
ns
50
ns
Hold time
10 −70
ns
Pn → PL
10
15
5
thold
5
5
−25
−20
75
25
20
90
35
30
60
20
15
65
35
25
45
15
10
5
ns
ns
Minimum CPU or CPD
pulse width; LOW
150
50
35
180
70
60
120
45
30
125
70
50
90
35
25
2,5
7
ns
10
15
5
tWCPL
tWMRH
tWPLL
tRMR
tRPL
fmax
ns
ns
Minimum MR
ns
pulse width; HIGH
10
15
5
ns
ns
see also waveforms
Fig.6
Minimum PL
ns
pulse width; LOW
10
15
5
ns
ns
Recovery time
for MR
ns
10
15
5
ns
ns
Recovery time
for PL
ns
10
15
5
ns
ns
Maximum clock
pulse frequency
MHz
10
15
14
18
MHz
MHz
9
January 1995
7
Philips Semiconductors
Product specification
HEF40193B
MSI
4-bit up/down binary counter
Fig.6 Waveforms showing recovery times for PL and MR, minimum pulse widths for CPU, CPD, PL and MR,
and set-up and hold times for P to PL. Set-up times and hold times are shown as positive values but may
be specified as negative values.
January 1995
8
Philips Semiconductors
Product specification
HEF40193B
MSI
4-bit up/down binary counter
Fig.7 Timing diagram.
APPLICATION INFORMATION
Some examples of applications for the HEF40193B are:
• Up/down difference counting
• Multistage ripple counting
• Multistage synchronous counting
Fig.8 Example of cascaded HEF40193B ICs.
January 1995
9
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