HEF4020B_08 [NXP]
14-stage binary counter; 14级二进制计数器
| 型号： | HEF4020B_08 |
| 厂家： | 
NXP |
| 描述： | 14-stage binary counter |
| 文件： | 总13页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4020B
14-stage binary counter
Rev. 04 — 4 December 2008
Product data sheet
1. General description
The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to
Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. A feature of the device is its high speed
(typ. 35 MHz at VDD = 15 V).
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
2. Features
I High speed operation
I Fully static operation
I 5 V, 10 V, and 15 V parametric ratings
I Standardized symmetrical output characteristics
I Operates across the full industrial temperature range −40 °C to +85 °C
I Complies with JEDEC standard JESD 13-B
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
3. Applications
I Industrial
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +85 °C.
Type number Package
Name
DIP16
SO16
Description
Version
HEF4020BP
HEF4020BT
plastic dual in-line package; 16-leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
SOT38-4
SOT109-1
HEF4020B
NXP Semiconductors
14-stage binary counter
5. Functional diagram
10
11
CP
T
14-STAGE COUNTER
MR
C
D
9
7
5
4
6
13 12 14 15
1
2
3
Q0 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13
001aad722
Fig 1. Functional diagram
CTR14
Q0
Q3
Q4
9
7
5
0
9
7
5
+
CT
10
11
Q5
Q6
Q7
Q8
4
6
4
6
10
11
CP
13
12
14
15
1
13
12
14
15
1
CT
Q9
MR
Q10
Q11
Q12
Q13
2
3
2
3
13
001aad723
001aad724
Fig 2. Logic symbol
Fig 3. IEC Logic symbol
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
FF
0
FF
1
FF
2
FF
3
FF
4
FF
5
FF
6
T
T
T
T
T
T
T
CP
Q
Q
RD
RD
RD
RD
RD
RD
RD
MR
Q0
Q3
Q4
Q5
Q6
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
FF
7
FF
8
FF
9
FF
10
FF
11
FF
12
FF
13
T
T
T
T
T
T
T
RD
RD
RD
RD
RD
RD
RD
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aad725
Fig 4. Logic diagram
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
2 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
6. Pinning information
6.1 Pinning
HEF4020B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Q11
Q12
Q13
Q5
V
DD
Q10
Q9
Q7
Q8
MR
CP
Q0
Q4
Q6
Q3
V
SS
001aaj101
Fig 5. Pin configuration
6.2 Pin description
Table 2.
Symbol
Q3 to Q13
VSS
Pin description
Pin
Description
7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3
parallel output (Q3 to Q13)
ground supply voltage
parallel output
8
Q0
9
CP
10
11
16
clock input (HIGH-to-LOW edge triggered)
master reset input (active HIGH)
supply voltage
MR
VDD
7. Functional description
Table 3.
Functional table[1]
Input
Output
Q0, Q3 to Q13
no change
count
CP
↑
MR
L
↓
L
X
H
L
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = positive-going transition; ↓ = negative-going transition.
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
3 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
1
2
4
8
16
32
64 128 256 512 1024 2048 4096 8192 16384
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
001aad726
Fig 6. Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
−0.5
-
Max
+18
Unit
V
supply voltage
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
±10
mA
V
VI
−0.5
-
VDD + 0.5
±10
IOK
output clamping current
input/output current
supply current
mA
mA
mA
°C
II/O
-
±10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
−65
−40
+150
+85
°C
Tamb −40 °C to +85 °C
[1]
[2]
DIP16 package
-
-
-
750
500
100
mW
mW
mW
SO16 package
P
power dissipation
per output
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
4 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
3
-
-
-
-
-
-
VI
input voltage
0
VDD
+85
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
−40
°C
∆t/∆V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
ns/V
ns/V
ns/V
0.08
10. Static characteristics
Table 6.
Static characteristics
VSS = 0 V; VI = VSS or VDD; unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = −40 °C Tamb = 25 °C
Tamb = 85 °C Unit
Min
Max
Min
Max
Min
Max
VIH
HIGH-level input voltage
|IO| < 1 µA
5 V
10 V
15 V
5 V
3.5
-
3.5
-
3.5
-
V
7.0
-
7.0
-
7.0
-
V
11.0
-
11.0
-
11.0
-
V
VIL
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
HIGH-level output current
|IO| < 1 µA
|IO| < 1 µA
|IO| < 1 µA
-
1.5
-
1.5
-
1.5
V
10 V
15 V
5 V
-
3.0
-
3.0
-
3.0
V
-
4.0
-
4.0
-
4.0
V
VOH
VOL
IOH
4.95
-
4.95
-
4.95
-
V
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
V
14.95
-
14.95
-
14.95
-
V
-
0.05
-
0.05
-
0.05
V
10 V
15 V
5 V
-
0.05
-
0.05
-
0.05
V
-
−1.7
−0.52
−1.3
−3.6
0.52
1.3
3.6
-
0.05
-
−1.4
−0.44
−1.1
−3.0
0.44
1.1
3.0
-
0.05
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
0.05
V
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
5 V
-
10 V
15 V
5 V
-
-
-
-
-
IOL
LOW-level output current
-
10 V
15 V
15 V
5 V
-
-
-
-
II
input leakage current
supply current
±0.3
20
40
80
-
±0.3
20
40
80
7.5
±1.0 µA
150 µA
300 µA
600 µA
IDD
IO = 0 A
-
-
-
10 V
15 V
-
-
-
-
-
-
-
CI
input capacitance
-
-
-
-
pF
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
5 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
11. Dynamic characteristics
Table 7.
Dynamic characteristics
VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula[1]
78 ns + (0.55 ns/pF) CL
34 ns + (0.23 ns/pF) CL
22 ns + (0.16 ns/pF) CL
53 ns + (0.55 ns/pF) CL
19 ns + (0.23 ns/pF) CL
12 ns + (0.16 ns/pF) CL
153 ns + (0.55 ns/pF) CL
79 ns + (0.23 ns/pF) CL
62 ns + (0.16 ns/pF) CL
78 ns + (0.55 ns/pF) CL
39 ns + (0.23 ns/pF) CL
27 ns + (0.16 ns/pF) CL
43 ns + (0.55 ns/pF) CL
14 ns + (0.23 ns/pF) CL
12 ns + (0.16 ns/pF) CL
10 ns + (1.00 ns/pF) CL
9 ns + (0.42 ns/pF) CL
6 ns + (0.28 ns/pF) CL
Min
Typ
105
45
30
80
30
20
180
90
70
105
50
35
70
25
20
60
30
20
25
15
10
65
50
45
60
35
25
10
25
35
Max Unit
tPHL
HIGH to LOW
CP to Q0;
see Figure 7
-
210
90
65
160
60
40
360
180
140
210
95
70
140
50
40
120
60
40
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
propagation delay
10 V
15 V
5 V
-
-
Qn to Qn + 1
-
10 V
15 V
5 V
-
-
MR to Qn;
see Figure 7
-
10 V
15 V
5 V
-
-
tPLH
LOW to HIGH
CP to Q0;
see Figure 7
-
propagation delay
10 V
15 V
5 V
-
-
Qn to Qn + 1
see Figure 7
-
10 V
15 V
5 V
-
-
tt
transition time
pulse width
-
10 V
15 V
5 V
-
-
tW
CP = HIGH;
minimum width;
see Figure 7
50
25
20
130
95
90
115
65
55
5
10 V
15 V
5 V
-
-
MR = HIGH;
minimum width;
see Figure 7
-
10 V
15 V
5 V
-
-
trec
recovery time
MR input;
see Figure 7
-
10 V
15 V
5 V
-
-
fmax
maximum
frequency
see Figure 7
-
10 V
15 V
13
18
-
-
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
6 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (µW)
PD = 600 × fi + Σ(fo × CL) × VDD
where:
2
PD
dynamic power
dissipation
fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
2
2
10 V
15 V
PD = 2800 × fi + Σ(fo × CL) × VDD
PD = 8200 × fi + Σ(fo × CL) × VDD
Σ(CL × fo) = sum of the outputs.
12. Waveforms
V
I
MR INPUT
V
M
V
SS
t
W
t
1/f
max
rec
V
I
CP INPUT
V
M
V
SS
t
W
t
t
t
PHL
PHL
PLH
V
OH
Q0 or Qn
OUTPUT
V
M
V
OL
t
t
t
t
001aae591
Measurement points are given in Table 9.
Fig 7. Propagation delays, minimum pulse widths, transition and recovery times and maximum clock frequency
Table 9. Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 8. Test circuit
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
7 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
Table 10. Test data
Supply voltage
VDD
Input
Load
VI
tr, tf
CL
5 V to 15 V
VSS or VDD
≤ 20 ns
50 pF
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
8 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 9. Package outline SOT38-4 (DIP16)
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
9 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
H
v
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 10. Package outline SOT109-1 (SO16)
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
10 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
14. Abbreviations
Table 11. Abbreviations
Acronym
DUT
Description
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
15. Revision history
Table 12. Revision history
Document ID
HEF4020B_4
Modifications:
Release date
20081204
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4020B_CNV_3
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Parallel output pins renamed Q0 to Q13 throughout.
• Temperature statement added to Section 1 “General description”.
• Section 2 “Features” added.
• Table 1 “Ordering information” restructured.
• Package version SOT38-1 changed to SOT38-4 in Section 4, and Figure 9. Package
SOT74 removed from Section 4.
• Figure 1 “Functional diagram”, Figure 4 “Logic diagram”, Figure 5 “Pin configuration”,
Figure 7 “Propagation delays, minimum pulse widths, transition and recovery times and
maximum clock frequency” and Figure 6 “Timing diagram” changed for pin name changes.
• Figure 2 “Logic symbol” and Figure 3 “IEC Logic symbol” added.
• Table 2 “Pin description” edited for pin name changes.
• Section 7 “Functional description” added.
•
Section 8 “Limiting values” and Section 10 “Static characteristics” added, taken from the
HE4000B Family Specifications data sheet.
• tRMR, tWCPH and tWMRH changed to trec and tW for Table 7 “Dynamic characteristics” and
Figure 7 “Propagation delays, minimum pulse widths, transition and recovery times and
maximum clock frequency”.
• 50 % replaced by VM for Figure 7 “Propagation delays, minimum pulse widths, transition
and recovery times and maximum clock frequency”.
• Table 9 “Measurement points”, Figure 8 “Test circuit” and Table 10 “Test data” added.
HEF4020B_CNV_3
HEF4020B_CNV_2
19950101
Product specification
-
HEF4020B_CNV_2
19950101
Product specification
-
-
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
11 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
16.2 Definitions
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4020B_4
© NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 4 December 2008
12 of 13
HEF4020B
NXP Semiconductors
14-stage binary counter
18. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11
8
9
10
11
12
13
14
15
16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
16.1
16.2
16.3
16.4
17
18
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 December 2008
Document identifier: HEF4020B_4
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