HEF4041BDF [NXP]
IC 4000/14000/40000 SERIES, QUAD 1-INPUT INV/NINV GATE, CDIP14, CERDIP-14, Gate;
| 型号： | HEF4041BDF |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, QUAD 1-INPUT INV/NINV GATE, CDIP14, CERDIP-14, Gate 栅 CD 输入元件 逻辑集成电路 |
| 文件： | 总4页 (文件大小：30K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4041B
buffers
Quadruple true/complement buffer
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4041B
buffers
Quadruple true/complement buffer
DESCRIPTION
The HEF4041B is a quadruple true/complement buffer
which provides both an inverted active LOW output
(O) and a non-inverted active HIGH output (O) for each
input (I).
The buffers exhibit high current output capability suitable
for driving TTL or high capacitive loads.
Fig.2 Pinning diagram.
HEF4041BP(N):
HEF4041BD(F):
HEF4041BT(D):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one buffer).
APPLICATION INFORMATION
Some examples of applications for the HEF4041B are:
• LOCMOS to DTL/TTL converter
• High current sink and source driver
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category BUFFERS
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4041B
buffers
Quadruple true/complement buffer
DC CHARACTERISTICS
VSS = 0 V; VI = VSS or VDD
Tamb (°C)
+25
VDD
V
VOH
V
VOL
V
SYMBOL
−40
+85
MIN. MAX. MIN. TYP. MIN. MAX.
Output (source) current
HIGH
5
10
15
5
4,6
9,5
1,6
4,5
1,3
3,6
2,6
7,0
1,0
2,7
mA
mA
mA
mA
mA
mA
mA
−IOH
−IOH
IOL
13,5
2,5
16,0
5,0
14,0 30,0 10,0
HIGH
4,0
8,0
4,0 1,35
4,5
20,0 35,0 15,0
3,0
Output (sink) current
LOW
4,75
10
15
0,4
2,0
1,7
0,5
1,5
7,5
6,0 12,0
23,0
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN.
TYP. MAX.
Propagation delays
In → On
HIGH to LOW
5
30
20
15
30
15
10
35
20
15
35
20
15
25
12
8
65 ns
17 ns
14 ns
12 ns
17 ns
9 ns
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
(0,27 ns/pF) CL
(0,11 ns/pF) CL
(0,08 ns/pF) CL
(0,27 ns/pF) CL
(0,11 ns/pF) CL
(0,08 ns/pF) CL
(0,27 ns/pF) CL
(0,11 ns/pF) CL
(0,08 ns/pF) CL
(0,27 ns/pF) CL
(0,11 ns/pF) CL
(0,08 ns/pF) CL
(0,40 ns/pF) CL
(0,21 ns/pF) CL
(0,14 ns/pF) CL
(0,40 ns/pF) CL
(0,21 ns/pF) CL
(0,14 ns/pF) CL
10
15
5
tPHL
tPLH
tPHL
tPLH
tTHL
tTLH
40 ns
30 ns
55 ns
30 ns
20 ns
75 ns
40 ns
30 ns
75 ns
40 ns
30 ns
50 ns
25 ns
20 ns
45 ns
25 ns
20 ns
LOW to HIGH
10
15
5
7 ns
In → On
22 ns
14 ns
12 ns
22 ns
14 ns
12 ns
5 ns
HIGH to LOW
10
15
5
LOW to HIGH
10
15
5
Output transition times
On → On
10
15
5
2 ns
HIGH to LOW
1 ns
25
12
8
5 ns
LOW to HIGH
10
15
2 ns
1 ns
January 1995
3
Philips Semiconductors
Product specification
HEF4041B
buffers
Quadruple true/complement buffer
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
2
Dynamic power
dissipation per
package (P)
5
3100 fi + ∑(foCL) × VDD
12 700 fi + ∑(foCL) × VDD
33 800 fi + ∑(foCL) × VDD
where
10
15
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
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