HEF4042BDB [NXP]
IC 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16, FF/Latch;
| 型号： | HEF4042BDB |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16, CERAMIC, DIP-16, FF/Latch |
| 文件： | 总6页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4042B
MSI
Quadruple D-latch
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4042B
MSI
Quadruple D-latch
DESCRIPTION
The HEF4042B is a 4-bit latch with four data inputs (D0 to
D3), four buffered latch outputs (O0 to O3), four buffered
complementary latch outputs (O0 to O3) and two common
enable inputs (E0 and E1). Information on D0 to D3 is
transferred to O0 to O3 while both E0 and E1 are in the
same state, either HIGH or LOW. O0 to O3 follow D0 to
D3 as long as both E0 and E1 remain in the same state.
When E0 and E1 are different, D0 to D3 do not affect O0 to
O3 and the information in the latch is stored.
O0 to O3 are always the complement of O0 to O3. The
exclusive-OR input structure allows the choice of either
polarity for E0 and E1. With one enable input HIGH, the
other enable input is active HIGH; with one enable input
LOW, the other enable input is active LOW.
Fig.2 Pinning diagram.
HEF4042BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4042BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4042BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
D0 to D3
E0 and E1
O0 to O3
O0 to O3
data inputs
enable inputs
parallel latch outputs
complementary parallel latch outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4042B are:
• Buffer storage
• Holding register
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
January 1995
2
Philips Semiconductors
Product specification
HEF4042B
MSI
Quadruple D-latch
FUNCTION TABLE
E0
E1
OUTPUT On
L
L
L
H
L
Dn
latched
latched
Dn
H
H
H
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage).
Fig.3 Logic diagram.
Fig.4 Logic diagram (one latch).
January 1995
3
Philips Semiconductors
Quadruple D-latch
AC CHARACTERISTICS
Product specification
HEF4042B
MSI
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN. TYP. MAX.
Propagation delays
D → O, O
HIGH to LOW
5
95
40
190 ns
80 ns
55 ns
175 ns
75 ns
60 ns
260 ns
105 ns
75 ns
245 ns
105 ns
75 ns
67 ns
28 ns
22 ns
57 ns
28 ns
22 ns
102 ns
38 ns
27 ns
92 ns
38 ns
27 ns
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
10
15
5
tPHL
30
85
LOW to HIGH
10
15
5
tPLH
tPHL
tPLH
40
30
E → O, O
130
50
HIGH to LOW
10
15
5
35
120
50
LOW to HIGH
10
15
35
Output transition
times
5
10
15
5
60
30
20
60
30
20
10
5
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
ns
10 ns
9 ns
6 ns
10 ns
9 ns
6 ns
+
+
+
+
+
+
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
HIGH to LOW
tTHL
tTLH
tsu
LOW to HIGH
10
15
5
Set-up time
30
20
20
15
15
15
90
40
30
D → E
10
15
5
ns
5
ns
Hold time
−5
0
ns
see also waveforms
Figs 5 and 6
D → E
10
15
5
thold
ns
0
ns
Minimum enable
pulse width
45
20
15
ns
10
15
tWE
ns
ns
VDD
V
TYPICAL FORMULA FOR P (W)
2
Dynamic power
dissipation per
package (P)
5
10
15
3800 fi + ∑ (foCL) × VDD
where
2
15 700 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
2
41 100 fi + ∑ (foCL) × VDD
V
DD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4042B
MSI
Quadruple D-latch
Either E0 or E1 is held HIGH or LOW while the other enable input is pulsed as
the function table shows.
Fig.5 Waveforms showing propagation delays for D to O, with latch enabled.
January 1995
5
Philips Semiconductors
Product specification
HEF4042B
MSI
Quadruple D-latch
Fig.6 Waveforms showing minimum enable pulse width, set-up time and hold time for E and D. Set-up and
hold-times are shown as positive values but may be specified as negative values.
January 1995
6
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