HEF4043B [NXP]
Quadruple R/S latch with 3-state outputs; 四R / S与三态输出锁存器
| 型号： | HEF4043B |
| 厂家： | 
NXP |
| 描述： | Quadruple R/S latch with 3-state outputs |
| 文件： | 总6页 (文件大小：51K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4043B
MSI
Quadruple R/S latch with 3-state
outputs
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4043B
MSI
Quadruple R/S latch with 3-state outputs
DESCRIPTION
The HEF4043B is a quadruple R/S latch with 3-state
outputs with a common output enable input (EO). Each
latch has an active HIGH set input (S0 to S3), an active
HIGH reset input (R0 to R3) and an active HIGH 3-state
output (O0 to O3).
When EO is HIGH, the state of the latch output (On) can be
determined from the function table below. When EO is
LOW, the latch outputs are in the high impedance
OFF-state. EO does not affect the state of the latch.
Fig.2 Pinning diagram.
The high impedance off-state feature allows common
busing of the outputs.
HEF4043BP(N): 16-lead DIL; plastic (SOT38-1)
HEF4043BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4043BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
PINNING
EO
common output enable input
set inputs (active HIGH)
S0 to S3
R0 to R3
O0 to O3
reset inputs (active HIGH)
3-state buffered latch outputs
FUNCTION TABLE
INPUTS
Sn
OUTPUT
On
EO
L
Rn
X
X
L
Z
H
H
X
L
H
H
H
L
H
L
latched
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state immaterial
Z = high impedance state
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4043B
MSI
Quadruple R/S latch with 3-state outputs
Fig.4 Logic diagram (one latch).
Fig.3 Logic diagram.
January 1995
3
Philips Semiconductors
Product specification
HEF4043B
MSI
Quadruple R/S latch with 3-state outputs
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
Rn → On
HIGH to LOW
5
90
35
25
65
25
15
60
30
20
60
30
20
180
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
63 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
38 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
7 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 tPHL
15
50
Sn → On
LOW to HIGH
5
135
50
10 tPLH
15
35
Output transition
times
5
120
60
10 tTHL
HIGH to LOW
15
40
5
120
60
LOW to HIGH
10 tTLH
15
40
3-state propagation delays
Output disable times
EO → On
5
45
20
10
50
20
10
90
35
ns
ns
ns
ns
ns
ns
HIGH
10 tPHZ
15
25
5
100
40
LOW
10 tPLZ
15
25
Output enable times
EO → On
5
25
15
10
40
20
15
15
10
8
50
30
25
80
45
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HIGH
10 tPZH
15
5
LOW
10 tPZL
15
Minimum Sn
5
30
20
16
30
20
16
pulse width; HIGH
10 tWSH
15
see also waveforms
Fig.5
Minimum Rn
5
15
10
8
pulse width; HIGH
10 tWRH
15
January 1995
4
Philips Semiconductors
Product specification
HEF4043B
MSI
Quadruple R/S latch with 3-state outputs
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
Dynamic power
dissipation per
package (P)
5
1100 fi + ∑(foCL) × VDD
where
10
15
4400 fi + ∑(foCL) × VDD
fi = input freq. (MHz)
2
11 400 fi + ∑(foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑(foCL) = sum of outputs
VDD = supply voltage (V)
Fig.5 Waveforms showing minimum Sn and Rn pulse widths.
APPLICATION INFORMATION
An example of application for the HEF4043B is:
• Four-bit storage with output enable
January 1995
5
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