HEF4049BP [NXP]
HEX inverting buffers; HEX反相缓冲器
| 型号： | HEF4049BP |
| 厂家： | 
NXP |
| 描述： | HEX inverting buffers |
| 文件： | 总5页 (文件大小：36K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4049B
buffers
HEX inverting buffers
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4049B
buffers
HEX inverting buffers
DESCRIPTION
HEF4049BP(N): 16-lead DIL; plastic (SOT38-1)
The HEF4049B provides six inverting buffers with high
current output capability suitable for driving TTL or high
capacitive loads. Since input voltages in excess of the
buffers’ supply voltage are permitted, the buffers may also
be used to convert logic levels of up to 15 V to standard
TTL levels. Their guaranteed fan-out into common bipolar
logic elements is shown in the table below.
HEF4049BD(F): 16-lead DIL; ceramic (cerdip) (SOT74)
HEF4049BT(D): 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
Guaranteed fan-out in common logic families
GUARANTEED
DRIVEN ELEMENT
FAN-OUT
standard TTL
74 LS
2
9
74 L
16
Fig.3 Logic diagram (one gate).
APPLICATION INFORMATION
Some examples of applications for the HEF4049B are:
• LOCMOS to DTL/TTL converter
• HIGH sink current for driving 2 TTL loads
• HIGH-to-LOW level logic conversion
Fig.1 Functional diagram.
Input protection
Fig.4 Input protection circuit that allows input
voltages in excess of VDD
.
Fig.2 Pinning diagram.
FAMILY DATA, IDD LIMITS category BUFFERS
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4049B
buffers
HEX inverting buffers
DC CHARACTERISTICS
VSS = 0 V; VI = VSS or VDD
T
amb (°C)
VDD
V
VO
V
HEF
SYMBOL
−40
+25
+85
MIN.
MAX.
MIN.
MAX.
MN.
MAX.
Output (sink)
current LOW
4,75
10
15
5
0,4
0,5
3,5
12,0
24,0
−
−
−
−
−
−
2,9
10,0
20,0
−
−
−
−
−
−
2,3
8,0
−
−
−
−
−
−
mA
mA
mA
mA
mA
mA
IOL
1,5
16,0
Output (source)
current HIGH
4,6
0,52
1,3
0,44
1,1
0,36
10
15
9,5
IOH
0,9
2,4
13,5
3,6
3,0
Output (source)
current HIGH
5
2,5
IOH
1,7
−
1,4
−
1,1
−
mA
Tamb (°C)
+25
VDD
V
VO
V
HEC
SYMBOL
−55
+125
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Output (sink)
current LOW
4,75
10
15
5
0,4
3,6
12,5
25,0
−
−
−
−
−
−
2,9
10,0
20,0
−
−
−
1,9
6,7
−
−
−
−
−
−
mA
mA
mA
mA
mA
mA
0,5 IOL
1,5
13,0
0,36
0,9
Output (source)
current HIGH
4,6
0,52
0,44
1,1
−
−
−
10
15
9,5
IOH
1,3
3,6
13,5
3,0
2,4
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
In → On
5
10
15
5
35
15
12
50
25
20
20
10
7
70
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
26 ns + (0,18 ns/pF) CL
11 ns + (0,08 ns/pF) CL
9 ns + (0,05 ns/pF) CL
23 ns + (0,55 ns/pF) CL
14 ns + (0,23 ns/pF) CL
12 ns + (0,16 ns/pF) CL
3 ns + (0,35 ns/pF) CL
3 ns + (0,14 ns/pF) CL
2 ns + (0,09 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
tPHL
tPLH
tTHL
tTLH
HIGH to LOW
25
100
50
LOW to HIGH
10
15
5
40
Output transition
times
40
10
15
5
20
HIGH to LOW
14
60
30
20
120
60
LOW to HIGH
10
15
40
January 1995
3
Philips Semiconductors
Product specification
HEF4049B
buffers
HEX inverting buffers
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
2 500 fi + ∑ (foCL) × VDD
where
2
11 000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
35 000 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
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