HEF4053BTT [NXP]
Triple single-pole double-throw analog switch; 三重单刀双掷模拟开关
| 型号： | HEF4053BTT |
| 厂家： | 
NXP |
| 描述： | Triple single-pole double-throw analog switch |
| 文件： | 总20页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4053B
Triple single-pole double-throw analog switch
Rev. 10 — 17 November 2011
Product data sheet
1. General description
The HEF4053B is a triple single-pole double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input
(Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All
three switches share an enable input (E). A HIGH on E causes all switches into the
high-impedance OFF-state, independent of Sn.
VDD and VSS are the supply voltage connections for the digital control inputs (Sn and E).
The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not
exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically
ground). VEE and VSS are the supply voltage connections for the switches.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
Table 1.
Ordering information
All types operate from 40 C to +125 C.
Type number
Package
Name
Description
Version
HEF4053BP
HEF4053BT
HEF4053BTT
DIP16
plastic dual in-line package; 16 leads (300 mil)
plastic small outline package; 16 leads; body width 3.9 mm
plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT38-4
SOT109-1
SOT403-1
SO16
TSSOP16
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
5. Functional diagram
E
6
V
DD
16
13 1Y1
12 1Y0
14 1Z
LOGIC
LEVEL
CONVERSION
S1 11
DECODER
1
2
2Y1
2Y0
LOGIC
LEVEL
S2 10
CONVERSION
11
10
9
S1
S2
S3
1Y0
1Y1
1Z
12
13
14
2
15 2Z
3
5
4
3Y1
2Y0
2Y1
2Z
1
LOGIC
LEVEL
CONVERSION
S3
9
3Y0
3Z
15
5
3Y0
3Y1
3Z
3
6
E
4
8
7
V
V
EE
001aae124
SS
001aae125
Fig 1. Logic symbol
Fig 2. Functional diagram
nZ
nY1
LEVEL
CONVERTER
Sn
nY0
LEVEL
CONVERTER
E
to other multiplexers/demultiplexers
001aae645
Fig 3. Logic diagram (one multiplexer/demultiplexer)
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
2 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
nYn
V
V
DD
DD
V
EE
nZ
from decoder
and enable logic
001aae644
Fig 4. Schematic diagram (one switch)
6. Pinning information
6.1 Pinning
HEF4053B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
3Z
V
DD
2Z
HEF4053B
1Z
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2Y1
2Y0
3Y1
3Z
V
DD
1Y1
1Y0
S1
2Z
1Z
3Y0
E
1Y1
1Y0
S1
3Y0
E
V
S2
EE
SS
V
S2
EE
SS
V
S3
V
S3
001aae643
001aaj899
Fig 5. Pin configuration for SOT38-4 (DIP16) and
SOT109-1 (SO16)
Fig 6. Pin configuration for SOT403-1 (TSSOP16)
6.2 Pin description
Table 2.
Symbol
E
Pin description
Pin
6
Description
enable input (active LOW)
supply voltage
VEE
7
VSS
8
ground supply voltage
select input
S1, S2, S3
11, 10, 9
12, 2, 5
13, 1, 3
14, 15, 4
16
1Y0, 2Y0, 3Y0
1Y1, 2Y1, 3Y1
1Z, 2Z, 3Z
VDD
independent input or output
independent input or output
independent output or input
supply voltage
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
3 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
7. Functional description
Table 3.
Function table [1]
Inputs
Channel on
E
L
Sn
L
nY0 to nZ
L
H
nY1 to nZ
H
X
switches OFF
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
VDD
Parameter
Conditions
Min
0.5
18
-
Max
+18
+0.5
10
Unit
V
supply voltage
supply voltage
input clamping current
[1]
VEE
referenced to VDD
V
IIK
pins Sn and E;
mA
VI < 0.5 V or VI > VDD + 0.5 V
VI
input voltage
0.5
-
VDD + 0.5
10
V
II/O
input/output current
supply current
mA
mA
C
C
IDD
Tstg
Tamb
Ptot
-
50
storage temperature
ambient temperature
total power dissipation
65
40
+150
+125
[2]
Tamb = 40 C to +125 C
DIP16 package
-
-
-
-
750
500
500
100
mW
mW
mW
mW
SO16 package
TSSOP16 package
per output
P
power dissipation
[1] To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there
is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE
.
[2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
3
Typ
Max
15
Unit
V
supply voltage
input voltage
see Figure 7
in free air
-
-
-
VI
0
VDD
+125
V
Tamb
ambient temperature
40
C
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
4 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 5.
Symbol
t/V
Recommended operating conditions …continued
Parameter Conditions
Min
Typ
Max
3.75
0.5
Unit
s/V
s/V
s/V
input transition rise and fall VDD = 5 V
-
-
-
-
-
-
rate
VDD = 10 V
VDD = 15 V
0.08
001aae646
15
V
DD
− V
SS
(V)
10
operating area
5
0
0
5
10
15
V
− V (V)
EE
DD
Fig 7. Operating area as a function of the supply voltages
10. Static characteristics
Table 6.
Static characteristics
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit
Min
Max
-
Min
Max
-
Min
Max
-
Min
Max
-
VIH
HIGH-level
input voltage
IO < 1 A
5 V
10 V
15 V
5 V
3.5
3.5
3.5
3.5
V
V
V
V
V
V
7.0
-
7.0
-
7.0
-
7.0
-
11.0
-
11.0
-
11.0
-
11.0
-
VIL
LOW-level
input voltage
IO < 1 A
-
-
-
-
1.5
3.0
4.0
0.1
-
-
-
-
1.5
3.0
4.0
0.1
-
-
-
-
1.5
3.0
4.0
1.0
-
-
-
-
1.5
3.0
4.0
10 V
15 V
15 V
II
input leakage
current
1.0 A
IS(OFF)
OFF-state
leakage
current
Z port;
all channels OFF;
see Figure 8
15 V
15 V
-
-
-
-
-
-
1000
200
-
-
-
-
-
-
-
-
nA
nA
Y port;
per channel;
see Figure 9
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
5 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 6.
Static characteristics …continued
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter
Conditions
VDD
Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 C Unit
Min
Max
5
Min
Max
5
Min
Max
150
300
600
-
Min
Max
IDD
supply current IO = 0 A
5 V
10 V
15 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
150 A
300 A
600 A
10
20
-
10
20
CI
input
Sn, E inputs
7.5
-
pF
capacitance
10.1 Test circuits
V
DD
S1 to S3
nY0
nY1
1
2
V
or V
SS
DD
switch
nZ
E
I
S
V
SS
= V
EE
V
DD
V
V
O
I
001aaj900
Fig 8. Test circuit for measuring OFF-state leakage current Z port
V
DD
S1 to S3
nY0
nY1
1
2
V
or V
DD
SS
switch
I
S
nZ
E
V
SS
= V
EE
V
SS
V
V
I
O
001aaj901
Fig 9. Test circuit for measuring OFF-state leakage current nYn port
10.2 ON resistance
Table 7.
ON resistance
Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V.
Symbol Parameter
Conditions
VI = 0 V to VDD VEE
see Figure 10 and Figure 11
VDD VEE Typ
Max
2500
245
Unit
RON(peak) ON resistance (peak)
;
5 V
350
80
10 V
15 V
60
175
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
6 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
Table 7.
ON resistance …continued
Tamb = 25 C; ISW = 200 A; VSS = VEE = 0 V.
Symbol Parameter
Conditions
VDD VEE Typ
Max
340
160
115
365
200
155
-
Unit
RON(rail)
ON resistance (rail)
VI = 0 V; see Figure 10 and Figure 11 5 V
115
50
40
120
65
50
25
10
5
10 V
15 V
5 V
VI = VDD VEE
see Figure 10 and Figure 11
;
10 V
15 V
5 V
RON
ON resistance mismatch
between channels
VI = 0 V to VDD VEE; see Figure 10
10 V
15 V
-
-
10.2.1 ON resistance waveform and test circuit
V
V
V
SW
DD
S1 to S3
nY0
nY1
1
2
V
or V
DD
SS
switch
nZ
E
V
SS
= V
EE
V
SS
I
V
I
SW
001aaj902
RON = VSW / ISW
.
Fig 10. Test circuit for measuring RON
001aae648
400
R
ON
(Ω)
V
= 5 V
DD
300
200
100
0
10 V
15 V
0
5
10
15
V (V)
I
Fig 11. Typical RON as a function of input voltage
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
7 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Tamb = 25 C; VSS = VEE = 0 V; for test circuit see Figure 15.
Symbol Parameter Conditions
tPHL
VDD
5 V
Typ
10
Max
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Figure 12
Sn to nYn, nZ; see Figure 13
10 V
15 V
5 V
5
10
5
10
200
85
400
170
130
30
10 V
15 V
5 V
65
tPLH
LOW to HIGH propagation delay nYn, nZ to nZ, nYn; see Figure 12
Sn to nYn, nZ; see Figure 13
15
10 V
15 V
5 V
5
10
5
10
275
100
65
555
200
130
400
230
220
525
190
130
400
245
215
565
205
140
10 V
15 V
5 V
tPHZ
tPZH
tPLZ
tPZL
HIGH to OFF-state
propagation delay
E to nYn, nZ; see Figure 14
E to nYn, nZ; see Figure 14
E to nYn, nZ; see Figure 14
E to nYn, nZ; see Figure 14
200
115
110
260
95
10 V
15 V
5 V
OFF-state to HIGH
propagation delay
10 V
15 V
5 V
65
LOW to OFF-state
propagation delay
200
120
110
280
105
70
10 V
15 V
5 V
OFF-state to LOW
propagation delay
10 V
15 V
11.1 Waveforms and test circuit
V
DD
nYn or nZ
input
V
V
M
DD
Sn input
V
M
V
V
EE
V
V
SS
t
t
PLH
PHL
t
t
PHL
PLH
V
V
O
O
90 %
nYn or nZ
output
nZ or nYn
output
V
M
10 %
switch ON
EE
switch OFF
switch OFF
EE
001aac290
001aac291
Measurement points are given in Table 9.
Measurement points are given in Table 9.
Fig 12. nYn, nZ to nZ, nYn propagation delays
Fig 13. Sn to nYn, nZ propagation delays
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
8 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
V
DD
E input
V
M
V
V
V
SS
t
t
PLZ
PZL
V
O
90 %
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
10 %
EE
t
t
PHZ
PZH
V
O
90 %
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
10 %
EE
switch ON
switch OFF
switch ON
001aac292
Measurement points are given in Table 9.
Fig 14. Enable and disable times
Table 9. Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
9 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
M
positive
pulse
V
M
10 %
0 V
t
W
V
V
DD
V
V
I
DD
V
I
S1
O
R
L
PULSE
GENERATOR
open
DUT
R
T
C
L
V
V
SS
EE
001aaj903
Test data is given in Table 10.
Definitions:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including test jig and probe.
RL = Load resistance.
Fig 15. Test circuit for measuring switching times
Table 10. Test data
Input
Load
CL
S1 position
[1]
nYn, nZ
Sn and E tr, tf
VM
RL
tPHL
tPLH
tPZH, tPHZ tPZL, tPLZ other
VEE VDD VEE
VDD or VEE VDD or VSS 20 ns
0.5VDD
50 pF
10 k
VDD or VEE VEE
[1] For nYn to nZ or nZ to nYn propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD
.
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
10 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
11.2 Additional dynamic parameters
Table 11. Additional dynamic characteristics
VSS = VEE = 0 V; Tamb = 25 C.
Symbol
Parameter
Conditions
VDD
Typ
0.25
0.04
0.04
13
Max
Unit
%
[1]
[1]
[1]
[1]
[1]
[1]
[1]
THD
total harmonic distortion
see Figure 16; RL = 10 k; CL = 15 pF; 5 V
channel ON; VI = 0.5VDD (p-p);
fi = 1 kHz
-
-
-
-
-
-
-
10 V
%
15 V
5 V
%
f(3dB)
3 dB frequency response see Figure 17; RL = 1 k; CL = 5 pF;
MHz
MHz
MHz
dB
channel ON; VI = 0.5VDD (p-p)
10 V
15 V
10 V
40
70
iso
isolation (OFF-state)
crosstalk voltage
crosstalk
see Figure 18; fi = 1 MHz; RL = 1 k;
CL = 5 pF; channel OFF;
VI = 0.5VDD (p-p)
50
Vct
digital inputs to switch; see Figure 19; 10 V
RL = 10 k; CL = 15 pF;
E or Sn = VDD (square-wave)
50
-
mV
dB
[1]
Xtalk
between switches; see Figure 20;
fi = 1 MHz; RL = 1 k;
10 V
50
-
VI = 0.5VDD (p-p)
[1] fi is biased at 0.5 VDD; VI = 0.5VDD (p-p).
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VEE = VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
where:
2
PD
dynamic power
dissipation
PD = 2500 fi + (fo CL) VDD
fi = input frequency in MHz;
fo = output frequency in MHz;
2
2
10 V
15 V
PD = 11500 fi + (fo CL) VDD
CL = output load capacitance in pF;
DD = supply voltage in V;
(CL fo) = sum of the outputs.
PD = 29000 fi + (fo CL) VDD
V
11.2.1 Test circuits
V
V
DD
DD
S1 to S3
nY0
nY1
1
2
S1 to S3
nY0
nY1
1
2
V
or V
V
or V
DD
DD
SS
SS
switch
R
switch
R
nZ
E
nZ
E
V
SS
= V
V
SS
= V
EE
EE
V
SS
C
L
V
SS
C
L
D
dB
L
L
f
f
i
i
001aaj904
001aaj905
Fig 16. Test circuit for measuring total harmonic
distortion
Fig 17. Test circuit for measuring frequency response
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
11 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
V
DD
S1 to S3
nY0
nY1
1
2
V
or V
DD
SS
switch
nZ
E
V
SS
= V
EE
V
SS
R
L
C
L
dB
f
i
001aaj906
Fig 18. Test circuit for measuring isolation (OFF-state)
0.5V
V
DD
DD
R
L
S1 to S3
nY0
nY1
1
switch
nZ
E
2
G
V
SS
= V
EE
R
L
C
L
V
O
V
V
or V
SS
DD
001aaj907
a. Test circuit
logic
input (Sn, E)
off
on
off
V
V
ct
O
001aaj908
b. Input and output pulse definitions
Fig 19. Test circuit for measuring crosstalk voltage between digital inputs and switch
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
12 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
V
DD
V
DD
S1 to S3
nY0
nY1
S1 to S3
nY0
nY1
V
DD
or V
SS
SS
V
or V
DD
SS
nZ
E
nZ
E
V
= V
EE
SS
V
= V
EE
SS
V
V
R
L
I
V
SS
R
L
V
R
L
O
R
L
V
O
V
I
001aaj909
001aaj910
a. Switch closed condition
Fig 20. Test circuit for measuring crosstalk between switches
b. Switch open condition
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
13 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
12. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 21. Package outline SOT38-4 (DIP16)
HEF4053B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
14 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 22. Package outline SOT109-1 (SO16)
HEF4053B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
15 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
D
E
A
X
c
y
H
v
M
A
E
Z
9
16
Q
(A )
3
A
2
A
A
1
pin 1 index
θ
L
p
L
1
8
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.40
0.06
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-18
SOT403-1
MO-153
Fig 23. Package outline SOT403-1 (TSSOP16)
HEF4053B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
16 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
13. Revision history
Table 13. Revision history
Document ID
HEF4053B v.10
Modifications:
Release date
20111117
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4053B v.9
• Legal pages updated.
• Changes in “General description”, “Features and benefits” and “Applications”.
HEF4053B v.9
20100325
20100224
20091127
20090924
20090825
20090713
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
-
-
-
-
HEF4053B v.8
HEF4053B v.7
HEF4053B v.6
HEF4053B v.5
HEF4053B v.4
HEF4053B_CNV v.3
HEF4053B_CNV v.2
-
HEF4053B v.8
HEF4053B v.7
HEF4053B v.6
HEF4053B v.5
HEF4053B v.4
HEF4053B_CNV v.3
HEF4053B_CNV v.2
HEF4053B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
17 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
14.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
14.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
HEF4053B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
18 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4053B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
19 of 20
HEF4053B
NXP Semiconductors
Triple single-pole double-throw analog switch
16. Contents
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
8
9
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
10
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
ON resistance waveform and test circuit . . . . . 7
10.1
10.2
10.2.1
11
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms and test circuit . . . . . . . . . . . . . . . . 8
Additional dynamic parameters . . . . . . . . . . . 11
Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
11.1
11.2
11.2.1
12
13
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
14
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
14.1
14.2
14.3
14.4
15
16
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 17 November 2011
Document identifier: HEF4053B
相关型号：
HEF4059BDF
IC 4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED DOWN DIVIDE BY N COUNTER, CDIP24, SOT-94, CERDIP-24, Counter
NXP
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