HEF4066BD [NXP]

Quadruple bilateral switches; 四双边开关


型号：	HEF4066BD
厂家：	NXP
描述：	Quadruple bilateral switches 四双边开关复用器开关复用器或开关信号电路输出元件
文件：	总8页 (文件大小：92K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC

• The IC04 LOCMOS HE4000B Logic

Package Outlines/Information HEF, HEC

HEF4066B

gates

Quadruple bilateral switches

January 1995

Product speciﬁcation

File under Integrated Circuits, IC04

Philips Semiconductors

Product speciﬁcation

HEF4066B

gates

Quadruple bilateral switches

disabled and a high impedance between Y and Z is

DESCRIPTION

established (OFF condition).

The HEF4066B has four independent bilateral analogue

switches (transmission gates). Each switch has two

input/output terminals (Y/Z) and an active HIGH enable

input (E). When E is connected to V_DDa low impedance

bidirectional path between Y and Z is established (ON

condition). When E is connected to V_SSthe switch is

The HEF4066B is pin compatible with the HEF4016B but

exhibits a much lower ON resistance. In addition the ON

resistance is relatively constant over the full input signal

range.

Fig.1 Functional diagram.

Fig.2 Pinning diagram.

PINNING

HEF4066BP(N): 14-lead DIL; plastic (SOT27-1)

E₀to E₃

Y₀to Y₃

Z₀to Z₃

enable inputs

HEF4066BD(F): 14-lead DIL; ceramic (cerdip)

(SOT73))

input/output terminals

HEF4066BT(D): 14-lead SO; plastic (SOT108-1)

( ): Package Designator North America

APPLICATION INFORMATION

An example of application for the HEF4066B is:

• Analogue and digital switching

Fig.3 Schematic diagram (one switch).

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4066B

gates

Quadruple bilateral switches

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

Power dissipation per switch

max. 100 mW

For other RATINGS see Family Speciﬁcations

DC CHARACTERISTICS

T_amb= 25 °C

V_DD

SYMBOL MIN. TYP. MAX.

CONDITIONS

E_nat V_DD

−

350 2500 Ω

ON resistance

R_ON

∆R_ON

I_OZ

245 Ω

175 Ω

340 Ω

160 Ω

115 Ω

365 Ω

200 Ω

155 Ω

V_is= V_SSto V_DD

see Fig.4

115

E_nat V_DD

V_is= V_SS

see Fig.4

120

E_nat V_DD

V_is= V_DD

see Fig.4

‘∆’ ON resistance

between any two

channels

−

Ω

E_nat V_DD

Ω

V_is= V_SSto V_DD

see Fig.4

Ω

OFF state leakage

current, any

−

E_nat V_SS

channel OFF

E_ninput voltage

LOW

−

200 nA

1 V

2,25

4,50

6,75

I_is= 10 µA

see Fig.9

V_IL

2 V

V_DD

SYMBOL

T_amb(°c)

CONDITIONS

−40

+25

+85

MAX. MAX. MAX.

Quiescent device

current

1,0

2,0

4,0

−

1,0

2,0

4,0

7,5 µA

15,0 µA

30,0 µA

V_SS= 0; all valid

input combinations;

V_I= V_SSor V_DD

E_nat V_SSor V_DD

I_DD

Input leakage current at E_n

± I_IN

300 1000 nA

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4066B

gates

Quadruple bilateral switches

Fig.4 Test set-up for measuring R_ON

E_nat V_DD

I_is= 200 µA

V_SS= 0 V

Fig.5 Typical R_ONas a function of input voltage.

NOTE

To avoid drawing V_DDcurrent out of terminal Z, when switch current flows into terminals Y, the voltage drop across the

bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no V_DDcurrent will flow out of

terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not

exceed V_DDor V_SS

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4066B

gates

Quadruple bilateral switches

(2)

AC CHARACTERISTICS ⁽¹⁾

V_SS= 0 V; T_amb= 25 °C; input transition times ≤ 20 ns

V_DD

SYMBOL TYP.

MAX.

Propagation delays

V_is→ V_os

HIGH to LOW

t_PHL

note 3

LOW to HIGH

t_PLH

Output disable times

E_n→ V_os

160

130

120

160

140

HIGH

t_PHZ

note 4

LOW

t_PLZ

Output enable times

E_n→ V_os

0,25

0,04

−

HIGH

t_PZH

note 4

note 5

note 6

note 7

note 8

note 9

LOW

t_PZL

Distortion, sine-wave

response

Crosstalk between

any two channels

MHz

−

Crosstalk; enable

input to output

−

OFF-state

−

feed-through

−

ON-state frequency

response

−

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4066B

gates

Quadruple bilateral switches

V_DD

TYPICAL FORMULA FOR P (µW)

Dynamic power

dissipation per

package (P)

800 f_i+ ∑ (f_oC_L) × V_DD

3 500 f_i+ ∑ (f_oC_L) × V_DD

10 100 f_i+ ∑ (f_oC_L) × V_DD

where

f_i= input freq. (MHz)

f_o= output freq. (MHz)

C_L= load capacitance (pF)

∑ (f_oC_L) = sum of outputs

V_DD= supply voltage (V)

Notes

1. V_isis the input voltage at a Y or Z terminal, whichever is assigned as input.

2. V_osis the output voltage at a Y or Z terminal, whichever is assigned as output.

3. R_L= 10 kΩ to V_SS; C_L= 50 pF to V_SS; E_n= V_DD; V_is= V_DD(square-wave); see Figs 6 and 10.

4. R_L= 10 kΩ; C_L= 50 pF to V_SS; E_n= V_DD(square-wave);

V_is= V_DDand R_Lto V_SSfor t_PHZand t_PZH

;

V_is= V_SSand R_Lto V_DDfor t_PLZand t_PZL; see Figs 6 and 11.

5. R_L= 10 kΩ; C_L= 15 pF; E_n= V_DD; V_is= ¹⁄₂V_DD(p-p)(sine-wave, symmetrical about ¹⁄₂V_DD); f_is= 1 kHz; see Fig.7.

6. R_L= 1 kΩ; V_is= ¹⁄₂V_DD(p-p)(sine-wave, symmetrical about ¹⁄₂V_DD);

V_os(B)

------------------

20 log

= -50 dB; E_n(A) = V_SS; E_n(B) = V_DD; see Fig. 8.

_is(A)

7. R_L= 10 kΩ to V_SS; C_L= 15 pF to V_SS; E_n= V_DD(square-wave); crosstalk is V_os(peak value); see Fig.6.

8. R_L= 1 kΩ; C_L= 5 pF; E_n= V_SS; V_is= ¹⁄₂V_DD(p-p)(sine-wave, symmetrical about ¹⁄₂V_DD);

V_os

--------

20 log

= -50 dB; see Fig. 7.

V_is

9. R_L= 1 kΩ; C_L= 5 pF; E_n= V_DD; V_is= ¹⁄₂V_DD(p-p)(sine-wave, symmetrical about ¹⁄₂V_DD);

V_os

--------

20 log

= -3 dB; see Fig. 7.

V_is

Fig.6

Fig.7

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4066B

gates

Quadruple bilateral switches

Fig.8

Fig.9

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4066B

gates

Quadruple bilateral switches

Fig.10 Waveforms showing propagation delays from V_isto V_os.

(1) V_isat V_DD

(2) V_isat V_SS

Fig.11 Waveforms showing output disable and enable times.

January 1995

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