HEF4072BT [NXP]
Dual 4-input OR gate; 双路4输入或门
| 型号： | HEF4072BT |
| 厂家： | 
NXP |
| 描述： | Dual 4-input OR gate |
| 文件： | 总4页 (文件大小：32K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4072B
gates
Dual 4-input OR gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4072B
gates
Dual 4-input OR gate
DESCRIPTION
The HEF4072B provides the positive dual 4-input OR
function. The outputs are fully buffered for highest noise
immunity and pattern insensitivity of output impedance.
Fig.2 Pinning diagram.
HEF4072BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4072BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4072BT(D): 14-lead SO; plastic
(SOT108-1)
Fig.1 Functional diagram.
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4072B
gates
Dual 4-input OR gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
In → On
HIGH to LOW
5
80
35
25
75
35
25
60
30
20
60
30
20
155
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
53 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
48 ns + (0,55 ns/pF) CL
24 ns + (0,23 ns/pF) CL
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tPHL
55
145
70
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
55
Output transition times
HIGH to LOW
120
60
10
15
5
40
120
60
LOW to HIGH
10
15
40
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
950 fi + ∑ (foCL) × VDD
where
2
10
15
4500 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
2
13 700 fi + ∑ (foCL) × VDD
VDD = supply voltage (V)
January 1995
3
WWW.ALLDATASHEET.COM
Copyright © Each Manufacturing Company.
All Datasheets cannot be modified without permission.
This datasheet has been download from :
www.AllDataSheet.com
100% Free DataSheet Search Site.
Free Download.
No Register.
Fast Search System.
www.AllDataSheet.com
相关型号：
©2020 ICPDF网 联系我们和版权申明