HEF4076BTD-T [NXP]
IC 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, PLASTIC, SOT-109-1, SO-16, FF/Latch;
| 型号： | HEF4076BTD-T |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, PLASTIC, SOT-109-1, SO-16, FF/Latch 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：68K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4076B
MSI
Quadruple D-type register with
3-state outputs
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4076B
MSI
Quadruple D-type register with 3-state outputs
Information on D0 to D3 is stored in the four flip-flops on the
LOW to HIGH transition of CP if both ED0 and ED1 are
LOW. A HIGH on either ED0 or ED1 prevents the flip-flops
from changing on the LOW to HIGH transition of CP,
independent of the information on D0 to D3. When both
EO0 and EO1 are LOW, the contents of the four flip-flops
are available at O0 to O3. A HIGH on either EO0 or
EO1 forces O0 to O3 into the high impedance OFF-state. A
HIGH on MR resets all four flip-flops, independent of all
other input conditions.
DESCRIPTION
The HEF4076B is a quadruple edge-triggered D-type
flip-flop with four data inputs (D0 to D3), two active LOW
data enable inputs (ED0 and ED1), a common clock input
(CP), four 3-state outputs (O0 to O3), two active LOW
output enable inputs (EO0 and EO1), and an overriding
asynchronous master reset input (MR).
Fig.2 Pinning diagram.
HEF4076BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4076BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4076BT(D): 16-lead SO; plastic
(SOT109-1)
Fig.1 Functional diagram.
( ): Package Designator North America
PINNING
FAMILY DATA, IDD LIMITS category MSI
D0 to D3
ED0, ED1
EO0, EO1
CP
data inputs
See Family Specifications
data enable inputs (active LOW)
output enable inputs (active LOW)
clock input (LOW to HIGH, edge-triggered)
master reset input
MR
O0 to O3
data outputs
January 1995
2
Philips Semiconductors
Product specification
HEF4076B
MSI
Quadruple D-type register with 3-state outputs
Fig.3 Logic diagram.
January 1995
3
Philips Semiconductors
Product specification
HEF4076B
MSI
Quadruple D-type register with 3-state outputs
Notes
FUNCTION TABLE
INPUTS
1. EO0 = EO1 = LOW
OUTPUTS
On
When either EO0 or EO1 is HIGH, the outputs are
disabled (high impedance OFF-state).
H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
MR
CP
ED0
ED1
Dn
H
L
X
X
H
X
X
X
X
L
no change
L
L
L
L
X
L
L
X
H
L
X
H
L
no change
= positive-going transition
= negative-going transition
H
L
L
X
X
no change
AC CHARACTERISTICS
SS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4
V
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Propagation delays
CP → On
HIGH to LOW
5
10
15
5
150
60
45
160
65
45
95
40
30
60
30
20
60
30
20
305 ns
123 ns
49 ns
37 ns
133 ns
54 ns
37 ns
68 ns
29 ns
22 ns
10 ns
9 ns
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL
tPHL
tPLH
tPHL
tTHL
tTLH
120 ns
85 ns
320 ns
130 ns
90 ns
190 ns
85 ns
65 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
LOW to HIGH
10
15
5
MR → On
HIGH to LOW
10
15
5
Output transition times
HIGH to LOW
10
15
5
6 ns
10 ns
9 ns
LOW to HIGH
10
15
6 ns
3-state propagation times
Output disable times
EOn → On
5
10
15
5
50
35
30
45
30
30
105 ns
70 ns
65 ns
90 ns
65 ns
60 ns
tPHZ
HIGH
LOW
10
15
tPLZ
January 1995
4
Philips Semiconductors
Product specification
HEF4076B
MSI
Quadruple D-type register with 3-state outputs
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
130 ns
Output enable times
EOn → On
5
65
30
20
60
25
20
10
15
5
tPZH
55 ns
40 ns
120 ns
50 ns
35 ns
HIGH
LOW
10
15
tPZL
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
MIN.
TYP. MAX.
Set-up times
5
10
0
−15
−10
−5
ns
Dn → CP
10
15
5
tsu
ns
0
ns
0
−50
−20
−15
30
ns
EDn → CP
10
15
5
tsu
0
ns
0
ns
Hold times
55
20
15
25
10
5
ns
Dn → CP
10
15
5
thold
10
ns
10
ns
−25
−10
−5
ns
EDn → CP
10
15
5
thold
ns
ns
see also waveforms
Fig.4
Minimum clock
120
45
30
55
30
20
90
35
20
4
60
ns
pulse width; LOW
10
15
5
tWCPL
tWMRH
tRMR
fmax
20
ns
15
ns
Minimum MR pulse
width; HIGH
25
ns
10
15
5
15
ns
10
ns
Recovery time
for MR
45
ns
10
15
5
15
ns
10
ns
Maximum clock
pulse frequency
8
MHz
MHz
MHz
10
15
11
16
22
32
January 1995
5
Philips Semiconductors
Product specification
HEF4076B
MSI
Quadruple D-type register with 3-state outputs
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
2200 fi + ∑ (foCL) × VDD
9300 fi + ∑ (foCL) × VDD
24 500 fi + ∑ (foCL) × VDD
where
2
2
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
January 1995
6
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
Fig.4 Waveforms showing propagation delays, output disable/enable times, minimum CP and MR pulse widths, set-up and hold times for
Dn to CP and EDn to CP, and recovery time for MR. Set-up and hold times are shown as positive values but may be specified as
negative values.
相关型号：
©2020 ICPDF网 联系我们和版权申明