HEF4078BN [NXP]

8-input NOR gate; 8输入NOR门
HEF4078BN
型号: HEF4078BN
厂家: NXP    NXP
描述:

8-input NOR gate
8输入NOR门

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INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF4078B  
gates  
8-input NOR gate  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
HEF4078B  
gates  
8-input NOR gate  
DESCRIPTION  
The HEF4078B provides the positive 8-input NOR  
function. The outputs are fully buffered for highest noise  
immunity and pattern insensitivity of output impedance.  
Fig.2 Pinning diagram.  
HEF4078BP(N): 14-lead DIL; plastic  
(SOT27-1)  
HEF4078BD(F): 14-lead DIL; ceramic (cerdip)  
(SOT73)  
HEF4078BT(D): 14-lead SO; plastic  
(SOT108-1)  
Fig.1 Functional diagram.  
( ): Package Designator North America  
FAMILY DATA,  
IDD LIMITS category GATES  
See Family Specifications  
Fig.3 Logic diagram.  
January 1995  
2
Philips Semiconductors  
Product specification  
HEF4078B  
gates  
8-input NOR gate  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
V
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL  
TYP.  
MAX.  
Propagation delays  
In On  
HIGH to LOW  
5
80  
160 ns  
53 ns  
24 ns  
17 ns  
53 ns  
24 ns  
17 ns  
+
+
+
+
+
+
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
10  
15  
5
tPHL  
35  
25  
80  
35  
25  
70 ns  
50 ns  
160 ns  
70 ns  
50 ns  
LOW to HIGH  
10  
15  
tPLH  
Output transition  
times  
5
10  
15  
5
60  
30  
20  
60  
30  
20  
120 ns  
60 ns  
40 ns  
120 ns  
60 ns  
40 ns  
10 ns  
9 ns  
6 ns  
10 ns  
9 ns  
6 ns  
+
+
+
+
+
+
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
HIGH to LOW  
tTHL  
LOW to HIGH  
10  
15  
tTLH  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
10  
15  
750 fi + ∑ (foCL) × VDD  
where  
2
2800 fi + ∑ (foCL) × VDD  
fi = input freq. (MHz)  
2
7500 fi + ∑ (foCL) × VDD  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
(foCL) = sum of outputs  
VDD = supply voltage (V)  
January 1995  
3

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