HEF4081BDF [NXP]
IC 4000/14000/40000 SERIES, QUAD 2-INPUT AND GATE, CDIP14, SOT-73, CERDIP-14, Gate;
| 型号： | HEF4081BDF |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, QUAD 2-INPUT AND GATE, CDIP14, SOT-73, CERDIP-14, Gate |
| 文件： | 总3页 (文件大小：29K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4081B
gates
Quadruple 2-input AND gate
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4081B
gates
Quadruple 2-input AND gate
DESCRIPTION
The HEF4081B provides the positive quadruple 2-input
AND function. The outputs are fully buffered for highest
noise immunity and pattern insensitivity of output
impedance.
Fig.2 Pinning diagram.
HEF4081BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4081BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
Fig.1 Functional diagram.
HEF4081BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4081B
gates
Quadruple 2-input AND gate
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL
TYP.
MAX.
Propagation delays
In → On
HIGH to LOW
5
55
110 ns
28 ns
14 ns
12 ns
18 ns
9 ns
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(0,55 ns/pF) CL
(0,23 ns/pF) CL
(0,16 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
(1,0 ns/pF) CL
(0,42 ns/pF) CL
(0,28 ns/pF) CL
10
15
5
tPHL
25
20
45
20
15
60
30
20
60
30
20
50 ns
40 ns
90 ns
40 ns
30 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
7 ns
Output transition times
HIGH to LOW
10 ns
9 ns
10
15
5
6 ns
10 ns
9 ns
LOW to HIGH
10
15
6 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
450 fi + ∑ (foCL) × VDD
where
2
2 900 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
11 700 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
January 1995
3
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