HEF4093BDF [NXP]

Quadruple 2-input NAND Schmitt trigger; 四路2输入与非施密特触发器


型号：	HEF4093BDF
厂家：	NXP
描述：	Quadruple 2-input NAND Schmitt trigger 四路2输入与非施密特触发器触发器
文件：	总6页 (文件大小：83K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

• The IC04 LOCMOS HE4000B Logic

Family Specifications HEF, HEC

• The IC04 LOCMOS HE4000B Logic

Package Outlines/Information HEF, HEC

HEF4093B

gates

Quadruple 2-input NAND Schmitt

trigger

January 1995

Product speciﬁcation

File under Integrated Circuits, IC04

Philips Semiconductors

Product speciﬁcation

HEF4093B

gates

Quadruple 2-input NAND Schmitt trigger

DESCRIPTION

The HEF4093B consists of four Schmitt-trigger circuits.

Each circuit functions as a two-input NAND gate with

Schmitt-trigger action on both inputs. The gate switches at

different points for positive and negative-going signals.

The difference between the positive voltage (V_P) and the

negative voltage (V_N) is defined as hysteresis voltage

(V_H).

Fig.2 Pinning diagram.

HEF4093BP(N): 14-lead DIL; plastic

(SOT27-1)

HEF4093BD(F): 14-lead DIL; ceramic (cerdip)

(SOT73)

HEF4093BT(D): 14-lead SO; plastic

(SOT108-1)

( ): Package Designator North America

Fig.3 Logic diagram (one gate).

FAMILY DATA, I_DDLIMITS category GATES

See Family Specifications

Fig.1 Functional diagram.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4093B

gates

Quadruple 2-input NAND Schmitt trigger

DC CHARACTERISTICS

V_SS= 0 V; T_amb= 25 °C

V_DD

SYMBOL

MIN.

0,4

TYP.

0,7

MAX.

Hysteresis

voltage

−

V_H

0,6

0,7

1,9

3,6

4,7

1,5

1,0

1,3

2,9

5,2

7,3

2,2

4,2

6,0

Switching levels

positive-going

input voltage

negative-going

input voltage

3,5

V_P

V_N

3,1

6,4

10,3

Fig.5 Waveforms showing definition of

V_P, V_Nand V_H; where V_Nand V_Pare

between limits of 30% and 70%.

Fig.4 Transfer characteristic.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4093B

gates

Quadruple 2-input NAND Schmitt trigger

AC CHARACTERISTICS

V_SS= 0 V; T_amb= 25 °C; C_L= 50 pF; input transition times ≤ 20 ns

V_DD

TYPICAL EXTRAPOLATION

SYMBOL

TYP. MAX.

FORMULA

Propagation delays

I_n→ O_n

HIGH to LOW

185 ns

80 ns

60 ns

170 ns

80 ns

60 ns

120 ns

60 ns

40 ns

120 ns

60 ns

40 ns

63 ns + (0,55 ns/pF) C_L

29 ns + (0,23 ns/pF) C_L

22 ns + (0,16 ns/pF) C_L

58 ns + (0,55 ns/pF) C_L

29 ns + (0,23 ns/pF) C_L

22 ns + (0,16 ns/pF) C_L

10 ns + (1,0 ns/pF) C_L

9 ns + (0,42 ns/pF) C_L

6 ns + (0,28 ns/pF) C_L

10 ns + (1,0 ns/pF) C_L

9 ns + (0,42 ns/pF) C_L

6 ns + (0,28 ns/pF) C_L

t_PHL

LOW to HIGH

t_PLH

t_THL

t_TLH

Output transition times

HIGH to LOW

LOW to HIGH

V_DD

TYPICAL FORMULA FOR P (µW)

Dynamic power

dissipation per

package (P)

1300 f_i+ ∑(f_oC_L) × V_DD

where

6400 f_i+ ∑(f_oC_L) × V_DD

f_i= input freq. (MHz)

f_o= output freq. (MHz)

C_L= load capacitance (pF)

∑ (f_oC_L) = sum of outputs

V_DD= supply voltage (V)

18 700 f_i+ ∑(f_oC_L) × V_DD

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4093B

gates

Quadruple 2-input NAND Schmitt trigger

Fig.6 Typical drain current as a function of input

Fig.7 Typical drain current as a function of input

voltage; V_DD= 5 V; T_amb= 25 °C.

voltage; V_DD=10 V; T_amb= 25 °C.

Fig.8 Typical drain current as a function of input

voltage; V_DD= 15 V; T_amb= 25 °C.

January 1995

Philips Semiconductors

Product speciﬁcation

HEF4093B

gates

Quadruple 2-input NAND Schmitt trigger

Fig.9 Typical switching levels as a function of supply voltage V_DD; T_amb= 25 °C.

APPLICATION INFORMATION

Some examples of applications for the HEF4093B are:

• Wave and pulse shapers

• Astable multivibrators

• Monostable multivibrators.

Fig.11 Schmitt trigger driven via a high impedance

Fig.10 The HEF4093B used as a astable multivibrator.

(R > 1 kΩ).

If a Schmitt trigger is driven via a high impedance (R > 1 kΩ) then it is necessary to incorporate a capacitor C of such

value that:

_DD– V_SS

C_p

------ ---------------------------

, otherwise oscillation can occur on the edges of a pulse.

V_H

C_pis the external parasitic capacitance between inputs and output; the value depends on the circuit board layout.

Note

The two inputs may be connected together, but this will result in a larger through-current at the moment of switching.

January 1995

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