HEF4093BD [NXP]
Quadruple 2-input NAND Schmitt trigger; 四路2输入与非施密特触发器型号: | HEF4093BD |
厂家: | NXP |
描述: | Quadruple 2-input NAND Schmitt trigger |
文件: | 总6页 (文件大小:83K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4093B
gates
Quadruple 2-input NAND Schmitt
trigger
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4093B
gates
Quadruple 2-input NAND Schmitt trigger
DESCRIPTION
The HEF4093B consists of four Schmitt-trigger circuits.
Each circuit functions as a two-input NAND gate with
Schmitt-trigger action on both inputs. The gate switches at
different points for positive and negative-going signals.
The difference between the positive voltage (VP) and the
negative voltage (VN) is defined as hysteresis voltage
(VH).
Fig.2 Pinning diagram.
HEF4093BP(N): 14-lead DIL; plastic
(SOT27-1)
HEF4093BD(F): 14-lead DIL; ceramic (cerdip)
(SOT73)
HEF4093BT(D): 14-lead SO; plastic
(SOT108-1)
( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES
See Family Specifications
Fig.1 Functional diagram.
January 1995
2
Philips Semiconductors
Product specification
HEF4093B
gates
Quadruple 2-input NAND Schmitt trigger
DC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C
VDD
V
SYMBOL
MIN.
0,4
TYP.
0,7
MAX.
Hysteresis
voltage
5
−
−
−
V
V
V
10
15
5
VH
0,6
0,7
1,9
3,6
4,7
1,5
3
1,0
1,3
2,9
5,2
7,3
2,2
4,2
6,0
Switching levels
positive-going
input voltage
negative-going
input voltage
3,5
7
V
V
V
V
V
V
10
15
5
VP
VN
11
3,1
6,4
10
15
4
10,3
Fig.5 Waveforms showing definition of
VP, VN and VH; where VN and VP are
between limits of 30% and 70%.
Fig.4 Transfer characteristic.
January 1995
3
Philips Semiconductors
Product specification
HEF4093B
gates
Quadruple 2-input NAND Schmitt trigger
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
SYMBOL
TYP. MAX.
FORMULA
Propagation delays
In → On
HIGH to LOW
5
90
40
30
85
40
30
60
30
20
60
30
20
185 ns
80 ns
60 ns
170 ns
80 ns
60 ns
120 ns
60 ns
40 ns
120 ns
60 ns
40 ns
63 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
58 ns + (0,55 ns/pF) CL
29 ns + (0,23 ns/pF) CL
22 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tPHL
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
Output transition times
HIGH to LOW
10
15
5
LOW to HIGH
10
15
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
1300 fi + ∑(foCL) × VDD
where
2
10
15
6400 fi + ∑(foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
2
18 700 fi + ∑(foCL) × VDD
January 1995
4
Philips Semiconductors
Product specification
HEF4093B
gates
Quadruple 2-input NAND Schmitt trigger
Fig.6 Typical drain current as a function of input
Fig.7 Typical drain current as a function of input
voltage; VDD = 5 V; Tamb = 25 °C.
voltage; VDD =10 V; Tamb = 25 °C.
Fig.8 Typical drain current as a function of input
voltage; VDD = 15 V; Tamb = 25 °C.
January 1995
5
Philips Semiconductors
Product specification
HEF4093B
gates
Quadruple 2-input NAND Schmitt trigger
Fig.9 Typical switching levels as a function of supply voltage VDD; Tamb = 25 °C.
APPLICATION INFORMATION
Some examples of applications for the HEF4093B are:
• Wave and pulse shapers
• Astable multivibrators
• Monostable multivibrators.
Fig.11 Schmitt trigger driven via a high impedance
Fig.10 The HEF4093B used as a astable multivibrator.
(R > 1 kΩ).
If a Schmitt trigger is driven via a high impedance (R > 1 kΩ) then it is necessary to incorporate a capacitor C of such
value that:
V
DD – VSS
C
Cp
------ ---------------------------
>
, otherwise oscillation can occur on the edges of a pulse.
VH
Cp is the external parasitic capacitance between inputs and output; the value depends on the circuit board layout.
Note
The two inputs may be connected together, but this will result in a larger through-current at the moment of switching.
January 1995
6
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