HEF4093BT-Q100,118_技术文档

HEF4093B-Q100

Quad 2-input NAND Schmitt trigger

Rev. 1 — 12 July 2012

Product data sheet

1. General description

The HEF4093B-Q100 is a quad two-input NAND gate. Each input has a Schmitt trigger

circuit. The gate switches at different points for positive-going and negative-going signals.

The difference between the positive voltage (V_T+) and the negative voltage (V_T) is

defined as hysteresis voltage (V_H).

It operates over a recommended V_DDpower supply range of 3 V to 15 V referenced to V_SS

(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Schmitt trigger input discrimination

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 ESD protection:

 MIL-STD-833, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )

 Complies with JEDEC standard JESD 13-B

3. Applications

 Wave and pulse shapers

 Astable multivibrators

 Monostable multivibrators

4. Ordering information

Table 1.

Ordering information

All types operate from 40 C to +125 C

Type number

Package

Name

Description

Version

HEF4093BT-Q100

SO14

plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

HEF4093B-Q100

NXP Semiconductors

Quad 2-input NAND Schmitt trigger

5. Functional diagram

1

1A

3

4

1Y

2Y

3Y

4Y

2

1B

5

2A

6

2B

nA

nB

nY

8

3A

001aag105

10

11

9

3B

12

4A

13

4B

001aag104

Fig 1. Functional diagram

Fig 2. Logic diagram (one gate)

6. Pinning information

6.1 Pinning

HEF4093B-Q100

1

2

3

4

5

6

7

14

13

12

11

10

9

1A

1B

VDD

4B

1Y

4A

2Y

4Y

2A

3Y

2B

3B

VSS

8

3A

aaa-003547

Fig 3. Pin configuration

HEF4093B_Q100

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Product data sheet

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6.2 Pin description

Table 2.

Symbol

1A to 4A

1B to 4B

1Y to 4Y

V_DD

Pin description

Description

input

1, 5, 8, 12

2, 6, 9, 13

3, 4, 10, 11

14

input

output

supply voltage

ground (0 V)

V_SS

7

7. Functional description

Table 3.

Function table^[1]

Input

nA

L

Output

nB

L

nY

H

L

H

L

H

L

[1] H = HIGH voltage level; L = LOW voltage level.

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V_SS= 0 V (ground).

Symbol Parameter

Conditions

Min

0.5

-

Max

+18

Unit

V

V_DD

I_IK

supply voltage

input clamping current

input voltage

V_I< 0.5 V or V_I> V_DD+ 0.5 V

V_O< 0.5 V or V_O> V_DD+ 0.5 V

10

mA

V

V_I

0.5

-

V_DD+ 0.5

10

I_OK

I_I/O

output clamping current

input/output current

supply current

mA

C

-

10

I_DD

T_stg

T_amb

P_tot

-

50

storage temperature

ambient temperature

total power dissipation

65

40

+150

+125

C

T_amb= 40 C to +125 C

SO14

[1]

-

500

100

mW

P

power dissipation

per output

[1] For SO14 package: above T_amb= 70 C, P_totderates linearly with 8 mW/K.

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Product data sheet

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9. Recommended operating conditions

Table 5.

Symbol

V_DD

Recommended operating conditions

Parameter

Conditions

Min

3

Max

15

Unit

V

supply voltage

V_I

input voltage

0

V_DD

+125

V

T_amb

ambient temperature

in free air

40

C

10. Static characteristics

Table 6.

Static characteristics

V_SS= 0 V; V_I= V_SSor V_DD; unless otherwise specified.

Symbol Parameter

Conditions

V_DD

T_amb= 40 C T_amb= +25 C T_amb= +85 C T_amb= +125 C Unit

Min

4.95

9.95

14.95

-

Max

Min

4.95

9.95

14.95

-

Max

Min

4.95

9.95

14.95

-

Max

Min

4.95

9.95

14.95

-

Max

V_OH

HIGH-level

output voltage

I_O < 1 A

5 V

10 V

15 V

5 V

-

V

-

V

-

V

V_OL

LOW-level

0.05

V

output voltage

10 V

15 V

5 V

-

0.05

-

0.05

-

0.05

-

0.05

V

-

0.05

-

0.05

-

0.05

-

0.05

V

I_OH

HIGH-level

output current

V_O= 2.5 V

V_O= 4.6 V

V_O= 9.5 V

V_O= 13.5 V

V_O= 0.4 V

V_O= 0.5 V

V_O= 1.5 V

1.7

0.64

1.6

4.2

0.64

1.6

4.2

-

1.4

0.5

1.3

3.4

0.5

1.3

3.4

-

1.1

0.36

0.9

2.4

0.36

0.9

2.4

-

1.1

0.36

0.9

2.4

0.36

0.9

2.4

-

mA

5 V

-

10 V

15 V

5 V

-

I_OL

LOW-level

output current

-

10 V

15 V

-

I_I

input leakage

current

0.1

1.0

1.0 A

I_DD

supply current all valid input

combinations;

5 V

10 V

15 V

-

0.25

0.5

1.0

-

0.25

0.5

-

7.5

15.0

30.0

-

7.5 A

15.0 A

30.0 A

I_O= 0 A

1.0

C_I

input

7.5

-

pF

capacitance

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Product data sheet

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11. Dynamic characteristics

Table 7.

Dynamic characteristics

T_amb= 25 C; C_L= 50 pF; t_r= t_f 20 ns; wave forms see Figure 4; test circuit see Figure 5; unless otherwise specified.

Symbol Parameter

Conditions

V_DD

Extrapolation formula^[1]Min

Typ

90

40

30

85

40

30

60

30

20

60

30

20

Max

185

80

Unit

ns

t_PHL

HIGH to LOW

nA or nB to nY 5 V

63 ns + (0.55 ns/pF)C_L

29 ns + (0.23 ns/pF)C_L

22 ns + (0.16 ns/pF)C_L

58 ns + (0.55 ns/pF)C_L

29 ns + (0.23 ns/pF)C_L

22 ns + (0.16 ns/pF)C_L

10 ns + (1.00 ns/pF)C_L

9 ns + (0.42 ns/pF)C_L

6 ns + (0.28 ns/pF)C_L

10 ns + (1.00 ns/pF)C_L

9 ns + (0.42 ns/pF)C_L

6 ns + (0.28 ns/pF)C_L

-

propagation delay

10 V

15 V

nA or nB to nY 5 V

10 V

60

t_PLH

t_THL

t_TLH

LOW to HIGH

propagation delay

170

80

15 V

60

HIGH to LOW output

transition time

nY to LOW

5 V

10 V

15 V

5 V

120

60

40

LOW to HIGH output

transition time

nA or nB to

HIGH

120

60

10 V

15 V

40

[1] Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C_Lin pF).

Table 8.

Dynamic power dissipation

V_SS= 0 V; t_r= t_f 20 ns; T_amb= 25 C.

Symbol Parameter

V_DD

5 V

Typical formula

where:

P_D

dynamic power

dissipation

P_D= 1300  f_i+ (f_o C_L)  V_DD²(W)

P_D= 6400  f_i+ (f_o C_L)  V_DD²(W)

P_D= 18700  f_i+ (f_o C_L)  V_DD²(W)

f_i= input frequency in MHz;

f_o= output frequency in MHz;

10 V

15 V

C_L= output load capacitance in pF;

(f_o C_L) = sum of the outputs;

V_DD= supply voltage in V.

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12. Waveforms

t

f

r

V

I

90 %

input

V

M

10 %

0 V

t

PLH

PHL

V

OH

90 %

output

V

M

10 %

V

OL

t

THL

TLH

001aag197

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

t_r, t_f= input rise and fall times.

Fig 4. Propagation delay and output transition time

Table 9.

Measurement points

Supply voltage

V_DD

Input

V_M

Output

V_M

5 V to 15 V

0.5V_DD

V

DD

V

O

I

G

DUT

C

L

R

T

001aag182

Test data given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

C_L= load capacitance including jig and probe capacitance.

R_T= termination resistance should be equal to the output impedance Z_oof the pulse generator.

Fig 5. Test circuit

Table 10. Test data

Supply voltage

V_DD

Input

Load

C_L

V_I

t_r, t_f

5 V to 15 V

V_SSor V_DD

 20 ns

50 pF

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13. Transfer characteristics

Table 11. Transfer characteristics

V_SS= 0 V; T_amb= 25 C; see Figure 6 and Figure 7.

Symbol Parameter Conditions

V_DD

5 V

Min

1.9

3.6

4.7

1.5

3

Typ

2.9

5.2

7.3

2.2

4.2

6.0

0.7

1.0

1.3

Max Unit

V_T+

V_T

V_H

positive-going threshold voltage

3.5

7

V

10 V

15 V

5 V

11

3.1

6.4

10.3

-

negative-going threshold voltage

hysteresis voltage

10 V

15 V

5 V

4

0.4

0.6

0.7

10 V

15 V

-

V

O

V

T+

V

I

V

H

V

T−

V

I

V

O

V

H

V

T+

T−

001aag107

001aag108

Fig 6. Transfer characteristic

Fig 7. Waveforms showing definition of V_T+and V_T

(between limits at 30 % and 70 %) and V_H

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001aag109

001aag110

200

1000

I

DD

(μA)

100

500

0

2.5

5

0

5

10

V (V)

I

V (V)

I

a. V_DD= 5 V; T_amb= 25 C

b. V_DD= 10 V; T_amb= 25 C

001aag111

2000

I

DD

(μA)

1000

0

10

20

V (V)

I

c. V_DD= 15 V; T_amb= 25 C

Fig 8. Typical drain current as a function of input

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001aag112

10

V

I

(V)

V

T+

T−

5

0

2.5

5

7.5

10

12.5

15

17.5

V

(V)

DD

T_amb= 25 C.

Fig 9. Typical switching levels as a function of supply voltage

14. Application information

Some examples of applications for the HEF4093B-Q100 are:

• Wave and pulse shapers

• Astable multivibrators

• Monostable multivibrators

C

p

V

DD

14

R

1

2

1

2

3

V

DD

C

7

001aag113

001aag114

Fig 10. Astable multivibrator

Fig 11. Schmitt trigger driven via a

high-impedance input

If a Schmitt trigger is driven via a high-impedance (R > 1 k), then it is necessary to

V

_DD– V_SS

C

incorporate a capacitor C with a value of ------ > ------------------------ ; otherwise oscillation can occur

C_PV_H

on the edges of a pulse.

C_pis the external parasitic capacitance between inputs and output; the value depends on

the circuit board layout.

Remark: The two inputs may be connected together, but this will result in a larger

through-current at the moment of switching.

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15. Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

D

E

A

X

v

c

y

H

M

A

E

Z

8

14

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

7

e

detail X

w

M

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

8.75

8.55

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.75

1.27

0.05

1.05

0.25

0.01

0.25

0.1

0.25

0.01

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.35

0.014 0.0075 0.34

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches

0.041

0.01 0.004

0.069

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT108-1

076E06

MS-012

Fig 12. Package outline SOT108-1 (SO14)

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16. Abbreviations

Table 12. Abbreviations

Acronym

HBM

ESD

Description

Human Body Model

ElectroStatic Discharge

Machine Model

Military

MM

MIL

17. Revision history

Table 13. Revision history

Document ID

Release date

20120712

Data sheet status

Change notice

Supersedes

HEF4093B_Q100 v.1

Product specification

-

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18. Legal information

18.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

Suitability for use in automotive applications — This NXP

18.2 Definitions

Semiconductors product has been qualified for use in automotive

applications. Unless otherwise agreed in writing, the product is not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and therefore such inclusion and/or use is at the customer's own

risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

18.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Semiconductors takes no

responsibility for the content in this document if provided by an information

source outside of NXP Semiconductors.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

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No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

19. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

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20. Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 2

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

Functional description . . . . . . . . . . . . . . . . . . . 3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3

Recommended operating conditions. . . . . . . . 4

Static characteristics. . . . . . . . . . . . . . . . . . . . . 4

Dynamic characteristics . . . . . . . . . . . . . . . . . . 5

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Transfer characteristics . . . . . . . . . . . . . . . . . . 7

Application information. . . . . . . . . . . . . . . . . . . 9

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

8

9

10

11

12

13

14

15

16

17

18

Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13

18.1

18.2

18.3

18.4

19

20

Contact information. . . . . . . . . . . . . . . . . . . . . 13

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 12 July 2012

Document identifier: HEF4093B_Q100


型号：	HEF4093BT-Q100,118
厂家：	NXP
描述：	HEF4093B-Q100 - Quad 2-input NAND Schmitt trigger SOIC 14-Pin
文件：	总14页 (文件大小：155K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HEF4093BT-Q100,118 [NXP]

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