HEF4094B [NXP]
8-stage shift-and-store bus register; 8级移位 - 和 - 存储总线寄存器
| 型号： | HEF4094B |
| 厂家： | 
NXP |
| 描述： | 8-stage shift-and-store bus register |
| 文件： | 总7页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4094B
MSI
8-stage shift-and-store bus register
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4094B
MSI
8-stage shift-and-store bus register
Two serial outputs (Os and O’s) are available for cascading
a number of HEF4094B devices. Data is available at Os on
positive-going clock edges to allow high-speed operation
in cascaded systems in which the clock rise time is fast.
The same serial information is available at O’s on the next
negative-going clock edge and provides cascading
HEF4094B devices when the clock rise time is slow.
DESCRIPTION
The HEF4094B is an 8-stage serial shift register having a
storage latch associated with each stage for strobing data
from the serial input to parallel buffered 3-state outputs
O0 to O7. The parallel outputs may be connected directly
to common bus lines. Data is shifted on positive-going
clock transitions. The data in each shift register stage is
transferred to the storage register when the strobe (STR)
input is HIGH. Data in the storage register appears at the
outputs whenever the output enable (EO) signal is HIGH.
Fig.2 Pinning diagram.
HEF4094BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4094BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4094BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
D
data input
clock input
strobe input
EO
output enable input
serial outputs
CP
STR
Os, O’s
Fig.1 Functional diagram.
O0 to O7 parallel outputs
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
January 1995
2
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Fig.3 Logic diagram.
Fig.4 One D-latch.
Philips Semiconductors
Product specification
HEF4094B
MSI
8-stage shift-and-store bus register
FUNCTION TABLE
INPUTS
EO STR
PARALLEL OUTPUTS
SERIAL OUTPUTS
CP
D
X
X
X
L
O0
Z
On
Z
Os
O’6
nc
O’s
nc
O7
nc
nc
nc
O7
L
L
X
X
L
Z
Z
H
H
H
H
nc
L
nc
O’6
O’6
O’6
nc
H
H
H
On-1
H
H
H
On-1
nc
nc
Notes
1. H = HIGH state (the more positive voltage)
2. L = LOW state (the less positive voltage)
3. X = state is immaterial
4.
5.
= positive-going transition
= negative-going transition
6. Z = high impedance off state
7. nc = no change
8. O’6 = the information in the seventh shift register stage
At the positive clock edge the information in the 7th register stage is transferred to the 8th register stage and the
Os output.
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
2100 fi + ∑ (foCL) × VDD
9700 fi + ∑ (foCL) × VDD
26 000 fi + ∑ (foCL) × VDD
where
2
2
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
4
Philips Semiconductors
Product specification
HEF4094B
MSI
8-stage shift-and-store bus register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
SYMBOL
TYP. MAX.
FORMULA
Propagation delays
CP → Os
HIGH to LOW
5
135
65
270
130
100
210
100
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
108 ns + (0,55 ns/pF) CL
54 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
78 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
32 ns + (0,16 ns/pF) CL
138 ns + (0,55 ns/pF) CL
64 ns + (0,23 ns/pF) CL
47 ns + (0,16 ns/pF) CL
123 ns + (0,55 ns/pF) CL
59 ns + (0,23 ns/pF) CL
47 ns + (0,16 ns/pF) CL
83 ns + (0,55 ns/pF) CL
39 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
73 ns + (0,55 ns/pF) CL
34 ns + (0,23 ns/pF) CL
27 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10
15
5
tPHL
50
105
50
LOW to HIGH
10
15
5
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tTHL
tTLH
40
CP → O’s
105
50
210
100
80
HIGH to LOW
10
15
5
40
105
50
210
100
80
LOW to HIGH
10
15
5
40
CP → On
165
75
330
150
110
300
140
110
220
100
70
HIGH to LOW
10
15
5
55
150
70
LOW to HIGH
10
15
5
55
STR → On
110
50
HIGH to LOW
10
15
5
35
100
45
200
90
LOW to HIGH
10
15
5
35
70
Output transition times
HIGH to LOW
60
120
60
10
15
5
30
20
40
60
120
60
LOW to HIGH
10
15
30
20
40
January 1995
5
Philips Semiconductors
Product specification
HEF4094B
MSI
8-stage shift-and-store bus register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN. TYP. MAX.
3-state propagation delays
Output enable times
EO → On
5
40
25
20
40
25
20
75
40
30
80
40
30
30
15
12
20
15
12
30
10
5
80
50
ns
ns
10
15
5
tPZH
HIGH
40
ns
80
ns
LOW
10
15
5
tPZL
50
ns
40
ns
Output disable times
EO → On
150
80
ns
10
15
5
tPHZ
ns
HIGH
60
ns
160
80
ns
LOW
10
15
5
tPLZ
ns
60
ns
Minimum clock
pulse width
LOW
60
30
24
40
30
24
60
20
15
5
ns
10
15
5
tWCPL
tWSTRH
tsu
ns
ns
Minimum strobe
pulse width
HIGH
ns
10
15
5
ns
ns
Set-up times
D → CP
ns
10
15
5
ns
ns
Hold times
−15
5
ns
D → CP
10
15
5
thold
20
20
5
ns
5
ns
Maximum clock
pulse frequency
10
22
28
MHz
MHz
MHz
10
15
fmax
11
14
January 1995
6
Philips Semiconductors
Product specification
HEF4094B
MSI
8-stage shift-and-store bus register
Fig.5 Timing diagram.
APPLICATION INFORMATION
Some examples of applications for the HEF4094B are:
• Serial-to-parallel data conversion
• Remote control holding register
Fig.6 Remote control holding register.
January 1995
7
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