HEF4094B_10_技术文档

HEF4094B

8-stage shift-and-store register

Rev. 08 — 2 April 2010

Product data sheet

1. General description

The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with

each stage for strobing data from the serial input to parallel buffered 3-state outputs

QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is

shifted on positive-going clock transitions. The data in each shift register stage is

transferred to the storage register when the strobe (STR) input is HIGH. Data in the

storage register appears at the outputs whenever the output enable (OE) signal is HIGH.

Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4094B

devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed

operation in cascaded systems with a fast clock rise time. The same serial data is

available at QS2 on the next negative going clock edge. This is used for cascading

HEF4094B devices when the clock has a slow rise time.

It operates over a recommended V_DDpower supply range of 3 V to 15 V referenced to V_SS

(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input. It is

also suitable for use over the industrial (−40 °C to +85 °C) and automotive (−40 °C to

+125 °C) temperature ranges.

2. Features and benefits

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Operates across the automotive temperature range −40 °C to +125 °C

Complies with JEDEC standard JESD 13-B

3. Ordering information

Table 1.

Ordering information

All types operate from −40 °C to +125 °C.

Type number

Package

Name

Description

Version

HEF4094BP

HEF4094BT

HEF4094BTS

DIP16

plastic dual in-line package; 16 leads (300 mil)

plastic small outline package; 16 leads; body width 3.9 mm

plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT38-4

SOT109-1

SOT338-1

SO16

SSOP16

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

4. Functional diagram

3

1

CP

STR

QS1

QS2

QP0

QP1

QP2

9

10

4

D

2

8-STAGE SHIFT

REGISTER

QS2

QS1

5

10

9

CP

3

6

2

D

QP3

QP4

QP5

QP6

QP7

7

STR

8-BIT STORAGE

REGISTER

1

14

13

12

11

OE

15

3-STATE OUTPUTS

OE

15

QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7

4

5

6

7

14

13

12

11

001aaf119

001aaf111

Fig 1. Functional diagram

Fig 2. Logic symbol

STAGE 0

STAGES 1 TO 6

STAGE 7

D

Q

D

Q

D

Q

QS1

CP

D

Q

QS2

FF 0

FF 7

CP

LE

LATCH

D

Q

D

Q

LE

LATCH 0

LATCH 7

STR

OE

001aag799

QP0

QP2

QP4

QP6

QP1

QP3

QP5

QP7

Fig 3. Logic diagram

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

2 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

5. Pinning information

5.1 Pinning

HEF4094B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

STR

D

V

DD

OE

CP

QP4

QP5

QP6

QP7

QS2

QS1

QP0

QP1

QP2

QP3

V

SS

001aae662

Fig 4. Pin configuration

5.2 Pin description

Table 2.

Symbol

STR

Pin description

Description

strobe input

data input

1

D

2

CP

3

clock input

QP0 to QP7

V_SS

4, 5, 6, 7, 14, 13, 12, 11

parallel output

8

ground supply voltage

serial output

QS1

9

QS2

10

15

16

serial output

OE

output enable input

supply voltage

V_DD

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

3 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

6. Functional description

Table 3.

Function table^[1]

Inputs

Parallel outputs

Serial outputs

CP

↑

OE

L

STR

X

D

X

L

QP0

Z

QPn

QS1

Q6S

NC

QS2

NC

Z

↓

L

X

Z

Q7S

NC

↑

H

L

NC

L

NC

Q6S

NC

↑

H

QPn −1

NC

↑

H

NC

↓

H

NC

Q7S

[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.

H = HIGH voltage level; L = LOW voltage level; X = don’t care;

↑ = positive-going transition; ↓ = negative-going transition;

Z = HIGH-impedance OFF-state; NC = no change;

Q6S = the data in register stage 6 before the LOW to HIGH clock transition;

Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

CLOCK INPUT

DATA INPUT

STROBE INPUT

OUTPUT ENABLE INPUT

INTERNAL Q0S (FF 0)

Z-state

OUTPUT QP0

INTERNAL Q6S (FF 6)

Z-state

OUTPUT QP6

SERIAL OUTPUT QS1

SERIAL OUTPUT QS2

001aaf117

Fig 5. Timing diagram

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

4 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to V_SS= 0 V (ground).

Symbol Parameter

Conditions

Min

Max

+18

Unit

V

V_DD

I_IK

supply voltage

−0.5

input clamping current

input voltage

V_I< −0.5 V or V_I> V_DD+ 0.5 V

V_O< −0.5 V or V_O> V_DD+ 0.5 V

-

±10

mA

V

V_I

−0.5

V_DD+ 0.5

±10

I_OK

I_I/O

output clamping current

input/output current

supply current

-

mA

°C

-

±10

I_DD

T_stg

T_amb

P_tot

-

50

storage temperature

ambient temperature

total power dissipation

−65

+150

+125

750

−40

°C

[1]

[2]

DIP16

-

mW

SO16

500

P

power dissipation

per output

100

[1] For DIP16 packages: above T_amb= 70 °C, P_totderates linearly with 12 mW/K.

[2] For SO16 packages: above T_amb= 70 °C, P_totderates linearly with 8 mW/K.

8. Recommended operating conditions

Table 5.

Symbol

V_DD

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max

15

Unit

supply voltage

3

-

V

V_I

input voltage

0

V_DD

+125

3.75

0.5

V

T_amb

ambient temperature

input transition rise and fall rate

in free air

−40

°C

Δt/ΔV

V_DD= 5 V

V_DD= 10 V

V_DD= 15 V

-

μs/V

0.08

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

5 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

9. Static characteristics

Table 6.

Static characteristics

V_SS= 0 V; V_I= V_SSor V_DD; unless otherwise specified.

Symbol Parameter

Conditions

V_DD

T_amb= −40 °C T_amb= +25 °C T_amb= +85 °C T_amb= +125 °C Unit

Min

3.5

7.0

11.0

-

Max

Min

3.5

7.0

11.0

-

Max

Min

3.5

7.0

11.0

-

Max

Min

3.5

7.0

11.0

-

Max

V_IH

HIGH-level

input voltage

|I_O| < 1 μA

5 V

10 V

15 V

5 V

-

V

-

V

-

V

V_IL

LOW-level

input voltage

1.5

V

10 V

15 V

5 V

-

3.0

-

3.0

-

3.0

-

3.0

V

-

4.0

-

4.0

-

4.0

-

4.0

V

V_OH

V_OL

I_OH

HIGH-level

output voltage

4.95

9.95

14.95

-

4.95

9.95

14.95

-

4.95

9.95

14.95

-

4.95

9.95

14.95

-

V

10 V

15 V

5 V

-

V

-

V

LOW-level

output voltage

0.05

V

10 V

15 V

5 V

-

0.05

-

0.05

-

0.05

-

0.05

V

-

0.05

-

0.05

-

0.05

-

0.05

V

HIGH-level

output current

V_O= 2.5 V

V_O= 4.6 V

V_O= 9.5 V

V_O= 13.5 V

V_O= 0.4 V

V_O= 0.5 V

V_O= 1.5 V

−1.7

−0.64

−1.6

−4.2

0.64

1.6

4.2

-

−1.4

−0.5

−1.3

−3.4

0.5

1.3

3.4

-

−1.1

−0.36

−0.9

−2.4

0.36

0.9

2.4

-

−1.1

−0.36

−0.9

−2.4

0.36

0.9

2.4

-

mA

μA

5 V

-

10 V

15 V

5 V

-

I_OL

LOW-level

output current

-

10 V

15 V

-

I_OZ

OFF-state

output current

QPn output

is HIGH;

0.4

12

V_O= 15 V

I_I

input leakage

current

15 V

-

±0.1

-

±0.1

-

±1.0

-

±1.0 μA

I_DD

supply current all valid input

combinations;

5 V

10 V

15 V

-

5

10

20

-

5

-

150

300

600

-

150 μA

300 μA

600 μA

10

20

7.5

I_O= 0 A

C_I

input

-

pF

capacitance

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

6 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

10. Dynamic characteristics

Table 7.

Dynamic characteristics

V_SS= 0 V; T_amb= 25 °C; for test circuit see Figure 10; unless otherwise specified.

Symbol Parameter

Conditions

V_DD

5 V

Extrapolation formula

108 ns + (0.55 ns/pF) C_L

54 ns + (0.23 ns/pF) C_L

42 ns + (0.16 ns/pF) C_L

78 ns + (0.55 ns/pF) C_L

39 ns + (0.23 ns/pF) C_L

32 ns + (0.16 ns/pF) C_L

138 ns + (0.55 ns/pF) C_L

64 ns + (0.23 ns/pF) C_L

47 ns + (0.16 ns/pF) C_L

83 ns + (0.55 ns/pF) C_L

39 ns + (0.23 ns/pF) C_L

27 ns + (0.16 ns/pF) C_L

78 ns + (0.55 ns/pF) C_L

39 ns + (0.23 ns/pF) C_L

32 ns + (0.16 ns/pF) C_L

78 ns + (0.55 ns/pF) C_L

39 ns + (0.23 ns/pF) C_L

32 ns + (0.16 ns/pF) C_L

123 ns + (0.55 ns/pF) C_L

59 ns + (0.23 ns/pF) C_L

47 ns + (0.16 ns/pF) C_L

73 ns + (0.55 ns/pF) C_L

34 ns + (0.23 ns/pF) C_L

27 ns + (0.16 ns/pF) C_L

10 ns + (1.00 ns/pF) C_L

9 ns + (0.42 ns/pF) C_L

6 ns + (0.28 ns/pF) C_L

Min

-

Typ

135

65

Max

270

130

100

210

100

80

Unit

ns

[1]

t_PHL

HIGH to LOW

CP to QS1;

see Figure 6

propagation delay

10 V

15 V

5 V

-

50

CP to QS2;

see Figure 6

-

105

50

10 V

15 V

5 V

-

40

CP to QPn;

see Figure 6

-

165

75

330

150

110

220

100

70

10 V

15 V

5 V

-

55

STR to QPn;

see Figure 7

-

110

50

10 V

15 V

5 V

-

35

t_PLH

LOW to HIGH

CP to QS1;

see Figure 6

-

105

50

210

100

80

propagation delay,

10 V

15 V

5 V

-

40

CP to QS2;

see Figure 6

-

105

50

210

100

80

10 V

15 V

5 V

-

40

CP to QPn;

see Figure 6

-

150

70

300

140

110

200

90

10 V

15 V

5 V

-

55

STR to QPn;

see Figure 7

-

100

45

10 V

15 V

5 V

-

35

70

t_t

transition time

-

60

120

60

10 V

15 V

5 V

-

30

-

20

40

t_PZH

t_PZL

t_PHZ

OFF-state to HIGH

propagation delay

OE to QPn;

see Figure 8

-

40

80

10 V

15 V

5 V

-

25

50

-

20

40

OFF-state to LOW

propagation delay

OE to QPn;

see Figure 8

-

40

80

10 V

15 V

5 V

-

25

50

-

20

40

HIGH to OFF-state

propagation delay

OE to QPn;

see Figure 8

-

75

150

80

10 V

15 V

-

40

-

30

60

HEF4094B_8

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Product data sheet

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7 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

Table 7.

Dynamic characteristics …continued

V_SS= 0 V; T_amb= 25 °C; for test circuit see Figure 10; unless otherwise specified.

Symbol Parameter

Conditions

V_DD

5 V

Extrapolation formula

Min

-

Typ

80

40

30

10

5

Max

Unit

ns

t_PLZ

t_su

t_h

LOW to OFF-state

propagation delay

OE to QPn;

see Figure 8

160

10 V

15 V

5 V

-

80

ns

-

60

ns

set-up time

D to CP;

see Figure 9

60

20

15

+5

20

60

30

24

40

30

24

5

-

ns

10 V

15 V

5 V

ns

hold time

D to CP;

see Figure 9

−15

5

ns

10 V

15 V

ns

5

ns

t_W

pulse width

minimum LOW 5 V

clock pulse;

see Figure 6

15 V

30

15

12

20

15

12

10

22

28

ns

10 V

ns

minimumHIGH 5 V

strobe pulse;

see Figure 7

15 V

ns

10 V

ns

f_max

maximum frequency see Figure 6

5 V

10 V

15 V

MHz

11

14

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C_Lin pF).

Table 8.

Dynamic power dissipation

V_SS= 0 V; t_r= t_f≤ 20 ns; T_amb= 25 °C.

Symbol

Parameter

V_DD

5 V

Typical formula for P_D(μW)

P_D= 2100 × f_i+ Σ(f_o× C_L) × V_DD

P_D= 9700 × f_i+ Σ(f_o× C_L) × V_DD

where:

2

P_D

dynamic power

dissipation

f_i= input frequency in MHz,

f_o= output frequency in MHz,

C_L= output load capacitance in pF,

10 V

15 V

2

P_D= 26000 × f_i+ Σ(f_o× C_L) × V_DD

V_DD= supply voltage in V,

Σ(f_o× C_L) = sum of the outputs.

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

8 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

11. Waveforms

1/f

max

V

I

CP input

V

M

GND

t

W

t

PHL

PLH

V

OH

QPn, QS1 output

V

M

V

OL

t

PHL

PLH

V

OH

QS2 output

V

M

V

OL

001aaf113

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 6. Clock to outputs propagation delays, and clock pulse width and maximum frequency

Table 9.

Measurement points

Supply voltage

V_DD

Input

V_M

Output

V_M

V_X

V_Y

5 V to 15 V

0.5V_DD

0.1V_DD

0.9V_DD

V

I

STR input

V

M

GND

t

W

t

PHL

PLH

V

OH

QPn output

V

M

V

OL

001aaj058

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 7. Strobe to output propagation delays, and strobe pulse width, set up and hold times

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

9 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

V

I

V

M

OE input

GND

t

PZL

t

PLZ

V

DD

output

LOW-to-OFF

OFF-to-LOW

V

M

V

X

V

OL

t

PHZ

PZH

V

OH

V

Y

output

HIGH-to-OFF

OFF-to-HIGH

V

M

GND

outputs

enabled

outputs

disabled

outputs

enabled

001aai545

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 8. 3-state output enable and disable times for OE input

V

I

V

CP input

M

GND

t

su

t

h

V

I

V

D input

M

GND

V

OH

V

QPn, QS1, QS2 output

M

V

OL

001aaf115

Measurement points are given in Table 9.

Logic levels: V_OLand V_OHare typical output voltage levels that occur with the output load.

Fig 9. Data input data set up and hold times

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

10 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

r

t

f

V

I

90 %

positive

pulse

M

10 %

0 V

t

W

001aaj781

a. Input waveform

V

EXT

R

V

DD

L

V

O

I

G

DUT

R

C

L

T

001aaj915

b. Test circuit

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

C_L= load capacitance including jig and probe capacitance.

R_L= load resistance.

R_T= termination resistance should be equal to the output impedance Z_oof the pulse generator.

Fig 10. Test circuit

Table 10. Test data

Supply voltage Input

V_EXT

Load

C_L

V_DD

V_I

t_r, t_f

t_PHL, t_PLH

open

t_PHZ, t_PZH

t_PLZ, t_PZL

R_L

5 V to 15 V

V_SSor V_DD

≤ 20 ns

V_SS

V_DD

50 pF

1 kΩ

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

11 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

12. Application information

Some examples of applications for the HEF4094B are:

• Serial-to-parallel data conversion

• Remote control holding register

DIGITALLY CONTROLLED

EQUIPMENT

DIGITALLY CONTROLLED

EQUIPMENT

(REQUIRES CONTINUOUS

DIGITAL CONTROL)

QP0

QP7

QS2

QP0

QP7

QS2

QP0

QP7

HEF4094B

D

STR

CP

STR

CP

STR

CP

CONTROL

AND

SYNC

CIRCUITRY

data

clock

from remote

control panel

001aae666

Fig 11. Remote control holding register

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

12 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

2

16

9

M

H

pin 1 index

E

1

8

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

2

1

E

max.

min.

max.

1.73

1.30

0.53

0.38

1.25

0.85

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

0.76

0.068 0.021 0.049 0.014

0.051 0.015 0.033 0.009

0.77

0.73

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.03

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

95-01-14

03-02-13

SOT38-4

Fig 12. Package outline SOT38-4 (DIP16)

HEF4094B_8

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Product data sheet

Rev. 08 — 2 April 2010

13 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

c

y

H

v

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 13. Package outline SOT109-1 (SO16)

HEF4094B_8

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 08 — 2 April 2010

14 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

8

1

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

p

1

2

3

E

max.

8^o

0^o

0.21

0.05

1.80

1.65

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

mm

2

0.25

0.65

1.25

0.2

0.13

0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT338-1

MO-150

Fig 14. Package outline SOT338-1 (SSOP16)

HEF4094B_8

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 08 — 2 April 2010

15 of 19

HEF4094B

NXP Semiconductors

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14. Revision history

Table 11. Revision history

Document ID

HEF4094B_8

Modifications:

HEF4094B_7

Modifications:

Release date

20100402

Data sheet status

Change notice

Supersedes

Product data sheet

-

HEF4094B_7

• Section 4 “Functional diagram” Logic diagram corrected.

20091216 Product data sheet

• Section 11 “Waveforms” Figure 10 “Test circuit”: updated.

-

HEF4094B_6

• Section 11 “Waveforms” Table 10 “Test data” t_PHZand t_PZHand t_PLZand t_PZL

values updated.

HEF4094B_6

20091103

20090728

20081030

19950101

Product data sheet

Product specification

-

HEF4094B_5

HEF4094B_4

HEF4094B_CNV_3

HEF4094B_CNV_2

-

HEF4094B_5

HEF4094B_4

HEF4094B_CNV_3

HEF4094B_CNV_2

HEF4094B_8

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 08 — 2 April 2010

16 of 19

HEF4094B

NXP Semiconductors

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15. Legal information

15.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

suitable for use in medical, military, aircraft, space or life support equipment,

15.2 Definitions

nor in applications where failure or malfunction of an NXP Semiconductors

product can reasonably be expected to result in personal injury, death or

severe property or environmental damage. NXP Semiconductors accepts no

liability for inclusion and/or use of NXP Semiconductors products in such

equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on a weakness or default in the

customer application/use or the application/use of customer’s third party

customer(s) (hereinafter both referred to as “Application”). It is customer’s

sole responsibility to check whether the NXP Semiconductors product is

suitable and fit for the Application planned. Customer has to do all necessary

testing for the Application in order to avoid a default of the Application and the

product. NXP Semiconductors does not accept any liability in this respect.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

15.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use in automotive applications — This NXP

Semiconductors product has been qualified for use in automotive

applications. The product is not designed, authorized or warranted to be

HEF4094B_8

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 08 — 2 April 2010

17 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

HEF4094B_8

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 08 — 2 April 2010

18 of 19

HEF4094B

NXP Semiconductors

8-stage shift-and-store register

17. Contents

1

2

3

4

General description. . . . . . . . . . . . . . . . . . . . . . 1

Features and benefits . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5

5.1

5.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

Functional description . . . . . . . . . . . . . . . . . . . 4

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5

Recommended operating conditions. . . . . . . . 5

Static characteristics. . . . . . . . . . . . . . . . . . . . . 6

Dynamic characteristics . . . . . . . . . . . . . . . . . . 7

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Application information. . . . . . . . . . . . . . . . . . 12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16

7

8

9

10

11

12

13

14

15

Legal information. . . . . . . . . . . . . . . . . . . . . . . 17

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17

15.1

15.2

15.3

15.4

16

17

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 2 April 2010

Document identifier: HEF4094B_8


型号：	HEF4094B_10
厂家：	NXP
描述：	8-stage shift-and-store register 8级移位 - 和 - 存储寄存器存储
文件：	总19页 (文件大小：169K)
中文：	中文翻译
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HEF4094B_10 [NXP]

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