HEF4104BPN [NXP]
IC 4000/14000/40000 SERIES, 4-BIT DRIVER, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, SOT-38-1, DIP-16, Bus Driver/Transceiver;
| 型号： | HEF4104BPN |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, 4-BIT DRIVER, COMPLEMENTARY OUTPUT, PDIP16, PLASTIC, SOT-38-1, DIP-16, Bus Driver/Transceiver 驱动 高压 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总14页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HEF4104B
Quad low-to-high voltage translator with 3-state outputs
Rev. 07 — 16 December 2009
Product data sheet
1. General description
The HEF4104B is a quad low voltage-to-high voltage translator with 3-state outputs. It
provides the capability of interfacing low voltage circuits to high voltage circuits. For
example low voltage Local Oxidation Complementary MOS (LOCMOS) and Transistor
Transistor Logic (TTL) to high voltage LOCMOS. It has four data inputs (A0 to A3), an
active HIGH output enable input (OE), four data outputs (B0 to B3) and their complements
(B0 to B3).
With OE = HIGH, the outputs B0 to B3 and B0 to B3 are in the low impedance ON-state,
either HIGH or LOW as determined by the inputs A0 to A3. With OE = LOW, the outputs
B0 to B3 and B0 to B3 are in the high-impedance OFF-state.
It uses a common negative supply (VSS) and separate positive supplies for the inputs
(VDD(A)) and the outputs (VDD(B)). VDD(A) must always be less than or equal to VDD(B), even
during power turn-on and turn-off. For the permissible operating range of VDD(A) and
V
DD(B) see Figure 4.
Each input protection circuit is terminated between VDD(B) and VSS. This allows the input
signals to be driven from any potential between VDD(B) and VSS, without regard to current
limiting. When driving from potentials greater than VDD(B) or less than VSS, the current at
each input must be limited to 10 mA.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is
also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.
2. Features
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Inputs and outputs are protected against electrostatic effects
Operates across the full industrial temperature range from −40 °C to +85 °C
Complies with JEDEC standard JESD 13-B
3. Applications
Industrial
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
4. Ordering information
Table 1.
Ordering information
All types operate from −40 °C to +85 °C.
Type number
Package
Name
Description
Version
HEF4104BP
HEF4104BT
DIP16
SO16
plastic dual in-line package; 16 leads (300 mil)
SOT38-4
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
5. Functional diagram
V
DD(A)
V
DD(B)
16
1
3
2
B0
B0
B1
B1
B2
B2
B3
B3
4
A0
LEVEL
CONVERTER
A0
A1
A2
A3
OE
B0
B0
B1
B1
B2
B2
B3
B3
5
6
A1
A2
7
LEVEL
CONVERTER
11
LEVEL
CONVERTER
10
9
LEVEL
CONVERTER
12
15
A3
13
14
LEVEL
CONVERTER
OE
LEVEL
CONVERTER
8
001aag264
V
SS
V
DD(A)
V
DD(B)
001aag262
Fig 1. Logic symbol
Fig 2. Logic diagram
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
2 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
6. Pinning information
6.1 Pinning
HEF4104B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
V
DD(A)
DD(B)
B0
OE
B3
B3
A3
A2
B2
B2
B0
A0
A1
B1
B1
V
SS
001aag263
Fig 3. Pin configuration
6.2 Pin description
Table 2.
Symbol
VDD(B)
Pin description
Pin
Description
supply voltage port B
1
B0 to B3
B0 to B3
A0 to A3
VSS
2, 7, 9, 14
complementary data output
data output
3, 6, 10, 13
4, 5, 11, 12
data input
8
common negative supply voltage (0 V)
output enable input
OE
15
16
VDD(A)
supply voltage port A
7. Functional description
Table 3.
Function table[1]
Control
Output
Bn
OE
H
Bn
An
Z
An
L
Z
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
3 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
VDD(A)
VDD(B)
IIK
Parameter
Conditions
Min
−0.5
−0.5
-
Max
+18
Unit
V
supply voltage A
supply voltage B
input clamping current
input voltage
port A; VDD(A) ≤ VDD(B)
port B; VDD(B) ≥ VDD(A)
VI < −0.5 V or VI > VDD(A) + 0.5 V
+18
V
±10
mA
V
VI
−0.5
-
VDD(A) + 0.5
±10
IOK
output clamping current
input/output current
supply current
VO < −0.5 V or VO > VDD(B) + 0.5 V
mA
mA
mA
°C
°C
II/O
-
±10
[1]
IDD
-
50
Tstg
storage temperature
ambient temperature
total power dissipation
−65
−40
+150
+85
Tamb
Ptot
Tamb = −40 °C to +85 °C
DIP16
[2]
[3]
-
-
-
750
500
100
mW
mW
mW
SO16
P
power dissipation
per output
[1] IDD is the combined current of IDD(A) and IDD(B)
.
[2] For DIP16 packages: above Tamb = 70 °C, Ptot derates linearly at 12 mW/K.
[3] For SO16 packages: above Tamb = 70 °C, Ptot derates linearly at 8 mW/K.
9. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
VDD(A)
VDD(B)
VI
Parameter
Conditions
Min
Typ
Max
≤ VDD(B)
15
Unit
supply voltage A
supply voltage B
input voltage
3
-
-
-
-
-
-
-
V
≥ VDD(A)
V
0
VDD(A)
+85
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
−40
°C
Δt/ΔV
VDD(A) = 5 V
VDD(A) = 10 V
VDD(A) = 15 V
-
-
-
3.75
0.5
μs/V
μs/V
μs/V
0.08
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
4 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
10. Static characteristics
Table 6.
Static characteristics
VDD(A) = VDD(B); VSS = 0 V; VI = VSS or VDD(A); unless otherwise specified.
[1]
Symbol Parameter
Conditions
VDD
Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Unit
Min
Max
Min
Max
Min
Max
VIH
HIGH-level
input voltage
|IO| < 1 μA
5 V
10 V
15 V
5 V
3.5
-
3.5
-
3.5
-
V
7.0
-
7.0
-
7.0
-
V
11.0
-
11.0
-
11.0
-
V
VIL
LOW-level
input voltage
|IO| < 1 μA
|IO| < 1 μA
|IO| < 1 μA
-
1.5
-
1.5
-
1.5
V
10 V
15 V
5 V
-
3.0
-
3.0
-
3.0
V
-
4.0
-
4.0
-
4.0
V
VOH
VOL
IOH
HIGH-level
output voltage
4.95
-
4.95
-
4.95
-
V
10 V
15 V
5 V
9.95
-
9.95
-
9.95
-
V
14.95
-
14.95
-
14.95
-
V
LOW-level
output voltage
-
0.05
-
0.05
-
0.05
V
10 V
15 V
5 V
-
0.05
-
0.05
-
0.05
V
-
−1.7
−0.52
−1.3
−3.6
0.52
1.3
3.6
-
0.05
-
−1.4
−0.44
−1.1
−3.0
0.44
1.1
3.0
-
0.05
-
−1.1
−0.36
−0.9
−2.4
0.36
0.9
2.4
-
0.05
V
HIGH-level
output current
VO = 2.5 V
VO = 4.6 V
VO = 9.5 V
VO = 13.5 V
VO = 0.4 V
VO = 0.5 V
VO = 1.5 V
-
-
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
5 V
10 V
15 V
5 V
-
-
-
-
IOL
LOW-level
output current
-
-
10 V
15 V
15 V
5 V
-
-
-
-
II
input leakage current
supply current
±0.3
20
40
80
1.6
±0.3
20
40
80
1.6
±1.0 μA
150 μA
300 μA
600 μA
12.0 μA
[2]
IDD
all valid input
combinations;
IO = 0 A
-
-
-
10 V
15 V
15 V
-
-
-
-
-
-
IOZ
OFF-state
output current
HIGH level;
VO = VDD(B)
-
-
-
LOW level;
VO = VSS
15 V
-
-
-
−1.6
-
-
−1.6
-
-
−12.0 μA
CI
input capacitance
digital inputs
-
7.5
-
pF
[1] VDD is the same as VDD(A) and VDD(B)
.
[2] IDD is the combined current of IDD(A) and IDD(B)
.
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
5 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
001aag265
15
V
DD(B)
(V)
operating area
10
5
0
0
5
10
15
V
DD(A)
(V)
The shaded area shows the permissible operating range.
Fig 4. VDD(B) as a function of VDD(A)
11. Dynamic characteristics
Table 7.
Dynamic characteristics
Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
Extrapolation formula[1] Min Typ
Max Unit
tPHL
tPLH
tTHL
tTLH
tPHZ
HIGH to LOW
propagation delay
An to Bn, Bn; see Figure 5
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
An to Bn, Bn; see Figure 5
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
143 ns + (0.55 ns/pF)CL
69 ns + (0.23 ns/pF)CL
57 ns + (0.16 ns/pF)CL
-
-
-
170
80
340
160
135
ns
ns
ns
65
LOW to HIGH
propagation delay
143 ns + (0.55 ns/pF)CL
69 ns + (0.23 ns/pF)CL
62 ns + (0.16 ns/pF)CL
-
-
-
170
80
340
160
140
ns
ns
ns
70
HIGH to LOW output Bn or Bn; see Figure 6
transition time
VDD(A) = VDD(B) = 5 V
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
-
-
-
60
30
20
120
60
ns
ns
ns
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
40
LOW to HIGH output Bn or Bn; see Figure 6
transition time
VDD(A) = VDD(B) = 5 V
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
-
-
-
60
30
20
120
60
ns
ns
ns
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
40
HIGH to OFF-state
propagation delay
OE to Bn, Bn; see Figure 6
VDD(A) = VDD(B) = 5 V
-
-
-
70
55
60
135
110
120
ns
ns
ns
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
6 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
Table 7.
Dynamic characteristics …continued
Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
Extrapolation formula[1] Min Typ
Max Unit
tPLZ
tPZH
tPZL
LOW to OFF-state
propagation delay
OE to Bn, Bn; see Figure 6
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
OE to Bn, Bn; see Figure 6
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
OE to Bn, Bn; see Figure 6
VDD(A) = VDD(B) = 5 V
VDD(A) = VDD(B) = 10 V
VDD(A) = VDD(B) = 15 V
-
-
-
70
55
55
135
105
110
ns
ns
ns
OFF-state to HIGH
propagation delay
-
-
-
195
95
395
195
165
ns
ns
ns
80
OFF-state to LOW
propagation delay
-
-
-
195
95
395
190
160
ns
ns
ns
80
[1] Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF).
Table 8.
Dynamic power dissipation
VDD(A) = VDD(B); VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
[1]
Symbol Parameter
PD dynamic power
dissipation
VDD
Typical formula (μW)
where
2
5 V PD = 3000 × fi + Σ(fo × CL) × VDD
fi = input frequency in MHz;
fo = output frequency in MHz;
2
2
10 V PD = 12200 × fi + Σ(fo × CL) × VDD
15 V PD = 31000 × fi + Σ(fo × CL) × VDD
CL = output load capacitance in pF;
Σ(fo × CL) = sum of the outputs;
VDD = supply voltage in V.
[1] VDD is the same as VDD(A) and VDD(B)
.
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
7 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
12. Waveforms
V
I
An input
V
M
0 V
t
t
t
PHL
PLH
V
OH
V
Y
Bn output
V
M
V
X
V
OL
t
t
THL
TLH
t
PLH
PHL
V
OH
V
Y
Bn output
V
X
V
OL
t
t
TLH
THL
001aaj783
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5. Data input (An) to data output (Bn, Bn) propagation delays and output transition times
V
I
OE input
V
M
V
SS
t
t
PLZ
PZL
V
OH
V
Y
output
LOW-to-OFF
OFF-to-LOW
V
X
V
OL
t
t
PHZ
PZH
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
X
V
OL
outputs on
outputs off
outputs on
001aaj782
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6. Enable and disable times
Table 9.
Input
VI
Measurement points
Output
VM
VM
VX
VY
VSS or VDD(A)
0.5VDD(A)
0.5VDD(B)
0.1VDD(B)
0.9VDD(B)
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
8 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
r
t
f
V
I
90 %
positive
pulse
V
M
M
10 %
0 V
t
W
001aaj781
a. Input waveforms
V
EXT
R
V
DD
L
V
V
O
I
G
DUT
R
T
C
L
001aaj915
b. Test circuit
Test data given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 7. Test circuit for measuring switching times
Table 10. Test data
Supplies
Input
tr, tf
Load
RL
VEXT
VDD(A) = VDD(B)
5 V to 15 V
CL
tPHL, tPLH
open
tPZL, tPLZ
tPZH, tPHZ
≤ 20 ns
1 kΩ
50 pF
VDD(B)
VSS
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
9 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
13. Package outline
DIP16: plastic dual in-line package; 16 leads (300 mil)
SOT38-4
D
M
E
A
2
A
A
1
L
c
e
w M
Z
b
1
(e )
1
b
b
2
16
9
M
H
pin 1 index
E
1
8
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
(1)
A
A
A
2
(1)
(1)
Z
1
w
UNIT
mm
b
b
b
c
D
E
e
e
L
M
M
H
1
2
1
E
max.
min.
max.
max.
1.73
1.30
0.53
0.38
1.25
0.85
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
8.25
7.80
10.0
8.3
4.2
0.51
3.2
2.54
0.1
7.62
0.3
0.254
0.01
0.76
0.068 0.021 0.049 0.014
0.051 0.015 0.033 0.009
0.77
0.73
0.26
0.24
0.14
0.12
0.32
0.31
0.39
0.33
inches
0.17
0.02
0.13
0.03
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
95-01-14
03-02-13
SOT38-4
Fig 8. Package outline SOT38-4 (DIP16)
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
10 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
v
c
y
H
M
A
E
Z
16
9
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
8
e
w
M
detail X
b
p
0
2.5
scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
p
Q
v
w
y
Z
θ
1
2
3
p
E
max.
0.25
0.10
1.45
1.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
6.2
5.8
1.0
0.4
0.7
0.6
0.7
0.3
mm
1.27
0.05
1.05
0.041
1.75
0.25
0.01
0.25
0.01
0.25
0.1
8o
0o
0.010 0.057
0.004 0.049
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.244
0.228
0.039 0.028
0.016 0.020
0.028
0.012
inches
0.069
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT109-1
076E07
MS-012
Fig 9. Package outline SOT109-1 (SO16)
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
11 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
14. Revision history
Table 11. Revision history
Document ID
HEF4104B_7
Release date
20091216
Data sheet status
Change notice
Supersedes
Product data sheet
-
HEF4104B_6
Modifications:
HEF4104B_6
• Section 12 “Waveforms” Figure 7 “Test circuit for measuring switching times” updated.
20091102
20090728
20090305
19950101
19950101
Product data sheet
Product data sheet
Product data sheet
Product specification
Product specification
-
-
-
-
-
HEF4104B_5
HEF4104B_4
HEF4104B_CNV_3
HEF4104B_CNV_2
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HEF4104B_5
HEF4104B_4
HEF4104B_CNV_3
HEF4104B_CNV_2
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
12 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
HEF4104B_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 16 December 2009
13 of 14
HEF4104B
NXP Semiconductors
Quad low-to-high voltage translator with 3-state outputs
17. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 December 2009
Document identifier: HEF4104B_7
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