HEF4104BTD [NXP]

IC 4000/14000/40000 SERIES, 4-BIT DRIVER, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOT-108, SO-14, Bus Driver/Transceiver;
HEF4104BTD
型号: HEF4104BTD
厂家: NXP    NXP
描述:

IC 4000/14000/40000 SERIES, 4-BIT DRIVER, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOT-108, SO-14, Bus Driver/Transceiver

驱动 高压 光电二极管 输出元件 逻辑集成电路
文件: 总5页 (文件大小:70K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
INTEGRATED CIRCUITS  
DATA SHEET  
For a complete data sheet, please also download:  
The IC04 LOCMOS HE4000B Logic  
Family Specifications HEF, HEC  
The IC04 LOCMOS HE4000B Logic  
Package Outlines/Information HEF, HEC  
HEF4104B  
MSI  
Quadruple low to high voltage  
translator with 3-state outputs  
January 1995  
Product specification  
File under Integrated Circuits, IC04  
Philips Semiconductors  
Product specification  
Quadruple low to high voltage translator  
with 3-state outputs  
HEF4104B  
MSI  
The device uses a common negative supply (VSS) and  
separate positive supplies for inputs (VDDI) and outputs  
(VDD0). VDDI must always be less than or equal to VDDO  
even during power turn-on and turn-off. For the  
permissible operating range of VDDI and VDDO see graph  
Fig.4.  
DESCRIPTION  
The HEF4104B quadruple low voltage to high voltage  
translator with 3-state outputs provides the capability of  
interfacing low voltage circuits to high voltage circuits,  
such as low voltage LOCMOS and TTL to high voltage  
LOCMOS. It has four data inputs (I0 to I3), an active HIGH  
output enable input (EO), four data outputs (O0 to O3) and  
their complements (O0 to O3).  
,
Each input protection circuit is terminated between  
VDDO and VSS. This allows the input signals to be driven  
from any potential between VDDO and VSS, without regard  
to current limiting. When driving from potentials greater  
than VDDO or less than VSS, the current at each input must  
be limited to 10 mA.  
With EO HIGH, O0 to O3 and O0 to O3 are in the low  
impedance ON-state, either HIGH or LOW as determined  
by I0 to I3; with EO LOW, O0 to O3 and O0 to O3 are in the  
high impedance OFF-state.  
Fig.2 Pinning diagram.  
HEF4104BP(N): 16-lead DIL; plastic  
(SOT38-1)  
HEF4104BD(F):  
16-lead DIL; ceramic (cerdip)  
(SOT74)  
HEF4104BT(D):  
16-lead SO; plastic  
(SOT109-1)  
( ): Package Designator North America  
PINNING  
I0 to I3  
EO  
data inputs  
output enable input  
data outputs  
O0 to O3  
O0 to O3  
complementary data outputs  
FAMILY DATA, IDD LIMITS category MSI  
See Family Specifications  
Fig.1 Functional diagram.  
January 1995  
2
Philips Semiconductors  
Product specification  
Quadruple low to high voltage translator  
with 3-state outputs  
HEF4104B  
MSI  
Fig.3 Logic diagram.  
January 1995  
3
Philips Semiconductors  
Product specification  
Quadruple low to high voltage translator  
with 3-state outputs  
HEF4104B  
MSI  
AC CHARACTERISTICS  
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns  
VDD  
TYPICAL EXTRAPOLATION  
FORMULA  
SYMBOL TYP. MAX.  
V
Propagation delays  
In On, On  
5
10  
15  
5
170  
80  
65  
170  
80  
70  
60  
30  
20  
60  
30  
20  
340  
160  
135  
340  
160  
140  
120  
60  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
143 ns  
69 ns  
57 ns  
143 ns  
69 ns  
62 ns  
10 ns  
9 ns  
+
+
+
+
+
+
+
+
+
+
+
+
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(0,55 ns/pF) CL  
(0,23 ns/pF) CL  
(0,16 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
(1,0 ns/pF) CL  
(0,42 ns/pF) CL  
(0,28 ns/pF) CL  
HIGH to LOW  
tPHL  
tPLH  
tTHL  
tTLH  
LOW to HIGH  
10  
15  
5
Output transition times  
HIGH to LOW  
10  
15  
5
40  
6 ns  
120  
60  
10 ns  
9 ns  
LOW to HIGH  
10  
15  
40  
6 ns  
3-state propagation  
delays  
Output disable times  
EO On, On  
HIGH  
5
10  
15  
5
70  
55  
60  
70  
55  
55  
135  
110  
120  
135  
105  
110  
ns  
ns  
ns  
ns  
ns  
ns  
tPHZ  
LOW  
10  
15  
tPLZ  
Output enable times  
EO On, On  
HIGH  
5
10  
15  
5
195  
95  
395  
195  
165  
395  
190  
160  
ns  
ns  
ns  
ns  
ns  
ns  
tPZH  
80  
195  
95  
LOW  
10  
15  
tPZL  
80  
VDD  
V
TYPICAL FORMULA FOR P (µW)  
2
Dynamic power  
dissipation per  
package (P)  
5
10  
15  
3 000 fi + ∑ (foCL) × VDD  
where  
2
12 200 fi + ∑ (foCL) × VDD  
fi = input freq. (MHz)  
2
31 000 fi + ∑ (foCL) × VDD  
fo = output freq. (MHz)  
CL = load capacitance (pF)  
(foCL) = sum of outputs  
V
DD = supply voltage (V)  
January 1995  
4
Philips Semiconductors  
Product specification  
Quadruple low to high voltage translator  
with 3-state outputs  
HEF4104B  
MSI  
Fig.4 VDDO as a function of VDDI; the shaded area shows the permissible operating range.  
January 1995  
5

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