HEF4505BDF [NXP]
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| 型号： | HEF4505BDF |
| 厂家： | 
NXP |
| 描述： | 暂无描述 存储 |
| 文件： | 总8页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4505B
LSI
64-bit, 1-bit per word random
access read/write memory
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
64-bit, 1-bit per word random access
read/write memory
HEF4505B
LSI
DESCRIPTION
The HEF4505B is a 64-bit, 1-bit per word, fully decoded
and completely static, random access memory. The
memory is strobed for reading or writing only when the
strobe input (ST), chip enable inputs (CE1 and CE2) are
HIGH simultaneously. The output data is available at the
data output (DOUT) only when the memory is strobed, the
read/write input (R/W) is HIGH and after the read access
time has passed. Note that the three-state output is initially
disabled and always goes to the LOW state before data is
valid. The output is disabled in the high-impedance
OFF-state, when the memory is not strobed or R/W is
LOW. R/W may remain HIGH during a read cycle or LOW
during a write cycle. The output data has the same polarity
as the input data.
Fig.1 Pinning diagram.
HEF4505BP(N):
HEF4505BD(F):
14-lead DIL; plastic
(SOT27-1)
14-lead DIL; ceramic (cerdip)
(SOT73)
( ): Package Designator North America
PINNING
SUPPLY VOLTAGE
A0 to A5
CE1, CE2
R/W
address inputs
chip enable inputs
read/write input
strobe input
RATING
OPERATING
4,5 to 15 V
−0,5 to +15
Note
ST
1. Minimum standby voltage for data retention is 3 V.
DIN
data input
DOUT
data output
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
FUNCTION TABLE
ST, CE1, CE2 R/W
DOUT
MODE
L
H
L
L
L
Z
Z
Z
disabled
write
H
H
disabled
H
equal to memory data read
Note
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
Z = high-impedance OFF-state
January 1995
2
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Fig.2 Functional diagram.
Philips Semiconductors
Product specification
64-bit, 1-bit per word random access
read/write memory
HEF4505B
LSI
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
Minimum strobe pulse
5
75
45
30
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
width; LOW
10
15
5
tSTL
22
15
350 700
250 500
210 420
220 440
125 250
75 150
330 660
135 270
100 200
40
Read cycle time
Write cycle time
10
15
5
tRC
10
15
5
tWC
tACC
tAR
303 ns + (0,55 ns/pF) CL
124 ns + (0,23 ns/pF) CL
92 ns + (0,16 ns/pF) CL
Read access time
Address recovery time
Read recovery time
10
15
5
80
40
10
15
5
20
25
10
180
120
90
90
10
15
5
tRR
60
45
75
35
Write recovery time
10
15
tWR
45
25
40
20
3-state propagation delays
Output disable times
5
10
15
5
105 210
60 125
55 115
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPHZ
tPLZ
,
Set-up times
−20 −40
−10 −20
−5 −10
−30 −60
−15 −30
−5 −10
An → ST
10
15
5
tsuA
tsuR
tsuD
tsuW
R/W → ST
10
15
5
160
75
80
35
20
DIN → ST
10
15
5
45
240 120
R/W → ST
10
15
100
75
50
35
January 1995
4
Philips Semiconductors
Product specification
64-bit, 1-bit per word random access
read/write memory
HEF4505B
LSI
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
−20 −40
Hold time
5
ns
ns
ns
DIN → ST
10
15
tholdD
5
−10
10
0
(1) Output in high impedance OFF-state.
(2) tSTHmin = tRCmax − tSTLmin
.
Fig.3 Read cycle timing diagram.
January 1995
5
Philips Semiconductors
Product specification
64-bit, 1-bit per word random access
read/write memory
HEF4505B
LSI
(1) tSTHmin = tWCmax − tSTLmin.
Fig.4 Write cycle timing diagram.
January 1995
6
Philips Semiconductors
Product specification
64-bit, 1-bit per word random access
read/write memory
HEF4505B
LSI
APPLICATION INFORMATION
Fig.5 256-word by n-bit static read/write memory using HEF4505B ICs.
January 1995
7
Philips Semiconductors
Product specification
64-bit, 1-bit per word random access
read/write memory
HEF4505B
LSI
Figure 5 shows a 256-word by n-bit static RAM system.
The outputs of the four HEF4505B circuits are tied
together to form 256 words by 1-bit. Additional bits are
attained by paralleling the inputs in groups of four.
Memories of larger words can be attained by decoding the
most significant bits of the address and AND-ing them with
the strobe input.
The memory system shown in Fig.5 can be interfaced
directly with other ICs of the LOCMOS HE family. No
external components are required.
Non-volatile information storage is allowed due to very low
power dissipation when the memory is powered by a small
standby battery. Figure 6 shows an optional standby
power supply circuit for making a LOCMOS memory
‘non-volatile’. When the usual power fails, a battery is used
to sustain operation or maintain stored information. While
normal power supply voltage is present, the battery is
trickle-charged through a resistor (R) which sets the
charging rate. In Fig.6 the sustaining voltage is VB, and + V
is the ordinary voltage from a power supply. VDD is
connected to the power supply pin of the memory.
Low-leakage diodes are recommended to conserve
battery power.
Fan-in and fan-out of the memory are limited only by speed
requirements. The extremely low input and output leakage
currents keep the output voltage levels from changing
significantly as more outputs are tied together. With the
output levels independent of fan-out, most of the power
supply range is available as logic swing, regardless of the
number of units wired together. As a result, high noise
immunity is maintained under all conditions.
Fig.6 Standby battery circuit.
January 1995
8
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