HEF4511B_09_技术文档

HEF4511B

BCD to 7-segment latch/decoder/driver

Rev. 06 — 7 December 2009

Product data sheet

1. General description

The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs

(D0 to D3), an active HIGH latch enable input (LE), an active LOW ripple blanking input

(BL), an active LOW lamp test input (LT), and seven active HIGH NPN bipolar transistor

segment outputs (Qa to Qg).

When LE is LOW and BL is HIGH, the state of the segment outputs (Qa to Qg) is

determined by the data on D0 to D3. When LE goes HIGH, the last data present on D0 to

D3 is stored in the latches and the segment outputs remain unchanged. When LT is LOW,

all of the segment outputs are HIGH independent of all other input conditions. With LT

HIGH, a LOW on BL forces all segment outputs LOW. The inputs LT and BL do not affect

the latch circuit.

It operates over a recommended V_DDpower supply range of 3 V to 15 V referenced to V_SS

(usually ground). Unused inputs must be connected to V_DD, V_SS, or another input. It is

also suitable for use over the industrial (−40 °C to +85 °C) and automotive (−40 °C to

+125 °C) temperature ranges.

2. Features

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Operates across the automotive temperature range −40 °C to +125 °C

Complies with JEDEC standard JESD 13-B

3. Applications

Automotive and industrial

4. Ordering information

Table 1.

Ordering information

All types operate from −40 °C to +125 °C.

Type number

Package

Name

Description

Version

HEF4511BP

HEF4511BT

DIP16

SO16

plastic dual in-line package; 16 leads (300 mil)

plastic small outline package; 16 leads; body width 3.9 mm

SOT38-4

SOT109-1

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

5. Functional diagram

7

1

2

6

D0

D1

D2

D3

5

4

3

LE

LATCHES

DECODER

DRIVERS

BL

LT

Qg

14

Qf

15

Qe

9

Qd

10

Qc

11

Qb

12

Qa

13

001aae675

Fig 1. Functional diagram

V

DD

driver

logic

I

OH

+

V

OH

−

V

SS

001aae677

Fig 2. Schematic diagram of output stage

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

2 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

6. Pinning information

6.1 Pinning

HEF4511B

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

D1

D2

LT

BL

LE

D3

D0

V

DD

Qf

Qg

Qa

Qb

Qc

Qd

Qe

V

SS

001aae676

Fig 4. Pin configuration DIP16 and SO16

6.2 Pin description

Table 2.

Symbol

LT

Pin description

Description

3

lamp test input (active LOW)

ripple blanking input (active LOW)

latch enable input (active HIGH)

address (data) input

BL

4

LE

5

D0 to D3

V_SS

7, 1, 2, 6

8

ground supply voltage

segment output

Qa to Qg

V_DD

13, 12, 11, 10, 9, 15, 14

16

supply voltage

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

4 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

7. Functional description

Table 3.

Function table^[1]

Inputs

Outputs

Display

LE

X

L

BL

X

LT

L

D3

X

L

D2

X

L

D1

X

L

D0

X

L

Qa

H

L

Qb

Qc

H

Qd

H

L

Qe

H

L

Qf

H

L

Qg

H

L

H

L

8

L

H

L

blank

H

L

H

L

H

L

H

L

H

L

0

L

H

L

H

L

1

L

H

L

H

L

H

L

H

L

H

L

2

L

H

L

H

L

3

L

H

L

H

L

H

L

4

L

H

L

H

L

H

L

5

L

H

L

H

L

6

L

H

L

H

L

H

L

H

7

L

H

X

H

L

H

L

H

L

H

L

8

L

H

X

H

9

L

H

X

L

blank

N.C.

L

H

X

L

H

N.C.

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; N.C. = no change.

a

g

f

b

e

c

d

001aaj494

Fig 5. Seven segment digital display with segment designation

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

5 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

I_IK

Parameter

Conditions

Min

−0.5

-

Max

+18

Unit

V

supply voltage

input clamping current

input voltage

V_I< −0.5 V or V_I> V_DD+ 0.5 V

V_O< −0.5 V or V_O> V_DD+ 0.5 V

±10

mA

V

V_I

−0.5

-

V_DD+ 0.5

±10

I_OK

output clamping current

input/output current

HIGH-level output current

supply current

mA

°C

I_I/O

-

±10

[1]

I_OH

−25

-

I_DD

50

T_stg

T_amb

P_tot

storage temperature

ambient temperature

total power dissipation

−65

−40

+150

+125

°C

T_amb= 125 °C

DIP16 package

SO16 package

per output

[2]

[3]

-

750

500

100

mW

P

power dissipation

[1] A destructive high current mode may occur if V_Iand V_Oare not constrained to the range V_SS≤ V_Ior V_O≤ V_DD

[2] For DIP16 package: P_totderates linearly with 12 mW/K above 70 °C.

.

[3] For SO16 package: P_totderates linearly with 8 mW/K above 70 °C.

9. Recommended operating conditions

Table 5.

Symbol

V_DD

Recommended operating conditions

Parameter

Conditions

Min

Typ

Max

15

Unit

supply voltage

3

-

V

V_I

input voltage

0

V_DD

+125

3.75

0.5

V

T_amb

ambient temperature

input transition rise and fall rate

in free air

−40

°C

Δt/ΔV

V_DD= 5 V

V_DD= 10 V

V_DD= 15 V

-

μs/V

0.08

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

6 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

10. Static characteristics

Table 6.

Static characteristics

V_SS= 0 V; V_I= V_SSor V_DD; unless otherwise specified.

Symbol Parameter Conditions V_DDT_amb= −40 °C T_amb= +25 °C T_amb= +85 °C T_amb= +125 °C Unit

Min

Max

Min

Max

Min

Max

Min

Max

V_IH

HIGH-level

input voltage

|I_O| < 1 μA

5 V

10 V

15 V

5 V

3.5

-

3.5

-

3.5

-

3.5

-

V

-

7.0

11.0

-

11.0

-

11.0

-

11.0

-

V_IL

LOW-level

input voltage

-

1.5

3.0

4.0

-

1.5

3.0

4.0

-

1.5

3.0

4.0

-

1.5

3.0

4.0

-

10 V

15 V

-

V_OH

V_OL

HIGH-level

output voltage

see Table 7

LOW-level

output voltage

|I_O| < 1 μA

5 V

10 V

15 V

5 V

-

0.05

-

0.05

-

0.05

-

0.05

V

0.05

-

0.05

V

-

0.05

-

0.05

-

0.05

-

0.05

V

I_OH

HIGH-level

output current

V_O= 2.5 V

V_O= 4.6 V

V_O= 9.5 V

−1.7

−0.64

−1.6

−4.2

0.64

1.6

4.2

-

−1.4

−0.5

−1.3

−3.4

0.5

1.3

3.4

-

−1.1

−0.36

−0.9

−2.4

0.36

0.9

2.4

-

−1.1

−0.36

−0.9

−2.4

0.36

0.9

2.4

-

mA

5 V

-

10 V

-

V_O= 13.5 V 15 V

-

I_OL

LOW-level

output current

V_O= 0.4 V

V_O= 0.5 V

V_O= 1.5 V

5 V

10 V

15 V

-

I_I

input leakage

current

±0.1

±1.0

±1.0 μA

I_DD

supply current I_O= 0 A

5 V

10 V

15 V

-

5

10

20

-

5

-

150

300

600

-

150

300

600

-

μA

pF

10

20

7.5

C_I

input

capacitance

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

7 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

Table 7.

Static characteristics for V_OH

V_SS= 0 V.

Symbol Parameter

I_OH

mA

0

V_DD

V

T_amb= −40 °C

T_amb= +25 °C

T_amb= +85 °C

T_amb= +125 °C Unit

Min

4.10

9.10

Typ

4.40

9.90

Min

V_OH

HIGH-level

5 V

4.10

V

output voltage

10 V

15 V

5 V

9.10

14.10

14.10 14.40

14.10

5

10

15

20

25

-

4.30

9.30

-

10 V

15 V

5 V

-

14.30

4.25

-

3.60

8.75

3.30

3.20

10 V

15 V

5 V

8.75

9.25

8.45

8.35

13.75

13.75 14.30

13.45

13.35

-

4.20

9.20

-

10 V

15 V

5 V

-

14.20

4.20

-

2.80

8.10

2.50

2.30

10 V

15 V

5 V

8.10

9.20

7.80

7.60

13.10

13.10 14.20

12.80

12.60

-

4.15

9.20

-

10 V

15 V

14.20

11. Dynamic characteristics

Table 8.

Dynamic characteristics

V_SS= 0 V; T_amb= 25 °C; for test circuit see Figure 8.

Symbol Parameter

Conditions

V_DD

5 V

Extrapolation formula^[1]

128 ns + (0.55 ns/pF)C_L

49 ns + (0.23 ns/pF)C_L

32 ns + (0.16 ns/pF)C_L

133 ns + (0.55 ns/pF)C_L

49 ns + (0.23 ns/pF)C_L

37 ns + (0.16 ns/pF)C_L

93 ns + (0.55 ns/pF)C_L

39 ns + (0.23 ns/pF)C_L

27 ns + (0.16 ns/pF)C_L

52 ns + (0.55 ns/pF)C_L

19 ns + (0.23 ns/pF)C_L

12 ns + (0.16 ns/pF)C_L

Min

Typ

Max

310

120

80

Unit

ns

t_PHL

HIGH to LOW

Dn → Qn;

see Figure 6

-

155

60

propagation delay

10 V

15 V

5 V

40

LE → Qn;

see Figure 6

160

60

320

120

90

10 V

15 V

5 V

45

BL → Qn;

see Figure 6

120

50

240

100

70

10 V

15 V

5 V

35

LT → Qn;

see Figure 6

80

160

60

10 V

15 V

30

20

40

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

8 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

Table 8.

Dynamic characteristics …continued

V_SS= 0 V; T_amb= 25 °C; for test circuit see Figure 8.

Symbol Parameter

Conditions

V_DD

5 V

Extrapolation formula^[1]

108 ns + (0.55 ns/pF)C_L

44 ns + (0.23 ns/pF)C_L

32 ns + (0.16 ns/pF)C_L

133 ns + (0.55 ns/pF)C_L

59 ns + (0.23 ns/pF)C_L

42 ns + (0.16 ns/pF)C_L

78 ns + (0.55 ns/pF)C_L

29 ns + (0.23 ns/pF)C_L

22 ns + (0.16 ns/pF)C_L

33 ns + (0.55 ns/pF)C_L

19 ns + (0.23 ns/pF)C_L

17 ns + (0.16 ns/pF)C_L

10 ns + (1.00 ns/pF)C_L

9 ns + (0.42 ns/pF)C_L

6 ns + (0.28 ns/pF)C_L

20 ns + (1.00 ns/pF)C_L

13 ns + (0.06 ns/pF)C_L

10 ns + (0.06 ns/pF)C_L

Min

Typ

135

55

40

160

70

50

105

40

30

60

30

25

60

30

20

25

16

13

25

12

9

Max

270

110

80

320

140

100

210

80

60

120

60

50

120

60

40

50

32

26

-

Unit

ns

t_PLH

LOW to HIGH

Dn → Qn;

see Figure 6

-

propagation delay

10 V

15 V

5 V

-

LE → Qn;

see Figure 6

-

10 V

15 V

5 V

-

BL → Qn;

see Figure 6

-

10 V

15 V

5 V

-

LT → Qn;

see Figure 6

-

10 V

15 V

5 V

-

t_THL

t_TLH

t_su

HIGH to LOW output see Figure 6

transition time

-

10 V

15 V

5 V

-

LOW to HIGH output see Figure 6

transition time

-

10 V

15 V

5 V

-

set-up time

hold time

Dn → LE;

see Figure 7

50

25

20

60

30

25

80

40

35

10 V

15 V

5 V

-

t_h

Dn → LE;

see Figure 7

30

15

12

40

20

17

-

10 V

15 V

5 V

-

t_W

pulse width

LE input LOW;

minimum width;

see Figure 7

-

10 V

15 V

-

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C_Lin pF).

Table 9.

Dynamic power dissipation P_D

P_Dcan be calculated from the formulas shown. V_SS= 0 V; t_r= t_f≤ 20 ns; T_amb= 25 °C.

Symbol

Parameter

V_DD

5 V

Typical formula for P_D(μW)

P_D= 1000 × f_i+ Σ(f_o× C_L) × V_DD

P_D= 4000 × f_i+ Σ(f_o× C_L) × V_DD

where:

2

P_D

dynamic power

dissipation

f_i= input frequency in MHz;

f_o= output frequency in MHz;

C_L= output load capacitance in pF;

10 V

15 V

2

P_D= 10000 × f_i+ Σ(f_o× C_L) × V_DD

V_DD= supply voltage in V;

Σ(f_o× C_L) = sum of the outputs.

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

9 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

12. Waveforms

V

I

LE

D2

LT

BL

V

M

V

SS

V

I

V

M

SS

V

I

SS

t

PHL

V

I

V

M

SS

t

PLH

t

PHL

V

OH

90 %

THL

V

Qg

M

10 %

V

OL

t

TLH

001aaj495

Conditions: D3 = LOW and D0 = D1 = HIGH.

Measurement points are given in Table 10.

Fig 6. Propagation delays and output transition times

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

10 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

V

I

V

M

LE input

V

SS

t

W

V

I

V

M

D2 input

V

SS

t

su

t

h

V

OH

Qg output

V

OL

001aae682

The shaded area indicates where the input is permitted to change for predictable output performance.

Conditions: D3 = LOW and D0 = D1 = BL = LT = HIGH.

Measurement points are given in Table 10.

Fig 7. Waveforms showing minimum LE pulse width, set-up, and hold time for Dn to LE

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

11 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

t

W

V

I

90 %

negative

pulse

V

M

10 %

0 V

t

r

f

t

r

t

f

V

I

90 %

positive

pulse

M

10 %

0 V

t

W

001aaj781

a. Input waveforms

V

DD

V

I

V

O

G

DUT

C

L

R

T

001aag182

b. Test circuit

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

C_L= Load capacitance including jig and probe capacitance.

R_T= Termination resistance should be equal to output impedance Z_oof the pulse generator.

Fig 8. Test circuit for measuring switching times

Table 10. Measurement points and test data

Supply voltage

Input

V_I

Load

C_L

V_M

t_r, t_f

5 V to 15 V

V_DD

0.5V_I

≤ 20 ns

50 pF

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

12 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

13. Application information

• Driving LED displays

• Driving incandescent displays

• Driving fluorescent displays

• Driving LCD displays

• Driving gas discharge displays

common anode

LED

V

DD

V

DD

≈ 1.7 V

common cathode

LED

≈ 1.7 V

V

SS

V

SS

001aae683

001aae684

Fig 9. Connection to common cathode LED display

readout

Fig 10. Connection to common anode LED display

readout

V

DD

V

DD

V

DD

direct

(low brightness)

(1)

to

filament

supply

V

SS

V

SS

V

SS

001aae685

001aae686

(1) A filament pre-warm resistor is recommended to

reduce filament thermal shock and increase the effective

cold resistance of the filament.

Fig 11. Connection to incandescent display readout

Fig 12. Connection to fluorescent display readout

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

13 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

exitation

appropriate

voltage

V

DD

V

DD

(square wave;

V

SS to DD)

1/4 HEF4070B

V

SS

V

SS

001aae687

001aae688

Direct DC drive of LCDs not recommended for life of

LCD readouts.

Fig 13. Connection to gas discharge display readout

Fig 14. Connection to LCD readout

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

14 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

14. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

D

M

E

A

2

A

1

L

c

e

w M

Z

b

1

(e )

1

b

2

16

9

M

H

pin 1 index

E

1

8

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

2

1

E

max.

min.

max.

1.73

1.30

0.53

0.38

1.25

0.85

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

0.76

0.068 0.021 0.049 0.014

0.051 0.015 0.033 0.009

0.77

0.73

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.03

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

95-01-14

03-02-13

SOT38-4

Fig 15. Package outline SOT38-4 (DIP16)

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

15 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

D

E

A

X

v

c

y

H

M

A

E

Z

16

9

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

8

e

w

M

detail X

b

p

0

2.5

scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.39

0.014 0.0075 0.38

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.020

0.028

0.012

inches

0.069

0.01 0.004

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-19

SOT109-1

076E07

MS-012

Fig 16. Package outline SOT109-1 (SO16)

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

16 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

15. Revision history

Table 11. Revision history

Document ID

HEF4511B_6

Release date

20091207

Data sheet status

Change notice

Supersedes

Product data sheet

-

HEF4511B_5

Modifications:

• Section 9 “Recommended operating conditions”: Δt/ΔV values updated.

HEF4511B_5

20090813

20090305

19950101

Product data sheet

Product specification

-

HEF4511B_4

HEF4511B_CNV_3

HEF4511B_CNV_2

-

HEF4511B_4

HEF4511B_CNV_3

HEF4511B_CNV_2

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

17 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

16. Legal information

16.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between information in this document and such

terms and conditions, the latter will prevail.

16.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

16.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

HEF4511B_6

Product data sheet

Rev. 06 — 7 December 2009

18 of 19

HEF4511B

NXP Semiconductors

BCD to 7-segment latch/decoder/driver

18. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ordering information. . . . . . . . . . . . . . . . . . . . . 1

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7

Functional description . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

Recommended operating conditions. . . . . . . . 6

Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

Dynamic characteristics . . . . . . . . . . . . . . . . . . 8

Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Application information. . . . . . . . . . . . . . . . . . 13

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17

8

9

10

11

12

13

14

15

16

Legal information. . . . . . . . . . . . . . . . . . . . . . . 18

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18

Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

16.1

16.2

16.3

16.4

17

18

Contact information. . . . . . . . . . . . . . . . . . . . . 18

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 7 December 2009

Document identifier: HEF4511B_6


型号：	HEF4511B_09
厂家：	NXP
描述：	BCD to 7-segment latch/decoder/driver BCD至7段锁存器/解码器/驱动器解码器驱动器锁存器 CD
文件：	总19页 (文件大小：531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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