HEF4517BTD [NXP]
IC 4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SO-16, Shift Register;
| 型号： | HEF4517BTD |
| 厂家： | 
NXP |
| 描述： | IC 4000/14000/40000 SERIES, 64-BIT RIGHT SERIAL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, PLASTIC, SO-16, Shift Register 移位寄存器 |
| 文件： | 总8页 (文件大小：79K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4517B
LSI
Dual 64-bit static shift register
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4517B
LSI
Dual 64-bit static shift register
When PE/EO is LOW the outputs are enabled and the
device is in the 64-bit serial mode.
DESCRIPTION
The HEF4517B consists of two identical, independent
64-bit static shift registers. Each register has separate
clock (CP), data input (D), parallel
input-enable/output-enable (PE/EO) and four 3-state
outputs of the 16th, 32nd, 48th and 64th bit positions
(O16 to O64). Data at the D input is entered into the first bit
on the LOW to HIGH transition of the clock, regardless of
the state of PE/EO.
When PE/EO is HIGH the outputs are disabled (high
impedance OFF-state), the 64-bit shift register is divided
into four 16-bit shift registers with D, O16, O32 and O48 as
data inputs of the 1st, 17th, 33rd, and 49th bit respectively.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4517B
LSI
Dual 64-bit static shift register
Fig.2 Pinning diagram.
HEF4517BP(N):
HEF4517BD(F):
HEF4517BT(D):
16-lead DIL; plastic (SOT38-1)
16-lead DIL; ceramic (cerdip) (SOT74)
16-lead SO; plastic (SOT109-1)
( ): Package Designator North America
PINNING
CPA, CPB
clock inputs
PE/EOA, PE/EOB
DA, DB
parallel input-enable/output-enable inputs
data inputs
O16A, O32A, O48A
3-state outputs/inputs
3-state outputs/inputs
3-state outputs
O16B, O32B, O48B
O64A, O64B
January 1995
3
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Fig.3 Logic diagram (one shift register).
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FUNCTION TABLE
INPUTS
INPUTS/OUTPUTS
O32 O48
MODE
CP
D
PE/EO
O16
O64
content of
64th bit
displayed
data entered
into 1st bit
L
content of
16th bit
displayed
content of
32nd bit
content of
48th bit
One 64-bit shift
register. The content of the
shift register is
displayed
displayed
shifted over one stage
data entered
into 1st bit
H
data at
data at
data at
remains in
‘Z’ state
Four 16-bit shift
O16 entered
O32 entered into O48 entered
33rd bit
register. The content of
the shift registers is
shifted over one stage.
into 17th bit
into 49th bit
X
X
L
no change
Z
no change
Z
no change
Z
no change
Z
no change
no change
H
Notes
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
Z = high impedance state
= positive-going transition
= negative-going transition
Philips Semiconductors
Product specification
HEF4517B
LSI
Dual 64-bit static shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns
VDD
V
TYPICAL FORMULA FOR P (µW)
2
2
Dynamic power
5
7 000 fi + ∑ (foCL) × VDD
where
dissipation per
package (P)
10
15
28 000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
70 000 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
V
DD = supply voltage (V)
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN. TYP. MAX.
V
Propagation delays
CP → On
HIGH to LOW
5
10
15
5
220
85
440
170
120
380
150
100
ns
ns
ns
ns
ns
ns
193 ns + (0,55 ns/pF) CL
74 ns + (0,23 ns/pF) CL
52 ns + (0,16 ns/pF) CL
163 ns + (0,55 ns/pF) CL
64 ns + (0,23 ns/pF) CL
42 ns + (0,16 ns/pF) CL
tPHL
60
190
75
LOW to HIGH
10
15
tPLH
50
Output transition
times
5
10
15
5
60
30
20
60
30
20
120
60
ns
ns
ns
ns
ns
ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tTHL
40
120
60
LOW to HIGH
10
15
tTLH
40
January 1995
6
Philips Semiconductors
Product specification
HEF4517B
LSI
Dual 64-bit static shift register
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
95
MAX.
Minimum clock
5
190
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
pulse width; LOW
10
15
5
tWCPL
40
30
10
5
60
Set-up times
30
see also waveforms
Fig.4.
On, D → CP
10
15
5
tsu
25
20
45
30
25
5
Hold time
15
10
10
On, D → CP
10
15
thold
3-state propagation
delays
Output disable times
PE/EO → On
HIGH
5
10
15
5
40
30
25
50
30
25
80
60
ns
ns
ns
ns
ns
ns
tPHZ
50
100
60
LOW
10
15
tPLZ
50
Output enable times
PE/EO → On
HIGH
5
10
15
5
45
25
20
60
30
25
5
90
50
ns
tPZH
tPZL
fmax
ns
40
ns
120
60
ns
LOW
10
15
5
ns
50
ns
Maximum clock
pulse frequency
2
6
8
MHz
MHz
MHz
10
15
12
16
January 1995
7
Philips Semiconductors
Product specification
HEF4517B
LSI
Dual 64-bit static shift register
Fig.4 Waveforms showing minimum clock pulse width, set-up and hold times for On (as data input) and D to CP.
January 1995
8
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