HEF4753BD [NXP]
Universal timer module; 通用定时器模块
| 型号： | HEF4753BD |
| 厂家： | 
NXP |
| 描述： | Universal timer module |
| 文件： | 总10页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
• The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4753B
LSI
Universal timer module
January 1995
Product specification
File under Integrated Circuits, IC04
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
transient-pulse suppression, pulse duration selector
DESCRIPTION
divider, counter, positive or negative edge delaying
module or low-frequency control circuit.
The HEF4753B is a universal timer module for counting
and dividing as well as for event-recognition and
manipulation of input sequences.
The following functions are included: synchronization and
edge-detection of the input signal, programmable counter,
clock divider with different lengths, operating mode
decoder, control logic and output multiplexer.
All manipulation possibilities depend on a time scaling,
which is adjustable by the 8-bit programmable counter and
the system clock. The system clock can be divided
internally by 1, 16, 256 or 4096 as input clock for the
counter. In all cases the manipulated input sequence
appears at the only output OUT.
Depending on the operating mode and the application, the
circuit works as a presettable 8-bit counter with
Fig.1 Functional diagram.
FAMILY DATA, IDD LIMITS category LSI
See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
FUNCTION TABLES
INPUTS
OPERATING MODE
LFC
Y
Z
L
L
L
H
H
L
H
L
counter
divider
H
L
delayed LOW to HIGH edge
delayed HIGH to LOW edge
transient pulse suppression
frequency recognition
H
H
H
H
L
H
H
H
L
L
LFC
digital pulse duration selector
Fig.2 Pinning diagram.
Notes
1. H = HIGH state (the more positive voltage).
2. L = LOW state (the less positive voltage).
HEF4753BP(N): 18-lead DIL; plastic
(SOT102-3)
HEF4753BD(N): 18-lead DIL; ceramic (cerdip)
(SOT133)
( ): Package Designator North America
Programmable 8-bit counter (1)
12-bit predivider
CLOCK FOR PROGRAMMABLE
INPUTS ACTIVE LOW
VALUE
W
X
COUNTER CP/X
A
B
C
D
E
F
1
2
L
L
L
H
L
X = 1
X =16
4
H
H
X = 256
X = 4096
8
H
16
32
64
128
G
H
Note
1. All inputs A to H HIGH is not allowed.
January 1995
3
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
FUNCTIONAL DESCRIPTION
Clock divider and decoder
Mode switch and output multiplexer
This function switches the chosen output to the output
(OUT) and gives the mode of which the edge at input IN
has to be detected. The inputs Z, Y and LFC give 7 modes
+1, that means in mode ‘Digital Filter’ the input LFC can be
HIGH or LOW.
The clock signal at input CP is, at its original frequency, the
system clock, but it also drives the programmable counter.
The counter input frequency can be predivided by the
factors 1/16, 1/256 and 1/4096, depending on the logic
state of inputs W and X (according to the function tables
above).
OPERATING MODES
The circuit has 6 operating modes which are activated by
the logic state of inputs LFC, Y and Z. An extra mode is
possible by using two circuits which are connected such so
they function as a digital band-filter.
8-bit programmable counter
The 8 inputs A to H are the set inputs of the 8 counter
flip-flops. The setting is triggered by an edge of the input
signal (at input IN) depending on of the chosen mode.
1. Counter mode (LFC = LOW; Y = LOW; Z = HIGH)
In this mode the output OUT should be connected to input
IN. If not, only one counter cycle starts after a transition at
input IN (see Fig.3 and note 1.).
Event flip-flops, synchronization and edge-detection
The event flip-flops are used to recognize the positive
and/or negative edge of the input signal at IN.
Parts of the flip-flops are used together with the
programmable 8-bit counter as a retriggerable mono-flop,
which defines the time scaling for event recognition.
The input IN is synchronized by the clock signal CP.
A
H
B
H
C
L
D
H
E
H
F
G
H
H
H
W
L
X
L
LFC
L
Y
L
Z
H
H
Fig.3 Timing diagram for counter mode; t1 = delay until set of 8-bit counter; t2 = delay to set 8-bit counter;
t3 = predefined delay by programming.
January 1995
4
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
2. Divider mode (LFC = LOW; Y = HIGH; Z = LOW)
In this mode the output OUT should be connected to input IN. If not, only one counter cycle starts after a transition at
input IN (see Fig.4 and note 1.).
A
L
B
L
C
H
D
H
E
H
F
G
H
H
H
W
L
X
L
LFC
L
Y
H
Z
L
H
Fig.4 Timing diagram for divider mode; t1 = delay until set of 8-bit counter; t2, t3 see Fig.3.
3. Delayed LOW to HIGH edge mode; see note 2. (LFC = HIGH; Y = HIGH; Z = LOW)
A
H
B
L
C
H
D
H
E
H
F
G
H
H
H
W
L
X
L
LFC
H
Y
H
Z
L
H
Fig.5 Timing diagram for delayed LOW to HIGH edge mode; t1 = delay until set of 8-bit counter; t2 = delay to
set 8-bit counter; t3 = predefined delay by programming; t4 = delay until next negative clock edge;
t5 = delay until next positive clock edge.
January 1995
5
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
4. Delayed HIGH to LOW edge mode; see note 2. (LFC = HIGH; Y = LOW; Z = HIGH)
A
H
B
L
C
H
D
H
E
H
F
G
H
H
H
W
L
X
L
LFC
H
Y
L
Z
H
H
Fig.6 Timing diagram for delayed HIGH to LOW edge mode; for t1 to t5 see Fig.5.
5. Transient pulse suppression and pulse delaying mode; see note 2. (LFC = Y = Z = HIGH)
In this mode the circuit is working as a digital low-pass filter. An undisturbed pulse will only be delayed (see Fig.7).
A
L
B
L
C
H
D
H
E
H
F
G
H
H
H
W
L
X
L
LFC
H
Y
H
Z
H
H
Fig.7 Timing diagram for transient pulse suppression and pulse delaying mode; for t1, t2 and t3 see Fig.5.
January 1995
6
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
6. Frequency recognition mode (LFC = LOW; Y = HIGH; Z = HIGH)
The incoming signal must be symmetrical within the limits as given by the specified delay time in note 2., to achieve lower
or higher frequency detection (see Fig.8).
A
L
B
H
C
L
D
H
E
H
F
G
H
H
H
W
L
X
L
LFC
L
Y
H
Z
H
H
Minimum dividing number is 3.
Fig.8 Timing diagram for frequency recognition mode; tx = time shorter than t3 (OUT = H); ty = time greater than
t3 (OUT = L); for t1, t2 and t3 see Fig.5.
January 1995
7
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
7. Digital pulse duration selector mode (Y = Z = LOW)
This mode is a combination of two circuits, both used for frequency recognition. Both circuits are driven by the same clock
and same input signal, but programmed for different frequencies. The LFC input of the low-frequency circuit is set to logic
LOW, the output is connected to the LFC input of the high-frequency circuit, whose output (OUT) is the ‘filter’ output. The
delay time depends on the same facts as given in note 2.. For timing diagram see Fig.9.
A
L
B
L
C
L
D
H
E
H
F
G
H
H
H
W
L
X
L
LFC
L
Y
H
Z
H
H
IC1
IC2
OUT
(IC1)
L
L
H
H
H
H
H
H
L
L
L
L
Minimum dividing number is 3.
Fig.9 Timing diagram for digital pulse duration selector mode; tIN1, tIN2 and tIN3 are the IN input pulse durations;
t1 = predefined delay by programming IC1; t2 = predefined delay by programming IC2.
Notes to operating modes
1. The number of clocks for one cycle in the counter and divider mode is:
a. Contents of programmable counter plus one if X = W = LOW.
b. Contents of programmable counter multiplied by 16, 256 or 4096 if X and/or W = HIGH.
2. The delay in the modes 3, 4, 6 and 7, and the delay which is identical to the maximum duration of the transient pulse
in mode 5 depend on the optional divided clock frequency, the input conditions of the 8-bit presetable counter and in
addition, different times of propagation delays, jitter and maximum one half of a clock frequency period.
January 1995
8
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
DC CHARACTERISTICS
VSS = 0 V
Tamb (°C)
+ 25
VDD VOH VOL
SYMBOL
−40
+ 85
V
V
V
MIN. MAX. MIN. MAX. MIN. MAX.
Output (sink)
current LOW
(pin 10)
4,75
10
15
5
0,4
2,7
9,5
−
−
−
−
−
−
2,3
8,0
−
−
−
−
−
−
1,8
6,3
−
−
−
−
−
−
mA
mA
mA
mA
mA
mA
0,5 IOL
1,5
24,0
0,6
20,0
0,5
16,0
0,4
Output (source)
current HIGH
(pin 10)
4,6
9,5
10
1,8
1,5
1,2
−IOH
15 13,5
6,0
5,0
4,0
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
420
MAX.
Propagation delays
5
10
15
5
850
360
250
900
400
280
60
ns
CP → OUT
tPHL
180
120
450
200
140
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HIGH to LOW
LOW to HIGH
10
15
5
tPLH
tTHL
tTLH
Output transition
times
10
15
5
15
30
HIGH to LOW
10
20
60
120
60
LOW to HIGH
10
15
5
30
20
40
Input rise and
fall times
10
15
5
tr, tf
no limit
pins 13, 14, 17
Maximum clock
pulse frequency
pins 17; δ = 50%
3
6
14
17
MHz
MHz
MHz
10
15
fmax
7
8
January 1995
9
Philips Semiconductors
Product specification
HEF4753B
LSI
Universal timer module
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
1 800 fi + ∑ (foCL) × VDD
where
2
8 000 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
2
19 000 fi + ∑ (foCL) × VDD
fo = output freq. (MHz)
CL = load capacitance (pF)
∑ (foCL) = sum of outputs
VDD = supply voltage (V)
January 1995
10
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NXP
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