I74F657DB [NXP]
Octal transceiver with 8-bit parit generator/checker; 八路收发器， 8位巴力发生器/检验
| 型号： | I74F657DB |
| 厂家： | 
NXP |
| 描述： | Octal transceiver with 8-bit parit generator/checker |
| 文件： | 总12页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F657
Octal transceiver with 8-bit parit
generator/checker
Process specification
IC15 Data Handbook
1990 Jul 30
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
The parity select (ODD/EVEN) input gives the user the option of
odd or even parity systems.
FEATURES
• Combines 74F245 and 74F280A functions in one package
• High impedance base input for reduced loading (70µA in
high and low states)
The parity (PARITY) pin is an output from the generator/checker
when transmitting from the port A to B (T/R = high) and an input
when receiving from port B to A port ( T/R = low).
• Ideal in applications where high output drive and light bus
loading are required (IIL is 70µA vs FAST std of 600µA)
When transmitting (T/R = high) the parity select (ODD/EVEN) input
is set, then the A port data is polled to determined the number of
high bits. The parity (PARITY) output then goes to the logic state
• 3–state buffer outputs sink 64mA and source 15mA
• Input diodes for termination effects
• 24–pin plastic slim DIP (300mil) package
determined by the parity select (ODD/EVEN) setting and by the
number of high bits on port A.
For example, if the parity select (ODD/EVEN) is set low (even
parity), and the number of high bits on port A is odd, then the parity
(PARITY) output will be high, transmitting even parity. If the number
of high bits on port A is even, then the parity (PARITY) output will
be low, keeping even parity.
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F657 is an octal transceiver featuring non–inverting
buffers with 3–state outputs and an 8–bit parity
generator/checker, and is intended for bus–oriented
applications. The buffers have a guaranteed current sinking
capability of 24mA at the A ports and 64mA at the B ports.
The transmit/receive (T/R) input determines the direction of
the data flow through the bidirectional transceivers.
Transmit (active high) enables data from A ports to B ports;
receive (active low) enables data from B ports to A ports.
The output enable (OE) input disables both the A and B ports by
placing them in a high impedance condition when the OE input is
high.
When in receive mode (T/R = low) the B port is polled to determine
the number of high bits. If parity select (ODD/EVEN) is low (even
parity) and the number of highs on port B is:
(1) odd and the parity (PARITY) input is high, then ERROR will be
high, significantly no error.
(2) even and the parity (PARITY) input is high, then ERROR will be
asserted low, indicating an error.
TYPE
TYPICAL PROPAGA-
TION DELAY
TYPICAL SUPPLY
CURRENT( TOTAL)
74F657
8.0ns
100mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
= 5V ±10%,
INDUSTRIAL RANGE
= 5V ±10%,
DESCRIPTION
PKG DWG #
V
V
CC
CC
T
amb
= 0°C to +70°C
T
amb
= –40°C to +85°C
24–pin plastic slim
DIP (300mil)
N74F657N
I74F657N
SOT222-1
24–pin plastic SOL
24–pin plastic SSOP
N74F657D
I74F657D
SOT137-1
SOT340-1
N74F657DB
I74F657DB
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
PINS
DESCRIPTION
A ports 3–state inputs
70µA/70µA
70µA/70µA
70µA/70µA
40µA/40µA
20µA/20µA
40µA/40µA
A0 – A7
B0 – B7
PARITY
T/R
3.5/0.117
B ports 3–state inputs
Parity input
3.5/0.117
3.5/0.117
2.0/0.066
1.0/0.033
Transmit/receive input
Parity select input
ODD/EVEN
OE
Output enable input (active low)
A ports 3–state outputs
B ports 3–state outputs
Parity output
2.0/0.066
150/40
A0 – A7
B0 – B7
PARITY
ERROR
3.0mA/24mA
15mA/64mA
15mA/64mA
15mA/64mA
750/106.7
750/106.7
750/106.7
Error output
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
2
90 July 30
853 1117 00081
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
PIN CONFIGURATION
LOGIC SYMBOL
T/R
A0
A1
A2
A3
A4
1
2
3
4
5
24 OE
23
22
21
20
B0
B1
B2
B3
2
3
4
5
6
8
9
10
A0 A1 A2 A3 A4 A5 A6 A7
T/R
1
24
11
13
12
PARITY
OE
6
7
8
9
19 GND
18 GND
ERROR
V
ODD/EVEN
CC
B0 B1 B2 B3 B4 B5 B6 B7
A5
A6
17
16
15
14
B4
B5
B6
B7
23 22 21 20 17 16 15 14
A7 10
ODD/EVEN 11
ERROR 12
13 PARITY
SF00414
V
= Pin 7
CC
GND = Pin 18, 19
SF00415
IEC/IEEE SYMBOL
24
1
G3
3 EN1/3G5 (REC)
3 EN2 (XMIT)
N4
11
2
23
1
Z11
2
22
21
3
4
20
5
17
16
6
8
15
14
9
10
11
2 k
13
4, 2
4, 1
.
.
.
5
12
18
SF00416
3
90 July 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
LOGIC DIAGRAM
1
T/R
24
OE
23
22
21
20
17
16
15
14
2
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
3
4
5
6
8
9
10
13
11
PARITY
ODD/EVEN
12
ERROR
V
= Pin 7,
CC
SF00417
GND = Pin 18, 19
4
90 July 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
FUNCTION TABLE
NUMBER OF INPUTS THAT ARE HIGH
INPUTS
INPUT/OUTPUT
PARITY
OUTPUTS
OE
T/R
ODD/EVEN
ERROR
OUTPUTS MODE
L
L
L
L
L
L
H
H
L
L
L
L
H
L
H
H
L
H
L
H
L
H
L
Z
Z
H
L
L
H
Transmit
Transmit
Receive
Receive
Receive
Receive
0, 2, 4, 6, 8
L
L
L
L
L
L
L
H
H
L
L
L
L
H
L
H
H
L
L
H
H
L
H
L
Z
Z
L
H
H
L
Transmit
Transmit
Receive
Receive
Receive
Receive
1, 3, 5, 7
L
Don’t care
H
X
X
Z
Z
Z
Notes to function table
1. H = High voltage level
2. L
3. X
4. Z
=
=
=
Low voltage level
Don’t care
High impedance ”’off” state
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
CC
V
IN
Supply voltage
Input voltage
Input current
V
I
IN
mA
V
I
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
V
OUT
CC
A0 – A7
48
mA
mA
°C
°C
°C
OUT
B0 – B7, PARITY, ERROR
Commercial range
Industrial range
128
T
amb
Operating free air temperature range
Storage temperature range
0 to +70
–40 to +85
–65 to +150
T
stg
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
MIN
NOM
MAX
V
Supply voltage
4.5
2.0
5.0
5.5
V
CC
IH
IL
V
V
High–level input voltage
Low–level input voltage
Input clamp current
V
0.8
–18
–3
V
I
I
mA
mA
mA
mA
mA
Ik
High–level output current
A0 – A7
B0 – B7, PARITY, ERROR
A0 – A7
OH
OL
–15
24
I
Low–level output current
B0 – B7, PARITY, ERROR
Commercial range
64
T
amb
Operating free air temperature range
0
+70
°C
°C
Industrial range
–40
+85
5
90 July 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN TYP
MAX
4,5
All outputs
I
= –3mA
±10%V
2.4
2.7
2.0
2.0
2.0
2.0
V
V
V
V
V
V
V
V
V
V
V
V
OH
CC
V
V
V
= MIN,
±5%V
CC
CC
5
V
OH
High-level output voltage
B0 – B7,
PARITY,
ERROR
= MAX,
= MIN
I
I
I
= –12mA
= –15mA
±10%V
IL
OH
OH
OL
CC
CC
±5%V
IH
4
±10%V
CC
CC
±5%V
4,5
A0 – A7
= 24mA
±10%V
0.35
0.35
0.38
0.42
0.42
0.50
0.50
0.55
0.55
0.55
CC
CC
V
V
V
= MIN,
±5%V
CC
4
V
V
Low-level output voltage
Input clamp voltage
B0 – B7,
PARITY,
ERROR
= MAX,
= MIN
I
OL
I
OL
I
OL
= 48mA
= 48mA
= 64mA
±10%V
OL
IL
CC
CC
CC
5
4
±5%V
±5%V
IH
V
CC
V
CC
V
CC
= MIN, I = I
IK
–0.73 -1.2
100
IK
I
OE, T/R,
ODD/EVEN
= 0.0V, V = 7.0V
µA
I
Input current at
I
I
maximum input voltage
A0 – A7
B0 – B7
= 5.5V, V = 5.5V
2
1
mA
mA
I
4
OOD/EVEN
20
µA
µA
µA
µA
µA
µA
5
I
High–level input current
Low–level input current
V
CC
V
CC
= MAX, V = 2.7V
40
IH
IL
I
4
OE, T/R
40
5
80
I
OOD/EVEN
OE, T/R
= MAX, V = 0.5V
–20
–40
I
Off–state output current,
high–level voltage applied
A0 – A7,
B0 – B7,
µA
µA
µA
µA
I
I
I
+ I
V
V
V
= MAX, V = 2.7V
70
–70
50
OZH
OZL
OZH
IH
CC
CC
CC
O
Off–state output current,
low–level voltage applied
+ I
PARITY
ERROR
= MAX, V = 0.5V
O
IL
Off–state output current,
High–level voltage applied
= MAX, V = 2.7V
O
Off–state output current,
low–level voltage applied
I
I
V
V
= MAX, V = 0.5V
–50
OZL
CC
O
3
Short circuit output current
A0 – A7
B0 – B7
= MAX
-60
-150
mA
mA
mA
mA
mA
mA
mA
OS
CC
-100
-225
4
I
90
90
125
135
150
160
CCH
5
4
5
I
Supply current (total)
I
V
CC
= MAX
106
106
98
CC
CCL
I
145
CCZ
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V = 5V, T
= 25°C.
amb
CC
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. For commercial range.
5. For industrial range.
6
90 July 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
AC ELECTRICAL CHARACTERISTICS
LIMITS
T
= +25°C
T
= –40°C to +85°C
T
= 0°C to +70°C
= +5.0V ± 10%
amb
amb
amb
V
V
= +5.0V ± 10%
SYMBOL
PARAMETER
TEST
V
= +5.0V
UNIT
CC
CC
CC
CONDITION
C = 50pF,
R = 500Ω
L
C = 50pF,
R = 500Ω
L
C = 50pF,
L
R = 500Ω
L
L
L
MIN
TYP MAX
MIN
MAX
MIN
MAX
t
t
Propagation delay
An to Bn or Bn to An
2.5
3.0
5.5
6.0
7.5
7.5
2.5
3.0
8.0
8.0
2.0
2.5
9.0
9.0
PLH
PHL
Waveform 2
ns
ns
t
t
Propagation delay
An to PARITY
7.0
7.0
10.0
10.0
14.0
15.0
7.0
7.0
16.0
16.0
5.5
6.5
16.5
19.0
PLH
PHL
Waveform 1, 2
t
t
Propagation delay
ODD/EVEN to PARITY,
ERROR
4.5
4.5
7.5
8.0
11.0
11.5
4.5
4.5
12.0
12.5
3.5
4.0
13.0
15.5
PLH
PHL
Waveform 1, 2
ns
t
t
Propagation delay
Bn to ERROR
8.0
8.0
14.0
14.0
20.5
20.5
7.5
7.5
22.5
22.5
7.5
7.5
24.5
25.0
PLH
PHL
Waveform 1, 2
Waveform 1, 2
Waveform 3, 4
Waveform 3, 4
ns
ns
ns
ns
t
t
Propagation delay
PARITY to ERROR
8.0
8.0
11.5
12.0
15.5
15.5
7.5
8.0
16.5
17.0
6.5
6.5
18.5
20.0
PLH
PHL
1
t
t
Output enable time
to high or low level
3.0
4.0
5.5
7.0
8.0
9.5
3.0
4.0
9.0
11.0
2.0
4.0
9.0
13.0
PZH
PZL
t
t
Output disable time
from high or low level
2.0
2.0
4.5
4.0
7.5
6.0
2.0
2.0
8.0
6.5
1.0
1.0
8.0
7.5
PHZ
PLZ
Note to AC electrical characteristics
1. These delay times reflect the 3-state recovery time only and not the signal through the buffers or the parity check circuitry. To assure VALID
information at the ERROR pin, time must be allowed for the signal to propagate through the drivers (B to A), through the parity check circuitry
(same as A to PARITY), and to the ERROR output. VALID data at the ERROR pin > (B to A) + (A to PARITY).
AC WAVEFORMS
OE
An, Bn,
V
V
M
ODD/EVEN,
PARITY
M
V
V
M
M
V
-0.3V
0V
OH
t
t
PHZ
PZH
t
t
PLH
PHL
An, Bn,
PARITY,
ERROR
PARITY,
ERROR
V
M
V
V
M
M
SF00418
SF00419
Waveform 1. Propagation delay for inverting outputs
Waveform 3. 3-state output enable time to high level and output
disable time from high level
An, Bn,
ODD/EVEN,
PARITY
V
V
M
M
OE
V
V
M
M
t
t
PHL
PLH
A , B
PARITY,
ERROR
n
n,
t
t
PLZ
PZL
V
V
M
M
3.5V
An, Bn,
PARITY,
ERROR
V
M
SF00420
V
+0.3V
OL
Waveform 2. Propagation delay for non-Inverting outputs
SF00421
Waveform 4. 3-state output enable time to low level and output
disable time from low level
Note to AC waveforms
1. For all waveforms, V = 1.5V.
M
7
90 July 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
TEST CIRCUIT AND WAVEFORMS
V
CC
t
w
AMP (V)
90%
7.0V
90%
NEGATIVE
PULSE
V
V
M
R
M
L
V
V
OUT
IN
10%
10%
PULSE
GENERATOR
D.U.T.
0V
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
T
L
t
t )
t
t )
TLH ( r
THL ( f
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for Open Collector Outputs
10%
10%
0V
t
w
SWITCH POSITION
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
DEFINITIONS:
R
L
C
L
R
T
=
=
=
Load resistor;
INPUT PULSE REQUIREMENTS
see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance;
see AC electrical characteristics for value.
Termination resistance should be equal to Z
pulse generators.
family
V
M
rep. rate
t
w
t
t
amplitude
TLH
THL
of
OUT
2.5ns
2.5ns
74F
3.0V
1.5V
1MHz
500ns
SF00128
8
90 July 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
DIP24: plastic dual in-line package; 24 leads (300 mil)
SOT222-1
9
1990 Jul 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
10
1990 Jul 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
11
1990 Jul 30
Philips Semiconductors
Product specification
Octal transceiver with 8-bit parity generator/checker
74F657
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05171
Document order number:
Philips
Semiconductors
相关型号：
I74F74D-T
IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.9 MM, PLASTIC, SO-14, FF/Latch
NXP
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