I74F74D,623 [NXP]
74F74 - Dual D-type flip-flop SOIC 14-Pin;
| 型号： | I74F74D,623 |
| 厂家： | 
NXP |
| 描述： | 74F74 - Dual D-type flip-flop SOIC 14-Pin 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总8页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F74
Dual D-type flip-flop
Product specification
1996 Mar 12
Supercedes data of 1990 Oct 23
IC15 Data Handbook
Philips
Semiconductors
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
FEATURE
PIN CONFIGURATION
• Industrial temperature range available (–40°C to +85°C)
RD0
D0
1
2
3
4
5
14
V
CC
DESCRIPTION
13 RD1
12 D1
The 74F74 is a dual positive edge-triggered D-type flip-flop featuring
individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input. When
set and reset are inactive (high), data at the D input is transferred to
the Q and Q outputs on the low-to-high transition of the clock. Data
must be stable just one setup time prior to the low-to-high transition of
the clock for predictable operation. Clock triggering occurs at a
voltage level and is not directly related to the transition time of the
positive-going pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels of the output.
CP0
SD0
Q0
11 CP1
10 SD1
Q0
6
7
9
8
Q1
Q1
GND
SF00045
TYPE
TYPICAL f
TYPICAL SUPPLY CURRENT (TOTAL)
max
74F74
125MHz
11.5mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE
INDUSTRIAL RANGE
= 5V ±10%,
DESCRIPTION
PKG. DWG. #
V
CC
= 5V ±10%,
V
CC
T
amb
= 0°C to +70°C
T
amb
= –40°C to +85°C
14-pin plastic DIP
14-pin plastic SO
N74F74N
I74F74N
SOT27-1
N74F74D
I74F74D
SOT108-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
D0, D1
DESCRIPTION
74F (U.L.) HIGH/LOW
1.0/1.0
LOAD VALUE HIGH/LOW
20µA/0.6mA
Data inputs
CP0, CP1
SD0, SD1
RD0, RD1
Q0, Q1, Q0, Q1
Clock inputs (active rising edge)
Set inputs (active low)
Reset inputs (active low)
Data outputs
1.0/1.0
20µA/0.6mA
1.0/3.0
20µA/1.8mA
1.0/3.0
20µA/1.8mA
50/33
1.0mA/20mA
NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
2
12
4
3
2
1
&
S
5
6
D0 D1
C1
C2
3
4
CP0
SD0
RD0
CP1
SD1
RD1
1D
R
1
11
10
13
10
11
12
13
S
9
8
Q0 Q0 Q1 Q1
2D
R
5
6
9
8
V
= Pin 14
CC
GND = Pin 7
SF00047
SF00046
2
1996 Mar 12
853 0335 16554
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
OUTPUTS
OPERATING
MODE
SD
L
RD
H
L
CP
X
X
X
↑
D
X
X
X
h
l
Q
H
Q
L
4, 10
SD
Asynchronous set
Asynchronous reset
Undetermined*
Load ”1”
H
L
L
H
5, 9
6, 8
1, 13
RD
Q
Q
L
H
H
H
H
H
H
H
H
L
3, 11
CP
↑
L
H
Load ”0”
H
↑
X
NC
NC
Hold
NOTES:
2, 12
D
H
h
=
=
High voltage level
High voltage level one setup time prior to low-to-high clock
V
= Pin 14
GND = Pin 7
CC
transition
L
l
=
=
Low voltage level
Low voltage level one setup time prior to low-to-high clock
SF00048
transition
NC= No change from the previous setup
X
↑
↑
*
=
=
=
=
Don’t care
Low-to-high clock transition
Not low-to-high clock transition
This setup is unstable and will change when either set or reset
return to the high level.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
UNIT
V
V
Supply voltage
Input voltage
Input current
CC
IN
V
V
I
mA
V
IN
V
OUT
OUT
Voltage applied to output in high output state
Current applied to output in low output state
–0.5 to V
40
CC
I
mA
°C
°C
°C
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
T
amb
Operating free air temperature range
Storage temperature range
T
stg
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
NOM
MAX
V
Supply voltage
5.0
5.5
V
V
CC
IH
IL
V
V
High-level input voltage
Low-level input voltage
Input clamp current
2.0
0.8
–18
–1
V
I
I
I
mA
mA
mA
°C
°C
Ik
High-level output current
Low-level output current
OH
OL
20
Commercial range
Industrial range
0
+70
+85
T
amb
Operating free air temperature range
–40
3
1996 Mar 12
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
LIMITS
1
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
2
MIN
2.5
TYP
MAX
±10%V
V
V
V
V
V
CC
V
OH
High-level output voltage
V
V
= MIN, V = MAX, V = MIN
I
= MAX
CC
IL
IH
OH
±5%V
2.7
3.4
CC
±10%V
0.30
0.30
-0.73
0.50
0.50
-1.2
CC
CC
V
V
Low-level output voltage
Input clamp voltage
= MIN, V = MAX, V = MIN
I
= MAX
OL
CC
IL
IH
OL
±5%V
V
V
= MIN, I = I
I IK
IK
CC
Input current at maximum input
voltage
I
I
= MAX, V = 7.0V
100
µA
I
CC
I
High-level input current
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V = 2.7V
20
-0.6
-1.8
-150
16
µA
mA
mA
mA
mA
IH
IL
I
Dn, CPn
= MAX, V = 0.5V
I
Low-level input
I
current
SDn, RDn
= MAX, V = 0.5V
I
3
I
I
Short-circuit output current
= MAX
= MAX
-60
OS
4
Supply current (total)
11.5
CC
NOTES:
1
2
3
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
All typical values are at V = 5V, T = 25°C.
CC
amb
Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4
Measure I with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.
CC
AC ELECTRICAL CHARACTERISTICS
LIMITS
V
= +5.0V
= +25°C
V
= +5.0V ± 10%
= 0°C to +70°C
V
amb
L
= +5.0V ± 10%
= –40°C to +85°C
CC
CC
CC
TEST
CONDITION
T
amb
T
amb
T
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω C = 50pF, R = 500Ω C = 50pF, R = 500Ω
L
L
L
L
L
MIN
TYP
MAX
MIN
MAX
MIN
MAX
f
Maximum clock frequency
Waveform 1
Waveform 1
100
125
100
90
MHz
ns
max
t
t
Propagation delay
CPn to Qn or Qn
3.8
4.4
5.3
6.2
6.8
8.0
3.8
4.4
7.8
9.2
3.8
4.4
8.5
9.2
PLH
PHL
t
t
Propagation delay
SDn, RDn to Qn or Qn
3.2
3.5
4.6
7.0
6.1
9.0
3.2
3.5
7.1
10.5
3.2
2.5
7.5
10.5
PLH
PHL
Waveform 2
ns
AC SETUP REQUIREMENTS
LIMITS
V
= +5.0V
= +25°C
V
= +5.0V ± 10%
= 0°C to +70°C
V
amb
L
= +5.0V ± 10%
= –40°C to +85°C
CC
CC
CC
TEST
CONDITION
T
amb
T
amb
T
SYMBOL
PARAMETER
UNIT
C = 50pF, R = 500Ω C = 50pF, R = 500Ω C = 50pF, R = 500Ω
L
L
L
L
L
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
t
(H)
(L)
Setup time, high or low
Dn to CPn
2.0
3.0
2.0
3.0
2.0
3.0
su
su
Waveform 1
Waveform 1
Waveform 1
Waveform 2
Waveform 3
ns
ns
ns
ns
ns
t (H)
Hold time, high or low
Dn to CPn
1.0
1.0
1.0
1.0
1.0
1.0
h
t (L)
h
t
w
t
w
(H)
(L)
CPn pulse width,
high or low
4.0
5.0
4.0
5.0
4.0
5.0
SDn, RDn pulse width,
low
t
w
(L)
4.0
2.0
4.0
2.0
4.0
2.0
Recovery time
SDn, RDn to CPn
t
rec
4
1996 Mar 12
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
AC WAVEFORMS
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to
change for predictable output performance.
t
(L)
Dn
w
V
t
V
V
V
M
M
M
M
SDn
RDn
V
V
M
M
t
(H)
t (H)
h
(L)
t (L)
h
su
su
1/f
M
max
t
(L)
w
V
V
M
t
(L)
M
CPn
Qn
w
V
V
M
V
M
t
(H)
w
t
t
PHL
PLH
t
PHL
t
PLH
Qn
Qn
V
V
V
M
M
M
V
V
M
M
M
t
t
PLH
PHL
t
t
PHL
PLH
V
M
V
M
V
Qn
SF00050
SF01276
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Waveform 1. Propagation delay for data to output, data setup
time and hold times, and clock width, and maximum clock
frequency
SDn or RDn
CPn
V
M
t
rec
V
M
SF00051
Waveform 3. Recovery time for set or reset to clock
TEST CIRCUIT AND WAVEFORMS
t
w
AMP (V)
0V
V
CC
90%
90%
NEGATIVE
PULSE
V
V
M
M
10%
10%
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t )
t
t )
THL ( f
TLH ( r
R
C
R
L
t
t )
T
L
t
t )
TLH ( r
THL ( f
AMP (V)
0V
90%
M
90%
POSITIVE
PULSE
V
V
M
10%
10%
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
t
w
Input Pulse Definition
INPUT PULSE REQUIREMENTS
R
L
C
L
R
T
=
=
=
Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
family
74F
V
rep. rate
t
w
t
t
THL
amplitude
M
TLH
Termination resistance should be equal to Z
pulse generators.
of
OUT
2.5ns 2.5ns
3.0V
1.5V
1MHz
500ns
SF00006
5
1996 Mar 12
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
6
1996 Mar 12
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
7
1996 Mar 12
Philips Semiconductors
Product specification
Dual D-type flip-flop
74F74
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
9397-750-05066
Document order number:
Philips
Semiconductors
相关型号：
I74F74D-T
IC F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.9 MM, PLASTIC, SO-14, FF/Latch
NXP
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