I74F777N [NXP]
Triple bidirectional latched bus transceiver 3-State open collector; 三重双向锁存总线收发器三态开路集电极
| 型号： | I74F777N |
| 厂家： | 
NXP |
| 描述： | Triple bidirectional latched bus transceiver 3-State open collector |
| 文件： | 总12页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
74F777
Triple bidirectional latched bus
transceiver (3-State + open collector)
Product specification
IC15 Data Handbook
1992 May 19
Philips
Semiconductors
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
74F777
range of 20 to 50 ohms and is terminated on each end with a 30 to
40 ohm resistor.
FEATURES
• Latching transceiver
The 74F777 is a triple bidirectional transceiver with Open Collector
B and 3–State A port output drivers. A latch function is provided for
the A port signals. The B port output driver is designed to sink
100mA from 2 volts to minimize crosstalk and ringing on the bus.
• High drive Open Collector output current with minimum output
swing
• Compatible with Test Mode (TM) bus specification
• Controlled output ramp
A separate output threshold clamp voltage (V ) is provided to
X
prevent the A port output High level from exceeding future high
• Multiple package options
density processor supply voltage levels. For 5 volt systems, V is
X
simply tied to V
CC.
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPLY CUR-
RENT( TOTAL)
The 74F777 is a triple bidirectional latched bus transceiver and is
intended to provide the electrical interface to a high performance
wired–OR bus. This bus has a loaded characteristics impedance
74F777
7.0ns
45mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
= 5V ±10%, T = 0°C to +70°C
INDUSTRIAL RANGE
PKG DWG #
V
CC
= 5V ±10%,
V
CC
amb
T
amb
= –40°C to +85°C
20–pin plastic DIP (300 mil)
20–pin PLCC
N74F777N
N74F777A
I74F777N
I74F777A
SOT146-1
SOT380-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
A0 – A2
B0 – B2
PNP latched inputs
3.5/0.117
5.0/0.167
70µA/70µA
100µA/100µA
Data inputs with threshold circuitry
A output enable inputs (active–High)
B output enable inputs (active–Low)
20µA/20µA
20µA/20µA
20µA/20µA
OEA0 – OEA2
OEB0 – OEB2
1.0/0.033
1.0/0.033
LE0 – LE2
A0 – A2
Latch enable inputs (active–Low)
3–State outputs
1.0/0.033
150/40
3mA/24mA
OC/100mA
B0 – B2
Open Collector outputs
OC/166.7
Note to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.
OC = Open Collector.
2
May 19, 1992
853–1645 06772
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
74F777
PIN CONFIGURATION
LOGIC DIAGRAM
LE0
LE1
1
2
3
4
5
6
7
8
9
20
19
V
V
CC
X
13
OEB0
1
17
B0
LE2
OEA0
A0
18 GND
LE0
LE
Q
Q
Q
5
Data
A0
B0
B1
17
16
15
14
4
OEA1
A1
B2
OEA0
12
GND
OEB1
OEA2
A2
13 OEB0
OEB1
2
16
B1
LE1
LE
12
7
Data
A1
GND 10
11 OEB2
SF00432
6
OEA1
11
OEB2
3
15
B2
LE2
PIN CONFIGURATION PLCC
LE
9
Data
A2
3
2
1
20 19
8
OEA2
4
5
6
18
17
16
15
14
OEA0
A0
GND
B0
V
= Pin 20, V = Pin 19,
X
CC
GND = Pin 10, 14, 18
SF00436
PLCC
B1
OEA1
A1
7
8
B2
IEC/IEEE SYMBOL
GND
OEA2
13
9
10 11 12 13
EN
17
1
5
C1
ID
SF00433
4
EN
12
2
16
15
LOGIC SYMBOL
7
6
5
7
9
11
3
LE0
LE1
A0 A1 A2
1
2
9
3
4
LE2
8
OEA0
OEA1
OEA2
OEB0
OEB1
OEB2
6
8
SF00435
13
12
11
19
V
X
B0 B1 B2
17 16 15
V
= Pin 20, V = Pin 19,
X
CC
GND = Pin 10, 14, 18
SF00434
3
May 19, 1992
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
74F777
FUNCTION TABLE
INPUTS
LATCH
STATE
H
OUTPUTS
An Bn
OPERATING MODE
An
H
L
Bn*
X
X
X
–
LEn
L
OEAn
OEBn
L
L
L
L
Z
Z
H**
L
A 3-State, data from A to B
L
L
X
–
H
L
L
L
Qn
(1)
Z
Qn
(1)
Z(2)
Z(2)
Qn
Z
A 3-State, latched data to B
Feedback: A to B, B to A
Preconditioned latch enabling
data transfer from B to A
Latch state to A and B
H
H
H
H
L
L
(1)
H
L
–
H
L
H
H
H
L
L
H (2)
H (2)
Qn
H
–
L
–
–
L
Qn
Z
H
L
X
X
X
H
L
H
H
H
H
H
H
H
L
L
L
Z
Z
B and A 3–State
X
–
H
L
L
Qn
H
Z
Z
H
H
H
H
H
L
Z
–
L
L
Z
B 3-State, data from B to A
–
H
L
H
H
Qn
H
L
Z
–
Qn
Qn
Z
Notes to function table
H
L
X
–
=
=
=
=
=
High voltage level
Low voltage level
Don’t care
Input not externally driven
High impedance (off) state
Z
Q = High or Low voltage level one setup time prior to the Low–to–High LE transition.
n
(1) = Condition will cause a feedback loop path: A to B and B to A.
(2) = The latch must be preconditioned such that B inputs may assume a High or Low level while OEB0 and OEB1 are Low and LE is High.
B * =Precaution should be taken to insure the B inputs do not float. If they do they are equal to Low state.
n
H**= Goes to level of pull-up voltage.
Each latch is independent. The latches may be run in any combination of modes.
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free air temperature range.)
SYMBOL
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +5.5
–30 to +5
UNIT
V
V
V
V
Supply voltage
Threshold control
Input voltage
CC
V
X
OEBn, OEAn, LEn
A0 – A2, B0 – B2
V
IN
V
I
IN
Input current
mA
V
I
Voltage applied to output in High output state
Current applied to output in
Low output state
–0.5 to V
V
OUT
CC
A0 – A2
48
mA
mA
°C
°C
°C
OUT
B0 – B2
200
T
amb
Operating free air
Commercial range
Industrial range
0 to +70
–40 to +85
–65 to +150
temperature range
T
stg
Storage temperature range
4
May 19, 1992
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
74F777
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
LIMITS
NOM
5.0
UNIT
MAX
MIN
4.5
2.0
1.6
Supply voltage
V
CC
5.5
V
V
High–level input voltage
V
IH
Except B0 – B2
B0 – B2
V
Low–level input voltage
Input clamp current
V
Except B0 – B2
B0 – B2
0.8
1.43
–18
–40
–3
V
IL
V
I
Ik
Except A0 – A2
A0 – A2
mA
mA
mA
mA
mA
°C
°C
High–level output current
Low–level output current
I
I
Except A0 – A2
A0 – A2
OH
24
OL
B0 – B2
100
+70
+85
T
amb
Operating free–air temperature range
Commercial range
Industrial range
0
–40
5
May 19, 1992
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
74F777
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
LIMITS
UNIT
1
2
CONDITIONS
MIN TYP
MAX
100
I
I
High–level output current
B0 – B2
B0 – B2
V
V
V
= MAX, V = MAX, V = MIN, V = 2.1V
µA
µA
V
OH
CC
CC
CC
IL
IH
OH
Power–off output current
High-level output voltage
= 0.0V, V = MAX, V = MIN, V = 2.1V
100
OFF
IL
IH
OH
= MIN,
I
= –3mA, V =V
2.5
2.5
V
CC
OH
X
CC
4
4
V
A0 – A2
V
V
= MAX,
= MIN
I
= –4mA, V = 3.13V
X
OH
IL
IH
OH
V
X
V
and 3.47V
A0 – A2
B0 – B2
V
V
V
V
V
= MIN,
I
OL
I
OL
I
OL
= 20mA, V = V
0.50
1.15
V
V
V
V
V
CC
X
cc
V
V
Low-level output voltage
Input clamp voltage
= MAX,
= MIN
= 100mA
= 4mA
OL
IL
0.40
IH
A0 – A2
= MIN, I = I
-0.5
-1.2
IK
CC
CC
I
IK
IK
Except A0 – A2
= MIN, I = I
I
Input current at
maximum input voltage
OEBn, OEAn,
LEn
I
V
= MAX, V = 7.0V
I
CC
I
100
1
µA
A0 – A2,
B0 – B2
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX, V = 5.5V
mA
I
OEBn, OEAn,
LEn
= MAX, V = 2.7V, Bn – An = 0V
I
I
I
High–level input current
Low–level input current
20
µA
µA
IH
B0 – B2
= MAX, V = 2.1V
100
I
OEBn, OEAn
LEn
,
= MAX, V = 0.5V
I
–20
µA
µA
IL
B0 – B2
= MAX, V = 0.3V
–100
I
Off–state output current,
High level voltage applied
µA
µA
µA
µA
mA
I
I
+ I
A0 – A2
= MAX, V = 2.7V
70
–70
100
10
OZH
IH
O
Off–state output current,
Low level voltage applied
+ I
A0 – A2
V
V
= MAX, V = 0.5V
I
OZL
IL
CC
= MAX, V = V , LE = OEAn = OEBn = 2.7V,
CC
X
CC
–100
–10
-60
A0 – A2 = 2.7V, B0 – B2 = 2.0V,
I
X
High level control current
V
= MAX, V = 3.13 & 3.47V, LE = OEAn =
CC
X
2.7V, OEBn = A0 – A2 = 2.7V, B0 – B2 = 2.0V
Short circuit output
V
CC
= MAX, Bn = 1.8V, OEAn = 2.0V,
I
I
A0 – A2 only
-150
OS
3
current
OEBn = 2.7V
I
I
I
V
CC
V
CC
V
CC
= MAX
40
55
45
60
80
67
mA
mA
mA
CCH
CCL
CCZ
Supply current (total)
= MAX, V = 0.5V
IL
CC
= MAX, V = 0.5V
IL
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
Unless otherwise specified, V =V for all test condition.
X
CC
2. All typical values are at V = 5V, T
3. Not more than one output should be shorted at a time. For testing I , the use of high-speed test apparatus and/or sample-and-hold
= 25°C.
CC
amb
OS
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I tests should be performed last.
OS
4. Due to test equipment limitations, actual test conditions are for V =1.8v and V = 1.3V.
IH
IL
6
May 19, 1992
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
74F777
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
T
= –40°C to
amb
T
V
= 0°C to +70°C
= +5.0V ±10%
T
V
= +25°C
= +5.0V
amb
amb
CC
+85°C
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
CC
V
CC
= +5.0V ±10%
C = 30pF, R = 9Ω
L
L
C = 30pF, R = 9Ω
L
L
C = 30pF, R = 9Ω
L
L
MIN
TYP MAX
MIN
MAX
MIN
MAX
8.0
7.5
t
t
Propagation delay
Bn to An
8.5
7.5
10.5
9.5
13.0
12.0
14.5
12.5
8.0
7.5
14.5
12.5
PLH
PHL
Waveform 1
ns
ns
Output enable time to
High or Low
OEAn to An
t
t
8.0
9.0
10.0
11.0
13.0
14.0
7.0
8.0
14.5
15.5
7.0
8.0
14.5
15.5
PZH
PZL
Waveform 3, 4
Output Disable time from
High or Low
OEAn to An
t
t
1.5
1.5
3.0
3.0
6.0
6.0
1.0
1.0
6.5
6.0
1.0
1.0
6.5
6.0
PHZ
PLZ
Waveform 3, 4
ns
B PORT LIMITS
T
= –40°C to
+85°C
= +5.0V ±10%
amb
T
V
C
= 0°C to +70°C
= +5.0V ± 10%
= 30pF, R = 9Ω
U
T
V
= +25°C
= +5.0V
amb
amb
CC
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
CC
V
CC
C = 30pF, R = 9Ω
D
U
D
C = 30pF, R = 9Ω
D
U
MIN
TYP MAX
MIN
MAX
MIN
MAX
t
t
Propagation delay
An to Bn
3.0
5.0
4.5
6.5
7.0
9.0
2.5
4.5
8.0
10.0
2.5
4.5
8.0
10.0
PLH
PHL
Waveform 1
Waveform 1
Waveform 1
ns
ns
ns
ns
t
t
Propagation delay
LEn to Bn
3.5
5.5
5.5
7.5
8.0
10.5
3.0
5.0
9.0
11.5
3.0
5.0
9.0
11.5
PLH
PHL
t
t
Enable/disable time
OEBn to An
3.0
6.0
5.0
8.0
7.5
10.5
3.0
5.5
8.0
12.0
3.0
5.5
8.0
12.0
PLH
PHL
t
t
Transition time, B port
1.3V to 1.7V, 1.7V to 1.3V
Test Circuits and
Waveforms
0.5
0.5
4.0
2.0
4.5
4.5
0.5
0.5
7.0
4.5
0.5
0.5
7.0
4.5
TLH
THL
AC SETUP REQUIREMENTS
LIMITS
T
= –40°C to
+85°C
= +5.0V ±10%
amb
T
V
C
= 0°C to +70°C
= +5.0V ± 10%
T
V
= +25°C
= +5.0V
amb
amb
CC
TEST
CONDITION
SYMBOL
PARAMETER
UNIT
CC
V
CC
C = 30pF, R = 9Ω
D
U
= 30pF, R = 9Ω
D
U
C = 30pF, R = 9Ω
D
U
MIN
TYP MAX
MIN
MAX
MIN
MAX
t
su
t
su
(H)
(L)
Setup time
An to LEn
4.0
4.5
4.5
4.5
4.5
4.5
Waveform 2
ns
t (H)
t (L)
h
Hold time
An to LEn
0.0
0.0
0.0
0.0
0.0
0.0
h
Waveform 2
Waveform 2
ns
ns
t
w
(L)
LEn pulse width, Low
5.5
6.5
6.5
AC WAVEFORMS
An, Bn, OEBn
An
V
V
V
V
V
V
M
M
M
M
M
M
t (L)
h
t (H)
su
t (H)
h
t
t
PLH
PHL
t (L)
su
t
w
(L)
An, Bn
V
V
V
M
V
M
LEn
V
M
M
M
SF00438
SF00437
Waveform 2. Data set-up and hold times and LE pulse width
Waveform 1. Propagation delay, data to output and
enable/disable time OEBn to Bn
7
May 19, 1992
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver (3–State +
Open Collector)
74F777
OEAn
OEAn
An
V
V
M
V
V
M
M
M
V
-0.3V
0V
OH
t
t
PHZ
PZH
t
t
PLZ
PZL
An
V
V
M
M
V
+0.3V
OL
SF00439
SF00440
Waveform 3. 3-State output enable time to High level and
output disable time from High level
Waveform 4. 3-State output enable time to Low level and output
disable time from Low level
Notes to AC waveforms
For all waveforms, V = 1.5V.
M
The shaded areas indicate when the input is permitted to change for predictable output performance.
TEST CIRCUITS AND WAVEFORMS
SWITCH POSITION
t
AMP (V)
low V
w
90%
90%
TEST
SWITCH
closed
open
NEGATIVE
PULSE
V
CC
V
V
M
M
t
, t
PLZ PZL
10%
10%
7.0V
All other
R
t
t
)
)
t
t )
L
THL ( f
TLH ( r
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
t
t )
TLH ( r
THL ( f
AMP (V)
low V
R
C
R
L
90%
M
90%
T
L
POSITIVE
PULSE
V
V
M
10%
10%
t
w
Test circuit for 3–State outputs on A port
V
7.0V
CC
Input pulse definition
INPUT PULSE REQUIREMENTS
R
family
U
V
V
OUT
IN
V
M
Low V
rep. rate
t
w
t
t
amplitude
TLH
THL
PULSE
D.U.T.
GENERATOR
A port
B port
3.0V
1.5V
1.0V
1MHz
500ns 2.5ns
500ns 4.0ns
2.5ns
4.0ns
0.0V
R
C
D
T
2.0V
1MHz
1.0V
Test circuit for outputs on B port
DEFINITIONS:
R
C
R
C
R
=
=
=
=
=
Load resistor; see AC electrical characteristics for value.
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Pull up resistor; see AC electrical characteristics for value.
L
L
U
D
T
Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value.
Termination resistance should be equal to Z
of pulse generators.
SF00431
OUT
8
May 19, 1992
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver
(3-State + open collector)
74F777
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
9
1992 May 19
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver
(3-State + open collector)
74F777
PLCC20: plastic leaded chip carrier; 20 leads
SOT380-1
10
1992 May 19
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver
(3-State + open collector)
74F777
NOTES
11
1992 May 19
Philips Semiconductors
Product specification
Triple bidirectional latched bus transceiver
(3-State + open collector)
74F777
Data sheet status
[1]
Data sheet
status
Product
status
Definition
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Righttomakechanges—PhilipsSemiconductorsreservestherighttomakechanges, withoutnotice, intheproducts, includingcircuits,standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Date of release: 10-98
Document order number:
9397-750-05178
Philips
Semiconductors
相关型号：
I74F786D,602
IC BUS ARBITER AND CONT SIG GEN, PDSO16, 3.90 MM, PLASTIC, SO-16, System Interface Logic
NXP
I74F786D,623
IC BUS ARBITER AND CONT SIG GEN, PDSO16, 3.90 MM, PLASTIC, SO-16, System Interface Logic
NXP
©2020 ICPDF网 联系我们和版权申明