ICM7555ID/01/CE151_技术文档

ICM7555

General purpose CMOS timer

Rev. 02 — 3 August 2009

Product data sheet

1. General description

The ICM7555 is a CMOS timer providing signiﬁcantly improved performance over the

standard NE/SE555 timer, while at the same time being a direct replacement for those

devices in most applications. Improved parameters include low supply current, wide

operating supply voltage range, low THRESHOLD, TRIGGER, and RESET currents, no

crowbarring of the supply current during output transitions, higher frequency performance

and no requirement to decouple CONTROL_VOLTAGE for stable operation.

The ICM7555 is a stable controller capable of producing accurate time delays or

frequencies.

In the one-shot mode, the pulse width of each circuit is precisely controlled by one

external resistor and capacitor. For astable operation as an oscillator, the free-running

frequency and the duty cycle are both accurately controlled by two external resistors and

one capacitor. Unlike the NE/SE555 device, the CONTROL_VOLTAGE terminal need not

be decoupled with a capacitor. The TRIGGER and RESET inputs are active LOW. The

output inverter can source or sink currents large enough to drive TTL loads or provide

minimal offsets to drive CMOS loads.

2. Features

I Exact equivalent in most applications for NE/SE555

I Low supply current: 80 µA (typical)

I Extremely low trigger, threshold, and reset currents: 20 pA (typical)

I High-speed operation: 500 kHz guaranteed

I Wide operating supply voltage range guaranteed 3 V to 16 V over full automotive

temperatures

I Normal reset function; no crowbarring of supply during output transition

I Can be used with higher-impedance timing elements than the NE/SE555 for longer

time constants

I Timing from microseconds through hours

I Operates in both astable and monostable modes

I Adjustable duty cycle

I High output source/sink driver can drive TTL/CMOS

I Typical temperature stability of 0.005 % / °C at 25 °C

I Rail-to-rail outputs

ICM7555

NXP Semiconductors

General purpose CMOS timer

3. Applications

I Precision timing

I Pulse generation

I Sequential timing

I Time delay generation

I Pulse width modulation

I Pulse position modulation

I Missing pulse detector

4. Ordering information

Table 1.

Ordering information

Type number Temperature range

Package

Name

SO8

Description

Version

ICM7555CD

ICM7555ID

ICM7555CN

ICM7555IN

T_amb= 0 °C to +70 °C

T_amb= −40 °C to +85 °C

T_amb= 0 °C to +70 °C

T_amb= −40 °C to +85 °C

plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

DIP8

plastic dual in-line package; 8 leads (300 mil)

SOT97-1

5. Functional diagram

flip-flop

V

RESET

4

DD

8

R

output

drivers

comparator A

comparator B

6

5

3

THRESHOLD

CONTROL_VOLTAGE

OUTPUT

R

DISCHARGE

7

2

TRIGGER

N

1

GND

1

GND

002aae403

Remark: Unused inputs should be connected to appropriate voltage from Table 3.

Fig 1. Functional diagram

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

2 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

6. Pinning information

6.1 Pinning

1

2

3

4

8

7

6

5

GND

TRIGGER

OUTPUT

RESET

V

DD

1

2

3

4

8

7

6

5

GND

TRIGGER

OUTPUT

RESET

V

DD

DISCHARGE

ICM7555CD

ICM7555ID

ICM7555CN

ICM7555IN

THRESHOLD

CONTROL_VOLTAGE

002aae400

002aae401

Fig 2. Pin conﬁguration for SO8

Fig 3. Pin conﬁguration for DIP8

6.2 Pin description

Table 2.

Symbol

GND

Pin description

Description

1

2

3

4

5

6

7

8

supply ground

TRIGGER

OUTPUT

RESET

start timer input; (active LOW)

timer logic level output

timer inhibit input; (active LOW)

timing capacitor upper voltage sense input

timing capacitor lower voltage sense input

timing capacitor discharge output

supply voltage

CONTROL_VOLTAGE

THRESHOLD

DISCHARGE

V_DD

7. Functional description

Refer to Figure 1 “Functional diagram”.

7.1 Function selection

Table 3.

Function selection

THRESHOLD voltage

TRIGGER voltage

RESET^[1]

OUTPUT

Discharge switch

don’t care

L

on

> ²⁄₃V+

V_th< ²⁄₃V+

> ¹⁄₃V+

V_trig> ¹⁄₃V+

< ¹⁄₃V+

H

L

on

stable

H

stable

off

don’t care

[1] RESET will dominate all other inputs; TRIGGER will dominate over THRESHOLD.

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

3 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

8. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

Max

Unit

V

supply voltage

input voltage

18

[1]

V_I

TRIGGER

−0.3

-

V_DD+ 0.3

100

V

CONTROL_VOLTAGE

THRESHOLD

RESET

V

I_O

P

output current

mA

[2][3]

power dissipation

T_amb= 25 °C (still air)

DIP8 package

-

1160

780

mW

°C

SO8 package

-

T_stg

T_sp

storage temperature

−65

+150

300

solder point temperature

soldering 60 s

-

°C

[1] Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater

than V_DD+ 0.3 V or less than GND − 0.3 V may cause destructive latch-up. For this reason it is recommended that no inputs from

external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple

systems, the supply of the ICM7555 must be turned on ﬁrst.

[2] Above 25 °C, derate at the following rates:

DIP8 package at 9.3 mW / °C

SO8 package at 6.2 mW / °C

[3] Refer to Section 11.2 “Power supply considerations” section.

9. Characteristics

Table 5.

Characteristics

T_amb= 25 °C unless otherwise speciﬁed.

Sym Parameter

bol

Conditions

_min≤ T_amb≤ T_max

Min

Typ

Max

Unit

V_DD

I_DD

supply voltage

supply current^[1]

T

3

-

16

V

V_DD= V_min

V_DD= V_max

50

180

200

300

µA

-

Astable mode timing^[2][3]

∆f/f frequency stability

-

1.0

0.1

50

5.0

%

∆f/∆V frequency variation with voltage

3.0

%/V

∆f/∆T frequency variation with

V_DD= 5 V

-

ppm/°C

temperature^[4]

V_DD= 10 V

75

ppm/°C

V_DD= 15 V

100

ppm/°C

V_I

input voltage

TRIGGER: V_DD= 5 V

CONTROL_VOLTAGE: V_DD= 5 V

THRESHOLD: V_DD= 5 V

RESET: V_DD= V_minand V_max

0.29V_DD0.31V_DD0.34V_DD

0.62V_DD0.65V_DD0.67V_DD

0.63V_DD0.65V_DD0.67V_DD

V

0.4V_DD

0.7V_DD

1.0V_DD

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

4 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

Table 5.

Characteristics …continued

T_amb= 25 °C unless otherwise speciﬁed.

Sym Parameter

bol

Conditions

Min

Typ

Max

Unit

I_I

input current

TRIGGER

V_DD= V_trig= V_max

V_DD= V_trig= 5 V

V_DD= V_trig= V_min

THRESHOLD

-

50

10

1

-

pA

V_DD= V_th= V_max

V_DD= V_th= 5 V

V_DD= V_th= V_min

RESET

-

50

10

1

-

pA

V_DD= V_rst= V_max

V_DD= V_rst= 5 V

V_DD= V_rst= V_min

V_DD= V_max; I_sink= 3.2 mA

V_DD= 5 V; I_sink= 3.2 mA

I_source= −1.0 mA

V_DD= V_max

-

100

20

-

pA

V

-

2

-

V_OL

LOW-level output voltage

HIGH-level output voltage

0.1

0.2

0.4

V

V_OH

15.25

4.0

-

15.7

4.5

-

V

V_DD= 5 V_max

-

V_o

output voltage

DISCHARGE:

0.2

0.4

V

_DD= 5 V; I_DIS= 10 mA

R_L= 10 MΩ; C_L= 10 pF;

_DD= 5 V

t_r(o)

output rise time^[4]

-

45

75

ns

V

t_f(o)

f_osc

output fall time^[4]

-

20

-

75

ns

oscillator frequency

astable mode

500

kHz

[1] The supply current value is essentially independent of the TRIGGER, THRESHOLD and RESET voltages.

[2] Astable timing is calculated using the following equation:

1.38

(R_A+ 2R_B)C

f =

--------------------------------

The components are deﬁned in Figure 15.

[3] R_A, R_B= 1 kΩ to 100 kΩ; C = 0.1 µF; 5 V < V_DD< 15 V

[4] Parameter is not 100 % tested.

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

5 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

10. Typical performance curves

002aae404

250

I

DD

(µA)

200

T

= −55 °C

+25 °C

amb

150

100

50

+125 °C

0

5

10

15

20

V

(V)

DD

Fig 4. Supply current versus supply voltage

002aae405

2

10

I

o(source)

(mA)

V

= 18 V

5 V

DD

2 V

10

1

−1

10

−1

2

10

1

10

V

− V (V)

O

DD

T_amb= +25 °C.

Fig 5. High output voltage drop versus output source current

002aae406

2

10

I

DIS

(mA)

10

V

= 18 V

5 V

DD

1

2 V

−1

10

−1

10

1

10

V

(V)

DIS

T_amb= +25 °C.

Fig 6. Discharge low output voltage versus discharge sink current

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

6 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

002aae407

2

10

I

V

= 18 V

5 V

o(sink)

(mA)

DD

2 V

10

1

−1

10

−1

10

1

10

V

(V)

OL

a. T_amb= +125 °C.

002aae408

2

10

I

V

= 18 V

5 V

2 V

o(sink)

(mA)

DD

10

1

−1

10

−1

10

b. T_amb= +25 °C.

002aae409

2

10

V

= 18 V

5 V

2 V

DD

I

o(sink)

(mA)

10

1

−1

10

−1

10

c. T_amb= −55 °C.

Fig 7. Low output voltage versus output sink current

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

7 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

002aae410

500

TRIGGER pulse width (ns)

V

= 18 V

5 V

DD

400

300

200

100

2 V

0

10

20

30

40

lowest voltage level of TRIGGER pulse (% V

)

DD

Fig 8. Minimum pulse width for triggering

002aae411

1000

t

PD

(ns)

T

= −55 °C

+25 °C

+125 °C

amb

750

500

250

0

10

20

30

40

lowest voltage level of TRIGGER pulse (% V

)

DD

Fig 9. Propagation delay versus voltage level of TRIGGER pulse (V_DD= 5 V)

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

8 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

002aae413

6

normalized frequency

(%)

4

2

0

−2

−4

0

5

10

15

20

V

(V)

DD

T_amb= +25 °C

R_A= R_B= 10 kΩ

C = 0.1 µF

Fig 10. Normalized frequency stability as a function of supply voltage (astable mode)

002aae414

4

normalized frequency

(%)

V

= 18 V

5 V

DD

2 V

2

0

−2

−4

−75

−25

25

75

125

T

(°C)

amb

R_A= R_B= 1 kΩ

C = 0.1 µF

Fig 11. Normalized frequency stability as a function of temperature (astable mode)

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

9 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

002aae415

2

10

C (µF)

10

1

−1

10

−2

−3

−4

−5

10

1 kΩ

10 kΩ

100 kΩ

1 MΩ

10 MΩ

−1

2

3

4

5

6

7

10

1

10

f (Hz)

V_DD= 5 V; T_amb= +25 °C

Fig 12. Free-running frequency as a function of R_A, R_Bresistance and external

capacitance

002aae416

2

10

C (µF)

10

1 kΩ

10 kΩ

100 kΩ

1 MΩ

1

10 MΩ

−1

10

−2

10

−3

10

−4

10

−5

10

−7

−6

−5

−4

−3

−2

−1

10

1

10

t

(s)

d

V_DD= 5 V; T_amb= +25 °C

Fig 13. Monostable time delay versus R_Aresistance and external capacitance

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

10 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

11. Application information

11.1 General

The ICM7555 device is, in most instances, a direct replacement for the NE/SE555 device.

However, it is possible to effect economies in the external component count using the

ICM7555. Because the NE/SE555 device produces large crowbar currents in the output

driver, it is necessary to decouple the power supply lines with a good capacitor close to

the device. The ICM7555 device produces no such transients. See Figure 14.

The ICM7555 produces supply current spikes of only 2 mA to 3 mA instead of

300 mA to 400 mA and supply decoupling is normally not necessary. Secondly, in most

instances, the CONTROL_VOLTAGE decoupling capacitors are not required since the

input impedance of the CMOS comparators on chip are very high. Thus, for many

applications, 2 capacitors can be saved using an ICM7555.

002aae417

500

I

DD

(mA)

300

(1)

100

(2)

−100

0

200

400

600

800

time (ns)

T_amb= +25 °C

(1) NE/SE555

(2) ICM7555

Fig 14. Supply current transient compared with a standard NE/SE555 device during an

output transition

11.2 Power supply considerations

Although the supply current consumed by the ICM7555 device is very low, the total

system supply can be high unless the timing components are high-impedance. Therefore,

high values for R and low values for C in Figure 15 and Figure 16 are recommended.

11.3 Output drive capability

The output driver consists of a CMOS inverter capable of driving most logic families

including CMOS and TTL. As such, if driving CMOS, the output swing at all supply

voltages will equal the supply voltage. At a supply voltage of 4.5 V or more, the ICM7555

will drive at least 2 standard TTL loads.

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

11 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

11.4 Astable operation

If the circuit is connected as shown in Figure 15, it will trigger itself and free run as a

multivibrator. The external capacitor charges through R_Aand R_Band discharges through

R_Bonly. Thus, the duty cycle (δ) may be precisely set by the ratio of these two resistors. In

this mode of operation, the capacitor charges and discharges between ¹⁄₃V_DDand

²⁄₃V_DD. Since the charge rate and the threshold levels are directly proportional to the

supply voltage, the frequency of oscillation is independent of the supply voltage.

1.38

(R_A+ 2R_B) × C

f =

δ =

(1)

(2)

--------------------------------------

R_A+ R_B

----------------------

R_A+ 2R_B

V

DD

1

2

3

4

8

7

6

5

GND

V

DD

R

A

TRIGGER

OUTPUT

RESET

DISCHARGE

THRESHOLD

OUTPUT

R

B

CONTROL_VOLTAGE

V

DD

C

002aae418

Fig 15. Astable operation

11.5 Monostable operation

In this mode of operation, the timer functions as a one-shot. Initially, the external

capacitor (C) is held discharged by a transistor inside the timer. Upon application of a

negative pulse to pin 2, TRIGGER, the internal ﬂip-ﬂop is set, which releases the

low-impedance on DISCHARGE; the external capacitor charges and drives the OUTPUT

HIGH. The voltage across the capacitor increases exponentially with a time constant

t = R_AC. When the voltage across the capacitor equals ²⁄₃V+, the comparator resets the

ﬂip-ﬂop, which in turn discharges the capacitor rapidly and also drives the OUTPUT to its

LOW state. TRIGGER must return to a HIGH state before the OUTPUT can return to a

LOW state.

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

12 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

V

DD

R

A

1

2

3

4

8

7

6

5

GND

V

DD

TRIGGER

OUTPUT

RESET

DISCHARGE

THRESHOLD

CONTROL_VOLTAGE

optional

capacitor

C

002aae419

V_DD≤ 18 V; t = 1.05 R_AC

Fig 16. Monostable operation

11.6 Control voltage

The CONTROL_VOLTAGE terminal permits the two trip voltages for the THRESHOLD

and TRIGGER internal comparators to be controlled. This provides the possibility of

oscillation frequency modulation in the astable mode, or even inhibition of oscillation,

depending on the applied voltage. In the monostable mode, delay times can be changed

by varying the applied voltage to the CONTROL_VOLTAGE pin.

11.7 RESET

The RESET terminal is designed to have essentially the same trip voltage as the standard

NE/SE555 device, i.e., 0.6 V to 0.7 V. At all supply voltages it represents an extremely

high input impedance. The mode of operation of the RESET function is, however, much

improved over the standard NE/SE555 device in that it controls only the internal ﬂip-ﬂop,

which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins.

This avoids the multiple threshold problems sometimes encountered with slow falling

edges in the NE/SE555 devices.

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

13 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

12. Package outline

SO8: plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

D

E

A

X

c

y

H

v

M

A

E

Z

5

8

Q

A

2

A

(A )

3

A

1

pin 1 index

θ

L

p

L

1

4

e

w

M

detail X

b

p

0

2.5

5 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

0.25

0.10

1.45

1.25

0.49

0.36

0.25

0.19

5.0

4.8

4.0

3.8

6.2

5.8

1.0

0.4

0.7

0.6

0.7

0.3

mm

1.27

0.05

1.05

0.041

1.75

0.25

0.01

0.25

0.01

0.25

0.1

8^o

0^o

0.010 0.057

0.004 0.049

0.019 0.0100 0.20

0.014 0.0075 0.19

0.16

0.15

0.244

0.228

0.039 0.028

0.016 0.024

0.028

0.012

inches 0.069

0.01 0.004

Notes

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-18

SOT96-1

076E03

MS-012

Fig 17. Package outline SOT96-1 (SO8)

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

14 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

DIP8: plastic dual in-line package; 8 leads (300 mil)

SOT97-1

D

M

E

A

2

A

1

L

c

w M

Z

b

1

e

(e )

1

M

H

b

2

8

5

pin 1 index

E

1

4

0

5

10 mm

scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

(1)

A

2

(1)

Z

1

w

UNIT

mm

b

c

D

E

e

L

M

H

1

2

1

E

max.

min.

max.

1.73

1.14

0.53

0.38

1.07

0.89

0.36

0.23

9.8

9.2

6.48

6.20

3.60

3.05

8.25

7.80

10.0

8.3

4.2

0.51

3.2

2.54

0.1

7.62

0.3

0.254

0.01

1.15

0.068 0.021 0.042 0.014

0.045 0.015 0.035 0.009

0.39

0.36

0.26

0.24

0.14

0.12

0.32

0.31

0.39

0.33

inches

0.17

0.02

0.13

0.045

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-12-27

03-02-13

SOT97-1

050G01

MO-001

SC-504-8

Fig 18. Package outline SOT97-1 (DIP8)

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

15 of 22

ICM7555

NXP Semiconductors

General purpose CMOS timer

13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

13.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

13.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

ICM7555_2

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Rev. 02 — 3 August 2009

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13.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 19) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 6 and 7

Table 6.

SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

≥ 350

220

< 2.5

235

220

≥ 2.5

220

Table 7.

Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 19.

ICM7555_2

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Rev. 02 — 3 August 2009

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 19. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

14. Soldering of through-hole mount packages

14.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

14.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

14.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

ICM7555_2

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14.4 Package related soldering information

Table 8.

Suitability of through-hole mount IC packages for dipping and wave soldering

Soldering method

Package

Dipping

Wave

CPGA, HCPGA

-

suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL

PMFP^[2]

suitable

-

suitable^[1]

not suitable

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

15. Abbreviations

Table 9.

Abbreviations

Description

Acronym

CMOS

TTL

Complementary Metal-Oxide Semiconductors

Transistor-Transistor Logic

SCR

Silicon-Controlled Rectiﬁer

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

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16. Revision history

Table 10. Revision history

Document ID

ICM7555_2

Release date

Data sheet status

Change notice

Supersedes

20090803

Product data sheet

-

ICM7555_1

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP

Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Provided separate pinning diagrams for SO8 and DIP8 packages (Figure 2 and Figure 3,

respectively).

• Added Table 2 “Pin description”.

• Table 4 “Limiting values”:

–

Symbols V_TRIG, V_CV, V_TH, V_RSTare replaced with V_I(speciﬁc pin names are now noted under

Conditions column).

–

Symbol/parameter “P_DMAX, maximum power dissipation” replaced with “P, power dissipation” (only

maximum values given).

–

Symbol/parameter “T_STG, storage temperature range” replaced with “T_stg, storage temperature”.

Symbol changed from “T_SOLD” to “T_sp, solder point temperature”

• Table 5 “Characteristics”:

–

Symbols ∆f/f, ∆f/∆V, ∆f/∆T, have been added for Astable mode timing.

–

Symbols V_TRIG, V_CV, V_TH, V_RSTare replaced with V_I(speciﬁc pin names are now noted under

Conditions column).

–

Symbols I_TRIG, I_TH, I_RSTare replaced with I_I(speciﬁc pin names are now noted under Conditions

column).

Symbol/parameter “V_DIS, discharge output voltage” changed to “V_o, output voltage” (speciﬁc pin

name is now noted under Conditions column).

–

Symbol/parameter “t_R, rise time of output” changed to “t_r(o), output rise time”.

Symbol/parameter “t_F, fall time of output” changed to “t_f(o), output fall time”.

Symbol “F_MAX” changed to “f_osc, oscillator frequency”.

• Section 11.4 “Astable operation”: changed symbol for duty cycle from “D” to “δ”.

• Added Section 12 “Package outline”.

• Added soldering information.

• Added Section 15 “Abbreviations”.

ICM7555_1

19940831

Product speciﬁcation

ECN 853-1192 13721

dated 1994 Aug 31

-

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

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17. Legal information

17.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

17.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

17.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

17.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

18. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

ICM7555_2

Product data sheet

Rev. 02 — 3 August 2009

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19. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7

7.1

8

Functional description . . . . . . . . . . . . . . . . . . . 3

Function selection. . . . . . . . . . . . . . . . . . . . . . . 3

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4

Typical performance curves . . . . . . . . . . . . . . . 6

9

10

11

Application information. . . . . . . . . . . . . . . . . . 11

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Power supply considerations . . . . . . . . . . . . . 11

Output drive capability . . . . . . . . . . . . . . . . . . 11

Astable operation . . . . . . . . . . . . . . . . . . . . . . 12

Monostable operation . . . . . . . . . . . . . . . . . . . 12

Control voltage . . . . . . . . . . . . . . . . . . . . . . . . 13

RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

11.1

11.2

11.3

11.4

11.5

11.6

11.7

12

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

13

Soldering of SMD packages . . . . . . . . . . . . . . 16

Introduction to soldering . . . . . . . . . . . . . . . . . 16

Wave and reﬂow soldering . . . . . . . . . . . . . . . 16

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 17

13.1

13.2

13.3

13.4

14

14.1

Soldering of through-hole mount packages . 18

Introduction to soldering through-hole mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Soldering by dipping or by solder wave . . . . . 18

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 18

Package related soldering information . . . . . . 19

14.2

14.3

14.4

15

16

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 19

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20

17

Legal information. . . . . . . . . . . . . . . . . . . . . . . 21

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

17.1

17.2

17.3

17.4

18

19

Contact information. . . . . . . . . . . . . . . . . . . . . 21

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 3 August 2009

Document identifier: ICM7555_2


型号：	ICM7555ID/01/CE151
厂家：	NXP
描述：	ICM7555IDSOT96-1 信息通信管理
文件：	总22页 (文件大小：122K)
中文：	中文翻译
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ICM7555ID/01/CE151 [NXP]

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