IP4778CZ38,118 [NXP]

IC SPECIALTY CONSUMER CIRCUIT, PDSO38, 4.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, SOT510-1, TSSOP-38, Consumer IC:Other;
IP4778CZ38,118
型号: IP4778CZ38,118
厂家: NXP    NXP
描述:

IC SPECIALTY CONSUMER CIRCUIT, PDSO38, 4.40 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, SOT510-1, TSSOP-38, Consumer IC:Other

光电二极管 商用集成电路
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IP4778CZ38  
HDMI ESD protection, DDC buffering and hot plug control  
Rev. 3 — 31 March 2011  
Product data sheet  
1. General description  
The IP4778CZ38 is designed for HDMI receiver host interface protection.  
The IP4778CZ38 includes DDC buffering, slew rate acceleration and decoupling, hot plug  
control, backdrive protection, CEC slew rate control, optional multiplexing of DDC signals,  
and high-level ESD protection diodes for all HDMI signals.  
The DDC lines are buffered using a new buffering concept which decouples the internal  
capacitive load from the external capacitive load. This allows higher PCB design flexibility  
for the DDC lines with respect to a maximum load of 50 pF. This buffering also boosts the  
DDC signals, allowing the use of longer HDMI cables having a higher capacitive load than  
700 pF. The CEC slew rate limiter prevents ringing on the CEC line and greatly reduces  
the number of discrete components needed by the CEC application. HDMI receiver and  
system GPIO applications are simplified by an internal hot plug driver module and hot plug  
control.  
The DDC, hot plug and CEC lines are backdrive protected to guarantee HDMI interface  
signals are not pulled down if the system is powered down or enters Standby mode.  
All TMDS intra-pairs are protected by a special diode configuration offering a low line  
capacitance of 0.7 pF only (to ground) and 0.05 pF between the TMDS pairs. These  
diodes provide protection to components downstream from ESD voltages of up to ±8 kV  
contact in accordance with the IEC 61000-4-2, level 4 standard.  
2. Features and benefits  
„ Pb-free and RoHS compliant  
„ Robust ESD protection without degradation after several ESD strikes  
„ Low leakage even after several hundred ESD discharges  
„ Very high diode switching speed (ns) and low line capacitance of 0.7 pF to ground and  
0.05 pF between channels ensures signal integrity  
„ DDC capacitive decoupling between system side and HDMI connector side and drive  
cable buffering with capacitive load (> 700 pF)  
„ Hot plug control for direct connection to system GPIO  
„ CEC ringing prevention by slew rate limiter  
„ DDC and hot plug enable signal for multiplexing and backdrive protection  
„ All TMDS lines with integrated rail-to-rail clamping diodes with downstream  
ESD protection of ±8 kV in accordance with IEC 61000-4-2, level 4  
„ Matched 0.5 mm trace spacing  
„ Component count reduction of HDMI receiver application  
 
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
„ Highest integration in a small footprint, PCB level, optimized RF routing, 38-pin  
TSSOP lead-free package  
„ Choice of system compatible or RF routing optimized pinning variants  
3. Applications  
„ The IP4778CZ38 can be used for a wide range of HDMI sink devices e.g.:  
‹ TV  
‹ Projectors  
‹ PC monitors  
‹ HDMI buffer modules (extensions of HDMI cable length)  
‹ HDMI picture performance quality enhancer modules  
4. Ordering information  
Table 1.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
IP4778CZ38  
TSSOP38 plastic thin shrink small outline package; 38 leads;  
body width 4.4 mm; lead pitch 0.5 mm  
SOT510-1  
IP4778CZ38/V  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
2 of 28  
 
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
5. Functional diagram  
TMDS_D2+  
TMDS_D1+  
TMDS_BIAS  
TMDS_D0+  
TMDS_CLK+  
5V0  
TMDS_D2  
TMDS_D1−  
TMDS_GND  
TMDS_D0−  
TMDS_CLK−  
TMDS_BIAS  
V
V
TMDS_BIAS  
V
CC(5V0)  
CC(5V0)  
CC(3V3)  
SLEW  
RATE  
ACCELERATOR  
HOT_PLUG_DET_OUT  
HOT_PLUG_DET_IN  
ENABLE  
DDC_CLK_OUT  
DDC_CLK_IN  
10 μA  
TMDS_BIAS  
V
TMDS_BIAS  
V
CC(5V0)  
CC(3V3)  
SLEW  
RATE  
ACCELERATOR  
CEC_OUT  
CEC_IN  
ENABLE  
DDC_DAT_OUT  
DDC_DAT_IN  
SLEW  
RATE  
LIMITER  
001aae863  
Fig 1. Functional diagram  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
3 of 28  
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
6. Pinning information  
6.1 Pinning  
1
2
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
V
TMDS_BIAS  
CC(5V0)  
ENABLE  
GND  
V
CC(3V3)  
3
GND  
4
TMDS_D2+  
n.c.  
n.c.  
5
TMDS_D2−  
TMDS_GND  
n.c.  
6
TMDS_GND  
TMDS_D1+  
n.c.  
7
8
TMDS_D1−  
TMDS_GND  
n.c.  
9
TMDS_GND  
TMDS_D0+  
n.c.  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
IP4778CZ38  
TMDS_D0−  
TMDS_GND  
n.c.  
TMDS_GND  
TMDS_CLK+  
n.c.  
TMDS_CLK−  
TMDS_GND  
CEC_OUT  
DDC_CLK_OUT  
DDC_DAT_OUT  
HOT_PLUG_DET_OUT  
TMDS_GND  
CEC_IN  
DDC_CLK_IN  
DDC_DAT_IN  
HOT_PLUG_DET_IN  
001aag032  
Fig 2. Pin configuration of IP4778CZ38  
1
2
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
V
TMDS_BIAS  
CC(5V0)  
ENABLE  
GND  
V
CC(3V3)  
3
GND  
4
TMDS_D2+  
TMDS_GND  
n.c.  
n.c.  
5
TMDS_GND  
TMDS_D2−  
n.c.  
6
7
TMDS_D1+  
TMDS_GND  
n.c.  
8
TMDS_GND  
TMDS_D1−  
n.c.  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
TMDS_D0+  
TMDS_GND  
n.c.  
IP4778CZ38/V  
TMDS_GND  
TMDS_D0−  
n.c.  
TMDS_CLK+  
TMDS_GND  
n.c.  
TMDS_GND  
TMDS_CLK−  
CEC_OUT  
DDC_CLK_OUT  
DDC_DAT_OUT  
HOT_PLUG_DET_OUT  
CEC_IN  
DDC_CLK_IN  
DDC_DAT_IN  
HOT_PLUG_DET_IN  
001aag031  
Fig 3. Pin configuration of IP4778CZ38/V  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
4 of 28  
 
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
6.2 Pin description  
Table 2.  
Symbol  
Pin description  
Pin  
Description  
IP4778CZ38  
IP4778CZ38/V  
VCC(5V0)  
1
1
supply voltage for DDC and hot plug  
circuits  
ENABLE  
GND  
2
3
2
3
enable for DDC and hot plug circuits  
ground for DDC, hot plug and CEC  
circuits[1]  
TMDS_D2+  
TMDS_GND  
n.c.  
4
4
ESD protection TMDS channel D2+[2]  
ground for TMDS channel[1]  
not connected[2]  
6
5
5
6
TMDS_D1+  
TMDS_GND  
n.c.  
7
7
ESD protection TMDS channel D1+[2]  
ground for TMDS channel[1]  
not connected[2]  
9
8
8
9
TMDS_D0+  
TMDS_GND  
n.c.  
10  
12  
11  
13  
10  
11  
12  
13  
ESD protection TMDS channel D0+[2]  
ground for TMDS channel[1]  
not connected[2]  
TMDS_CLK+  
ESD protection TMDS channel  
CLK+[2]  
TMDS_GND  
n.c.  
15  
14  
16  
14  
15  
16  
ground for TMDS channel[1]  
not connected[2]  
CEC_IN  
CEC signal input to system  
controller[3]  
DDC_CLK_IN  
17  
17  
DDC clock input to system  
controller[3]  
DDC_DAT_IN  
18  
19  
18  
19  
DDC data input to system controller[3]  
HOT_PLUG_DET_IN  
hot plug Detect input from system  
GPIO[3]  
HOT_PLUG_DET_OUT 20  
20  
hot plug Detect output to HDMI  
connector[4]  
DDC_DAT_OUT  
DDC_CLK_OUT  
21  
22  
21  
22  
DDC data output to HDMI connector[4]  
DDC clock output to HDMI  
connector[4]  
CEC_OUT  
23  
25  
23  
24  
CEC signal output to HDMI  
connector[3]  
TMDS_CLK−  
ESD protection TMDS channel  
CLK[2]  
TMDS_GND  
n.c.  
24  
26  
28  
27  
29  
31  
30  
25  
26  
27  
28  
29  
30  
31  
ground for TMDS channel[1]  
not connected[2]  
ESD protection TMDS channel D0[2]  
ground for TMDS channel[1]  
not connected[2]  
TMDS_D0−  
TMDS_GND  
n.c.  
TMDS_D1−  
TMDS_GND  
ESD protection TMDS channel D1[2]  
ground for TMDS channel[1]  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
5 of 28  
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
Table 2.  
Pin description …continued  
Symbol  
Pin  
Description  
IP4778CZ38  
IP4778CZ38/V  
n.c.  
32  
34  
33  
35  
36  
32  
33  
34  
35  
36  
not connected[2]  
TMDS_D2−  
TMDS_GND  
n.c.  
ESD protection TMDS channel D2[2]  
ground for TMDS channel[1]  
not connected[2]  
GND  
ground for DDC, hot plug and CEC  
circuits[1]  
VCC(3V3)  
37  
38  
37  
38  
supply voltage for CEC circuit  
TMDS_BIAS  
bias input for TMDS ESD protection.  
This pin must be connected to a  
0.1 μF capacitor.  
[1] Pins GND and TMDS_GND are internally connected.  
[2] This pin must always be connected to the IC pin located opposite via a PCB track to guarantee correct  
functionality; see Figure 15.  
[3] VCC(3V3) referenced logic level in.  
[4] VCC(5V0) referenced logic level out.  
7. Limiting values  
Table 3.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
VCC  
Parameter  
Conditions  
Min  
Max  
5.5  
Unit  
V
supply voltage  
input voltage  
GND 0.5  
GND 0.5  
VI  
at input pins  
5.5  
V
[1]  
[2]  
VESD  
electrostatic discharge  
voltage  
connector side pins (to ground);  
IEC 61000-4-2, level 4  
contact  
8  
+8  
kV  
board side pins; IEC 61000-4-2, level 1  
contact  
2  
-
+2  
8
kV  
Ptot  
Tstg  
total power dissipation  
storage temperature  
DDC operating at 100 kHz  
mW  
55  
+125 °C  
[1] Connector side pins:  
TMDS_D2+, TMDS_D2, TMDS_D1+, TMDS_D1, TMDS_D0+, TMDS_D0,  
TMDS_CLK+, TMDS_CLK,  
CEC_OUT,  
DDC_DAT_OUT and DDC_CLK_OUT,  
HOT_PLUG_DET_OUT.  
[2] Board side pins:  
CEC_IN,  
DDC_DAT_IN and DDC_CLK_IN,  
HOT_PLUG_DET_IN,  
ENABLE.  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
6 of 28  
 
 
 
 
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
8. Static characteristics  
Table 4.  
TMDS protection circuit  
Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
Zener diode  
VBRzd  
Zener diode breakdown  
voltage  
I = 1 mA  
6
-
9
V
Rdyn  
dynamic resistance  
back current  
I = 1 A; IEC 61000-4-5/9  
positive transient  
-
-
2.4  
1.3  
-
-
Ω
Ω
negative transient  
Protection diode  
Ibck  
from pins TMDS_x to pin TMDS_BIAS;  
VCC(5V0) = 0 V; VCC(3V3) = 0 V  
-
0.1  
5
μA  
IL(r)  
reverse leakage current  
forward voltage  
VI = 3.0 V  
-
-
-
1
-
-
-
μA  
V
VF  
0.7  
8
[1]  
VCL(ch)trt(pos)  
positive transient channel  
clamping voltage  
VESD = 8 kV per IEC 61000-4-2; voltage  
30 ns after trigger  
V
TMDS channel: pins TMDS_x  
[2]  
[2]  
Cch(TMDS)  
TMDS channel capacitance VCC(5V0) = 5 V; f = 1 MHz; Vbias = 2.5 V  
-
-
0.7  
-
-
pF  
pF  
ΔCch(TMDS)  
TMDS channel capacitance VCC(5V0) = 5 V; f = 1 MHz; Vbias = 2.5 V  
difference  
0.05  
[2]  
Cch(mutual)  
mutual channel capacitance between signal pin TMDS_x and  
pin n.c.; VCC(5V0) = 0 V; f = 1 MHz;  
Vbias = 2.5 V  
-
0.07  
-
pF  
[1] This measurement is performed with a 0.1 μF external capacitor on pin TMDS_BIAS.  
[2] This parameter is guaranteed by design.  
Table 5.  
DDC circuit  
VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ Max  
Unit  
Supplies: pins VCC(5V0) and VCC(3V3)  
VCC(5V0) supply voltage (5.0 V)  
VCC(3V3) supply voltage (3.3 V)  
4.5  
2.7  
-
5.0 5.5  
3.3 5.5  
0.5 1.0  
V
V
ICC(5V0)  
supply current (5.0 V)  
VCC(5V0) = 5.5 V;  
mA  
both channels HIGH:  
DDC_DAT_OUT = VCC(5V0)  
DDC_CLK_OUT = VCC(5V0)  
;
V
CC(5V0) = 5.5 V;  
-
-
0.5 1.0  
mA  
both channels LOW:  
DDC_DAT_IN = GND;  
DDC_CLK_IN = GND;  
DDC_DAT_OUT = open;  
DDC_CLK_OUT = open  
ICC(3V3)  
supply current (3.3 V)  
no pull-up resistor  
-
0.1  
μA  
connected to VCC(3V3)  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
7 of 28  
 
 
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
Table 5.  
DDC circuit …continued  
VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ Max  
Unit  
Board side: pins DDC_CLK_OUT and DDC_DAT_OUT  
Used as input  
VIH  
VIL  
IIL  
HIGH-level input voltage  
LOW-level input voltage  
LOW-level input current  
input clamping voltage  
input leakage current  
input capacitance  
0.7 × VCC(3V3)  
-
-
-
-
-
5.5  
V
0.5  
0.3 × VCC(3V3)  
V
VI = 0.2 V  
-
-
-
1
μA  
V
VIK  
ILI  
Ii = 18 mA  
1.2  
±1  
VI = 3.6 V  
μA  
Ci  
VI = 3 V or 0 V  
VCC(3V3) = 3.3 V  
VCC(3V3) = 3.0 V  
-
-
8
8
10  
10  
pF  
pF  
Used as output  
VOL  
IOH  
Co  
LOW-level output voltage  
IOL = 100 μA or 6 mA  
VO = 3.6 V  
-
-
200 -  
mV  
HIGH-level output current  
output capacitance  
-
1
μA  
VI = 3 V or 0 V  
VCC(3V3) = 3.3 V  
VCC(3V3) = 3.0 V  
-
-
8
8
10  
10  
pF  
pF  
Connector side: pins DDC_CLK_IN and DDC_DAT_IN  
Used as input  
VIH  
VIL  
IIL  
HIGH-level input voltage  
LOW-level input voltage  
LOW-level input current  
-
-
-
410 -  
400 -  
mV  
mV  
μA  
DDC_DAT_OUT,  
-
10  
DDC_CLK_OUT, VI = 0.2 V  
VIK  
ILI  
input clamping voltage  
input leakage current  
input capacitance  
II = 18 mA  
-
-
-
-
1.2  
±1  
V
VI = 3.6 V  
μA  
Ci  
VI = 3 V or 0 V  
VCC(3V3) = 3.3 V  
VCC(3V3) = 3.0 V  
-
-
7
7
9
9
pF  
pF  
Used as output  
VOL  
IOH  
Co  
LOW-level output voltage  
IOL = 100 μA or 3 mA  
VO = 3.6 V  
-
-
700 -  
mV  
HIGH-level output current  
output capacitance  
-
1
μA  
VI = 3 V or 0 V  
VCC(3V3) = 3.3 V  
VCC(3V3) = 3.0 V  
-
-
8
8
10  
10  
pF  
pF  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
8 of 28  
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
Table 6.  
CEC circuit  
VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Board side: input pin CEC_IN  
[1]  
[2]  
CI(ch-GND)(levsh) level shifting input capacitance  
from channel to ground  
VCC(3V3) = 0 V; f = 1 MHz;  
-
-
12  
10  
16  
-
pF  
Vbias = 2.5 V  
SRr  
rising slew rate  
VI > 1.8 V  
mV/μs  
N-FET  
ΔVon  
on-state voltage drop  
N-FET state = on;  
-
125  
140  
mV  
VCC(3V3) = 2.5 V; VS = GND;  
I
DS = 3 mA  
Connector side: output pin CEC_OUT  
ILI  
input leakage current  
dynamic resistance  
1  
+0.1  
+1  
μA  
Rdyn  
I = 1 A; IEC 61000-4-5/9  
positive transient  
-
-
-
2.4  
1.3  
8
-
-
-
Ω
Ω
V
negative transient  
[3]  
VCL(ch)trt(pos)  
positive transient channel  
clamping voltage  
VESD = 8 kV per IEC 61000-4-2;  
voltage 30 ns after trigger;  
Tamb = 25 °C  
[1] This parameter is guaranteed by design.  
[2] For level shifting N-FET.  
[3] This measurement is performed with a 0.1 μF external capacitor on pin TMDS_BIAS.  
Table 7.  
Enable circuit  
VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Board side: input pin ENABLE[1]  
VIH  
VIL  
IIL  
HIGH-level input voltage  
LOW-level input voltage  
LOW-level input current  
HIGH = enable  
LOW = disable  
0.7 × VCC(3V3)  
-
VCC(5V0) + 0.5  
V
0.5  
-
0.3 × VCC(3V3)  
V
VI = 0.2 V;  
-
10  
-
μA  
VCC(3V3) = 5.5 V  
ILI  
Ci  
input leakage current  
input capacitance  
1  
+0.1 +1  
μA  
VI = 3 V or 0 V  
-
3
7
pF  
[1] The ENABLE pin has to be connected permanently to VCC(3V3) if no enable control is needed.  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
9 of 28  
 
 
 
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
Table 8.  
hot plug control circuit  
VCC(5V0) = 4.5 V to 5.5 V; VCC(3V3) = 2.7 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Board side: input pin HOT_PLUG_DET_IN  
VIH  
VIL  
IIL  
HIGH-level input voltage HIGH = hot plug off  
0.7 × VCC(3V3)  
-
VCC(5V0) + 0.5  
V
LOW-level input voltage  
LOW-level input current  
input leakage current  
input capacitance  
LOW = hot plug on  
0.5  
-
0.3 × VCC(3V3)  
V
VI = 2.0 V; VCC(3V3) = 5.5 V  
-
10  
+0.1  
4
-
μA  
μA  
pF  
ILI  
1  
-
+1  
7
Ci  
VI = 3 V or 0 V  
Connector side: output pin HOT_PLUG_DET_OUT  
ILI  
input leakage current  
input capacitance  
on-state voltage  
1  
-
+0.1  
6
+1  
7
μA  
pF  
Ci  
VI = 3 V or 0 V  
II = 5 mA  
Von  
-
400  
-
mV  
9. Dynamic characteristics  
Table 9.  
DDC circuits  
VCC(3V3) = 2.7 V to 5.5 V; VCC(5V0) = 4.5 V to 5.5 V; GND = 0 V; Tamb = 25 °C; unless otherwise specified.  
Symbol  
Board side to connector side; see Figure 4  
Pins DDC_CLK_IN to DDC_CLK_OUT and DDC_DAT_IN to DDC_DAT_OUT  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
[1]  
[1]  
tPLH  
tPHL  
LOW to HIGH propagation delay  
HIGH to LOW propagation delay  
150  
125  
270  
210  
300  
225  
ns  
ns  
Pins DDC_CLK_OUT and DDC_DAT_OUT  
tTLH  
tTHL  
LOW to HIGH transition time  
HIGH to LOW transition time  
RL = 1.35 kΩ; CL = 50 pF  
90  
2
110  
3
130  
5
ns  
ns  
[1]  
Connector side to board side; see Figure 5  
Pins DDC_CLK_OUT to DDC_CLK_IN and DDC_DAT_OUT to DDC_DAT_IN  
tPLH  
tPHL  
LOW to HIGH propagation delay  
HIGH to LOW propagation delay  
90  
20  
110  
30  
130  
40  
ns  
ns  
[1]  
[1]  
Pins DDC_CLK_IN and DDC_DAT_IN  
tTLH  
tTHL  
LOW to HIGH transition time  
HIGH to LOW transition time  
100  
2
120  
3
140  
5
ns  
ns  
Enable: pin ENABLE  
tsu set-up time  
[2]  
[2]  
pin ENABLE = HIGH before start  
condition  
100  
100  
-
-
-
-
ns  
ns  
th  
hold time  
pin ENABLE = HIGH after stop  
condition  
[1] Typical values were measured with VCC(3V3) = 3.3 V; VCC(5V0) = 5.0 V.  
[2] Pin ENABLE should only change state when the DDC bus is in an idle state.  
IP4778CZ38  
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Product data sheet  
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IP4778CZ38  
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HDMI ESD protection, DDC buffering and hot plug control  
9.1 AC Waveforms  
3.3 V  
input: board side  
0.7 V  
5.0 V  
t
PLH  
output: connector side  
1.5 V  
001aag034  
a. Propagation delay tPLH  
input: board side  
3.3 V  
1.65 V  
0.1 V  
t
t
PLH  
PHL  
output: connector side  
5.0 V  
80 %  
(1)  
2.5 V  
20 %  
0.3V  
CC(5V0)  
V
OL  
t
t
TLH  
THL  
001aag035  
(1) Dotted line indicates effect without slew rate accelerator.  
b. Propagation delay tPHL and transition time  
Fig 4. Board side to connector side operation  
IP4778CZ38  
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NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
output: connector side  
5.0 V  
0.3V  
CC(5V0)  
V
OL  
t
t
PLH  
PHL  
input: board side  
3.3 V  
80 %  
1.65 V  
20 %  
V
IL  
t
t
TLH  
THL  
001aag036  
Propagation delay output to input and transition time input  
Fig 5. Connector side to board side operation  
10. Application information  
10.1 TMDS  
To protect the TMDS lines and also to comply with the impedance requirements of the  
HDMI specification, the IP4778CZ38 provides ESD protection with a low capacitive load.  
The dominant value for the TMDS line impedance is the capacitive load to ground. The  
IP4778CZ38 has a capacitive load of only 0.7 pF.  
TMDS_D2+  
TMDS_D1+  
TMDS_BIAS  
TMDS_D0+  
TMDS_CLK+  
V
CC(5V0)  
TMDS_D2−  
TMDS_D1−  
TMDS_GND  
TMDS_D0−  
TMDS_CLK−  
001aag039  
Fig 6. ESD protection of TMDS lines  
IP4778CZ38  
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IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
10.2 DDC circuit  
The DDC-bus circuit contains full capacitive decoupling between the HDMI connector and  
the DDC-bus lines on the PCB. The capacitive decoupling ensures that the maximum  
capacitive load is within the 50 pF maximum of the HDMI specification.  
The slew rate accelerator supports high capacitive load on the HDMI cable side. Various  
HDMI cable suppliers produce low-cost and long (typically 25 m) HDMI cables with a  
capacitive load of up to 6 nF.  
The slew rate accelerator boosts the DDC signal independent of which side of the bus is  
releasing the signal. The DDC module provides a level shifting and a multiplex option  
which is enabled by the ENABLE signal.  
TMDS_BIAS  
V
TMDS_BIAS  
V
CC(5V0)  
CC(5V0)  
SLEW  
RATE  
SLEW  
RATE  
ACCELERATOR  
ACCELERATOR  
ENABLE  
ENABLE  
DDC_CLK_OUT  
DDC_DAT_OUT  
DDC_CLK_IN  
DDC_DAT_IN  
001aag040  
001aag041  
a. DDC clock  
b. DDC data  
Fig 7. DDC circuit  
5.0 V  
(1)  
(1)  
0.3V  
CC(5V0)  
001aag042  
(1) Dotted line indicates effect without slew rate accelerator.  
Fig 8. DDC output waveform  
IP4778CZ38  
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NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
10.3 Hot plug driver circuit  
The IP4778CZ38 includes a hot plug driver circuit that simplifies the hot plug application.  
The circuit can be connected directly to GPIO pins.  
The hot plug control input is actively pulled LOW to ensure that at system standby or  
start-up, the hot plug signal is HIGH even if a GPIO pin is in a 3-state condition.  
For correct CEC handling, it is essential that the hot plug signal is at HIGH-level in  
Standby mode. The HDMI source requires a hot plug signal so that it can read out the  
EDID information to initiate a proper start-up CEC sequence.  
TMDS_BIAS  
V
V
CC(3V3)  
CC(5V0)  
HOT_PLUG_DET_OUT  
HOT_PLUG_DET_IN  
10 μA  
001aag043  
Fig 9. Hot plug driver circuit  
IP4778CZ38  
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NXP Semiconductors  
10.4 CEC  
HDMI ESD protection, DDC buffering and hot plug control  
The CEC signal can generate distortions caused by signal ringing in a 1 kHz domain. The  
CEC slew rate limiter ensures that a signal does not ring independently of the CEC slave  
that is releasing the signal.  
A MOSFET transistor implements the backdrive protection which blocks signals during a  
power-down state.  
The slew rate of the CEC bus is controlled by a slew rate that is defined independently of  
the load (ohmic and capacitive) at the CEC bus.  
TMDS_BIAS  
V
CC(3V3)  
CEC_OUT  
CEC_IN  
SLEW  
RATE  
LIMITER  
001aag044  
Fig 10. CEC module  
(1)  
(1)  
0.8 V  
001aag045  
(1) Dotted line indicates effect without slew rate limiter.  
Fig 11. CEC output waveform  
IP4778CZ38  
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NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
10.5 Multiplexing  
Up to four HDMI interface ports can exist on an HDMI receiver. The DDC and hot plug  
signals are both needed to support various HDMI connectors, multiplexing and switching  
of the TMDS lines. The CEC bus has to remain functional in order to detect activity such  
as a brake in support.  
ENABLE  
ENABLE  
ENABLE  
input 1  
input 2  
input 3  
DDC_CLK_IN  
DDC_DAT_IN  
HOT_PLUG_DET_IN  
DDC_CLK_IN  
DDC_DAT_IN  
HOT_PLUG_DET_IN  
DDC_CLK_IN  
DDC_DAT_IN  
DDC_CLK_IN  
DDC_DAT_IN  
HOT_PLUG_DET_IN  
HOT_PLUG_DET_IN  
001aag046  
Fig 12. Example of multiplexing both DDC and hot plug  
The combination of a TMDS switch and the IP4778CZ38 is a cost-effective way to attain  
various HDMI ports by using a single input HDMI receiver device. The ENABLE signal  
activates the HDMI DDC and hot plug lines at the port that is selected by the system  
controller.  
IP4778CZ38  
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Product data sheet  
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IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
10.6 Backdrive protection  
The HDMI contains various signals which can partly supply current into an HDMI device  
that is powered down.  
Typically, the DDC lines and the CEC signals can force 5 V into the switched-off device.  
The IP4778CZ38 ensures that at power-down, the critical signals are blocked to prevent  
any damage to the HDMI sink and HDMI source.  
supply off  
5 V  
HDMI source  
HDMI sink  
backdrive current  
2
HDMI ASIC  
I C-bus ASIC  
001aag047  
Fig 13. Backdrive protection  
IP4778CZ38  
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IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
10.7 Application schematic  
Figure 14 shows a typical application where the IP4778CZ38 provides a simplified  
interface to an HDMI port. This application requires only a few external components to  
adapt the HDMI port to the parameters of the HDMI receiver device or HDMI multiplexer.  
V
V
u/c: >3V3 = enabled  
0V = disabled  
CC(5V0)  
CC(3V3)  
BAV40  
100  
kΩ  
1.5  
kΩ  
1.5  
kΩ  
27  
kΩ  
47  
kΩ  
47  
kΩ  
HDMI  
CONNECTOR  
1
2
ENABLE  
37  
TMDS_D2+  
TMDS_D2−  
4
5
35  
34  
TMDS_D2+  
TMDS_D2−  
TMDS_D1+  
TMDS_D1−  
7
8
32  
31  
TMDS_D1+  
TMDS_D1−  
IP4778CZ38  
TMDS_D0+  
TMDS_D0−  
10  
11  
12  
13  
14  
29  
28  
TMDS_D0+  
TMDS_D0−  
TMDS_CLK+  
TMDS_CLK−  
26  
25  
TMDS_CLK+  
TMDS_CLK−  
CEC  
CEC_IN  
DDC_CLK_IN  
DDC_DAT_IN  
16  
17  
18  
19  
23  
22  
21  
20  
DDC_CLK  
DDC_DAT  
HOTPLUG_DET  
HOT_PLUG_DET_IN  
1 kΩ  
3, 6, 9, 12, 15,  
24, 27, 30, 33, 36  
+5 V  
7, 8  
EDID  
1 μF  
100 Ω  
100 Ω  
6
5
1, 2, 3, 4  
001aah830  
Fig 14. Schematic of IP4778CZ38 application  
IP4778CZ38  
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IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
10.8 Typical application  
IP4778CZ38  
V
CC(5V0)  
1
2
3
4
5
6
7
8
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
ENABLE  
V
stand by  
CC(3V3)  
TMDS_D2+  
TMDS_GND  
TMDS_D2−  
TMDS_D1+  
TMDS_GND  
TMDS_D1−  
TMDS_D0+  
TMDS_GND  
TMDS_D0−  
TMDS_CLK+  
TMDS_GND  
TMDS_CLK−  
CEC  
1
TMDS_D2+  
TMDS_D2−  
TMDS_D1+  
TMDS_D1−  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
TMDS_D0+  
TMDS_D0−  
TMDS_CLK+  
TMDS_CLK−  
CEC_IN  
DDC_CLK_IN  
DDC_DAT_IN  
n.c.  
DDC_CLK  
DDC_DAT  
GND  
HOT_PLUG_DET_IN  
+5 V  
HOTPLUG_DET  
19  
HDMI  
connector  
R
R
R
R
CEC  
27 kΩ  
R
R
R
R
HP  
data  
clock  
CEC  
data  
clock  
DDC  
100 Ω 1 kΩ  
1.5 kΩ 1.5 kΩ 100 kΩ  
47 kΩ 47 kΩ  
8
1
7
6
5
4
+3.3 V  
+5.0 V  
EDID  
2
3
001aag049  
Fig 15. Application showing optimized PCB microstrip lines  
This application ensures that the EDID (stored in the EEPROM) can be read out in  
Standby mode, even if long cables are used, to guarantee correct CEC wake-up handling.  
To wake up the system from Standby to normal operation, the HDMI source has to first  
read the EDID in order to hand over the port ID via the CEC protocol. This ensures that  
the HDMI starts up and switches to the correct HDMI port to display the HDMI source  
which initiates the CEC wake-up sequence.  
The CEC bus is enabled by activating the VCC(3V3) standby supply.  
The RF routing optimized pin position variant allows optimum design layout of the RF  
routing microstrips to ensure that the impedance of the TMDS lines remain within the  
specification limits. Part of the microstrips comprise a solid ground plane which is located  
beneath the device.  
IP4778CZ38  
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Product data sheet  
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NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
11. Test information  
V
V
V
CC  
CC(3V3)  
CC(5V0)  
R
L
V
I
V
O
G
DUT  
R
C
L
term  
001aah468  
See Table 10 for test data.  
Rterm = termination resistance should be equal to output impedance Zo of the pulse generator.  
RL = load resistance.  
CL = load capacitance.  
Fig 16. Test circuit for DDC and CEC lines  
Table 10. Test data  
Test  
RL  
CL  
VCC  
DDC lines  
CEC line  
1.35 kΩ  
27 kΩ  
50 pF  
50 pF  
VCC(5V0)  
VCC(3V3)  
IP4778CZ38  
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NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
12. Package outline  
TSSOP38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm;  
lead pitch 0.5 mm  
SOT510-1  
E
H
D
A
X
c
v
M
A
y
E
Z
20  
38  
A
(A )  
3
2
A
A
1
pin 1 index  
θ
L
p
L
1
19  
detail X  
w
M
b
e
p
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions).  
A
(1)  
(2)  
(1)  
Z
UNIT  
A
A
A
b
c
D
E
e
H
L
L
p
v
w
y
θ
1
2
3
p
E
max.  
8o  
0o  
0.15  
0.05  
0.95  
0.85  
0.27  
0.17  
0.20  
0.09  
9.8  
9.6  
4.5  
4.3  
0.7  
0.5  
0.49  
0.21  
mm  
1.1  
0.5  
1
0.2  
0.25  
6.4  
0.08  
0.08  
Notes  
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.  
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
03-02-18  
05-11-02  
SOT510-1  
MO-153  
Fig 17. Package outline SOT510-1 (TSSOP38)  
IP4778CZ38  
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NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
13. Soldering of SMD packages  
This text provides a very brief insight into a complex technology. A more in-depth account  
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow  
soldering description”.  
13.1 Introduction to soldering  
Soldering is one of the most common methods through which packages are attached to  
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both  
the mechanical and the electrical connection. There is no single soldering method that is  
ideal for all IC packages. Wave soldering is often preferred when through-hole and  
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not  
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high  
densities that come with increased miniaturization.  
13.2 Wave and reflow soldering  
Wave soldering is a joining technology in which the joints are made by solder coming from  
a standing wave of liquid solder. The wave soldering process is suitable for the following:  
Through-hole components  
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board  
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless  
packages which have solder lands underneath the body, cannot be wave soldered. Also,  
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,  
due to an increased probability of bridging.  
The reflow soldering process involves applying solder paste to a board, followed by  
component placement and exposure to a temperature profile. Leaded packages,  
packages with solder balls, and leadless packages are all reflow solderable.  
Key characteristics in both wave and reflow soldering are:  
Board specifications, including the board finish, solder masks and vias  
Package footprints, including solder thieves and orientation  
The moisture sensitivity level of the packages  
Package placement  
Inspection and repair  
Lead-free soldering versus SnPb soldering  
13.3 Wave soldering  
Key characteristics in wave soldering are:  
Process issues, such as application of adhesive and flux, clinching of leads, board  
transport, the solder wave parameters, and the time during which components are  
exposed to the wave  
Solder bath specifications, including temperature and impurities  
IP4778CZ38  
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Product data sheet  
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IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
13.4 Reflow soldering  
Key characteristics in reflow soldering are:  
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to  
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus  
reducing the process window  
Solder paste printing issues including smearing, release, and adjusting the process  
window for a mix of large and small components on one board  
Reflow temperature profile; this profile includes preheat, reflow (in which the board is  
heated to the peak temperature) and cooling down. It is imperative that the peak  
temperature is high enough for the solder to make reliable solder joints (a solder paste  
characteristic). In addition, the peak temperature must be low enough that the  
packages and/or boards are not damaged. The peak temperature of the package  
depends on package thickness and volume and is classified in accordance with  
Table 11 and 12  
Table 11. SnPb eutectic process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
235  
350  
220  
< 2.5  
2.5  
220  
220  
Table 12. Lead-free process (from J-STD-020C)  
Package thickness (mm) Package reflow temperature (°C)  
Volume (mm3)  
< 350  
260  
350 to 2000  
> 2000  
260  
< 1.6  
260  
250  
245  
1.6 to 2.5  
> 2.5  
260  
245  
250  
245  
Moisture sensitivity precautions, as indicated on the packing, must be respected at all  
times.  
Studies have shown that small packages reach higher temperatures during reflow  
soldering, see Figure 18.  
IP4778CZ38  
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IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
maximum peak temperature  
= MSL limit, damage level  
temperature  
minimum peak temperature  
= minimum soldering temperature  
peak  
temperature  
time  
001aac844  
MSL: Moisture Sensitivity Level  
Fig 18. Temperature profiles for large and small components  
For further information on temperature profiles, refer to Application Note AN10365  
“Surface mount reflow soldering description”.  
14. Abbreviations  
Table 13. Abbreviations  
Acronym  
CEC  
Description  
Consumer Electronics Control  
Data Display Channel  
DDC  
DVD  
Digital Video Disk  
DVI  
Digital Video Interface  
EDID  
Extended Display Identification Data  
Electrically Erasable Programmable Read-Only Memory  
ElectroStatic Discharge  
EEPROM  
ESD  
FET  
Field-Effect Transistor  
GPIO  
HDMI  
MOSFET  
RoHS  
TMDS  
General Purpose Input/Output  
High-Definition Multimedia Interface  
Metal Oxide Semiconductor Field Effect Transistor  
Restriction of Hazardous Substances  
Transition Minimized Differential Signaling  
15. Glossary  
HDMI sink — Device which receives HDMI signals e.g. a TV set.  
HDMI source — Device which transmit HDMI signal e.g. a DVD player.  
IP4778CZ38  
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Product data sheet  
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IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
16. Revision history  
Table 14. Revision history  
Document ID  
IP4778CZ38 v.3  
Modifications:  
Release date  
20110331  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
IP4778CZ38 v.2  
Section 1 “General description”: updated.  
Section 2 “Features and benefits”: updated.  
Section 14 “Abbreviations”: updated.  
Section 17 “Legal information”: updated.  
IP4778CZ38 v.2  
IP4778CZ38 v.1  
20090212  
Product data sheet  
-
-
IP4778CZ38 v.1  
-
20080410  
Objective data sheet  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
25 of 28  
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
17. Legal information  
17.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
malfunction of an NXP Semiconductors product can reasonably be expected  
17.2 Definitions  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
17.3 Disclaimers  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
26 of 28  
 
 
 
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
Quick reference data — The Quick reference data is an extract of the  
liability, damages or failed product claims resulting from customer design and  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
17.4 Licenses  
Purchase of NXP ICs with HDMI technology  
non-automotive qualified products in automotive equipment or applications.  
Use of an NXP IC with HDMI technology in equipment that complies with  
the HDMI standard requires a license from HDMI Licensing LLC, 1060 E.  
Arques Avenue Suite 100, Sunnyvale CA 94085, USA, e-mail:  
admin@hdmi.org.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
17.5 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
18. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
IP4778CZ38  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2011. All rights reserved.  
Product data sheet  
Rev. 3 — 31 March 2011  
27 of 28  
 
 
 
IP4778CZ38  
NXP Semiconductors  
HDMI ESD protection, DDC buffering and hot plug control  
19. Contents  
1
2
3
4
5
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features and benefits . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 2  
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3  
6
6.1  
6.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
7
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7  
Dynamic characteristics . . . . . . . . . . . . . . . . . 10  
AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . 11  
8
9
9.1  
10  
Application information. . . . . . . . . . . . . . . . . . 12  
TMDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
DDC circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Hot plug driver circuit . . . . . . . . . . . . . . . . . . . 14  
CEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
Multiplexing. . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Backdrive protection. . . . . . . . . . . . . . . . . . . . 17  
Application schematic. . . . . . . . . . . . . . . . . . . 18  
Typical application . . . . . . . . . . . . . . . . . . . . . 19  
10.1  
10.2  
10.3  
10.4  
10.5  
10.6  
10.7  
10.8  
11  
12  
Test information. . . . . . . . . . . . . . . . . . . . . . . . 20  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 21  
13  
Soldering of SMD packages . . . . . . . . . . . . . . 22  
Introduction to soldering . . . . . . . . . . . . . . . . . 22  
Wave and reflow soldering . . . . . . . . . . . . . . . 22  
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 22  
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 23  
13.1  
13.2  
13.3  
13.4  
14  
15  
16  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 25  
17  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 26  
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
17.1  
17.2  
17.3  
17.4  
17.5  
18  
19  
Contact information. . . . . . . . . . . . . . . . . . . . . 27  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2011.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 31 March 2011  
Document identifier: IP4778CZ38  
 

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