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IP4853CX24 [NXP]

SD, MMC and microSD memory card integrated level shifter with PSU, EMI filter and ESD protection; SD ， MMC和microSD记忆卡集成的电平转换器与电源， EMI滤波器和ESD保护
IP4853CX24
型号： IP4853CX24
厂家： NXP    NXP
描述：

SD, MMC and microSD memory card integrated level shifter with PSU, EMI filter and ESD protection
SD ， MMC和microSD记忆卡集成的电平转换器与电源， EMI滤波器和ESD保护

转换器 电平转换器
文件： 总19页 (文件大小：105K)
中文：  中文翻译
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IP4853CX24  
SD, MMC and microSD memory card integrated level shifter  
with PSU, EMI filter and ESD protection  
Rev. 02 — 15 June 2009  
Product data sheet  
1. Product profile  
1.1 General description  
The IP4853CX24 is a device that fully integrates a bidirectional level shifter or voltage  
translator, EMI filter and ESD protection diodes. It is specifically designed to be used for  
memory card interfaces such as SD, microSD and MultiMediaCard (MMC) memory cards.  
The integrated power supply unit supplies memory cards with 2.9 V directly from the  
battery. This enables a 1.8 V operating host-side device (e.g. a processor interface) to  
communicate with a 2.9 V compliant memory card using its integrated level shifter.  
Radiation from digital signals in the higher harmonics, close to typical mobile phone  
frequencies, is suppressed by the EMI filter.  
The IP4853CX24 is fabricated using monolithic silicon technology in a Wafer Level  
Chip-Scale Package (WLCSP) with 0.4 mm pitch.  
1.2 Features  
I Dark Green compliant.  
I Pb-free, RoHS compliant  
I Integrated EMI filters  
I Feedback channel for clock synchronization  
I Integrated ESD protection according to IEC 61000-4-2, level 4  
I WLCSP with 0.4 mm pitch  
1.3 Applications  
I SD memory card, microSD memory card and MMC interfaces in latest electronic  
appliances such as:  
N Mobile phone or smart phone  
N Digital camera  
N Card reader in (laptop) computer  
I Appliances requiring one or several of the following features:  
N Level shifting and voltage translation from 1.8 V to 2.9 V and from 2.9 V to 1.8 V  
N ESD protection according to IEC 61000-4-2, level 4  
N Power supply regulation from battery to 2.9 V card memory voltage  
N EMI filtering  
N Integration of interface-specific biasing resistor network  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
2. Pinning information  
2.1 Pinning  
bump A1  
index area  
IP4853CX24  
1
2
3
4
5
A
B
C
D
E
001aah951  
Transparent top view  
Fig 1.  
Pin configuration for WLCSP24 package  
Table 1.  
Pin allocation table  
Pin Symbol  
Pin Symbol  
Pin Symbol  
Pin Symbol  
Pin Symbol  
A1  
B1  
DATA2_H  
DATA3_H  
A2  
B2  
DIR_CMD  
n.c.  
A3  
B3  
DIR_0  
VCC  
A4  
B4  
VBAT  
VSD  
A5  
B5  
DATA2_SD  
DATA3_SD  
C1 CLK_IN  
C2 ENABLE  
D2 CMD_H  
C3 GND  
D3 CD  
C4 GND  
C5 CLK_SD  
D1 DATA0_H  
D4 CMD_SD  
D5 DATA0_SD  
E1  
DATA1_H  
E2  
CLK_FB  
E3  
DIR_1_3  
E4  
WP  
E5  
DATA1_SD  
2.2 Pin description  
Table 2.  
Symbol[1]  
DATA2_H  
DIR_CMD  
DIR_0  
Pin description  
Pin  
A1  
A2  
A3  
A4  
A5  
B1  
B2  
B3  
B4  
B5  
C1  
Type[2]  
Description  
I/O  
I
data 2 input or output on host-side  
direction control input for command  
direction control input for data 0  
I
VBAT  
S
supply voltage from battery for regulator  
DATA2_SD  
DATA3_H  
n.c.  
I/O  
I/O  
-
data 2 input or output on memory card-side  
data 3 input or output on host-side  
not connected  
VCC  
S
supply voltage for host-side circuits  
output supply voltage for memory card  
data 3 input or output on memory card-side  
clock signal input  
VSD  
O
I/O  
I
DATA3_SD  
CLK_IN  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
2 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
Table 2.  
Pin description …continued  
Symbol[1]  
ENABLE  
GND  
Pin  
C2  
C3  
C4  
C5  
D1  
D2  
D3  
D4  
D5  
E1  
E2  
E3  
E4  
E5  
Type[2]  
Description  
I
device enable input  
S
supply ground  
GND  
S
supply ground  
CLK_SD  
DATA0_H  
CMD_H  
CD  
O
clock signal output on memory card-side  
data 0 input or output on host-side  
command input or output on host-side  
card detect switch biasing output  
command input or output on memory card-side  
data 0 input or output on memory card-side  
data 1 input or output on host-side  
clock feedback output to host  
I/O  
I/O  
O
CMD_SD  
DATA0_SD  
DATA1_H  
CLK_FB  
DIR_1_3  
WP  
I/O  
I/O  
I/O  
O
I
direction control input for data 1, data 2 and data 3  
write protect switch biasing output  
data 1 input or output on memory card-side  
O
DATA1_SD  
I/O  
[1] The pin names relate particularly to SD memory cards, but also apply to microSD and MMC memory cards.  
[2] I = input, O = output, I/O = input and output, S = power supply.  
3. Ordering information  
Table 3.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
IP4853CX24  
WLCSP24 wafer level chip-size package; 24 bumps;  
IP4853CX24  
2.01 × 2.01 × 0.61 mm  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
3 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
4. Block diagram  
host side  
SD card side  
A4  
B4  
C5  
VOLTAGE  
REGULATOR  
V
VSD  
BAT  
R1  
R2  
R3  
R4  
C1  
E2  
CLK_IN  
CLK_FB  
CLK_SD  
A2  
D2  
A3  
D1  
E3  
DIR_CMD  
CMD_H  
DIR_0  
R10  
D4  
D5  
E5  
CMD_SD  
R11  
DATA0_SD  
DATA1_SD  
DATA0_H  
DIR_1_3  
R12  
E1  
A1  
B1  
DATA1_H  
DATA2_H  
DATA3_H  
R13  
R5  
R6  
A5  
B5  
DATA2_SD  
DATA3_SD  
R7  
B3  
C2  
V
CC  
C3, C4  
GND  
ENABLE  
R14  
R15  
E4  
D3  
WP  
CD  
IP4853CX24  
001aah980  
Fig 2. Block diagram  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
4 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
5. Functional description  
5.1 Logic control signals  
Table 4.  
Control signal truth table  
VBAT ≥ 2.7 V.  
Control  
Pin  
Host-side  
Pin  
Memory card-side  
Level[1]  
Function  
Pin  
Function  
Pin ENABLE = HIGH and VCC ≥ 1.62 V  
DIR_CMD  
DIR_0  
H
L
CMD_H  
CMD_H  
DATA0_H  
DATA0_H  
input  
CMD_SD  
CMD_SD  
DATA0_SD  
DATA0_SD  
output  
input  
output  
input  
H
L
output  
input  
output  
input  
DIR_1_3  
H
DATA1_H,  
DATA2_H,  
DATA3_H  
DATA1_SD,  
DATA2_SD,  
DATA3_SD  
output  
L
-
DATA1_H,  
DATA2_H,  
DATA3_H  
output  
output  
DATA1_SD,  
DATA2_SD,  
DATA3_SD  
input  
-
CLK_FB  
CLK_SD  
output  
Pin ENABLE = LOW or VCC ≤ 0.8 V  
DIR_CMD  
DIR_0  
X
X
X
CMD_H  
high-Z  
high-Z  
high-Z  
CMD_SD  
high-Z  
high-Z  
high-Z  
DATA0_H  
DATA0_SD  
DIR_1_3  
DATA1_H,  
DATA2_H,  
DATA3_H  
DATA1_SD,  
DATA2_SD,  
DATA3_SD  
-
-
CLK_FB  
high-Z  
CLK_SD  
high-Z  
[1] H = HIGH; L = LOW and X = don’t care.  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
5 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
6. Limiting values  
Table 5.  
Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).  
Symbol Parameter  
Conditions  
Min  
−0.5  
−0.5  
−0.5  
Max  
+3.5  
+5.5  
+5.0  
Unit  
V
VCC  
supply voltage  
VBAT  
battery supply voltage  
4 ms transient  
operating  
V
V
VI  
input voltage  
at I/O pins  
4 ms transient  
operating  
−0.5  
−0.5  
-
+5.5  
+5.0  
550  
V
V
Ptot  
total power dissipation  
storage temperature  
ambient temperature  
Tamb = −30 °C to +70 °C  
mW  
°C  
°C  
Tstg  
−55  
−30  
+150  
+85  
Tamb  
VESD  
electrostatic discharge  
voltage  
pin VBAT and all memory card-side pins to ground;  
according to IEC 61000-4-2, level 4  
contact  
-
-
-
±8000  
±15000  
±2000  
V
V
V
air discharge  
all other pins to ground; according to IEC 61340-3-1,  
human body model  
7. Recommended operating conditions  
Table 6.  
Operating conditions  
Symbol Parameter  
Conditions  
Min  
1.62  
2.7[1]  
0
Max  
2.1  
5.0  
2.1  
2.9  
Unit  
V
VCC  
VBAT  
VI  
supply voltage  
battery supply voltage  
input voltage  
V
host-side  
V
memory card-side; VBAT ≥ 3.2 V  
active mode; pin ENABLE = HIGH  
host-side  
0
V
VO  
output voltage  
0
0
-
VCC  
V
memory card-side  
VO(reg)  
V
∆t/∆V  
time difference over  
voltage change  
host-side; between 0.2VCC and 0.7VCC  
memory card-side; between 0.2VO(reg) and 0.7VO(reg)  
2
2
ns/V  
ns/V  
-
[1] The device is still fully functional, but the voltage on pin VSD might drop below the recommended memory card supply voltage.  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
6 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
8. Static characteristics  
Table 7.  
Static characteristics  
At recommended operating conditions; Tamb = −30 °C to +85 °C; voltages are referenced to GND (ground = 0 V);  
unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ[1] Max  
Unit  
Voltage regulator output: pin VSD  
VO(reg)  
regulator output voltage  
CL = 1 µF  
IO(reg) = 0 A  
-
2.9  
2.987  
-
V
IO(reg) = 200 mA; VBAT ≥ 2.9 V  
IO(reg) = 200 mA  
2.75  
-
-
-
V
∆Vdo(reg) regulator dropout voltage  
150  
mV  
variation  
IO(reg)  
IO(sc)  
Iq(reg)  
regulator output current  
-
-
-
-
200  
-
mA  
mA  
µA  
short-circuit output current  
-
-
-
500  
200  
2
regulator quiescent current pin ENABLE = HIGH (active mode)  
pin ENABLE = LOW (not active  
mode)  
µA  
Cext  
external capacitance  
recommended capacitor at pin VSD  
-
1.0  
-
µF  
Control and data inputs  
Host-side: pins ENABLE, DIR_0, DIR_1_3, DIR_CMD, CLK_IN and DATA0_H to DATA3_H  
VIH  
VIL  
Cch  
HIGH-level input voltage  
LOW-level input voltage  
channel capacitance  
0.65 × VCC  
-
-
-
-
V
-
-
0.3  
20  
V
[2]  
[2]  
VI = 0 V; fi = 1 MHz  
pF  
Memory card-side: pins CMD_SD and DATA0_SD to DATA3_SD  
VIH  
VIL  
Cch  
HIGH-level input voltage  
LOW-level input voltage  
channel capacitance  
0.65 × VO(reg)  
-
-
-
-
V
-
-
0.3  
20  
V
VI = 0 V; fi = 1 MHz  
pF  
Control and data outputs  
Host-side: pins CLK_FB, CMD_H and DATA0_H to DATA3_H  
VOH  
VOL  
HIGH-level output voltage IO = −3 mA; VI = VIH  
LOW-level output voltage IO = 3 mA; VI = VIL  
V
CC − 0.45  
-
-
-
V
V
-
0.45  
Memory card-side: pins CLK_SD, CMD_SD and DATA0_SD to DATA3_SD, CD and WP  
VOH  
VOL  
ILRzd  
HIGH-level output voltage IO = −6 mA; VI = VIH  
V
O(reg) − 0.45 -  
-
V
LOW-level output voltage  
IO = 6 mA; VI = VIL  
VI = 3 V  
-
-
-
0.45  
100  
V
Zener diode reverse  
leakage current  
-
nA  
Rs  
series resistance  
pull-down resistance  
pull-up resistance  
R1 to R6; tolerance ±20 %  
R7; tolerance ±30 %  
32  
40  
48  
Ω
Rpd  
Rpu  
329  
10.5  
49  
470  
15  
611  
19.5  
91  
kΩ  
kΩ  
kΩ  
kΩ  
R10; tolerance ±30 %  
R11 to R13; tolerance ±30 %  
R14 and R15; tolerance ±30 %  
70  
70  
100  
130  
[1] Typical values are measured at Tamb = 25 °C.  
[2] EMI filter line capacitance per data channel from I/O pin to driver; Cch is guaranteed by design.  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
7 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
9. Dynamic characteristics  
Table 8.  
Voltage regulator  
Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Voltage regulator output: pin VSD  
PSRR  
power supply rejection ratio  
VBAT = 3.0 V; Vripple(p-p) = 223.6 mV  
(0 dBm); Rsource = 50 Ω  
fripple = 1 kHz  
40  
30  
-
-
-
-
-
dB  
dB  
µs  
fripple = 10 kHz  
-
tstartup(reg) regulator start-up time  
VCC = 1.8 V; VBAT = 3.0 V;  
200  
IO(reg) = 200 mA; CL = 1 µF; see Figure 3  
V
I
50 %  
ENABLE  
GND  
t
startup(reg)  
V
O(reg)  
97 %  
regulator  
output  
0 V  
001aah981  
Measuring points: ENABLE signal at 0.5VCC and regulator output signal at 0.97VO(reg)  
.
Fig 3. Regulator start-up time  
Table 9. Frequency response of integrated EMI filters  
Tamb = 25 °C; unless otherwise specified.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Clock, command and data channels[1]  
αil  
insertion loss  
Rsource = 50 Ω; CL = 10 pF; RL = 50 Ω  
fi = 401 MHz to 800 MHz  
9
-
-
-
-
-
dB  
dB  
dB  
fi = 801 MHz to 1.4 GHz  
17  
32  
fi = 1.4 GHz to 6.0 GHz  
-
[1] Guaranteed by design.  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
8 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
Table 10. Output rise and fall times  
VBAT = 3.5 V; VO(reg) = 2.9 V; unless otherwise specified; transition time is the same as output rise time and output fall time;  
see Figure 4 for timing diagram and Figure 5 for test circuit.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Memory card-side outputs: pins CLK_SD, CMD_SD and DATA0_SD to DATA3_SD  
Reference points at 70 % and 20 %  
tt  
transition time  
CL = 20 pF; RL = 100 kΩ  
Tamb = +25 °C; VCC = 1.8 V  
Tamb = −30 °C; VCC = 1.9 V  
Tamb = +70 °C; VCC = 1.62 V  
CL = 40 pF; RL = 100 kΩ  
Tamb = +25 °C; VCC = 1.8 V  
Tamb = −30 °C; VCC = 1.9 V  
Tamb = +70 °C; VCC = 1.62 V  
-
-
-
1.5  
1.5  
1.8  
2.5  
2.5  
2.8  
ns  
ns  
ns  
-
-
-
2.7  
2.7  
2.9  
3.6  
3.6  
3.8  
ns  
ns  
ns  
Reference points at 90 % and 10 %  
tt transition time  
CL = 20 pF; RL = 100 kΩ  
Tamb = +25 °C; VCC = 1.8 V  
Tamb = −30 °C; VCC = 1.9 V  
Tamb = +70 °C; VCC = 1.62 V  
-
-
-
3.0  
2.9  
3.7  
4.2  
4.1  
4.9  
ns  
ns  
ns  
Host-side outputs: pins CLK_FB, CMD_H and DATA0_H to DATA3_H  
Reference points at 70 % and 20 %  
tt  
transition time  
CL = 5 pF; RL = 100 kΩ  
Tamb = +25 °C; VCC = 1.8 V  
Tamb = −30 °C; VCC = 1.9 V  
Tamb = +70 °C; VCC = 1.62 V  
CL = 20 pF; RL = 100 kΩ  
Tamb = +25 °C; VCC = 1.8 V  
Tamb = −30 °C; VCC = 1.9 V  
Tamb = +70 °C; VCC = 1.62 V  
-
-
-
1.5  
1.3  
1.6  
2.4  
2.3  
2.5  
ns  
ns  
ns  
-
-
-
1.7  
1.4  
1.8  
2.9  
2.5  
3.0  
ns  
ns  
ns  
Reference points at 90 % and 10 %  
tt  
transition time  
CL = 5 pF; RL = 100 kΩ  
Tamb = +25 °C; VCC = 1.8 V  
Tamb = −30 °C; VCC = 1.9 V  
Tamb = +70 °C; VCC = 1.62 V  
-
-
-
2.4  
2.3  
2.5  
3.1  
3.0  
3.2  
ns  
ns  
ns  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
9 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
Table 11. Propagation delay of time domain response driver part  
VBAT = 3.5 V; VO(reg) = 2.9 V; Rsource = 50 Ω; propagation delay measurements include PCB delays and connectors;  
see Figure 4 for timing diagram and Figure 5 for test circuit.  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Host-side inputs to memory card-side outputs  
[1]  
[1]  
[1]  
tPD  
propagation delay  
nominal case; Tamb = +27 °C; VCC = 1.8 V  
CL = 20 pF  
6.2  
7.3  
7.0  
8.2  
7.8  
9.1  
ns  
ns  
CL = 40 pF  
best case; Tamb = −30 °C; VCC = 1.9 V  
CL = 20 pF  
5.7  
6.5  
6.5  
7.5  
7.3  
8.5  
ns  
ns  
CL = 40 pF  
worst case; Tamb = +70 °C; VCC = 1.62 V  
CL = 20 pF  
CL = 40 pF  
6.7  
7.5  
7.8  
8.8  
8.9  
ns  
ns  
10.1  
Memory card-side inputs to host-side outputs  
tPD  
propagation delay  
nominal case; Tamb = +27 °C; VCC = 1.8 V  
CL = 5 pF  
4.2  
6.3  
6.0  
7.2  
7.8  
8.1  
ns  
ns  
CL = 20 pF  
best case; Tamb = −30 °C; VCC = 1.9 V  
CL = 5 pF  
4
5.9  
6.7  
6.9  
8.5  
ns  
ns  
CL = 20 pF  
5.1  
worst case; Tamb = +70 °C; VCC = 1.62 V  
CL = 5 pF  
5.4  
6.7  
6.5  
8.0  
7.7  
9.2  
ns  
ns  
CL = 20 pF  
Host-side pins CLK_IN to CLK_FB  
tPD propagation delay  
nominal case; Tamb = +27 °C; VCC = 1.8 V  
CL = 5 pF  
7.6  
8.2  
9.2  
9.9  
10.7  
11.6  
ns  
ns  
CL = 20 pF  
best case; Tamb = −30 °C; VCC = 1.9 V  
CL = 5 pF  
6.7  
7.6  
8.1  
8.8  
9.5  
ns  
ns  
CL = 20 pF  
10.5  
worst case; Tamb = +70 °C; VCC = 1.62 V  
CL = 5 pF  
8.5  
9.1  
10.7  
11.4  
12.9  
13.9  
ns  
ns  
CL = 20 pF  
[1] tPD is the same as HIGH-to-LOW propagation delay (tPHL) and LOW-to-HIGH propagation delay (tPLH).  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
10 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
V
I
V
M
A, B input  
GND  
t
t
PLH  
PHL  
V
OH  
B, A output  
V
M
001aae967  
V
OL  
Measuring points: host-side at 0.5VCC and memory card-side at 0.5VO(reg)  
.
VOL and VOH are typical output voltage levels that occur with the output load.  
Fig 4. Output rise and fall times and data input to output propagation delay times (host-side to card-side or  
card-side to host-side)  
Table 12. Power dissipation per channel  
VCC = 1.8 V; VBAT = 4 V; all values are typical; memory card-side CL = 20 pF and host-side  
CL = 5 pF.  
Frequency (MHz)  
IBAT (mA)  
ICC (mA)  
P (mW)[1]  
Host-side input to memory card-side output  
Data channel  
1.0  
0.79  
3.30  
5.79  
12.3  
0.002  
0.020  
0.037  
0.090  
3.16  
13.3  
23.2  
49.4  
10.0  
20.0  
50.0  
Clock channel  
1.0  
0.44  
3.1  
0.05  
0.59  
0.97  
2.36  
1.85  
13.5  
23.4  
53.1  
10.0  
20.0  
5.4  
50.0  
12.2  
Memory card-side input to host-side output  
Data channel  
1.0  
0.18  
0.42  
0.66  
1.4  
0.1  
0.9  
10.0  
20.0  
50.0  
0.96  
1.91  
4.5  
3.41  
6.1  
13.7  
[1] Power consumption is largely dependent on capacitive load connected to a driver output:  
P = VCC × ICC + VBAT × IBAT  
.
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
11 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
10. Test information  
t
W
V
I
70 %  
negative  
input  
50 %  
20 %  
50 %  
0 V  
t
t
r
f
t
t
f
r
V
I
70 %  
50 %  
positive  
input  
50 %  
20 %  
0 V  
t
W
V
BAT  
V
CC  
V
V
O
I
R
PULSE  
source  
GENERATOR  
DUT  
50 Ω  
t = t = 1.8 ns  
r
f
C
L
R
L
R
term  
001aah982  
Definitions test circuit:  
Rsource = source resistance of pulse generator.  
Rterm = termination resistance should be equal to output impedance Z0 of the pulse generator.  
CL = load capacitance including jig and probe capacitance.  
RL = load resistance.  
Fig 5. Load circuitry for measuring switching time  
11. Marking  
bump A1  
indicator  
LASER MARKING  
AREA  
001aah952  
top view  
Fig 6. Marking of IP4853CX24  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
12 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
12. Package outline  
WLCSP24: wafer level chip-size package; 24 bumps; 2.01 x 2.01 x 0.61 mm  
IP4853CX24  
D
bump A1  
index area  
A
2
E
A
A
1
detail X  
e
1
e
b
E
D
C
B
A
e
e
2
1
2
3
4
5
X
0
1
2 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
UNIT  
A
A
1
A
2
b
D
E
e
e
1
e
2
max 0.66 0.22 0.44 0.29 2.06 2.06  
nom 0.61 0.20 0.41 0.26 2.01 2.01  
mm  
0.4  
1.6  
1.6  
min  
0.56 0.18 0.38 0.23 1.96 1.96  
REFERENCES  
JEDEC JEITA  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
08-04-14  
09-06-11  
IP4853CX24  
Fig 7. Package outline IP4853CX24 (WLCSP24)  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
13 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
13. Packing information  
3° to 8°  
K
B - B  
A
D
1
K
0
P
A
0
5° max  
G
W
B
1
0
W
B
B
F
E
P
D
0
T
1
0.05 / 40  
A
2
P
T
0
A - A  
direction of feed  
001aai051  
Fig 8. Tape and reel information  
Table 13. Tape dimensions  
Description  
Item  
Symbol  
Specification (mm)  
Dimension  
8.00  
1.20  
0.75  
1.50  
1.75  
4.00  
2.00  
3.50  
2.20  
2.20  
0.80  
0.50  
4.00  
20°  
Tolerance  
±0.1  
Overall dimensions  
tape width  
thickness  
distance  
diameter  
distance  
pitch  
W
K
max.  
min.  
G
Sprocket holes[1]  
D0  
E
+0.1  
±0.1  
P0  
P2  
F
±0.1  
Distance between  
center lines  
length direction  
width direction  
length  
±0.05  
±0.05  
±0.05  
±0.05  
±0.05  
+0.1  
Compartments  
A0  
B0  
K0  
D1  
P
width  
depth  
hole diameter  
pitch  
±0.1  
Device  
rotation  
θ
max.  
±0.07  
max.  
max.  
min.  
Carrier tape antistatic[2] film thickness  
Cover tape[3]  
T
0.25  
5.75  
0.1  
width  
W1  
T1  
R
film thickness  
in winding direction  
Bending radius  
30  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
14 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
[1] Cumulated pitch error: ±0.2 mm per 10 pitches.  
[2] Carbon loaded polystyrene 100 % recyclable.  
[3] The cover tape shall not overlap the sprocket holes.  
14. Design and assembly recommendations  
14.1 PCB design guidelines  
To achieve optimum performance it is recommended to use a Non-Solder Mask Design  
(NSMD) PCB design, also known as a copper defined design, incorporating laser-drilled  
micro-vias connecting the ground pads to a buried ground-plane layer. This results in the  
lowest possible ground inductance and provides the best high frequency and ESD  
performance. Refer to Table 14 for the recommended PCB design parameters.  
Table 14. Recommended PCB design parameters  
PCB pad size  
225 µm diameter  
100 µm  
Micro-via diameter  
Solder mask opening  
Copper thickness  
Copper finish  
335 µm diameter  
20 µm to 40 µm  
OSP  
PCB material  
FR4  
14.2 PCB assembly guidelines for Pb-free soldering  
Table 15. Assemble recommendations  
Solder screen aperture size  
Solder screen thickness  
Solder paste: Pb-free  
Solder/flux ratio  
255 µm diameter  
100 µm (0.004")  
SnAg[1]Cu[2]  
50 : 50  
Solder reflow profile  
see Figure 9  
[1] 3 to 4.  
[2] 0.5 to 0.9.  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
15 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
T
(°C)  
T
reflow(peak)  
250  
230  
217  
cooling rate  
pre-heat  
t (s)  
t
t
3
1
t
2
t
t
4
5
001aai161  
The device is capable of withstanding at least three reflows of this profile.  
Fig 9. Pb-free solder reflow profile  
Table 16. Characteristics  
Symbol  
Parameter  
Conditions  
Min  
230  
60  
Typ  
Max Unit  
Treflow(peak) peak reflow temperature ∆T = 0 °C to +5 °C  
-
-
-
255  
180  
300  
°C  
s
t1  
t2  
time 1  
time 2  
soak time  
time from T = 25 °C to  
240  
s
Treflow(peak)  
t3  
time 3  
time 4  
time 5  
time during T ≥ 250 °C  
time during T ≥ 230 °C  
time during T > 217 °C  
cooling rate  
-
-
-
-
-
-
30  
s
t4  
10  
30  
-
50  
s
t5  
150  
−6  
s
dT/dt  
rate of change of  
temperature  
°C/s  
°C/s  
pre-heat  
2.5  
4.0  
15. Abbreviations  
Table 17. Abbreviations  
Acronym  
DUT  
Description  
Device Under Test  
EMI  
ElectroMagnetic Interference  
ElectroStatic Discharge  
Flame Retard 4  
ESD  
FR4  
MMC  
NSMD  
OSP  
MultiMediaCard  
Non-Solder Mask Design  
Organic Solderability Preservation  
Printed-Circuit Board  
Power Supply Unit  
PCB  
PSU  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
16 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
Table 17. Abbreviations …continued  
Acronym Description  
RoHS  
SD  
Restriction of Hazardous Substances  
Secure Digital  
WLCSP  
Wafer Level Chip-Scale Package  
16. Revision history  
Table 18. Revision history  
Document ID  
IP4853CX24_2  
Modifications:  
Release date  
20090615  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
IP4853CX24_1  
• Table 11: Added minimum values and values for ‘host-side pins CLK_IN to CLK_FB’.  
• Table 7: Changed maximum value for regulator quiescent current (not active mode).  
• Table 8: Moved values from maximum to minimum for power supply rejection ratio.  
• Removed /LF from all instances of type number IP4853CX24.  
IP4853CX24_1  
20080722  
Product data sheet  
-
-
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
17 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
17. Legal information  
17.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
17.2 Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
17.3 Disclaimers  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
17.4 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
18. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
IP4853CX24_2  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
Rev. 02 — 15 June 2009  
18 of 19  
IP4853CX24  
NXP Semiconductors  
SD, MMC and microSD memory card integrated level shifter  
19. Contents  
1
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
General description. . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
1.1  
1.2  
1.3  
2
2.1  
2.2  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 2  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2  
3
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Functional description . . . . . . . . . . . . . . . . . . . 5  
Logic control signals . . . . . . . . . . . . . . . . . . . . . 5  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Recommended operating conditions. . . . . . . . 6  
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7  
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8  
Test information. . . . . . . . . . . . . . . . . . . . . . . . 12  
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13  
Packing information. . . . . . . . . . . . . . . . . . . . . 14  
4
5
5.1  
6
7
8
9
10  
11  
12  
13  
14  
14.1  
14.2  
Design and assembly recommendations . . . 15  
PCB design guidelines . . . . . . . . . . . . . . . . . . 15  
PCB assembly guidelines for Pb-free  
soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15  
15  
16  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17  
17  
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18  
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
17.1  
17.2  
17.3  
17.4  
18  
19  
Contact information. . . . . . . . . . . . . . . . . . . . . 18  
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2009.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 15 June 2009  
Document identifier: IP4853CX24_2  

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