IRF840 [NXP]

PowerMOS transistor Avalanche energy rated; 功率MOS晶体管额定雪崩能量


型号：	IRF840
厂家：	NXP
描述：	PowerMOS transistor Avalanche energy rated 功率MOS晶体管额定雪崩能量晶体晶体管
文件：	总7页 (文件大小：62K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Philips Semiconductors

Product specification

PowerMOS transistor

Avalanche energy rated

IRF840

FEATURES

SYMBOL

QUICK REFERENCE DATA

• Repetitive Avalanche Rated

• Fast switching

V_DSS= 500 V

I_D= 8.5 A

• High thermal cycling performance

• Low thermal resistance

R_DS(ON)≤ 0.85 Ω

GENERAL DESCRIPTION

PINNING

SOT78 (TO220AB)

N-channel, enhancement mode

DESCRIPTION

tab

field-effect

power

transistor,

intended for use in off-line switched

mode power supplies, T.V. and

computer monitor power supplies,

d.c.tod.c. converters, motorcontrol

circuits and general purpose

switching applications.

gate

drain

source

drain

tab

1 2 3

The IRF840 is supplied in the

SOT78 (TO220AB) conventional

leaded package.

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V_DSS

V_DGR

V_GS

I_D

Drain-source voltage

T_j= 25 ˚C to 150˚C

500

± 30

8.5

Drain-gate voltage

T_j= 25 ˚C to 150˚C; R_GS= 20 kΩ

Gate-source voltage

Continuous drain current

T_mb= 25 ˚C; V_GS= 10 V

T_mb= 100 ˚C; V_GS= 10 V

T_mb= 25 ˚C

5.4

I_DM

P_D

T_j, T_stg

Pulsed drain current

Total dissipation

Operating junction and

storage temperature range

147

150

T_mb= 25 ˚C

˚C

- 55

AVALANCHE ENERGY LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

E_AS

Non-repetitive avalanche

energy

Unclamped inductive load, I_AS= 7.4 A;

t_p= 0.22 ms; T_jprior to avalanche = 25˚C;

531

_DD≤ 50 V; R_GS= 50 Ω; V_GS= 10 V; refer

to fig:17

E_AR

Repetitive avalanche energy¹I_AR= 8.5 A; t_p= 2.5 µs; T_jprior to

avalanche = 25˚C; R_GS= 50 Ω; V_GS= 10 V;

refer to fig:18

Repetitive and non-repetitive

avalanche current

I_AS, I_AR

8.5

1 pulse width and repetition rate limited by T_jmax.

March 1999

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

Avalanche energy rated

IRF840

THERMAL RESISTANCES

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

R_{th j-mb}

R_{th j-a}

Thermal resistance junction

to mounting base

Thermal resistance junction in free air

to ambient

0.85 K/W

K/W

ELECTRICAL CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

V_(BR)DSSDrain-source breakdown

CONDITIONS

MIN. TYP. MAX. UNIT

V_GS= 0 V; I_D= 0.25 mA

V_DS= V_GS; I_D= 0.25 mA

500

voltage

∆V_(BR)DSS/ Drain-source breakdown

0.1

%/K

∆T_j

voltage temperature

coefficient

R_DS(ON)

V_GS(TO)

g_fs

Drain-source on resistance

Gate threshold voltage

Forward transconductance

V_GS= 10 V; I_D= 4.8 A

V_DS= V_GS; I_D= 0.25 mA

V_DS= 30 V; I_D= 4.8 A

2.0

3.5

0.6

3.0

0.85

4.0

Ω

I_DSS

Drain-source leakage current V_DS= 500 V; V_GS= 0 V

µA

V_DS= 400 V; V_GS= 0 V; T_j= 125 ˚C

250

200

I_GSS

Gate-source leakage current V_GS= ±30 V; V_DS= 0 V

Q_g(tot)

Q_gs

Q_gd

Total gate charge

Gate-source charge

Gate-drain (Miller) charge

I_D= 8.5 A; V_DD= 400 V; V_GS= 10 V

5.5

t_d(on)

t_r

t_d(off)

t_f

Turn-on delay time

Turn-on rise time

Turn-off delay time

Turn-off fall time

V_DD= 250 V; R_D= 30 Ω;

R_G= 9.1 Ω

L_d

L_s

Internal drain inductance

Internal source inductance

Measured from tab to centre of die

Measured from drain lead to centre of die

Measured from source lead to source

bond pad

3.5

4.5

7.5

C_iss

C_oss

C_rss

Input capacitance

Output capacitance

Feedback capacitance

V_GS= 0 V; V_DS= 25 V; f = 1 MHz

960

140

SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS

T_j= 25 ˚C unless otherwise specified

SYMBOL PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

I_S

Continuous source current

(body diode)

T_mb= 25˚C

8.5

I_SM

Pulsed source current (body T_mb= 25˚C

diode)

V_SD

Diode forward voltage

I_S= 8.5 A; V_GS= 0 V

1.2

t_rr

Q_rr

Reverse recovery time

Reverse recovery charge

I_S= 8.5 A; V_GS= 0 V; dI/dt = 100 A/µs

440

6.4

µC

March 1999

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

Avalanche energy rated

IRF840

Normalised Power Derating

PD%

PHP6N60

Zth j-mb, Transient thermal impedance (K/W)

D = 0.5

120

110

100

0.1

0.2

0.1

0.05

0.02

0.01

0.001

t_p

D =

single pulse

10us

1us

100us

1ms

10ms

100ms

Tmb /

100

120

140

tp, pulse width (s)

Fig.1. Normalised power dissipation.

PD% = 100 P_D/P_{D 25 ˚C}= f(T_mb)

Fig.4. Transient thermal impedance.

Z_{th j-mb}= f(t); parameter D = t_p/T

Normalised Current Derating

ID%

PHP8N50

10 V

ID, Drain current (Amps)

Tj = 25 C

120

110

100

7 V

6.5 V

6 V

5.5 V

5 V

VGS = 4.5 V

Tmb /

100

120

140

25 30

VDS, Drain-Source voltage (Volts)

Fig.2. Normalised continuous drain current.

ID% = 100 I_D/I_{D 25 ˚C}= f(T_mb); conditions: V_GS≥ 10 V

Fig.5. Typical output characteristics.

I_D= f(V_DS); parameter V_GS

ID / A

PHP8N50

Tj = 25 C

BUK457-500B

RDS(on), Drain-Source on resistance (Ohms)

100

4.5 V

5 V

5.5 V

VGS = 6 V

1.5

tp = 10 us

6.5 V

7 V

RDS(ON) = VDS/ID

100 us

1 ms

10 V

10 ms

0.5

100 ms

0.1

100

VDS / V

1000

ID, Drain current (Amps)

Fig.3. Safe operating area. T_mb= 25 ˚C

I_D& I_DM= f(V_DS); I_DMsingle pulse; parameter t_p

Fig.6. Typical on-state resistance.

R_DS(ON)= f(I_D); parameter V_GS

March 1999

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

Avalanche energy rated

IRF840

VGS(TO) / V

ID, Drain current (Amps)

PHP8N50

max.

VDS > ID x RDS(on)max

typ.

min.

Tj = 150 C

Tj = 25 C

-60 -40 -20

Tj /

80 100 120 140

VGS, Gate-Source voltage (Volts)

Fig.7. Typical transfer characteristics.

I_D= f(V_GS); parameter T_j

Fig.10. Gate threshold voltage.

V_GS(TO)= f(T_j); conditions: I_D= 0.25 mA; V_DS= V_GS

SUB-THRESHOLD CONDUCTION

ID / A

gfs, Transconductance (S)

PHP8N50

1E-01

1E-02

1E-03

1E-04

1E-05

1E-06

VDS > ID x RDS(on)max

Tj = 25 C

150 C

2 %

typ

98 %

ID, Drain current (A)

VGS / V

Fig.8. Typical transconductance.

g_fs= f(I_D); parameter T_j

Fig.11. Sub-threshold drain current.

I_D= f(V_GS); conditions: T_j= 25 ˚C; V_DS= V_GS

Normalised RDS(ON) = f(Tj)

PHP8N50

Junction capacitances (pF)

10000

1000

100

Ciss

Coss

Crss

-60 -40 -20

20 40 60 80 100 120 140

Tj /

100

1000

VDS, Drain-Source voltage (Volts)

Fig.9. Normalised drain-source on-state resistance.

a = R_DS(ON)/R_{DS(ON)25 ˚C}= f(T_j); I_D= 4.25 A; V_GS= 10 V

Fig.12. Typical capacitances, C_iss, C_oss, C_rss.

C = f(V_DS); conditions: V_GS= 0 V; f = 1 MHz

March 1999

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

Avalanche energy rated

IRF840

PHP8N50

IF, Source-Drain diode current (Amps)

VGS = 0 V

PHP8N50E

Gate-source voltage, VGS (V)

14 ID = 8.5A

200V

Tj = 25 C

100V

VDD = 400 V

150 C

Tj = 25 C

Gate charge, QG (nC)

0.2

0.4

0.6

0.8

1.2

1.4

VSDS, Source-Drain voltage (Volts)

Fig.13. Typical turn-on gate-charge characteristics.

V_GS= f(Q_G); parameter V_DS

Fig.16. Source-Drain diode characteristic.

I_F= f(V_SDS); parameter T_j

Switching times (ns)

PHP8N50

1000

100

VDD = 250 V

VGS = 10 V

RD = 30 Ohms

Non-repetitive Avalanche current, IAS (A)

25 C

Tj = 25 C

Tj prior to avalanche = 125 C

td(off)

VDS

PHP8N50E

td(on)

0.1

1E-06

1E-05

1E-04

1E-03

1E-02

Avalanche time, tp (s)

RG, Gate resistance (Ohms)

Fig.14. Typical switching times; t_d(on), t_r, t_d(off), t_f= f(R_G)

Fig.17. Maximum permissible non-repetitive

avalanche current (I_AS) versus avalanche time (t_p);

unclamped inductive load

Normalised Drain-source breakdown voltage

V(BR)DSS @ Tj

1.15

Maximum Repetitive Avalanche Current, IAR (A)

V(BR)DSS @ 25 C

1.1

Tj prior to avalanche = 25 C

1.05

125 C

0.1

0.95

0.9

PHP8N50E

1E-03 1E-02

0.01

1E-06

1E-05

1E-04

Avalanche time, tp (s)

0.85

-100

-50

100

150

Tj, Junction temperature (C)

Fig.15. Normalised drain-source breakdown voltage;

V_(BR)DSS/V_{(BR)DSS 25 ˚C}= f(T_j)

Fig.18. Maximum permissible repetitive avalanche

current (I_AR) versus avalanche time (t_p)

March 1999

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

Avalanche energy rated

IRF840

MECHANICAL DATA

Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220

SOT78

(1)

10 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

UNIT

max.

4.5

4.1

1.39

1.27

0.9

0.7

1.3

1.0

0.7

0.4

15.8

15.2

6.4

5.9

10.3

9.7

15.0

13.5

3.30

2.79

3.8

3.6

3.0

2.7

2.6

2.2

3.0

2.54

Note

1. Terminals in this zone are not tinned.

REFERENCES

EUROPEAN

PROJECTION

OUTLINE

VERSION

ISSUE DATE

IEC

JEDEC

EIAJ

97-06-11

SOT78

TO-220

Fig.19. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)

Notes

1. This product is supplied in anti-static packaging. The gate-source input must be protected against static

discharge during transport or handling.

2. Refer to mounting instructions for SOT78 (TO220AB) package.

3. Epoxy meets UL94 V0 at 1/8".

March 1999

Rev 1.000

Philips Semiconductors

Product specification

PowerMOS transistor

Avalanche energy rated

IRF840

DEFINITIONS

Data sheet status

Objective specification

This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification

This data sheet contains final product specifications.

Limiting values

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and

operation of the device at these or at any other conditions above those given in the Characteristics sections of

this specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Philips Electronics N.V. 1999

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the

The information presented in this document does not form part of any quotation or contract, it is believed to be

accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any

consequence of its use. Publication thereof does not convey nor imply any license under patent or other

industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these

products can be reasonably expected to result in personal injury. Philips customers using or selling these products

for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting

from such improper use or sale.

March 1999

Rev 1.000

IRF840 [NXP]

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