ISP1106W_技术文档

ISP1105/1106/1107

Advanced Universal Serial Bus transceivers

Rev. 06 — 30 November 2001

Product data

1. General description

The ISP1105/1106/1107 range of Universal Serial Bus (USB) transceivers are fully

compliant with the Universal Serial Bus Speciﬁcation Rev. 1.1. They are ideal for

portable electronics devices such as mobile phones, digital still cameras, Personal

Digital Assistants (PDA) and Information Appliances (IA).

They allow USB Application Speciﬁc ICs (ASICs) and Programmable Logic Devices

(PLDs) with power supply voltages from 1.65 V to 3.6 V to interface with the physical

layer of the Universal Serial Bus. They have an integrated 5 V to 3.3 V voltage

regulator for direct powering via the USB supply V_BUS

.

The ISP1105/1106/1107 range can be used as a USB device transceiver or a USB

host transceiver. They can transmit and receive serial data at both full-speed

(12 Mbit/s) and low-speed (1.5 Mbit/s) data rates.

ISP1105 allows single/differential input modes selectable by a MODE input and it is

available in HBCC16 package. ISP1106 allows only differential input mode and is

available in both TSSOP16 and HBCC16 packages. ISP1107 allows only

single-ended input mode and is available in both TSSOP16 and HBCC16 packages.

2. Features

■ Complies with Universal Serial Bus Speciﬁcation Rev. 1.1

■ Integrated bypassable 5 V to 3.3 V voltage regulator for powering via USB V_BUS

■ V_BUSdisconnection indication through VP and VM

■ Used as a USB device transceiver or a USB host transceiver

■ Supports full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) serial data rates

■ Stable RCV output during SE0 condition

■ Two single-ended receivers with hysteresis

■ Low-power operation

■ Supports an I/O voltage range from 1.65 V to 3.6 V

■ 4 kV on-chip ESD protection

■ Full industrial operating temperature range −40 to +85 °C

■ Available in small TSSOP16 (except ISP1105) and HBCC16 packages.

ISP1105/1106/1107

Philips Semiconductors

Advanced USB transceivers

3. Applications

■ Portable electronic devices, such as:

◆ Mobile phone

◆ Digital still camera

◆ Personal Digital Assistant (PDA)

◆ Information Appliance (IA).

4. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

ISP1105W^[1]

ISP1106W

ISP1107W

HBCC16

plastic, heatsink bottom chip carrier; 16 terminals; body 3 × 3 × 0.65 mm

SOT639-2

ISP1106DH

ISP1107DH

TSSOP16

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

[1] The ground terminal of ISP1105W is connected to the exposed diepad (heatsink).

4.1 Ordering options

Table 2:

Product

ISP1105

ISP1106

ISP1107

Selection guide

Package(s)

Description

HBCC16

Supports both single-ended and differential input modes^[1]

Supports only the differential input mode^[2]

Supports only the single-ended input mode^[3]

TSSOP16 or HBCC16

[1] Refer to Table 5 and Table 6.

[2] Refer to Table 6.

[3] Refer to Table 5.

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Advanced USB transceivers

5. Functional diagram

3.3 V

VOLTAGE

REGULATOR

V

CC(5.0)

reg(3.3)

CC(I/O)

V

pu(3.3)

SOFTCON

OE

(2)

1.5 kΩ

(1)

33 Ω (1%)

D+

D−

SPEED

(3)

VMO/FSE0

(3)

(1)

VPO/VO

33 Ω (1%)

(4)

MODE

LEVEL

SHIFTER

SUSPND

RCV

ISP1105

ISP1106

ISP1107

VP

VM

MBL301

GND

(1) Use a 39 Ω resistor (1%) for a USB v2.0 compliant output impedance range.

(2) Connect to D− for low-speed operation.

(3) Pin function depends on device type see Section 7.2.

(4) Only for ISP1105.

Fig 1. Functional diagram (combined ISP1105, ISP1106 and ISP1107).

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ISP1105/1106/1107

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Advanced USB transceivers

6. Pinning information

6.1 Pinning

6

7

8

6

7

8

D−

SUSPND

5

9

5

9

D+

VM

VP

4

3

2

10

11

12

VM

VP

4

3

2

10

11

12

ISP1105W

ISP1106W

VPO/VO

VMO/FSE0

VPO/VO*

VMO/FSE0*

ISP1107W*

GND

(exposed diepad)

RCV

V

13

1

16

15

14

reg(3.3)

16

15

14

reg(3.3)

OE

Bottom view

MBL303

Bottom view

MBL304

The asterisk (*) denotes that the signal names VO and

FSE0 apply to the ISP1107W.

Fig 2. Pinning diagram HBCC16 (ISP1105).

Fig 3. Pinning diagram HBCC16 (ISP1106 and

ISP1107).

V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CC(5.0)

reg(3.3)

pu(3.3)

SOFTCON

OE

VMO/FSE0*

VPO/VO*

D+

RCV

ISP1106DH

ISP1107DH*

VP

VM

D−

SUSPND

GND

SPEED

V

CC(I/O)

MBL302

The asterisk (*) denotes that the signal names VO and FSE0 apply to the ISP1107DH.

Fig 4. Pinning diagram TSSOP16 (ISP1106 and ISP1107).

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Advanced USB transceivers

6.2 Pin description

Table 3:

Pin description

Symbol^[1]

Type

Description

ISP1105

HBCC16

ISP1106/7 ISP1106/7

HBCC16

TSSOP16

OE

1

3

I

input for output enable (CMOS level with respect to V_CC(I/O),

active LOW); enables the transceiver to transmit data on

the USB bus

RCV

2

3

4

5

O

differential data receiver output (CMOS level with respect to

V_CC(I/O)); driven LOW when input SUSPND is HIGH; the

output state of RCV is preserved and stable during an SE0

condition

VP

3

4

O

single-ended D+ receiver output (CMOS level with respect

to V_CC(I/O)); for external detection of single-ended zero

(SE0), error conditions, speed of connected device; driven

HIGH when no supply voltage is connected to V_CC(5.0)and

V_reg(3.3)

VM

4

5

6

7

single-ended D− receiver output (CMOS level with respect

to V_CC(I/O)); for external detection of single-ended zero

(SE0), error conditions, speed of connected device; driven

HIGH when no supply voltage is connected to V_CC(5.0)and

V_reg(3.3)

SUSPND

MODE

5

6

I

suspend input (CMOS level with respect to V_CC(I/O)); a

HIGH level enables low-power state while the USB bus is

inactive and drives output RCV to a LOW level

mode input (CMOS level with respect to V_CC(I/O)); a HIGH

level enables the differential input mode (VPO, VMO)

whereas a LOW level enables a single-ended input mode

(VO, FSE0). see Table 5 and Table 6

[2]

GND

-

6

7

8

9

-

ground supply

V_CC(I/O)

7

supply voltage for digital I/O pins (1.65 to 3.6 V). When

V_CC(I/O)is not connected, the (D+, D−) pins are in

three-state. This supply pin is totally independent of

V_CC(5.0)and V_reg(3.3)and must never exceed the V_reg(3.3)

voltage.

SPEED

8

10

I

speed selection input (CMOS level with respect to V_CC(I/O));

adjusts the slew rate of differential data outputs D+ and D−

according to the transmission speed:

LOW: low-speed (1.5 Mbit/s)

HIGH: full-speed (12 Mbit/s)

D−

9

11

12

13

14

AI/O

negative USB data bus connection (analog, differential); for

low-speed mode connect to pin V_pu(3.3)via a 1.5 kΩ resistor

D+

10

11

10

11

12

AI/O

positive USB data bus connection (analog, differential); for

full-speed mode connect to pin V_pu(3.3)via a 1.5 kΩ resistor

VPO/VO

I

driver data input (CMOS level with respect to V_CC(I/O)

Schmitt trigger); see Table 5 and Table 6

,

VMO/FSE0 12

driver data input (CMOS level with respect to V_CC(I/O)

Schmitt trigger); see Table 5 and Table 6

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Advanced USB transceivers

Table 3:

Pin description…continued

Symbol^[1]

Type

Description

ISP1105

HBCC16

ISP1106/7 ISP1106/7

HBCC16

TSSOP16

V_reg(3.3)

13

15

-

Internal regulator option: regulated supply voltage output

(3.0 to 3.6 V) during 5 V operation; a decoupling capacitor

of at least 0.1 µF is required

Regulator bypass option: used as a supply voltage input

for 3.3 V operation. (3.3 V ±10%)

V_CC(5.0)

14

15

14

15

16

1

-

Internal regulator option: supply voltage input

(4.0 to 5.5 V); can be connected directly to USB supply

V_BUS

Regulator bypass option: connect to V_reg(3.3)

V_pu(3.3)

pull-up supply voltage (3.3 V ±10%); connect an external

1.5 kΩ resistor on D+ (full-speed) or D− (low-speed); pin

function is controlled by input SOFTCON:

SOFTCON = LOW — V_pu(3.3)ﬂoating (high impedance);

ensures zero pull-up current

SOFTCON = HIGH — V_pu(3.3)= 3.3 V; internally connected

to V_reg(3.3)

SOFTCON 16

16

2

I

software controlled USB connection input; a HIGH level

applies 3.3 V to pin V_pu(3.3), which is connected to an

external 1.5 kΩ pull-up resistor; this allows USB

connect/disconnect signalling to be controlled by software

[1] Symbol names with an overscore (e.g. NAME) indicate active LOW signals.

[2] Down bonded to the exposed diepad.

7. Functional description

7.1 Function selection

Table 4:

SUSPND

L

Function table

OE

(D+, D−)

RCV

VP/VM

Function

L

driving &

receiving

active

normal driving

(differential receiver active)

L

H

L

receiving^[1]

active

inactive^[2]

active

receiving

driving during ‘suspend’^[3]

H

driving

(differential receiver inactive)

H

high-Z^[1]

inactive^[2]

active

low-power state

[1] Signal levels on (D+, D−) are determined by other USB devices and external pull-up/down resistors.

[2] In ‘suspend’ mode (SUSPND = HIGH) the differential receiver is inactive and output RCV is always

LOW. Out-of-suspend (‘K’) signalling is detected via the single-ended receivers VP and VM.

[3] During suspend, the slew-rate control circuit of low-speed operation is disabled. The (D+, D−) lines

are still driven to their intended states, without slew-rate control. This is permitted because driving

during suspend is used to signal remote wake-up by driving a ‘K’ signal (one transition from idle to

‘K’ state) for a period of 1 to 15 ms.

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ISP1105/1106/1107

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Advanced USB transceivers

7.2 Operating functions

Table 5:

Driving function using single-ended input data interface (OE = L) [for

ISP1107 and ISP1105 (MODE = L)]

FSE0

VO

L

Data

differential logic 0

differential logic 1

SE0

L

H

L

H

SE0

Table 6:

Driving function using differential input data interface (OE = L) [for ISP1106

and ISP1105 (MODE = H)]

VMO

VPO

L

Data

L

SE0

H

differential logic 1

differential logic 0

illegal state

H

L

H

Table 7:

Receiving function (OE = H)

(D+, D−)

RCV

VP^[1]

VM^[1]

differential logic 0

differential logic 1

SE0

L

H

L

H

L

H

RCV*^[2]

[1] VP = VM = H indicates the sharing mode (V_CC(5.0)/V_reg(3.3)is disconnected).

[2] RCV* denotes the signal level on output RCV just before SE0 state occurs. This level is stable during

the SE0 period.

7.3 Power supply conﬁgurations

The ISP1105/1106/1107 can be used with different power supply conﬁgurations,

which can be changed dynamically. An overview is given in Table 9.

Normal mode — Both V_CC(I/O)and V_CC(5.0)or (V_CC(5.0)and V_reg(3.3)) are connected.

For 5 V operation, V_CC(5.0)is connected to a 5 V source (4.0 to 5.5 V). The internal

voltage regulator then produces 3.3 V for the USB connections. For 3.3 V operation,

both V_CC(5.0)and V_reg(3.3)are connected to a 3.3 V source (3.0 to 3.6 V). V_CC(I/O)is

independently connected to a voltage source (1.65 V to 3.6 V), depending on the

supply voltage of the external circuit.

Disable mode — V_CC(I/O)is not connected, V_CC(5.0)or (V_CC(5.0)and V_reg(3.3)) are

connected. In this mode, the internal circuits of the ISP1105/1106/1107 ensure that

the (D+, D−) pins are in three-state and the power consumption drops to the

low-power (suspended) state level. Some hysteresis is built into the detection of

V_CC(I/O)lost.

Sharing mode — V_CC(I/O)is connected, (V_CC(5.0)and V_reg(3.3)) are not connected. In

this mode, the (D+, D−) pins are made three-state and the ISP1105/1106/1107 allows

external signals of up to 3.6 V to share the (D+, D−) lines. The internal circuits of the

ISP1105/1106/1107 ensure that virtually no current (maximum 10 µA) is drawn via

the (D+, D−) lines. The power consumption through pin V_CC(I/O)drops to the

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ISP1105/1106/1107

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Advanced USB transceivers

low-power (suspended) state level. Both the VP and VM pins are driven HIGH to

indicate this mode. Pin RCV is made LOW. Some hysteresis is built into the detection

of V_reg(3.3)lost.

Table 8:

Pins

Pin states in Disable or Sharing mode

Disable mode state

Sharing mode state

V_CC(5.0)/V_reg(3.3)

5 V input / 3.3 V output

3.3 V input / 3.3 V input

not present

V_CC(I/O)

V_pu(3.3)

(D+, D−)

(VP, VM)

RCV

not present

high impedance (off)

high impedance

invalid^[1]

1.65 V to 3.6 V input

high impedance (off)

high impedance

H

invalid^[1]

L

Inputs (VO/VPO, FSE0/VMO,

SPEED, MODE^[2], SUSPND, OE,

SOFTCON)

high impedance

[1] High impedance or driven LOW.

[2] ISP1105 only.

Table 9:

Power supply conﬁguration overview

V_CC(5.0)or

V_reg(3.3)

V_CC(I/O)

Conﬁguration

Special characteristics

connected

Normal mode

Disable mode

-

not connected

(D+, D−) and V_pu(3.3)high

impedance; VP, VM, RCV:

invalid^[1]

not connected

connected

Sharing mode

(D+, D−) and V_pu(3.3)high

impedance;

VP, VM driven HIGH;

RCV driven LOW

[1] High impedance or driven LOW.

7.4 Power supply input options

The ISP1105/1106/1107 range has two power supply input options:

Internal regulator — V_CC(5.0)is connected to 4.0 to 5.5 V. The internal regulator is

used to supply the internal circuitry with 3.3 V (nominal). The V_reg(3.3)pin becomes a

3.3 V output reference.

Regulator bypass — V_CC(5.0)and V_reg(3.3)are connected to the same supply. The

internal regulator is bypassed and the internal circuitry is supplied directly from the

V_reg(3.3)power supply. The voltage range is 3.0 to 3.6 V to comply with the USB

speciﬁcation.

The supply voltage range for each input option is speciﬁed in Table 10.

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ISP1105/1106/1107

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Advanced USB transceivers

Table 10: Power supply input options

Input option

V_CC(5.0)

V_reg(3.3)

V_CC(I/O)

Internal

regulator

supply input for internal voltage reference

supply input for digital

I/O pins

regulator

output

(4.0 to 5.5 V)

(3.3 V, 300 µA)

(1.65 V to 3.6 V)

Regulator

bypass

connected to V_reg(3.3)

with maximum voltage (3.0 V to 3.6 V)

drop of 0.3 V

supply input

supply input for digital

I/O pins

(1.65 V to 3.6 V)

(2.7 to 3.6 V)

8. Limiting values

Table 11: Absolute maximum ratings

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC(5.0)

V_CC(I/O)

V_reg(3.3)

V_I

Parameter

Conditions

Min

−0.5

-

Max

Unit

V

supply voltage

+6.0

I/O supply voltage

regulated supply voltage

DC input voltage

+4.6

V

+4.6

V

V_CC(I/O)+ 0.5

100

V

I_latchup

V_esd

latch-up current

electrostatic discharge voltage^[1]

V_I= −1.8 to 5.4 V

I_LI< 1 µA

mA

pins D+, D−, V_CC(5.0)

,

-

±4000

V

V_reg(3.3), GND

other pins

-

±2000

+125

V

T_stg

storage temperature

−40

°C

[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor (Human Body Model). Refer to EIA/JEDEC Standard speciﬁcation

EIA/JESD22-A114-A.

Table 12: Recommended operating conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_CC(5.0)

supply voltage (Internal

regulator option)

5 V operation

4.0

5.0

5.5

V

V_reg(3.3)

supply voltage (Regulator

bypass option)

3.3 V operation

3.0

3.3

3.6

V

V_CC(I/O)

V_I

I/O supply voltage

input voltage

1.65

0

-

3.6

V

V_CC(I/O)

3.6

V_I(AI/O)

input voltage on analog I/O

0

pins (D+/D−)

T_amb

operating ambient temperature

−40

-

+85

°C

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ISP1105/1106/1107

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Advanced USB transceivers

9. Static characteristics

Table 13: Static characteristics: supply pins

V_CC= 4.0 to 5.5 V or V_reg(3.3)= 3.0 to 3.6 V; V_CC(I/O)= 1.65 to 3.6 V; V_GND= 0 V; see Table 10 for valid voltage level

combinations; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

V_reg(3.3)

regulated supply voltage

output

Internal regulator option;

3.0^[2]

3.3

3.6

V

I_load≤ 300 µA

I_CC

operating supply current

full-speed transmitting and receiving

at 12 Mbit/s; C_L= 50 pF on D+/D−

-

4

1

-

8^[3]

2^[3]

500

mA

µA

I_CC(I/O)

I_CC(idle)

operating I/O supply current full-speed transmitting and receiving

at 12 Mbit/s

[4]

supply current during

full-speed idle and SE0

full-speed idle: V_D+> 2.7 V,

V_D−< 0.3 V; SE0: V_D+< 0.3 V,

V_D−< 0.3 V

I_{CC(I/O)(static)}

I_CC(susp)

static I/O supply current

suspend supply current

full-speed idle, SE0 or suspend

SUSPND = HIGH

-

20

µA

[4]

I_CC(dis)

disable mode supply current V_CC(I/O)not connected

I_{CC(I/O)(sharing)}sharing mode I/O supply

current

V_CC(5.0)or V_reg(3.3)not connected

I_Dx(sharing)

sharing mode load current

on pins D+ and D−

V_CC(5.0)or V_reg(3.3)not connected;

SOFTCON = LOW; V_Dx= 3.6 V

-

10

µA

V_th(reg3.3)

regulated supply voltage

detection threshold

1.65 V ≤ V_CC(I/O)≤ V_reg(3.3)

2.7 V ≤ V_reg(3.3)≤ 3.6 V

;

supply lost

-

0.8

V

supply present

V_CC(I/O)= 1.8 V

2.4^[5]

-

V_hys(reg3.3)

V_th(I/Osup)

regulated supply voltage

detection hysteresis

-

0.45

I/O supply voltage detection V_reg(3.3)= 2.7 to 3.6 V

threshold

supply lost

-

0.5

V

supply present

1.4

-

V_hys(I/Osup)

I/O supply voltage detection V_reg(3.3)= 3.3 V

hysteresis

0.45

[1] I_loadincludes the pull-up resistor current via pin V_pu(3.3)

[2] In ‘suspend’ mode, the minimum voltage is 2.7 V.

[3] Characterized only, not tested in production.

.

[4] Excluding any load current and V_pu(3.3)/V_swsource current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 µA typ.).

[5] When V_CC(I/O)< 2.7 V, the minimum value for V_{th(reg3.3)(present)}is 2.0 V.

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ISP1105/1106/1107

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Advanced USB transceivers

Table 14: Static characteristics: digital pins

V_CC(I/O)= 1.65 to 3.6 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_CC(I/O)= 1.65 to 3.6 V

Input levels

V_IL

LOW-level input voltage

-

0.3V_CC(I/O)

-

V

V_IH

HIGH-level input voltage

0.6V_CC(I/O)

Output levels

I_OL= 100 µA

I_OL= 2 mA

-

0.15

V

V_OL

LOW-level output voltage

HIGH-level output voltage

0.4

I_OH= 100 µA

I_OH= 2 mA

V

_CC(I/O)− 0.15

_CC(I/O)− 0.4

-

V_OH

V

Leakage current

I_LI

input leakage current

-

±1

µA

Example 1: V_CC(I/O)= 1.8 V ± 0.15 V

Input levels

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.5

-

V

V_IH

1.2

Output levels

I_OL= 100 µA

I_OL= 2 mA

-

0.15

V

V_OL

LOW-level output voltage

HIGH-level output voltage

-

0.4

I_OH= 100 µA

I_OH= 2 mA

1.5

1.25

-

V_OH

Example 2: V_CC(I/O)= 2.5 V ± 0.2 V

Input levels

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.7

-

V

V_IH

1.7

Output levels

I_OL= 100 µA

I_OL= 2 mA

-

0.15

V

V_OL

LOW-level output voltage

HIGH-level output voltage

-

0.4

I_OH= 100 µA

I_OH= 2 mA

2.15

1.9

-

V_OH

Example 3: V_CC(I/O)= 3.3 V ± 0.3 V

Input levels

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.9

-

V

V_IH

2.15

Output levels

I_OL= 100 µA

I_OL= 2 mA

-

0.15

V

V_OL

LOW-level output voltage

HIGH-level output voltage

-

0.4

I_OH= 100 µA

I_OH= 2 mA

2.85

2.6

-

V_OH

Capacitance

C_IN

input capacitance

pin to GND

-

10

pF

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Advanced USB transceivers

Table 15: Static characteristics: analog I/O pins (D+, D−)

V_CC= 4.0 to 5.5 V or V_reg(3.3)= 3.0 to 3.6 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input levels

Differential receiver

V_DI

differential input sensitivity

|V_I(D+)− V_I(D−)

|

0.2

0.8

-

V

V_CM

differential common mode

voltage

includes V_DIrange

2.5

Single-ended receiver

V_IL

LOW-level input voltage

-

0.8

-

V

V_IH

HIGH-level input voltage

hysteresis voltage

2.0

0.4

V_hys

0.7

Output levels

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

R_L= 1.5 kΩ to +3.6 V

R_L= 15 kΩ to GND

-

0.3

3.6

V

2.8^[1]

Leakage current

I_LZ

OFF-state leakage current

-

±1

µA

Capacitance

C_IN

transceiver capacitance

driver output impedance

pin to GND

20

pF

Resistance

Z_DRV

[2]

[3]

steady-state drive

34

39

45

44

Ω

Z_DRV2

driver output impedance for steady-state drive

USB 2.0

40.5

49.5

Z_INP

R_SW

input impedance

10

-

MΩ

internal switch resistance at

pin V_pu(3.3)

10

Ω

Termination

[4]

V_TERM

termination voltage for

3.0^[5]

-

3.6

V

upstream port pull-up (R_PU

)

[1] V_OH(min)= V_reg(3.3)− 0.2 V.

[2] Includes external resistors of 33 Ω ±1% on both D+ and D−.

[3] Includes external resistors of 39 Ω ±1% on both D+ and D−. This range complies with Universal Serial Bus Speciﬁcation Rev. 2.0.

[4] This voltage is available at pins V_reg(3.3)and V_pu(3.3)

[5] In ‘suspend’ mode the minimum voltage is 2.7 V.

.

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10. Dynamic characteristics

Table 16: Dynamic characteristics: analog I/O pins (D+, D−)^[1]

V_CC= 4.0 to 5.5 V or V_reg(3.3)= 3.0 to 3.6 V; V_CC(I/O)= 1.65 to 3.6 V; V_GND= 0 V; see Table 10 for valid voltage level

combinations; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

Full-speed mode (SPEED = HIGH)

t_FR

rise time

C_L= 50 to 125 pF;

10 to 90% of |V_OH− V_OL|;

see Figure 5

4

-

20

ns

t_FF

fall time

C_L= 50 to 125 pF;

90 to 10% of |V_OH− V_OL|;

see Figure 5

FRFM

V_CRS

differential rise/fall time

excluding the ﬁrst transition

from Idle state

90

-

111.1

2.0

%

V

matching (t_FR/t_FF

)

[2]

output signal crossover

voltage

excluding the ﬁrst transition

from Idle state; see Figure 8

1.3

Low-speed mode (SPEED = LOW)

t_LR

rise time

C_L= 50 to 600 pF;

10 to 90% of |V_OH− V_OL|;

see Figure 5

75

-

300

ns

t_LF

fall time

C_L= 50 to 600 pF;

90 to 10% of |V_OH− V_OL|;

see Figure 5

LRFM

differential rise/fall time

excluding the ﬁrst transition

from Idle state

80

-

125

2.0

%

V

matching (t_LR/t_LF

)

[2]

V_CRS

output signal crossover

voltage

excluding the ﬁrst transition

from idle state; see Figure 8

1.3

Driver timing

Full-speed mode (SPEED = HIGH)

t_PLH(drv)

t_PHL(drv)

driver propagation delay

LOW-to-HIGH; see Figure 8

HIGH-to-LOW; see Figure 8

-

18

ns

(VO/VPO, FSE0/VMO to

D+,D−)

t_PHZ

t_PLZ

t_PZH

t_PZL

driver disable delay

(OE to D+,D−)

HIGH-to-OFF; see Figure 6

LOW-to-OFF; see Figure 6

OFF-to-HIGH; see Figure 6

OFF-to-LOW; see Figure 6

-

15

ns

driver enable delay

(OE to D+,D−)

Low-speed mode (SPEED = LOW)

Not speciﬁed: low-speed delay timings are dominated by the slow rise/fall times t_LRand t_LF.

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Table 16: Dynamic characteristics: analog I/O pins (D+, D−)^[1]…continued

V_CC= 4.0 to 5.5 V or V_reg(3.3)= 3.0 to 3.6 V; V_CC(I/O)= 1.65 to 3.6 V; V_GND= 0 V; see Table 10 for valid voltage level

combinations; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Receiver timings (full-speed and low-speed mode)

Differential receiver

t_PLH(rcv)

t_PHL(rcv)

propagation delay

LOW-to-HIGH; see Figure 7

HIGH-to-LOW; see Figure 7

-

15

ns

(D+,D− to RCV)

Single-ended receiver

t_PLH(se)propagation delay

t_PHL(se)(D+,D− to VP, VM)

LOW-to-HIGH; see Figure 7

HIGH-to-LOW; see Figure 7

-

18

ns

[1] Test circuit: see Figure 11.

[2] Characterized only, not tested. Limits guaranteed by design.

1.65 V

0.9 V

logic input 0.9 V

0 V

t

, t

t

, t

FR LR

FF LF

t

PHZ

PLZ

PZH

PZL

V

OH

90%

V

OH

V

−0.3 V

OH

differential

data lines

V

CRS

V

+0.3 V

10%

OL

V

MGS966

OL

MGS963

Fig 5. Rise and fall times.

Fig 6. Timing of OE to D+, D−.

2.0 V

1.65 V

differential

data lines

V

CRS

0.9 V

logic input 0.9 V

0 V

0.8 V

t

PLH(rcv)

PLH(se)

PHL(rcv)

t

PHL(drv)

t

PHL(se)

PLH(drv)

V

OH

V

OH

differential

data lines

0.9 V

logic output

V

CRS

V

OL

MGS965

MGS964

Fig 7. Timing of D+, D− to RCV, VP, VM.

Fig 8. Timing of VO/VPO, FSE0/VMO to D+, D−.

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11. Test information

test point

(1)

33 Ω

500 Ω

D.U.T.

50 pF

V

MBL142

V = 0 V for t_PZH, t_PHZ

V = V_reg(/3.3)for t_PZL, t_PLZ

(1) Complies with USB 1.1. For USB 2.0 a resistor of 39 Ω must be used.

Fig 9. Load for enable and disable times.

test point

D.U.T.

25 pF

MGS968

Fig 10. Load for VM, VP and RCV.

V

pu(3.3)

(1)

test point

1.5 kΩ

D.U.T.

D+/D−

(2)

33 Ω

15 kΩ

C

L

MGS967

Load capacitance:

C_L= 50 pF or 125 pF (full-speed mode, minimum or maximum timing)

C_L= 50 pF or 600 pF (low-speed mode, minimum or maximum timing)

(1) Full-speed mode: connected to D+, low-speed mode: connected to D−.

(2) Complies with USB 1.1. For USB 2.0 a resistor of 39 Ω must be used.

Fig 11. Load for D+, D−.

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12. Package outline

HBCC16: plastic thermal enhanced bottom chip carrier; 16 terminals; body 3 x 3 x 0.65 mm

SOT639-2

b

v

M

C

A B

D

B

A

E

w

f

v

M

C

A

B

w

M

C

terminal 1

index area

b

1

b

2

v

M

C

A B

w

b

v

M

C

A B

2

w

C

detail X

e

1

C

D

h

e

y

C

1

5

9

e

4

E

e

h

2

1/2 e

4

1

13

16

A

1

1/2 e

X

3

A

2

e

3

A

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

b

E

h

e

w

b

D

E

e

3

e

f

v

y

1

UNIT

1

2

1

2

h

2

4

max.

0.10 0.7

0.05 0.6

0.33 0.33 0.38

0.27 0.27 0.32

3.1 1.45

2.9 1.35

3.1 1.45

2.9 1.35

0.23

0.17

mm

0.8

0.1 0.05 0.2

0.5

2.5

2.45 2.45

0.08

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

SOT639-2

MO-217

01-11-13

Fig 12. HBCC16 package outline.

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TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

D

E

A

X

c

y

H

v

M

A

E

Z

9

16

Q

(A )

3

A

2

A

1

pin 1 index

θ

L

p

L

1

8

detail X

w

M

b

p

e

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

(2)

(1)

UNIT

A

b

c

D

E

e

H

L

Q

v

w

y

Z

θ

1

2

3

p

E

p

max.

8^o

0^o

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

6.6

6.2

0.75

0.50

0.4

0.3

0.40

0.06

mm

1.10

0.65

0.25

1.0

0.2

0.13

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-04-04

99-12-27

SOT403-1

MO-153

Fig 13. TSSOP16 package outline.

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13. Packaging

The ISP1105/1106/1107W (HBCC16 package) is delivered on a Type A carrier tape,

see Figure 14. The tape dimensions are given in Table 17.

The reel diameter is 330 mm. The reel is made of polystyrene (PS) and is not

designed for use in a baking process.

The cumulative tolerance of 10 successive sprocket holes is ±0.02 mm. The camber

must not exceed 1 mm in 100 mm.

idth

4

A0

K0

W

B0

P1

Type A

direction of feed

A0

K0

4

W

B0

elongated

sprocked hole

P1

direction of feed

MLC338

Type B

Fig 14. Carrier tape dimensions.

Table 17: Type A carrier tape dimensions for ISP1105/1106/1107W

Dimension

Value

3.3

Unit

mm

A₀

B₀

K₀

P₁

W

3.3

1.1

8.0

12.0 ±0.3

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14. Soldering

14.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne

pitch SMDs. In these situations reﬂow soldering is recommended.

14.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 250 °C. The top-surface

temperature of the packages should preferable be kept below 220 °C for thick/large

packages, and below 235 °C small/thin packages.

14.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

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During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated ﬂux will eliminate the

need for removal of corrosive residues in most applications.

14.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

14.5 Package related soldering information

Table 18: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package

Soldering method

Wave

Reﬂow^[1]

suitable

BGA, HBGA, LFBGA, SQFP, TFBGA

not suitable

not suitable^[2]

HBCC, HLQFP, HSQFP, HSOP, HTQFP,

HTSSOP, HVQFN, SMS

PLCC^[3], SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended^[3][4]

not recommended^[5]

[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[2] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board

and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top

version).

[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger

than 0.8 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

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15. Additional soldering information

15.1 (H)BCC packages: footprint

The surface material of the terminals on the resin protrusion consists of a 4-layer

metal structure (Au, Pd, Ni and Pd). The Au + Pd layer (0.1 µm min.) ensures

solderability, the Ni layer (5 µm min.) prevents diffusion, and the Pd layer on top

(0.5 µm min.) ensures effective wire bonding.

Terminal

PCB land

Solder resist mask

Stencil mask

All dimensions in mm

Solder land

Normal

0.05

b

1

b

1

Solder resist

Solder stencil

b

0.05

For exact dimensions

see package outline

drawing (SOT639-2)

Corner

0.05

b

2

b

2

0.05

0.3 (8×)

0.05

Cavity

0.05

Stencil print thickness:

0.1 to 0.12 mm

0.1

(4×)

E

h

004aaa123

D

h

0.05

Cavity: exposed diepad, either functioning as heatsink or as ground connection; only for HBCC packages.

Fig 15. (H)BCC footprint and solder resist mask dimensions.

15.2 (H)BCC packages: reﬂow soldering proﬁle

The conditions for reﬂow soldering of (H)BCC packages are as follows:

• Preheating time: minimum 90 s at T = 145 to 155 °C

• Soldering time: minimum 90 s (BCC) or minimum 100 s (HBCC) at T > 183 °C

• Peak temperature:

– Ambient temperature: T_amb(max)= 260 °C

– Device surface temperature: T_case(max)= 255 °C.

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16. Revision history

Table 19: Revision history

Rev Date

CPCN

-

Description

06 20011130

Product data; sixth version. Supersedes ISP1105_1106_1107-05 of 3 Sept 2001 (9397

750 08643). Modiﬁcations:

• Changed the HBCC16 package version from SOT639-1 to SOT639-2 in:

– Table 1 “Ordering information” on page 2.

– Section 12 “Package outline” on page 16.

– Figure 15 “(H)BCC footprint and solder resist mask dimensions.” on page 21.

• Section 7.4 “Power supply input options”: Removed the last sentence “The internal

regulator is not used in single-ended mode and is shutdown.” from the Internal regulator

deﬁnition.

05 20010903

04 20010802

-

Product data; ﬁfth version. Supersedes ISP1105_1106_1107-04 of 2 Aug 2001 (9397

750 08643). Modiﬁcations:

• Replaced front-page logo with new USB basic-speed logo.

Preliminary data; fourth version. Supersedes ISP1105_1106_1107-03 of 4 July 2001

(9397 750 08515). Modiﬁcations:

• Section 1 “General description”: removed backward compatibility with PDIUSBP11A.

• Section 2 “Features”:

– Removed backward compatibility with PDIUSBP11A.

– Added ‘on-chip’ for the ESD protection.

– Changed the I/O voltage range from ‘1.8 V, 2.5 V or 3.3 V’ into ‘1.65 V to 3.6 V’.

• Section 6.2 “Pin description”: changed the description for pin V_CC(I/O)

.

• Section 7.3 “Power supply conﬁgurations”: changed V_CC(I/O)range from ‘1.8 V, 2.5 V or

3.3 V’ into ‘1.65 to 3.6 V’ in the description of Normal mode, in Table 8 and in Table 10.

• Table 13 “Static characteristics: supply pins”: removed table note for I_CCreferencing the

USB On-The-Go speciﬁcation.

• Table 14 “Static characteristics: digital pins”: changed the commonly supported types of

V_CC(I/O)into examples.

• Section 15.1 “(H)BCC packages: footprint”: added paragraph on terminal composition.

• Section 15.2 “(H)BCC packages: reﬂow soldering proﬁle”: changed peak temperature

from 220 °C ±5 °C to 260 °C (ambient) and 255 °C (device surface).

03 20010704

-

Preliminary data; third version. Supersedes ISP1107-02 of 5 February 2001

(9397 750 07879). Modiﬁcation:

• ISP1107, ISP1106 and ISP1105 combined into one datasheet.

02 20010205

01 20000223

-

Objective speciﬁcation; second version. Supersedes ISP1107-01 of 23 February 2000

(9397 750 06899). ISP1107 stand-alone datasheet only.

Objective speciﬁcation; initial version. ISP1107 stand-alone datasheet only.

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17. Data sheet status

Data sheet status^[1]

Product status^[2]

Deﬁnition

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips Semiconductors

reserves the right to change the speciﬁcation in any manner without notice.

Preliminary data

Product data

Qualiﬁcation

Production

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published at a

later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to

improve the design and supply the best possible product.

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the right to

make changes at any time in order to improve the design, manufacturing and supply. Changes will be

communicated according to the Customer Product/Process Change Notiﬁcation (CPCN) procedure

SNW-SQ-650A.

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

18. Deﬁnitions

19. Disclaimers

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes, without notice, in the products, including circuits, standard

cells, and/or software, described or contained herein in order to improve

design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

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Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2

Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

2

3

4

4.1

5

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

Functional description . . . . . . . . . . . . . . . . . . . 6

Function selection. . . . . . . . . . . . . . . . . . . . . . . 6

Operating functions. . . . . . . . . . . . . . . . . . . . . . 7

Power supply conﬁgurations. . . . . . . . . . . . . . . 7

Power supply input options. . . . . . . . . . . . . . . . 8

7.1

7.2

7.3

7.4

8

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 9

Static characteristics. . . . . . . . . . . . . . . . . . . . 10

Dynamic characteristics . . . . . . . . . . . . . . . . . 13

Test information. . . . . . . . . . . . . . . . . . . . . . . . 15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

9

10

11

12

13

14

14.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Introduction to soldering surface mount

packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 19

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 20

Package related soldering information . . . . . . 20

14.2

14.3

14.4

14.5

15

15.1

15.2

Additional soldering information . . . . . . . . . . 21

(H)BCC packages: footprint . . . . . . . . . . . . . . 21

(H)BCC packages: reﬂow soldering proﬁle. . . 21

16

17

18

19

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 23

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 30 November 2001

Document order number: 9397 750 08872


型号：	ISP1106W
厂家：	NXP
描述：	Advanced Universal Serial Bus transceivers 高级通用串行总线收发器总线收发器线路驱动器或接收器驱动程序和接口接口集成电路
文件：	总24页 (文件大小：540K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1106W [NXP]

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