ISP1181_技术文档

ISP1181

Full-speed Universal Serial Bus interface device

Rev. 01 — 13 March 2000

Objective speciﬁcation

1. General description

The ISP1181 is a Universal Serial Bus (USB) interface device which complies with

Universal Serial Bus Speciﬁcation Rev. 1.1. It provides full-speed USB

communication capacity to microcontroller or microprocessor-based systems. The

ISP1181 communicates with the system’s microcontroller or microprocessor through

a high-speed general-purpose parallel interface.

The fully autonomous Direct Memory Access (DMA) operation - auto download, auto

repeat, auto execution - removes the need for the device to re-enable or re-initialize

the DMA operation every time.

The modular approach to implementing a USB interface device allows the designer to

select the optimum system microcontroller from the wide variety available. The ability

to re-use existing architecture and ﬁrmware investments shortens development time,

eliminates risks and reduces costs. The result is fast and efﬁcient development of the

most cost-effective USB peripheral solution.

The ISP1181 is ideally suited for application in many personal computer peripherals,

such as printers, scanners, external mass storage (zip drive) devices and digital still

cameras. It offers an immediate cost reduction for applications that currently use

SCSI implementations.

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2. Features

■ Complies with Universal Serial Bus Speciﬁcation Rev. 1.1 and most Device Class

speciﬁcations

■ High performance USB interface device with integrated Serial Interface Engine

(SIE), FIFO memory, transceiver and 3.3 V voltage regulator

■ Interrupt endpoint can be conﬁgured in ‘rate feedback’ mode

■ High speed (11.1 Mbyte/s or 90 ns read/write cycle) parallel interface

■ Fully autonomous and multi-conﬁguration DMA operation

■ Up to 14 programmable USB endpoints with 2 ﬁxed control IN/OUT endpoints

■ Integrated physical 2462 bytes of multi-conﬁguration FIFO memory

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer

■ Seamless interface with most microcontrollers/microprocessors

■ Bus-powered capability with low power consumption and low ‘suspend’ current

■ 6 MHz crystal oscillator with integrated PLL for low EMI

ISP1181

Full-speed USB interface

Philips Semiconductors

■ Controllable LazyClock (24 kHz) output during ‘suspend’

■ Software controlled connection to the USB bus (SoftConnect™)

■ Good USB connection indicator that blinks with trafﬁc (GoodLink™)

■ Clock output with programmable frequency (up to 48 MHz)

■ Complies with the ACPI™, OnNow™ and USB power management requirements

■ Internal power-on and low-voltage reset circuit, with possibility of a software reset

■ Operation over the extended USB bus voltage range (4.0 to 5.5 V) with 5 V

tolerant I/O pads

■ Operating temperature range −40 to +85 °C

■ 8 kV in-circuit ESD protection for lower cost of external components

■ Full-scan design with high fault coverage

■ Available in a TSSOP48 package.

3. Applications

■ Personal digital assistant (PDA)

■ Digital camera

■ Communication device, e.g.

◆ router

◆ modem

■ Printer

■ Scanner.

4. Ordering information

Table 1: Ordering information

Type number

Package

Name

Description

Version

ISP1181DGG

TSSOP48

Plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

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ISP1181

Full-speed USB interface

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6. Pinning information

6.1 Pinning

handbook, halfpage

V

1

2

3

4

5

6

7

8

9

48 XTAL1

47 XTAL2

46 GND

CC(5.0)

REGGND

V

reg(3.3)

D−

D+

45 CLKOUT

44 RESET

43 CS

V

BUS

GL

WAKEUP

SUSPEND

42 ALE

41 WR

40 RD

EOT 10

DREQ 11

39

A0

38 AD

V

37

DACK 12

CC(3.3)

ISP1181DGG

SDWR 13

36 GND

SDRD 14

35 DATA1

34 DATA2

33 DATA3

32 DATA4

31 DATA5

30 DATA6

29 DATA7

28 DATA8

27 DATA9

INT 15

READY 16

BUS_CONF0 17

BUS_CONF1 18

DATA15 19

DATA14 20

DATA13 21

DATA12 22

DATA11 23

DATA10 24

V

26

ref(5.0)

25 GND

MGL892

Fig 2. Pin conﬁguration TSSOP48.

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ISP1181

Full-speed USB interface

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6.2 Pin description

Table 2: Pin description for TSSOP48

Symbol^[1]

1

Type Description

V_CC(5.0)

-

supply voltage (3.0 to 5.5 V)

voltage regulator ground supply

REGGND

V_reg(3.3)

2

3

regulated supply voltage (3.3 V ± 10%) from internal

regulator; used to connect decoupling capacitor and pull-up

resistor on D+ line;

Remark: Cannot be used to supply external devices.

D−

4

5

6

7

AI/O USB D− connection (analog)

AI/O USB D+ connection (analog)

D+

V_BUS

GL

I

V_BUSsensing input

O

GoodLink LED indicator output (open-drain, 8 mA); the LED

is default ON, blinks OFF upon USB trafﬁc; to connect an

LED use a 330 Ω series resistor;

WAKEUP

8

9

I

wake-up input (edge triggered, LOW to HIGH); generates a

remote wake-up from ‘suspend’ state

SUSPEND

O

‘suspend’ state indicator output (4 mA); used as power switch

control output (active LOW) for powered-off application or as

resume signal to the CPU (active HIGH) for powered-on

application

EOT

10

11

12

I

End-Of-Transfer input (programmable polarity, see Table 23);

used by the DMA controller to force the end of a DMA transfer

by the ISP1181

DREQ

DACK

O

I

DMA request output (4 mA; programmable polarity, see

Table 23); signals to the DMA controller that the ISP1181

wants to start a DMA transfer

DMA acknowledge input (programmable polarity, see

Table 23); used by the DMA controller to signal the start of a

DMA transfer requested by the ISP1181

SDWR

SDRD

INT

13

14

15

16

I

DMA write strobe input; used only in bus conﬁguration

mode 1 (separate PIO and DMA ports)

I

DMA read strobe input; used only in bus conﬁguration

mode 1 (separate PIO and DMA ports)

O

interrupt output; programmable polarity (active HIGH or LOW)

and signalling (level or pulse); see Table 23

READY

I/O ready output; a LOW level indicates that ISP1181 is

processing a previous command or data and is not ready for

the next PIO command or data transfer; a HIGH level signals

that ISP1181 will complete a PIO data transfer; applies only

to a PIO port or a PIO port shared with a DMA port

BUS_CONF1 17

BUS_CONF0 18

I

bus conﬁguration selector; see Table 3

I

DATA15

19

I/O

bit 15 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA14

20

I/O

bit 14 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

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ISP1181

Full-speed USB interface

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Table 2: Pin description for TSSOP48

Symbol^[1]

Type Description

DATA13

DATA12

DATA11

DATA10

21

I/O

bit 13 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

22

23

24

bit 12 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 11 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 10 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

GND

25

26

27

-

ground supply

V_ref(5.0)

DATA9

-

I/O pin reference voltage (3.0 to 5.5 V)

I/O

bit 9 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA8

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

28

29

30

31

32

33

34

35

I/O

bit 8 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 7 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 6 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 5 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 4 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 3 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 2 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

bit 1 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

GND

36

37

-

ground supply

V_CC(3.3)

supply voltage (3.0 to 3.6 V); leave this pin unconnected

when using the internal regulator

AD

38

I/O

multiplexed bi-directional address and data line; represents

address A0 or bit 0 of D[15:0] in conjunction with input ALE;

level-sensitive input or slew-rate controlled output (4 mA)

Address phase: a HIGH-to-LOW transition on input ALE

latches the level on this pin as address A0 (1 = command,

0 = data)

Data phase: during reading this pin outputs bit D[0]; during

writing the level on this pin is latched as bit D[0]

A0

39

I

address input; selects command (A0 = 1) or data (A0 = 0); in

a multiplexed address/data bus conﬁguration this pin is not

used and must be tied HIGH (connect to V_CCor V_reg(3.3)

)

RD

40

41

I

read strobe input

WR

write strobe input

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ISP1181

Full-speed USB interface

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Table 2: Pin description for TSSOP48

Symbol^[1]

Type Description

ALE

42

I

address latch enable input; a HIGH-to-LOW transition latches

the level on pin AD0 as address information in a multiplexed

address/data bus conﬁguration; must be tied LOW (connect

to DGND) for a separate address/data bus conﬁguration

CS

43

44

I

chip select input

RESET

reset input (Schmitt trigger); a LOW level produces an

asynchronous reset; connect to V_CCfor power-on reset

(internal POR circuit)

CLKOUT

GND

45

46

47

O

-

programmable clock output (2 mA)

ground supply

XTAL2

O

crystal oscillator output (6 MHz); connect a fundamental

parallel-resonant crystal; leave this pin open when using an

external clock source on pin XTAL1

XTAL1

48

I

crystal oscillator input (6 MHz); connect a fundamental

parallel-resonant crystal or an external clock source (leaving

pin XTAL2 is unconnected)

[1] Symbol names with an overscore (e.g. NAME) represent active LOW signals.

7. Functional description

The ISP1181 is a full-speed USB interface device with up to 14 conﬁgurable

endpoints. It has a fast general-purpose parallel interface for communication with

many types of microcontrollers or microprocessors. It supports different bus

conﬁgurations (see Table 3) and local DMA transfers of up to 16 bytes per cycle. The

block diagram is given in Figure 1.

The ISP1181 has 2462 bytes of internal FIFO memory, which is shared among the

enabled USB endpoints. The type and FIFO size of each endpoint can be individually

conﬁgured, depending on the required packet size. Isochronous and bulk endpoints

are double-buffered for increased data throughput. Interrupt IN endpoints can be

conﬁgured in rate-feedback mode.

The ISP1181 requires a single supply voltage of 3.0 to 5.5 V and has an internal

3.3 V voltage regulator for powering the analog USB transceiver. It supports

bus-powered operation.

The ISP1181 operates on a 6 MHz oscillator frequency. A programmable clock output

is available up to 48 MHz. During ‘suspend’ state the 24 kHz LazyClock frequency

can be output.

7.1 Analog transceiver

The transceiver is compliant with Universal Serial Bus Speciﬁcation Rev. 1.1. It

interfaces directly with the USB cable through external termination resistors.

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ISP1181

Full-speed USB interface

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7.2 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for

speed and needs no ﬁrmware intervention. The functions of this block include:

synchronization pattern recognition, parallel/serial conversion, bit (de-)stufﬁng, CRC

checking/generation, Packet IDentiﬁer (PID) veriﬁcation/generation, address

recognition, handshake evaluation/generation.

7.3 Memory Management Unit (MMU) and integrated RAM

The MMU and the integrated RAM provide the conversion between the USB speed

(12 Mbit/s bursts) and the parallel interface to the microcontroller (max. 12 Mbyte/s).

This allows the microcontroller to read and write USB packets at its own speed.

7.4 SoftConnect

The connection to the USB is accomplished by bringing D+ (for high-speed USB

devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1181 the 1.5 kΩ pull-up

resistor is integrated on-chip and is not connected to V_CCby default. The connection

is established through a command sent by the external/system microcontroller. This

allows the system microcontroller to complete its initialization sequence before

deciding to establish connection with the USB. Re-initialization of the USB connection

can also be performed without disconnecting the cable.

The ISP1181 will check for USB V_BUSavailability before the connection can be

established. V_BUSsensing is provided through pin V_BUS

.

Remark: Note that the tolerance of the internal resistors is 25%. This is higher than

the 5% tolerance speciﬁed by the USB speciﬁcation. However, the overall V_SEvoltage

speciﬁcation for the connection can still be met with a good margin. The decision to

make use of this feature lies with the USB equipment designer.

7.5 GoodLink

Indication of a good USB connection is provided at pin GL through GoodLink

technology. During enumeration the LED indicator will blink on momentarily. When

the ISP1181 has been successfully enumerated (the device address is set), the LED

indicator will remain permanently on. Upon each successful packet transfer (with

ACK) to and from the ISP1181 the LED will blink off for 100 ms. During ‘suspend’

state the LED will remain off.

This feature provides a user-friendly indicator of the status of the USB device, the

connected hub and the USB trafﬁc. It is a useful ﬁeld diagnostics tool for isolating

faulty equipment. It can therefor help to reduce ﬁeld support and hotline overhead.

A register bit can be set to stop the GoodLink LED blinking in trafﬁc (see Table 20).

The LED indicator will then be permanently on.

7.6 Bit clock recovery

The bit clock recovery circuit recovers the clock from the incoming USB data stream

using a 4× over-sampling principle. It is able to track jitter and frequency drift as

speciﬁed by the USB Speciﬁcation Rev. 1.1.

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Full-speed USB interface

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7.7 Voltage regulator

A 5 V to 3.3 V voltage regulator is integrated on-chip to supply the analog transceiver

and internal logic. This voltage is available at pin V_reg(3.3)to supply an external 1.5 kΩ

pull-up resistor on the D+ line. Alternatively, the ISP1181 provides SoftConnect

technology via an integrated 1.5 kΩ pull-up resistor (see Section 7.4).

7.8 PLL clock multiplier

A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.

This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No

external components are required for the operation of the PLL.

7.9 Parallel I/O (PIO) and Direct Memory Access (DMA) interface

A generic PIO interface is deﬁned for speed and ease-of-use. It also allows direct

interfacing to most microcontrollers. To a microcontroller, the ISP1181 appears as a

memory device with an 8/16-bit data bus and an 1-bit address bus. The ISP1181

supports both multiplexed and non-multiplexed address and data buses.

The ISP1181 can also be conﬁgured as a DMA slave device to allow more efﬁcient

data transfer. One of the 14 endpoint FIFOs may directly transfer data to/from the

local shared memory. The DMA interface can be conﬁgured independently from the

PIO interface.

8. Modes of operation

The ISP1181 has four bus conﬁguration modes, selected via pins BUS_CONF1 and

BUSCONF0:

Mode 0

Mode 1

Mode 2

Mode 3

16-bit I/O port shared with 8-bit or 16-bit DMA port

separate 8-bit I/O port and 8-bit DMA port

8-bit I/O port shared with 8-bit or 16-bit DMA port

reserved.

The bus conﬁgurations for each of these modes are given in Table 3. Typical interface

circuits for each mode are given in Section 20.1.

Table 3: Bus conﬁguration modes

Mode

BUS_CONF[1:0]

PIO width

DMA width

Description

DMAWD = 0

DMAWD = 1

0

1

0

1

0

1

D[15:0]

D[7:0];

D[15:8]

D[7:0]

D[15:0]

multiplexed address/data on pin AD0;

bus is shared by 16-bit I/O port and 8-bit

or 16-bit DMA port

1

2

D[7:0]

illegal

multiplexed address/data on pin AD0;

bus has separate I/O port (8-bit) and

DMA port (8-bit)

D[7:0]

D[15:0]

reserved

multiplexed address/data on pin AD0;

bus is shared by 8-bit I/O port and 8-bit

or 16-bit DMA port

3

reserved

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Full-speed USB interface

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9. Endpoint descriptions

Each USB device is logically composed of several independent endpoints. An

endpoint acts as a terminus of a communication ﬂow between the host and the

device. At design time each endpoint is assigned a unique number (endpoint

identiﬁer, see Table 4). The combination of the device address (given by the host

during enumeration), the endpoint number and the transfer direction allows each

endpoint to be uniquely referenced.

The ISP1181 has 16 endpoints: endpoint 0 (control IN and OUT) plus 14 conﬁgurable

endpoints, which can be individually deﬁned as interrupt/bulk/isochronous, IN or OUT.

Each enabled endpoint has an associated FIFO, which can be accessed either via

the parallel I/O interface or via DMA.

9.1 Endpoint access

Table 4 lists the endpoint access modes and programmability. All endpoints support

I/O mode access. Endpoints 1 to 14 also support DMA access. FIFO DMA access is

selected and enabled via bits EPIDX[3:0] and DMAEN of the DMA Conﬁguration

Register. A detailed description of the DMA operation is given in Section 10.

Table 4: Endpoint access and programmability

Endpoint

identiﬁer

FIFO size (bytes)

Double

buffering

I/O mode

access

DMA mode

access

Endpoint type

0

64 (ﬁxed)

no

yes

no

control OUT^[1]

control IN^[1]

0

64 (ﬁxed)

no

yes

no

1

programmable

supported

programmable

2

3

4

5

6

7

8

9

10

11

12

13

14

[1] IN: input for the USB host (ISP1181 transmits); OUT: output from the USB host (ISP1181 receives).

[2] The data ﬂow direction is determined by bit EPDIR in the Endpoint Conﬁguration Register.

[3] The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes.

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Full-speed USB interface

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9.2 Endpoint FIFO size

The size of the FIFO determines the maximum packet size that the hardware can

support for a given endpoint. Only enabled endpoints are allocated space in the

shared FIFO storage, disabled endpoints have zero bytes. Table 5 lists the

programmable FIFO sizes.

The following bits in the Endpoint Conﬁguration Register (ECR) affect FIFO

allocation:

endpoint enable bit (FIFOEN)

•

size bits of an enabled endpoint (FFOSZ[3:0])

isochronous bit of an enabled endpoint (FFOISO).

Remark: Register changes that affect the allocation of the shared FIFO storage

among endpoints must not be made while valid data is present in any FIFO of the

enabled endpoints. Such changes will render all FIFO contents undeﬁned.

Table 5: Programmable FIFO size

FFOSZ[3:0]

0000

Non-isochronous

8 bytes

Isochronous

16 bytes

0001

16 bytes

32 bytes

0010

32 bytes

48 bytes

0011

64 bytes

0100

reserved

96 bytes

0101

128 bytes

160 bytes

192 bytes

256 bytes

0110

0111

1000

interrupt IN 8 bytes,

rate feedback mode

1001

1010

1011

interrupt IN 16 bytes,

rate feedback mode

320 bytes

384 bytes

512 bytes

interrupt IN 32 bytes,

rate feedback mode

interrupt IN 64 bytes,

rate feedback mode

1100

1101

1110

1111

reserved

640 bytes

768 bytes

896 bytes

1023 bytes

Each programmable FIFO can be conﬁgured independently via its ECR, but the total

physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes

(512 bytes for non-isochronous FIFOs).

Table 6 shows an example of a conﬁguration ﬁtting in the maximum available space of

2462 bytes. The total number of logical bytes in the example is 1311. The physical

storage capacity used for double buffering is managed by the device hardware and is

transparent to the user.

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Full-speed USB interface

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Table 6: Memory conﬁguration example

Physical size

(bytes)

Logical size

(bytes)

Endpoint description

64

control IN (64 byte ﬁxed)

64

control OUT (64 byte ﬁxed)

2046

16

1023

16

double-buffered 1023-byte isochronous endpoint

16-byte interrupt OUT

16

16-byte interrupt IN

128

64

double-buffered 64-byte bulk OUT

double-buffered 64-byte bulk IN

64

9.3 Endpoint initialization

In response to the standard USB request Set Interface, the ﬁrmware must program all

16 ECRs of the ISP1181 in sequence (see Table 4), whether the endpoints are

enabled or not. The hardware will then automatically allocate FIFO storage space.

If all endpoints have been conﬁgured successfully, the ﬁrmware must return an empty

packet to the control IN endpoint to acknowledge success to the host. If there are

errors in the endpoint conﬁguration, the ﬁrmware must stall the control IN endpoint.

When reset by hardware or via the USB bus, the ISP1181 disables all endpoints and

clears all ECRs, except for the control endpoint which is ﬁxed and always enabled.

Endpoint initialization can be done at any time; however, it is valid only after

enumeration.

9.4 Endpoint I/O mode access

When an endpoint event occurs (a packet is transmitted or received), the associated

endpoint interrupt bits (EPn) of the Interrupt Register (IR) will be set by the SIE. The

ﬁrmware then responds to the interrupt and selects the endpoint for processing.

The endpoint interrupt bit will be cleared by reading the Endpoint Status Register

(ESR). The ESR also contains information on the status of the endpoint buffer.

For an OUT (= receive) endpoint, the packet length and packet data can be read from

ISP1181 using the Read Buffer command. When the whole packet has been read,

the ﬁrmware sends a Clear Buffer command to enable the reception of new packets.

For an IN (= transmit) endpoint, the packet length and data to be sent can be written

to ISP1181 using the Write Buffer command. When the whole packet has been

written to the buffer, the ﬁrmware sends a Validate Buffer command to enable data

transmission to the host.

9.5 Special actions on control endpoints

Control endpoints require special ﬁrmware actions. The arrival of a SETUP packet

ﬂushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for

the control IN and OUT endpoints. The microcontroller needs to re-enable these

commands by sending an Acknowledge Setup command to both control endpoints.

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This ensures that the last SETUP packet stays in the buffer and that no packets can

be sent back to the host until the microcontroller has explicitly acknowledged that it

has seen the SETUP packet.

10. DMA transfer

Direct Memory Access (DMA) is a method to transfer data from one location to

another in a computer system, without intervention of the central processor (CPU).

Many different implementations of DMA exist. The ISP1181 supports two methods:

8237 compatible mode: based on the DMA subsystem of the IBM personal

computers (PC, AT and all its successors and clones); this architecture uses the

Intel 8237 DMA controller and has separate address spaces for memory and I/O

•

DACK-only mode: based on the DMA implementation in some embedded RISC

processors, which has a single address space for both memory and I/O.

•

The ISP1181 supports DMA transfer for all 14 conﬁgurable endpoints (see Table 4).

Only one endpoint at a time can be selected for DMA transfer. The DMA operation of

the ISP1181 can be interleaved with normal I/O mode access to other endpoints.

The following features are supported:

Single-cycle or burst transfers (up tot 16 bytes per cycle)

Programmable transfer direction (read or write)

•

Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions,

short/empty packet

Programmable signal levels on pins DREQ, DACK and EOT

Automatic DMA counter reload and transfer restart following EOT.

•

10.1 Selecting an endpoint for DMA transfer

The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA

Conﬁguration Register, as shown in Table 7. The transfer direction (read or write) is

automatically set by bit EPDIR in the associated ECR, to match the selected endpoint

type (OUT endpoint: read; IN endpoint: write).

Asserting input DACK automatically selects the endpoint speciﬁed in the DMA

Conﬁguration Register, regardless of the current endpoint used for I/O mode access.

Table 7: Endpoint selection for DMA transfer

Endpoint

identiﬁer

EPIDX[3:0]

Transfer direction

EPDIR = 0

EPDIR = 1

IN: write

1

2

3

4

5

6

7

0010

0011

0100

0101

0110

0111

1000

OUT: read

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ISP1181

Full-speed USB interface

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Table 7: Endpoint selection for DMA transfer

Endpoint

identiﬁer

EPIDX[3:0]

Transfer direction

EPDIR = 0

OUT: read

EPDIR = 1

IN: write

8

1001

1010

1011

1100

1101

1110

1111

9

10

11

12

13

14

10.2 8237 compatible mode

The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware

Conﬁguration Register (see Table 22). The pin functions for this mode are shown in

Table 8.

Table 8: 8237 compatible mode: pin functions

Symbol

DREQ

DACK

EOT

Description

DMA request

DMA acknowledge

end of transfer

read strobe

I/O

Function

O

I

ISP1181 requests a DMA transfer

DMA controller conﬁrms the transfer

DMA controller terminates the transfer

instructs ISP1181 to put data on the bus

instructs ISP1181 to get data from the bus

I

RD

I

WR

write strobe

I

The DMA subsystem of an IBM compatible PC is based on the Intel 8237 DMA

controller. It operates as a ‘ﬂy-by’ DMA controller: the data is not stored in the DMA

controller, but it is transferred between an I/O port and a memory address. A typical

example of ISP1181 in 8237 compatible DMA mode is given in Figure 3.

The 8237 has two control signals for each DMA channel: DRQ (DMA Request) and

DACK (DMA Acknowledge). General control signals are HRQ (Hold Request), HLDA

(Hold Acknowledge) and EOP (End-Of-Process). The bus operation is controlled via

MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write).

idth

MEMR

MEMW

AD,

RAM

DATA1 to DATA15

DMA

CPU

CONTROLLER

8237

ISP1181

DREQ

DACK

DREQ

HRQ

HLDA

DACK

HLDA

RD

IOR

WR

IOW

MGS778

Fig 3. ISP1181 in 8237 compatible DMA mode.

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The following example shows the steps which occur in a typical DMA transfer:

1. ISP1181 receives a data packet in one of its endpoint FIFOs; the packet must be

transferred to memory address 1234H.

2. ISP1181 asserts the DREQ signal requesting the 8237 for a DMA transfer.

3. The 8237 asks the CPU to release the bus by asserting the HRQ signal.

4. After completing the current instruction cycle, the CPU places the bus control

signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and

asserts HLDA to inform the 8237 that it has control of the bus.

5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR

control signals.

6. The 8237 asserts DACK to inform the ISP1181 that it will start a DMA transfer.

7. The ISP1181 now places the byte or word to be transferred on the data bus lines,

because its RD signal was asserted by the 8237.

8. The 8237 waits one DMA clock period and then de-asserts MEMW and IOR. This

latches and stores the byte or word at the desired memory location. It also

informs the ISP1181 that the data on the bus lines has been transferred.

9. The ISP1181 de-asserts the DREQ signal to indicate to the 8237 that DMA is no

longer needed. In Single cycle mode this is done after each byte or word, in

Burst mode following the last transferred byte or word of the DMA cycle.

10. The 8237 de-asserts the DACK output indicating that the ISP1181 must stop

placing data on the bus.

11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the

address lines in three-state and de-asserts the HRQ signal, informing the CPU

that it has released the bus.

12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating

the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the

CPU resumes the execution of instructions.

For a typical bulk transfer the above process is repeated 64 times, once for each byte.

After each byte the address register in the DMA controller is incremented and the

byte counter is decremented. When using 16-bit DMA the number of transfers is 32

and address incrementing and byte counter decrementing is done by 2 for each word.

10.3 DACK-only mode

The DACK-only DMA mode is selected by setting bit DAKOLY in the Hardware

Conﬁguration Register (see Table 22). The pin functions for this mode are shown in

Table 9. A typical example of ISP1181 in DACK-only DMA mode is given in Figure 4.

Table 9: DACK-only mode: pin functions

Symbol

DREQ

DACK

Description

I/O

O

I

Function

DMA request

ISP1181 requests a DMA transfer

DMA acknowledge

DMA controller conﬁrms the transfer;

also functions as data strobe

EOT

RD

End-Of-Transfer

read strobe

I

DMA controller terminates the transfer

not used

WR

write strobe

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In DACK-only mode the ISP1181 uses the DACK signal as data strobe. Input signals

RD and WR are ignored. This mode is used in CPU systems that have a single

address space for memory and I/O access. Such systems have no separate MEMW

and MEMR signals: the RD and WR signals are also used as memory data strobes.

idth

ISP1181

DMA

CONTROLLER

CPU

DREQ

DACK

HRQ

HLDA

RD

AD,

RAM

DATA1 to DATA15

WR

MGS779

Fig 4. ISP1181 in DACK-only DMA mode.

10.4 End-Of-Transfer conditions

10.4.1 Bulk endpoints

A DMA transfer to/from a bulk endpoint can be terminated by any of the following

conditions (bit names refer to the DMA Conﬁguration Register, see Table 26):

An external End-Of-Transfer signal occurs on input EOT

•

The internal DMA Counter Register reaches zero (CNTREN = 1)

A short/empty packet is received on an enabled OUT endpoint (SHORTP = 1)

DMA operation is disabled by clearing bit DMAEN.

External EOT: When reading from an OUT endpoint, an external EOT will stop the

DMA operation and clear any remaining data in the current FIFO. For a double-

buffered endpoint the other (inactive) buffer is not affected.

When writing to an IN endpoint, an EOT will stop the DMA operation and the data

packet in the FIFO (even if it is smaller than the maximum packet size) will be sent to

the USB host at the next IN token.

DMA Counter Register zero: An EOT from the DMA Counter Register is enabled by

setting bit CNTREN in the DMA Conﬁguration Register. The ISP1181 has a 16-bit

DMA Counter Register, which speciﬁes the number of bytes to be transferred. When

DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from

the DMA Counter Register. When the internal counter reaches zero an EOT condition

is generated and the DMA operation stops.

Short/empty packet: Normally, the transfer byte count must be set via a control

endpoint before any DMA transfer takes place. When a short/empty packet has been

enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the

presence of a short/empty packet in the data. This mechanism permits the use of a

fully autonomous data transfer protocol.

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When reading from an OUT endpoint, reception of a short/empty packet at an OUT

token will stop the DMA operation after transferring the data bytes of this packet.

When writing to an IN endpoint, a short packet transferred at an IN token will stop the

DMA operation after all bytes have been transferred. If the number of bytes in the

buffer is zero, ISP1181 will automatically send an empty packet.

Table 10: Summary of EOT conditions for a bulk endpoint

EOT condition

EOT input

OUT endpoint

IN endpoint

EOT is active

DMA Counter Register

Short packet

counter reaches zero

short packet is received and counter reaches zero in the

transferred middle of the buffer

empty packet is received and empty packet is automatically

Empty packet

transferred

appended when needed^[1]

DMAEN bit in DMA

DMAEN = 0

Conﬁguration Register

[1] If short/empty packet EOT is enabled (SHORTP = 1 in DMA Conﬁguration Register) and DMA

Counter Register is zero.

10.4.2 Isochronous endpoints

A DMA transfer to/from an isochronous endpoint can be terminated by any of the

following conditions (bit names refer to the DMA Conﬁguration Register, see

Table 26):

An external End-Of-Transfer signal occurs on input EOT

The internal DMA Counter Register reaches zero (CNTREN = 1)

An End-Of-Packet (EOP) signal is detected

•

DMA operation is disabled by clearing bit DMAEN.

Table 11: Recommended EOT usage for isochronous endpoints

EOT condition

OUT endpoint

do not use

preferred

IN endpoint

preferred

EOT input active

DMA Counter Register zero

End-Of-Packet

preferred

do not use

10.4.3 DMA auto-restart

If the AUTOLD bit in the DMA Conﬁguration Register is set, the DMA operation will

automatically restart when the last transfer has been completed. First the internal

DMA counter is reloaded from of the DMA Counter Register. Output DREQ is then

asserted to request a new DMA transfer for an IN endpoint, or when the buffer of an

OUT endpoint buffer has been ﬁlled.

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11. Suspend and resume

11.1 Suspend conditions

The ISP1181 detects a USB ‘suspend’ status in the following cases:

A J-state is present on the USB bus for 3 ms

•

V

_BUSis lost (weak pull-up/down on D+ and D−)

SoftConnect is disabled by clearing bit SOFTCT in the Mode Register, with

external pull-ups disabled by EXTPUL = 0 in the Hardware Conﬁguration Register.

In this situation ISP1181 is effectively disconnected from the USB bus.

ISP1181 will remain in ‘suspend’ state for at least 5 ms, before responding to external

wake-up events such as global resume, bus trafﬁc, wake-up on CS or WAKEUP. The

typical timing is shown in Figure 5.

^{handbook, full}G^paO^geS^wU^idtS^hP

suspend

>5 ms

start detection of

wake-up conditions

WAKEUP

MGS949

Fig 5. Typical suspend timing.

Bus-powered devices that are suspended must not consume more than 500 µA of

current. This is achieved by shutting down the power to system components or

supplying them with a reduced voltage.

ISP1181 can either be in powered-on or powered-off mode during ‘suspend’ state.

This is controlled by bit PWROFF in the Hardware Conﬁguration Register. A full

explanation of these modes is given in Section 11.1.1 and Section 11.1.2.

The steps leading up to ‘suspend’ status are as follows:

1. Upon detection of a ‘wake-up’ to ‘suspend’ transition ISP1181 sets bit SUSPND

in the Interrupt Register. This will generate an interrupt if bit IESUSP in the

Interrupt Enable Register is set.

2. When the ﬁrmware detects a ‘suspend’ condition it must prepare all system

components for ‘suspend’ state:

a. All signals connected to ISP1181 must enter appropriate states to meet the

power consumption requirements of ‘suspend’ state.

b. All input pins of ISP1181 must have a CMOS logic 0 or logic 1 level. Pin

settings differ for powered-on and powered-off application.

3. In the interrupt service routine the ﬁrmware must check the current status of the

USB bus. When bit BUSTATUS in the Interrupt Register is logic 0, the USB bus

has left ‘suspend’ mode and the process must be aborted. Otherwise, the next

step can be executed.

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4. To meet the ‘suspend’ current requirements for a bus-powered device, the

internal clocks must be switched off by clearing bit CLKRUN in the Hardware

Conﬁguration Register.

5. When the ﬁrmware has set and cleared the GOSUSP bit in the Mode Register,

the ISP1181 enters ‘suspend’ state. In powered-off application, the ISP1181

asserts output SUSPEND and switches off the internal clocks after 2 ms.

11.1.1 Powered-on application

In powered-on application (PWROFF = 0 in the Hardware Conﬁguration Register) the

power supply of the CPU and other parts of the circuit is not switched off. The CPU is

normally placed in low-power mode. The SUSPEND output of ISP1181 is normally

HIGH and pulses LOW for 10 ms upon a ‘resume’ condition. This signal can be used

to wake up the CPU. The signal timing is shown in Figure 6.

^{handbook, full}G^paO^geS^wU^idS^thP

WAKEUP

0.5 ms

10 ms

SUSPEND

MGS780

Fig 6. Suspend and resume timing for powered-on application.

In powered-on application ISP1181 drives its output pins, while the inputs are driven

by the application. Bi-directional pins are placed in three-state and driven HIGH or

LOW by the application. A summary of appropriate pin states is given in Table 12.

Table 12: Pin states in powered-on application

Type

Appropriate state

A0

I/O (three-state) externally driven^[1]to logic 0 or logic 1

DATA[15:0]

SUSPEND

WAKEUP

INT

I/O (three-state) depends on state of inputs RD and CS

O

ISP1181 drives logic 1

I

externally driven to logic 1

O (three-state)

ISP1181 drives logic 0 or logic 1

externally driven to logic 1

RESET

CS

I

externally driven to logic 0 or logic 1 (default: logic 1)

externally driven to logic 1

RD

I

WR

I

XTAL1

CLKOUT

I

externally driven to logic 1, if external oscillator is used

ISP1181 drives logic 0

O (three-state)

[1] ‘Externally driven’ refers to logic outside the ISP1181.

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The USB connections D+ and D− remain powered and logically connected to the

USB bus. If a crystal oscillator is used, powering down during ‘suspend’ is managed

by the internal logic of ISP1181. When using an external oscillator on pin XTAL1, a

stable logic 1 level must be applied during ‘suspend’ state.

Figure 7 shows a typical bus-powered modem application using ISP1181 in

powered-on mode. The SUSPEND output is connected to the reset input (RST) of the

8031 microcontroller via an external inverter. This allows a ‘resume’ condition to wake

up the 8031 from power-down mode. The ISP1181 is woken up via the USB bus

(global resume) or by the ring detection circuit on the telephone line.

idth

V

BUS

V

CC

8031

RST

V

CC(5.0)

D+

D−

USB

ISP1181

SUSPEND

WAKEUP

RING DETECTION

LINE

MGS781

Fig 7. SUSPEND and WAKEUP signals in a powered-on modem application.

11.1.2 Powered-off application

In powered-off application (PWROFF = 1 in the Hardware Conﬁguration Register) the

supply of the CPU and other parts of the circuit is removed during ‘suspend’ state.

The SUSPEND output is active HIGH during ‘suspend’ state, making it suitable as a

power switch control signal, e.g. for an external oscillator.

Input pins of ISP1181 are pulled to ground via the pin buffers. Outputs are made

three-state to prevent current ﬂowing in the application. Bi-directional pins are made

three-state and must be pulled to ground externally by the application. The power

supply of external pull-ups must also be removed to reduce power consumption.

handbook, full pagewidth

GOSUSP

WAKEUP

2 ms

0.5 ms

SUSPEND

MGS782

Fig 8. Suspend and resume timing for powered-off application.

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Table 13: Pin states in powered-off application

Type

Appropriate state

A0

I/O (three-state) powered off; internally connected to ground (logic 0)

DATA[15:0]

SUSPEND

WAKEUP

INT

O

ISP1181 drives logic 1

I

powered off; internally connected to ground (logic 0)

externally driven^[1]to logic 1

O (three-state)

RESET

CS

I

powered off; internally connected to ground (logic 0)

ISP1181 drives logic 0

RD

I

WR

I

XTAL1

CLKOUT

I

O (three-state)

[1] ‘Externally driven’ refers to logic outside the ISP1181.

When external components are powered-off, it is possible that interface signals RD,

WR and CS have unknown values immediately after leaving ‘suspend’ state. To

prevent corruption of its internal registers, ISP1181 enables a locking mechanism

once suspend is enabled.

After wake-up from suspend’ state, all internal registers except the Unlock Register

are write-protected. A special unlock operation is needed to re-enable write access.

This prevents data corruption during power-up of external components.

Figure 9 shows a typical bus-powered modem application using ISP1181 in

powered-off mode. The SUSPEND output is used to switch off power to the

microcontroller and other external circuits during ‘suspend’ state. The ISP1181 is

woken up via the USB bus (global resume) or by the ring detection circuit on the

telephone line.

idth

V

BUS

V

CC

power

switch

MICRO-

CONTROLLER

V

CC(5.0)

D+

D−

USB

ISP1181

SUSPEND

WAKEUP

RING DETECTION

LINE

MGS783

Fig 9. SUSPEND and WAKEUP signals in a powered-off modem application.

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11.2 Resume conditions

For both application modes (powered-on and powered-off) wake-up from ‘suspend’

state is initiated either by the USB host or by the application:

USB host: drives a K-state on the USB bus (global resume)

•

Application: remote wake-up via a HIGH level on input WAKEUP or a LOW level

on input CS (if enabled via bit WKUPCS in the Hardware Conﬁguration Register).

The steps of a wake-up sequence are as follows:

1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the

clock signals are routed to all internal circuits of the ISP1181.

2. The SUSPEND output is de-asserted and the RESUME bit in the Interrupt

Register is set. This will generate an interrupt if bit IERESUME in the Interrupt

Enable Register is set.

3. Maximum 15 ms after starting the wake-up sequence the ISP1181 resumes its

normal functionality.

4. In case of a remote wake-up ISP1181 drives a K-state on the USB bus for 10 ms.

5. Following the de-assertion of output SUSPEND, the application restores itself

and other system components to normal operating mode.

6. After wake-up the internal registers of ISP1181 are write-protected to prevent

corruption by inadvertent writing during power-up of external components. The

ﬁrmware must send an Unlock Device command to the ISP1181 to restore its full

functionality. See Section 12.3.2 for more details.

11.3 Control bits in suspend and resume

Table 14: Summary of control bits

Register

Bit

Function

Interrupt

SUSPND

a transition from ‘awake’ to ‘suspend’ state was

detected

BUSTATUS

monitors USB bus status (logic 1 = suspend);

used when interrupt is serviced

Interrupt Enable

Mode

IESUSP

SOFTCT

GOSUSP

enables output INT to signal ‘suspend’ state

enables SoftConnect pull-up resistor to USB bus

a HIGH-to-LOW transition enables ‘suspend’

state

SNDRSU

EXTPUL

a HIGH-to-LOW transition enables sending a

10 ms resume signal (K-state)

Hardware

Conﬁguration

selects internal (SoftConnect) or external pull-up

resistor

WKUPCS

PWROFF

all

enables wake-up on LOW level of input CS

selects powered-off mode during ‘suspend’ state

Unlock

sending data AA37H unlocks the internal

registers for writing after a ‘resume’

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12. Commands and registers

The functions and registers of ISP1181 are accessed via commands, which consist

of a command code followed by optional data bytes (read or write action). An

overview of the available commands and registers is given in Table 15.

A complete access consists of two phases:

1. Command phase: when address bit A0 = 1, the ISP1181 interprets the data on

the lower byte of the bus (bits D7 to D0) as a command code. Commands without

a data phase are executed immediately.

2. Data phase (optional): when address bit A0 = 0, the ISP1181 transfers the data

on the bus to or from a register or endpoint FIFO. Multi-byte registers are

accessed least signiﬁcant byte/word ﬁrst.

The following applies for register or FIFO access in 16-bit bus mode:

The upper byte (bits D15 to D8) in command phase or the undeﬁned byte in data

phase are ignored.

•

The access of registers is word-aligned: byte access is not allowed.

•

If the packet length is odd, the upper byte of the last word in an IN endpoint buffer

is not transmitted to the host. When reading from an OUT endpoint buffer, the

upper byte of the last word must be ignored by the ﬁrmware. The packet length is

stored in the ﬁrst 2 bytes of the endpoint buffer.

Table 15: Command and register summary

Name

Destination

Code (Hex)

Transaction^[1]

Initialization commands

Write Control OUT Conﬁguration

[6]

Endpoint Conﬁguration Register

endpoint 0 OUT

20

write 1 byte/word

read 1 byte/word

Write Control IN Conﬁguration

Endpoint Conﬁguration Register

endpoint 0 IN

21

[6] [3]

[6]

Write Endpoint n Conﬁguration

(n = 1 to 14)

Endpoint Conﬁguration Register

endpoint 1 to 14

22 to 2F

30

Read Control OUT Conﬁguration

Endpoint Conﬁguration Register

endpoint 0 OUT

[6]

Read Control IN Conﬁguration

Endpoint Conﬁguration Register

endpoint 0 IN

31

[6]

Read Endpoint n Conﬁguration

(n = 1 to 14)

Endpoint Conﬁguration Register

endpoint 1 to 14

32 to 3F

[6]

Write/Read Device Address

Write/Read Mode Register

Address Register

Mode Register

B6/B7

B8/B9

BA/BB

C2/C3

write/read 1 byte/word

write/read 4 bytes

Write/Read Hardware Conﬁguration Hardware Conﬁguration Register

Write/Read Interrupt Enable

Register

Interrupt Enable Register

[6]

Write/Read DMA Conﬁguration

Write/Read DMA Counter

Reset Device

DMA Conﬁguration Register

DMA Counter Register

resets all registers

F0/F1

F2/F3

F6

write/read 1 byte/word

write/read 2 bytes

none

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Table 15: Command and register summary

Name

Destination

Code (Hex)

Transaction^[1]

Data ﬂow commands

Write Control OUT Buffer

Write Control IN Buffer

illegal: endpoint is read-only

FIFO endpoint 0 IN

(00)

-

01

N ≤ 64 bytes

Write Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14

(IN endpoints only)

02 to 0F

isochronous: N ≤ 1023 bytes

interrupt/bulk: N ≤ 64 bytes

N ≤ 64 bytes

Read Control OUT Buffer

Read Control IN Buffer

FIFO endpoint 0 OUT

10

illegal: endpoint is write-only

(11)

-

Read Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14

(OUT endpoints only)

12 to 1F

isochronous:

N ≤ 1023 bytes^[7]

interrupt/bulk: N ≤ 64 bytes

[6]

Write Control OUT Status

Write Control IN Status

Endpoint Status Register

endpoint 0 OUT

40

write 1 byte/word

[6]

Endpoint Status Register

endpoint 0 IN

41

write 1 byte/word

[6]

Write Endpoint n Status

(n = 1 to 14)

Endpoint Status Register n

endpoint 1 to 14

42 to 4F

50

write 1 byte/word

[6]

Read Control OUT Status

Endpoint Status Register

endpoint 0 OUT

read 1 byte/word

[6]

Read Control IN Status

Endpoint Status Register

endpoint 0 IN

51

read 1 byte/word

[6]

Read Endpoint n Status

(n = 1 to 14)

Endpoint Status Register n

endpoint 1 to 14

52 to 5F

read 1 byte/word

Validate Control OUT Buffer

Validate Control IN Buffer

illegal: IN endpoints only^[2]

FIFO endpoint 0 IN^[2]

(60)

-

61

none^[3]

Validate Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14

(IN endpoints only)^[2]

62 to 6F

Clear Control OUT Buffer

Clear Control IN Buffer

FIFO endpoint 0 OUT

illegal^[4]

70

none^[3]

-

(71)

Clear Endpoint n Buffer

(n = 1 to 14)

FIFO endpoint 1 to 14

(OUT endpoints only)^[4]

72 to 7F

none^[3]

[6]

Check Control OUT Status ^[5]

Endpoint Status Image Register

endpoint 0 OUT

D0

read 1 byte/word

[6]

Check Control IN Status ^[5]

Endpoint Status Image Register

endpoint 0 IN

D1

read 1 byte/word

[6]

Check Endpoint n Status

(n = 1 to 14)^[5]

Endpoint Status Image Register n

endpoint 1 to 14

D2 to DF

F4

read 1 byte/word

Acknowledge Setup

Endpoint 0 IN and OUT

none^[3]

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Table 15: Command and register summary

Name

Destination

Code (Hex)

Transaction^[1]

General commands

Read Control OUT Error Code

[6]

Error Code Register

endpoint 0 OUT

A0

read 1 byte/word

[6]

Read Control IN Error Code

Error Code Register

endpoint 0 IN

A1

read 1 byte/word

[6]

Read Endpoint n Error Code

(n = 1 to 14)

Error Code Register

endpoint 1 to 14

A2 to AF

read 1 byte/word

Unlock Device

all registers with write access

Scratch Register

B0

write 2 bytes

write/read 2 bytes

read 2 bytes

read 4 bytes

Write/Read Scratch Register

Read Frame Number

Read Chip ID

B2/B3

B4

Frame Number Register

Chip ID Register

B5

Read Interrupt Register

Interrupt Register

C0

[1] With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) DIV 2.

[2] Validating an OUT endpoint buffer causes unpredictable behaviour of ISP1181.

[3] In 8-bit bus mode this command requires more time to complete than other commands. See Table 60.

[4] Clearing an IN endpoint buffer causes unpredictable behaviour of ISP1181.

[5] Reads a copy of the Status Register: executing this command does not clear any status bits or interrupt bits.

[6] In 8-bit mode, the upper byte is invalid.

[7] During isochronous transfer in 16-bit mode, because N ≤ 1023, the ﬁrmware must take care of the upper byte.

12.1 Initialization commands

Initialization commands are used during the enumeration process of the USB

network. These commands are used to conﬁgure and enable the embedded

endpoints. They also serve to set the USB assigned address of ISP1181 and to

perform a device reset.

12.1.1 Write/Read Endpoint Conﬁguration

This command is used to access the Endpoint Conﬁguration Register (ECR) of the

target endpoint. It deﬁnes the endpoint type (isochronous or bulk/interrupt), direction

(OUT/IN), FIFO size and buffering scheme. It also enables the endpoint FIFO. The

register bit allocation is shown in Table 16. A bus reset will disable all endpoints.

The allocation of FIFO memory only takes place after all 16 endpoints have been

conﬁgured in sequence (from endpoint 0 OUT to endpoint 14). Although the control

endpoints have ﬁxed conﬁgurations, they must be included in the initialization

sequence and be conﬁgured with their default values (see Table 4). Automatic FIFO

allocation starts when endpoint 14 has been conﬁgured.

Remark: If any change is made to an endpoint conﬁguration which affects the

allocated memory (size, enable/disable), the FIFO memory contents of all endpoints

becomes invalid. Therefore, all valid data must be removed from enabled endpoints

before changing the conﬁguration.

Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)

Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)

Transaction — write/read 1 byte

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Table 16: Endpoint Conﬁguration Register: bit allocation

Bit

7

FIFOEN

0

6

EPDIR

0

5

DBLBUF

0

4

FFOISO

0

3

2

1

0

Symbol

Reset

Access

FFOSZ[3:0]

0

R/W

Table 17: Endpoint Conﬁguration Register: bit description

Bit

Symbol

Description

7

FIFOEN

A logic 1 indicates an enabled FIFO with allocated memory.

A logic 0 indicates a disabled FIFO (no bytes allocated).

6

EPDIR

This bit deﬁnes the endpoint direction (0 = OUT, 1 = IN); it also

determines the DMA transfer direction (0 = read, 1 = write)

5

4

DBLBUF

FFOISO

A logic 1 indicates that this endpoint has double buffering.

A logic 1 indicates an isochronous endpoint. A logic 0 indicates

a bulk or interrupt endpoint.

3 to 0

FFOSZ[3:0]

Selects the FIFO size according to Table 5

12.1.2 Write/Read Device Address

This command is used to set the USB assigned address in the Address Register and

enable the USB device. The Address Register bit allocation is shown in Table 18.

A USB bus reset sets the device address to 00H and enables the device. In response

to the standard USB request Set Address the ﬁrmware must issue a Write Device

Address command, followed by sending an empty packet to the host. The new device

address is activated when the host acknowledges the empty packet.

Code (Hex): B6/B7 — write/read Address Register

Transaction — write/read 1 byte

Table 18: Address Register: bit allocation

Bit

7

DEVEN

0

6

5

4

3

2

1

0

Symbol

Reset

Access

DEVADR[6:0]

0

R/W

Table 19: Address Register: bit description

Bit

7

Symbol

Description

A logic 1 enables the device.

DEVEN

6 to 0

DEVADR[6:0] This ﬁeld speciﬁes the USB device address.

12.1.3 Write/Read Mode Register

This command is used to access the ISP1181 Mode Register, which consists of

1 byte (bit allocation: see Table 19). In 16-bit bus mode the upper byte is ignored.

The Mode Register controls the DMA bus width, resume and suspend modes,

interrupt activity, GoodLink signalling and SoftConnect operation. It can be used to

enable debug mode, where all errors and Not Acknowledge (NAK) conditions will

generate an interrupt.

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Code (Hex): B8/B9 — write/read Mode Register

Transaction — write/read 1 byte

Table 20: Mode Register: bit allocation

Bit

7

DMAWD

0^[1]

6

SNDRSU

0

5

GOSUSP

0

4

reserved

0

3

INTENA

0^[1]

2

DBGMOD

0^[1]

1

DISGLBL

0^[1]

0

SOFTCT

0^[1]

Symbol

Reset

Access

R/W

[1] Unchanged by a bus reset.

Table 21: Mode Register: bit description

Bit

Symbol

Description

7

DMAWD

A logic 1 selects 16-bit DMA bus width (bus conﬁguration modes

0 and 2). A logic 0 selects 8-bit DMA bus width. Bus reset value:

unchanged.

6

5

SNDRSU

GOSUSP

Writing a logic 1 followed by a logic 0 will generate an upstream

‘resume’ signal of 10 ms duration, after a 5 ms delay.

Writing a logic 1 followed by a logic 0 will activate ‘suspend’

mode.

4

3

2

-

reserved

INTENA

DBGMOD

A logic 1 enables all interrupts. Bus reset value: unchanged.

A logic 1 enables debug mode. where all NAKs and errors will

generate an interrupt. A logic 0 selects normal operation, where

interrupts are generated on every ACK (bulk endpoints) or after

every data transfer (isochronous endpoints). Bus reset value:

unchanged.

1

0

DISGLBL

SOFTCT

A logic 1 disables GoodLInk LED blinking on USB trafﬁc. The

LED will be continuously on (GL = LOW) after successful

enumeration. Bus reset value: unchanged.

A logic 1 enables SoftConnect (see Section 7.4). This bit is

ignored if EXTPUL = 1 in the Hardware Conﬁguration Register

(see Table 22). Bus reset value: unchanged.

12.1.4 Write/Read Hardware Conﬁguration

This command is used to access the Hardware Conﬁguration Register, which

consists of 2 bytes. The ﬁrst (lower) byte contains the device conﬁguration and

control values, the second (upper) byte holds the clock control bits and the clock

division factor. The bit allocation is given in Table 22. A bus reset will not change any

of the programmed bit values.

The Hardware Conﬁguration Register controls the connection to the USB bus, clock

activity and power supply during ‘suspend’ state, output clock frequency, DMA

operating mode and pin conﬁgurations (polarity, signalling mode).

Code (Hex): BA/BB — write/read Hardware Conﬁguration Register

Transaction — write/read 2 bytes

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Table 22: Hardware Conﬁguration Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

EXTPUL

NOLAZY

CLKRUN

CKDIV[3:0]

0

R/W

7

0

R/W

6

1

R/W

5

0

R/W

4

0

1

R/W

1

R/W

0

R/W

3

WKUPCS

0

2

PWROFF

1

Symbol

Reset

Access

DAKOLY

0

DRQPOL

1

DAKPOL

0

EOTPOL

0

INTLVL

0

INTPOL

0

R/W

Table 23: Hardware Conﬁguration Register: bit description

Bit

15

14

Symbol

-

Description

reserved

EXTPUL

A logic 1 indicates that an external 1.5 kΩ pull-up resistor is

used on pin D+ and that SoftConnect is not used. Bus reset

value: unchanged.

13

12

NOLAZY

CLKRUN

A logic 1 disables output on pin CLKOUT of the LazyClock

frequency (24 kHz) during ‘suspend’ state. A logic 0 causes pin

CLKOUT to switch to LazyClock output after approximately 2 ms

delay, following the setting of bit GOSUSP in the Mode Register.

Bus reset value: unchanged.

A logic 1 indicates that the internal clocks are always running,

even during ‘suspend’ state. A logic 0 switches off the internal

oscillator and PLL, when they are not needed. During ‘suspend’

state this bit must be made logic 0 to meet the suspend current

requirements. The clock is stopped after a delay of

approximately 2 ms, following the setting of bit GOSUSP in the

Mode Register. Bus reset value: unchanged.

11 to 8

CKDIV[3:0]

This ﬁeld speciﬁes the clock division factor N, which controls the

clock frequency on output CLKOUT. The output frequency in

MHz is given by 48 ⁄ (N + 1) . The clock frequency range is

3 to 48 MHz (N = 0 to 15). with a reset value of 12 MHz (N = 3).

The hardware design guarantees no glitches during frequency

change. Bus reset value: unchanged.

7

6

5

4

3

DAKOLY

DRQPOL

DAKPOL

EOTPOL

WKUPCS

A logic 1 selects DACK-only DMA mode. A logic 0 selects 8237

compatible DMA mode. Bus reset value: unchanged.

Selects DREQ signal polarity (0 = active LOW, 1 = active

HIGH). Bus reset value: unchanged.

Selects DACK signal polarity (0 = active LOW, 1 = active HIGH).

Bus reset value: unchanged.

Selects EOT signal polarity (0 = active LOW, 1 = active HIGH).

Bus reset value: unchanged.

A logic 1 enables remote wake-up via a LOW level on input CS.

Bus reset value: unchanged.

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Table 23: Hardware Conﬁguration Register: bit description

Bit

Symbol

Description

2

PWROFF

A logic 1 enables powering-off during ‘suspend’ state. Output

SUSPEND is conﬁgured as a power switch control signal for

external devices (HIGH during ‘suspend’). Bus reset value:

unchanged.

1

0

INTLVL

Selects the interrupt signalling mode on output INT (0 = level,

1 = pulsed). In pulsed mode an interrupt produces an 83 ms

pulse. See Section 13 for details. Bus reset value: unchanged.

INTPOL

Selects INT signal polarity (0 = active LOW, 1 = active HIGH).

Bus reset value: unchanged.

12.1.5 Write/Read Interrupt Enable Register

This command is used to individually enable/disable interrupts from all endpoints, as

well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,

resume, reset). A bus reset will not change any of the programmed bit values.

The command accesses the Interrupt Enable Register, which consists of 4 bytes. The

bit allocation is given in Table 24.

Code (Hex): C2/C3 — write/read Interrupt Enable Register

Transaction — write/read 4 bytes

Table 24: Interrupt Enable Register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R/W

23

0

R/W

22

0

R/W

21

0

R/W

19

0

R/W

18

0

R/W

17

0

R/W

16

R/W

20

Symbol

Reset

Access

Bit

IEP14

0

IEP13

0

IEP12

0

IEP11

0

IEP10

0

IEP9

0

IEP8

0

IEP7

0

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

Symbol

Reset

Access

Bit

IEP6

0

IEP5

0

IEP4

0

IEP3

0

IEP2

0

IEP1

0

IEP0IN

0

IEP0OUT

0

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

Access

reserved

0

reserved

0

IENOSOF

0

IESOF

0

IEEOT

0

IESUSP

0

IERESM

0

IERST

0

R/W

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Table 25: Interrupt Enable Register: bit description

Bit

Symbol

Description

31 to 24

-

reserved; must write logic 0

23 to 10

IEP14 to IEP1 A logic 1 enables interrupts from the indicated endpoint.

9

IEP0IN

IEP0OUT

-

A logic 1 enables interrupts from the control IN endpoint.

A logic 1 enables interrupts from the control OUT endpoint.

reserved

8

7, 6

5

IENOSOF

IESOF

IEEOT

IESUSP

IERESM

IERST

A logic 1 enables 1 ms interrupts upon loss of SOF.

A logic 1 enables interrupt upon SOF detection.

A logic 1 enables interrupt upon EOT detection.

A logic 1 enables interrupt upon detection of ‘suspend’ state.

A logic 1 enables interrupt upon detection of a ‘resume’ state.

A logic 1 enables interrupt upon detection of a bus reset.

4

3

2

1

0

12.1.6 Write/Read DMA Conﬁguration

This command deﬁnes the DMA conﬁguration of ISP1181 and enables/disables DMA

transfers. The command accesses the DMA Conﬁguration Register, which consists of

2 bytes. The bit allocation is given in Table 26. A bus reset will clear bits DMAEN and

AUTOLD (DMA and auto-restart disabled), all other bits remain unchanged.

Code (Hex): F0/F1 — write/read DMA Conﬁguration

Transaction — write/read 2 bytes

Table 26: DMA Conﬁguration Register: bit allocation

Bit

15

CNTREN

0^[1]

14

SHORTP

0^[1]

13

reserved

0^[1]

12

reserved

0^[1]

11

reserved

0^[1]

10

reserved

0^[1]

9

reserved

0^[1]

8

reserved

0^[1]

Symbol

Reset

Access

Bit

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

7

6

Symbol

Reset

Access

EPDIX[3:0]

DMAEN

0

AUTOLD

0

BURSTL[1:0]

0^[1]

R/W

[1] Unchanged by a bus reset.

Table 27: DMA Conﬁguration Register: bit description

Bit

Symbol

Description

15

CNTREN

A logic 1 enables the generation of an EOT condition, when the

DMA Counter Register reaches zero. Bus reset value:

unchanged.

14

SHORTP

A logic 1 enables short/empty packet mode. When receiving

(OUT endpoint) a short/empty packet an EOT condition is

generated. When transmitting (IN endpoint) an empty packet is

appended when needed. Bus reset value: unchanged.

13 to 8

7 to 4

-

reserved

EPDIX[3:0]

Indicates the destination endpoint for DMA, see Table 7.

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Table 27: DMA Conﬁguration Register: bit description

Bit

Symbol

Description

3

DMAEN

Writing a logic 1 enables DMA transfer, a logic 0 forces the end

of an ongoing DMA transfer and generates an EOT interrupt.

Reading this bit indicates whether DMA is enabled (0 = DMA

stopped, 1 = DMA enabled). This bit is cleared by a bus reset.

2

AUTOLD

A logic 1 enables automatic restarting of DMA transfers. This bit

is cleared by a bus reset.

1 to 0

BURSTL[1:0] Selects the DMA burst length:

00 — single-cycle mode (1 byte)

01 — burst mode (4 bytes)

10 — burst mode (8 bytes)

11 — burst mode (16 bytes).

Bus reset value: unchanged.

12.1.7 Write/Read DMA Counter

This command accesses the DMA Counter Register, which consists of 2 bytes. The

bit allocation is given in Table 28. Writing to the register sets the number of bytes for a

DMA transfer. Reading the register returns the number of remaining bytes in the

current transfer. A bus reset will not change the programmed bit values.

The internal DMA counter is automatically reloaded from the DMA Counter Register,

when DMA is re-enabled (DMAEN = 1) or upon completion of a DMA transfer, when

auto-restart is enabled (AUTOLD = 1). See Section 12.1.6 for more details.

Code (Hex): F2/F3 — write/read DMA Counter Register

Transaction — write/read 2 bytes

Table 28: DMA Counter Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

DMACRH[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

DMACRL[7:0]

0

R/W

Table 29: DMA Counter Register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

DMACRH[7:0] DMA Counter Register (high byte)

DMACRL[7:0] DMA Counter Register (low byte)

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12.1.8 Reset Device

This command resets the ISP1181 in the same way as an external hardware reset via

input RESET. All registers are initialized to their ‘reset’ values.

Code (Hex): F6 — reset the device

Transaction — none

12.2 Data ﬂow commands

Data ﬂow commands are used to manage the data transmission between the USB

endpoints and the system microcontroller. Much of the data ﬂow is initiated via an

interrupt to the microcontroller. The data ﬂow commands are used to access the

endpoints and determine whether the endpoint FIFOs contain valid data.

Remark: The IN buffer of an endpoint contains input data for the host, the OUT buffer

receives output data from the host.

12.2.1 Write/Read Endpoint Buffer

This command is used to access endpoint FIFO buffers for reading or writing. First,

the buffer pointer is reset to the beginning of the buffer. Following the command, a

maximum of (N + 2) bytes can be written or read, N representing the size of the

endpoint buffer. For 16-bit access the maximum number of words is (M + 1), with M

given by (N + 1) DIV 2. After each read/write action the buffer pointer is automatically

incremented by 1 (8-bit bus width) or by 2 (16-bit bus width).

In DMA access the ﬁrst 2 bytes or the ﬁrst word (the packet length) are skipped:

transfers start at the third byte or the second word of the endpoint buffer. When

reading, the ISP1181 can detect the last byte/word via the EOP condition. When

writing to a bulk/interrupt endpoint, the endpoint buffer must be completely ﬁlled

before sending the data to the host. Exception: when a DMA transfer is stopped by an

external EOT condition, the current buffer content (full or not) is sent to the host.

Remark: Reading data after a Write Endpoint Buffer command or writing data after a

Read Endpoint Buffer command data will cause unpredictable behaviour of ISP1181.

Code (Hex): 01 to 0F — write (control IN, endpoint 1 to 14)

Code (Hex): 10, 12 to 1F — read (control OUT, endpoint 1 to 14)

Transaction — write/read maximum N + 2 bytes (isochronous endpoint: N ≤ 1023,

bulk/interrupt endpoint: N ≤ 32)

The data in the endpoint FIFO must be organized as shown in Table 30. Examples of

endpoint FIFO access are given in Table 31 (8-bit bus) and Table 32 (16-bit bus).

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Table 30: Endpoint FIFO organization

Byte #

(8-bit bus)

Word #

(16-bit bus)

Description

0

0 (lower byte)

0 (upper byte)

1 (lower byte)

1 (upper byte)

..

packet length (lower byte)

packet length (upper byte)

data byte 1

1

2

3

data byte 2

..

(N + 1)

M = (N + 1) DIV 2

data byte N

Table 31: Example of endpoint FIFO access (8-bit bus width)

A0

1

Phase

command

data

Bus lines

D[7:0]

..

Byte #

Description

-

command code (00H to 1FH)

packet length (lower byte)

packet length (upper byte)

data byte 1

0

1

2

3

4

5

..

0

data

0

data

0

data

data byte 2

0

data

data byte 3

0

data

data byte 4

..

Table 32: Example of endpoint FIFO access (16-bit bus width)

A0

Phase

Bus lines

D[7:0]

Word #

Description

1

command

-

command code (00H to 1FH)

D[15:8]

D[15:0]

..

-

ignored

0

..

data

..

0

1

2

..

packet length

data word 1 (data byte 2, data byte 1)

data word 2 (data byte 4, data byte 3)

..

Remark: There is no protection against writing or reading past a buffer’s boundary,

against writing into an OUT buffer or reading from an IN buffer. Any of these actions

could cause an incorrect operation. Data residing in an OUT buffer are only

meaningful after a successful transaction. Exception: during DMA access of a

double-buffered endpoint, the buffer pointer automatically points to the secondary

buffer after reaching the end of the primary buffer.

12.2.2 Write/Read Endpoint Status

This command is used to read the status of the endpoint FIFO or stall the endpoint by

writing. The command accesses the Endpoint Status Register, the bit allocation of

which is shown in Table 33.

A stalled control endpoint is automatically unstalled when it receives a SETUP token,

regardless of the packet content. If the endpoint should stay in its stalled state, the

microcontroller can re-stall it with the Write Endpoint Status command.

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When a stalled endpoint is unstalled (either by the Set Endpoint Status command or

by receiving a SETUP token), it is also re-initialized. This ﬂushes the buffer: in and if it

is an OUT buffer it waits for a DATA 0 PID, if it is an IN buffer it writes a DATA 0 PID.

Code (Hex): 40 to 4F — write (control OUT, control IN, endpoint 1 to 14)

Code (Hex): 50 to 5F — read (control OUT, control IN, endpoint 1 to 14)

Transaction — write/read 1 byte

Table 33: Endpoint Status Register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

EPSTAL

EPFULL1

EPFULL0

reserved

OVER

SETUPT

CPUBUF

reserved

WRITE

Reset

0

Access

R/W

R

R/W

R

R/W

Table 34: Endpoint Status Register: bit description

Bit

Symbol

Description

7

EPSTAL

Writing a logic 1 will stall the endpoint. The endpoint is

automatically unstalled upon reception of a SETUP token.

Reading this bit indicates whether the endpoint is stalled or not

(1 = stalled, 0 = not stalled).

6

5

4

3

EPFULL1

EPFULL0

-

A logic 1 indicates that the secondary endpoint buffer is full.

A logic 1 indicates that the primary endpoint buffer is full.

reserved

OVERWRITE This bit is set by hardware, a logic 1 indicating that a new Setup

packet has overwritten the previous setup information, before it

was acknowledged or before the endpoint was stalled. This bit is

cleared by reading, if writing the setup data has ﬁnished.

Firmware must check this bit before sending an Acknowledge

Setup command or stalling the endpoint. Upon reading a logic 1

the ﬁrmware must stop ongoing setup actions and wait for a new

Setup packet.

2

1

SETUPT

CPUBUF

A logic 1 indicates that the buffer contains a Setup packet.

This bit indicates which buffer is currently selected for CPU

access (0 = primary buffer, 1 = secondary buffer).

0

-

reserved

12.2.3 Validate Endpoint Buffer

This command signals the presence of valid data for transmission to the USB host, by

setting the Buffer Full ﬂag of the selected IN endpoint. This indicates that the data in

the buffer is valid and can be sent to the host, when the next IN token is received. For

a double-buffered endpoint this command switches the current FIFO for CPU access.

Remark: For special aspects of the control IN endpoint see Section 9.5.

Code (Hex): 61 to 6F — validate endpoint buffer (control IN, endpoint 1 to 14)

Transaction — none

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12.2.4 Clear Endpoint Buffer

This command unlocks and clears the buffer of the selected OUT endpoint, allowing

the reception of new packets. Reception of a complete packet causes the Buffer Full

ﬂag of an OUT endpoint to be set. Any subsequent packets are refused by returning a

NAK condition, until the buffer is unlocked using this command. For a double-buffered

endpoint this command switches the current FIFO for CPU access.

Remark: For special aspects of the control OUT endpoint see Section 9.5.

Code (Hex): 70, 72 to 7F — clear endpoint buffer (control OUT, endpoint 1 to 14)

Transaction — none

12.2.5 Check Endpoint Status

This command is used to check the status of the selected endpoint FIFO without

clearing any status or interrupt bits. The command accesses the Endpoint Status

Image Register, which contains a copy of the Endpoint Status Register. The bit

allocation of the Endpoint Status Image Register is shown in Table 35.

Code (Hex): D0 to DF — check status (control OUT, control IN, endpoint 1 to 14)

Transaction — write/read 1 byte

Table 35: Endpoint Status Image Register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

EPSTAL

EPFULL1

EPFULL0

reserved

OVER

SETUPT

CPUBUF

reserved

WRITE

Reset

0

Access

R

Table 36: Endpoint Status Image Register: bit description

Bit

Symbol

Description

7

EPSTAL

This bit indicates whether the endpoint is stalled or not

(1 = stalled, 0 = not stalled).

6

5

4

3

EPFULL1

EPFULL0

-

A logic 1 indicates that the secondary endpoint buffer is full.

A logic 1 indicates that the primary endpoint buffer is full.

reserved

OVERWRITE This bit is set by hardware, a logic 1 indicating that a new Setup

packet has overwritten the previous setup information, before it

was acknowledged or before the endpoint was stalled. This bit is

cleared by reading, if writing the setup data has ﬁnished.

Firmware must check this bit before sending an Acknowledge

Setup command or stalling the endpoint. Upon reading a logic 1

the ﬁrmware must stop ongoing setup actions and wait for a new

Setup packet.

2

1

SETUPT

CPUBUF

A logic 1 indicates that the buffer contains a Setup packet.

This bit indicates which buffer is currently selected for CPU

access (0 = primary buffer, 1 = secondary buffer).

0

-

reserved

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12.2.6 Acknowledge Setup

This command is acknowledges to the host that a Setup packet was received. It

re-enables the Validate Buffer and Clear Buffer commands for the control IN and

control OUT endpoints. These commands are disabled automatically when a Setup

packet is received, see Section 9.5.

Remark: The Acknowledge Setup command must be sent to both control endpoints

(IN and OUT).

Code (Hex): F4 — acknowledge setup

Transaction — none

12.3 General commands

12.3.1 Read Endpoint Error Code

This command returns the status of the last transaction of the selected endpoint, as

stored in the Error Code Register. Each new transaction overwrites the previous

status information. The bit allocation of the Error Code Register is shown in Table 37.

Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)

Transaction — read 1 byte

Table 37: Error Code Register: bit allocation

Bit

7

6

5

4

3

2

1

0

RTOK

0

Symbol

Reset

Access

UNREAD

DATA01

reserved

ERROR[3:0]

0

R

Table 38: Error Code Register: bit description

Bit

Symbol

Description

7

UNREAD

A logic 1 indicates that a new event occurred before the

previous status was read.

6

DATA01

Indicates the PID type of the last successfully received packet

(0 = DATA0 PID, 1 = DATA1 PID).

5

-

reserved

4 to 1

0

ERROR[3:0]

RTOK

Error code. For error description, see Table 39.

A logic 1 indicates that data was received or transmitted

successfully.

Table 39: Transaction error codes

Error code

(Binary)

Description

0000

0001

0010

0011

no error

PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0

PID unknown; encoding is valid, but PID does not exist

unexpected packet; packet is not of the expected type (token, data, or

acknowledge), or is a SETUP token to a non-control endpoint

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Table 39: Transaction error codes

Error code

Description

(Binary)

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

token CRC error

data CRC error

time-out error

babble error

unexpected end-of-packet

sent or received NAK (Not AcKnowledge)

sent Stall; a token was received, but the endpoint was stalled

overﬂow; the received packet was larger than the available buffer space

sent empty packet (ISO only)

bit stufﬁng error

sync error

wrong (unexpected) toggle bit in DATA PID; data was ignored

12.3.2 Unlock Device

This command unlocks the ISP1181 from write-protection mode after a ‘resume’. In

‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption

by external devices during a ‘resume’. Register access for reading is not blocked.

After waking up from ‘suspend’ state, the ﬁrmware must unlock the registers and

FIFOs via this command, by writing the unlock code (AA37H) into the Lock Register

(8-bit bus: lower byte ﬁrst). The bit allocation of the Lock Register is given in Table 40.

Code (Hex): B0 — unlock the device

Transaction — write 2 bytes (unlock code)

Table 40: Lock Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

UNLOCKH[7:0] = AAH

1

W

7

0

W

6

1

W

5

0

W

4

1

W

3

0

W

2

1

W

1

0

W

0

Symbol

Reset

Access

UNLOCKL[7:0] = 37H

0

1

0

1

W

Table 41: Error Code Register: bit description

Bit

Symbol

Description

15 to 0

UNLOCK[15:0] Sending data AA37H unlocks the internal registers and FIFOs

for writing, following a ‘resume’.

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12.3.3 Write/Read Scratch Register

This command accesses the 16-bit Scratch Register, which can be used by the

ﬁrmware to save and restore information, e.g. the device status before powering

down in ‘suspend’ state. The register bit allocation is given in Table 42.

Code (Hex): B2/B3 — write/read Scratch Register

Transaction — write/read 2 bytes

Table 42: Scratch Information Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

SFIRH[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

4

Symbol

Reset

Access

SFIRL[7:0]

0

R/W

Table 43: Scratch Information Register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

SFIRH[7:0]

SFIRL[7:0]

Scratch Information Register (high byte)

Scratch Information Register (low byte)

12.3.4 Read Frame Number

This command returns the frame number of the last successfully received SOF. It is

followed by reading one or two bytes from the Frame Number Register, containing the

frame number (lower byte ﬁrst). The Frame Number Register is shown in Table 44.

Remark: After a bus reset, the value of the Frame Number Register is undeﬁned.

Code (Hex): B4 — read frame number

Transaction — read 1 or 2 bytes

Table 44: Frame Number Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset^[1]

Access

Bit

reserved

SOFRH[2:0]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset^[1]

Access

SOFRL[7:0]

0

R

[1] Reset value undeﬁned after a bus reset.

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Table 45: Example of Frame Number Register access (8-bit bus width)

A0

1

Phase

command

data

Bus lines

D[7:0]

Byte #

Description

-

command code (B4H)

0

D[7:0]

0

1

frame number (lower byte)

frame number (upper byte)

0

data

D[7:0]

Table 46: Example of Frame Number Register access (16-bit bus width)

A0

Phase

Bus lines

D[7:0]

Word #

Description

1

command

-

command code (B4H)

ignored

D[15:8]

D[15:0]

-

0

data

0

frame number

12.3.5 Read Chip ID

This command reads the chip identiﬁcation code and hardware version number. The

ﬁrmware must check this information to determine the supported functions and

features. This command accesses the Chip ID Register, which is shown in Table 47.

Code (Hex): B5 — read chip ID

Transaction — read 2 bytes

Table 47: Chip ID Register: bit allocation

Bit

15

14

13

12

CHIPIDH[7:0]

<tbd>

11

10

9

8

Symbol

Reset

Access

Bit

R

7

6

5

4

3

2

1

0

Symbol

Reset

Access

CHIPIDL[7:0]

<tbd>

R

Table 48: Scratch Information Register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

CHIPIDH[7:0] Chip ID Register (high byte)

CHIPIDL[7:0] Chip ID Register (low byte)

12.3.6 Read Interrupt Register

This command indicates the sources of interrupts as stored in the 4-byte Interrupt

Register. Each individual endpoint has its own interrupt bit. The bit allocation of the

Interrupt Register is shown in Table 49. Bit BUSTATUS is used to verify the current

bus status in the interrupt service routine. Interrupts are enabled via the Interrupt

Enable Register, see Section 12.1.5.

Code (Hex): C0 — read interrupt register

Transaction — read 4 bytes

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Table 49: Interrupt Register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

23

22

21

20

EP11

0

19

EP10

0

18

17

16

Symbol

Reset

Access

Bit

EP14

EP13

EP12

EP9

EP8

EP7

0

R

15

14

13

12

EP3

0

11

EP2

0

10

9

8

Symbol

Reset

Access

Bit

EP6

EP5

EP4

EP1

EP0IN

EP0OUT

0

R

7

6

5

4

3

2

1

0

Symbol

Reset

Access

BUSTATUS

reserved

NOSOF

SOF

0

EOT

0

SUSPND

RESUME

RESET

0

R

Table 50: Interrupt Register: bit description

Bit

Symbol

Description

31 to 24

-

reserved

23 to 10

EP14 to EP1 A logic 1 indicates the interrupt source(s): endpoint 14 to 1

9

8

7

6

5

EP0IN

EP0OUT

BUSTATUS

-

A logic 1 indicates the interrupt source: control IN endpoint

A logic 1 indicates the interrupt source: control OUT endpoint

Monitors the current USB bus status (0 = awake, 1 = suspend).

reserved

NOSOF

A logic 1 indicates that an SOF was lost; interrupt is issued

every 1 ms; after 3 missed SOFs ‘suspend’ state is entered.

4

3

SOF

EOT

A logic 1 indicates that a SOF condition was detected.

A logic 1 indicates that an internal EOT condition was generated

by the DMA Counter reaching zero.

2

SUSPND

A logic 1 indicates that an ‘awake’ to ‘suspend’ change of state

was detected on the USB bus.

1

0

RESUME

RESET

A logic 1 indicates that a ‘resume’ state was detected.

A logic 1 indicates that a bus reset condition was detected,

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13. Interrupts

Figure 10 shows the interrupt logic of the ISP1181. Each of the indicated USB events

is logged in a status bit of the Interrupt Register. Corresponding bits in the Interrupt

Enable Register determine whether or not an event will generate an interrupt.

Interrupts can be masked globally by means of the INTENA bit of the Mode Register

(see Table 21).

The active level and signalling mode of the INT output is controlled by the INTPOL

and INTLVL bits of the Hardware Conﬁguration Register (see Table 23). Default

settings after reset are active LOW and level mode. When pulse mode is selected, a

pulse of 83 ns is generated when the OR-ed combination of all interrupt bits changes

from logic 0 to logic 1.

interrupt register

handbook, full pagewidth

RESET

SUSPND

RESUME

SOF

.

EP14

...

EP0IN

EP0OUT

EOT

.

device mode

register

INTENA

interrupt enable

register

PULSE

GENERATOR

IERST

IESUSP

IERESM

IESOF

IEP14

1

0

.

hardware configuration

register

INTLVL

INTPOL

...

IEP0IN

IEP0OUT

IEEOT

INT

MGS772

Fig 10. Interrupt logic.

Bits RESET, RESUME, EOT and SOF are cleared upon reading the Interrupt

Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated

Endpoint Status Register.

Bit BUSTATUS follows the USB bus status exactly, allowing the ﬁrmware to get the

current bus status when reading the Interrupt Register.

SETUP and OUT token interrupts are generated after ISP1181 has acknowledged

the associated data packet. In bulk transfer mode, the ISP1181 will issue interrupts

for every ACK received for an OUT token or transmitted for an IN token.

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In isochronous mode, an interrupt is issued upon each packet transaction. The

ﬁrmware must take care of timing synchronization with the host. This can be done via

the loss of Start-Of-Frame (NOSOF) interrupt, enabled via bit IENOSOF in the

Interrupt Enable Register. If a Start-Of-Frame is lost, NOSOF interrupts are

generated every 1 ms. This allows the ﬁrmware to keep data transfer synchronized

with the host. After 3 missed SOF events the ISP1181 will enter ‘suspend’ state.

An alternative way of handling isochronous data transfer is to enable both the SOF

and the NOSOF interrupts and disable the interrupt for each isochronous endpoint.

14. Power supply

The ISP1181 is powered from a single supply voltage, ranging from 4.0 to 5.5 V. An

integrated voltage regulator provides a 3.3 V supply voltage for the internal logic and

the USB transceiver. This voltage is available at pin V_reg(3.3)for connecting an

external pull-up resistor on USB connection D+. See Figure 11.

The ISP1181 can also be operated from a 3.0 to 3.6 V supply, as shown in Figure 12.

In that case the internal voltage regulator is disabled and pin V_reg(3.3)must be

connected to V_CC

.

handbook, halfpage

ISP1181

V

4.0 to 5.5 V

3.0 to 3.6 V

CC(5.0)

V

n.c.

CC(3.3)

V

reg(3.3)

MGS773

MGS774

Fig 11. ISP1181 with a 4.0 to 5.5 V supply.

Fig 12. ISP1181 with a 3.0 to 3.6 V supply.

15. Crystal oscillator and LazyClock

The ISP1181 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal

(fundamental). A typical circuit is shown in Figure 13. Alternatively, an external clock

signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open.

handbook, halfpage

CLKOUT

ISP1181

18 pF

XTAL2

6 MHz

XTAL1

18 pF

MGS777

Fig 13. Typical oscillator circuit.

The 6 MHz oscillator frequency is multiplied to 48 MHz by an internal PLL. This

frequency is used to generate a programmable clock output signal at pin CLKOUT,

ranging from 3 to 48 MHz.

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In ‘suspend’ state the normal CLKOUT signal is not available, because the crystal

oscillator and the PLL are switched off to save power. Instead, the CLKOUT signal

can be switched to the LazyClock frequency of 24 kHz.

The oscillator operation and the CLKOUT frequency are controlled via the Hardware

Conﬁguration Register, as shown in Figure 14. The following bits are involved:

CLKRUN switches the oscillator on and off

•

CLKDIV[3:0] is the division factor determining the normal CLKOUT frequency

NOLAZY controls the LazyClock signal output during ‘suspend’ state.

hardware

handbook, full pagewidth

configuration

register

CLKRUN

SUSPEND

enable

6 MHz

enable

48 MHz

PLL 8×

.

1

0

XTAL OSC

÷ (N + 1)

CLKOUT

N

4

[

]

CKDIV 3:0

NOLAZY

24 kHz

LAZYCLOCK

.

enable

NOLAZY

MGS775

Fig 14. Oscillator and LazyClock logic.

When ISP1181 enters ‘suspend’ state (by setting and clearing bit GOSUSP in the

Mode Register), outputs SUSPEND and CLKOUT change state after approximately

2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but

changes to the 24 kHz LazyClock frequency.

When resuming from ‘suspend’ state by a positive pulse on input WAKEUP, output

SUSPEND is cleared and the clock signal on CLKOUT restarted after a 0.5 ms delay.

The timing of the CLKOUT signal at ‘suspend’ and ‘resume’ is given in Figure 15.

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^{handbook, full}G^paO^geS^wU^idtS^hP

WAKEUP

1.8 to 2.2 ms

0.5 ms

SUSPEND

CLKOUT

PLL circuit stable

3 to 4 ms

MGS776

If enabled, the 24 kHz LazyClock frequency will be output on pin CLKOUT during ‘suspend’ state.

Fig 15. CLKOUT signal timing at ‘suspend’ and ‘resume’.

16. Power-on reset

The ISP1181 has an internal power-on reset (POR) circuit. Input pin RESET can be

directly connected to V_CC. The clock signal on output CLKOUT starts 0.5 ms after

power-on and normally requires 3 to 4 ms to stabilize.

The triggering voltage of the POR circuit is 2.0 V nominal. A POR is automatically

generated when V_CCgoes below the trigger voltage for a duration longer than 50 µs.

POR

handbook, full pagewidth

(1)

V

CC

≤ 350 µs

1 ms

2.0 V

0 V

t

3

1

2

> 50 µs

MGT026

t₁: clock is running

t₂: BUS_CONF pins are sampled

t₃: registers are accessible

(1) Supply voltage (5 V or 3.3 V), connected externally to pin RESET.

Fig 16. Power-on reset timing.

A hardware reset disables all USB endpoints and clears all ECRs, except for the

control endpoint which is ﬁxed and always enabled. Section 9.3 explains how to

(re)initialize the endpoints.

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17. Limiting values

Table 51: Absolute maximum ratings

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

Parameter

Conditions

Min

−0.5

-

Max

Unit

V

supply voltage

+6.0

V_I

input voltage

V_CC+ 0.5

V

I_latchup

V_esd

T_stg

latchup current

V_I< 0 or V_I> V_CC

200

mA

V

[1] [2]

electrostatic discharge voltage

storage temperature

total power dissipation

I_LI< 15 µA

-

±4000^[3]

+150

−60

-

°C

mW

P_tot

<tbf>

[1] Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ resistor.

[2] Values are given for device only; in-circuit V_esd(max)= ±8000 V.

[3] For open-drain pins V_esd(max)= ±2000 V.

Table 52: Recommended operating conditions

Symbol

V_CC

Parameter

Conditions

Min

Max

5.5

3.6

Unit

supply voltage

input voltage

4.0

0

V

V_I

V_I(AI/O)

input voltage on analog I/O pins

0

(D+/D−)

V_O(od)

T_amb

open-drain output pull-up voltage

operating ambient temperature

0

V_CC

V

−40

+85

°C

18. Static characteristics

Table 53: Static characteristics; supply pins

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

V_reg(3.3)

I_CC

Parameter

Conditions

Min

3.0^[1]

Typ

3.3

<tbf>

-

Max

3.6

-

Unit

V

regulated supply voltage

operating supply current

suspend supply current

-

mA

µA

I_CC(susp

)

1.5 kΩ pull-up on upstream

port D+ (pin DP0)

<tbf>

no pull-up on upstream port

-

<tbf>

µA

D+ (pin DP0)

[1] In ‘suspend’ mode the minimum voltage is 2.7 V.

Table 54: Static characteristics: digital pins

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_IL

Parameter

Conditions

Min

Typ

Max

Unit

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

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Table 54: Static characteristics: digital pins

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Schmitt trigger inputs

V_th(LH)positive-going threshold

Parameter

Conditions

Min

Typ

Max

Unit

1.4

0.9

0.4

-

1.9

1.5

0.7

V

voltage

V_th(HL)

negative-going threshold

voltage

V_hys

hysteresis voltage

Output levels

V_OL

LOW-level output voltage

(open drain outputs)

I_OL= rated drive

-

0.4

0.1

V

I_OL= 20 µA

Leakage current

I_LI

input leakage current

-

±5

µA

Open-drain outputs

I_OZ

OFF-state output current

Table 55: Static characteristics: analog I/O pins (D+, D−)^[1]

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_DI

Parameter

Conditions

Min

Typ

Max

Unit

differential input sensitivity

|V_I(D+)− V_I(D−)

|

0.2

0.8

-

V

V_CM

differential common mode

voltage

includes V_DIrange

2.5

V_IL

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Output levels

V_OL

V_OH

LOW-level output voltage

HIGH-level output voltage

R_L= 1.5 kΩ to +3.6V

R_L= 15 kΩ to GND

-

0.3

3.6

V

2.8

Leakage current

I_LZ

OFF-state leakage current

-

±10

µA

Capacitance

C_IN

transceiver capacitance

pin to GND

20

pF

Resistance

R_PU

pull-up resistance on D+

driver output impedance

input impedance

SoftConnect = ON

steady-state drive

1.1

29

10

-

1.9

44

-

kΩ

Ω

[2]

Z_DRV

Z_INP

MΩ

Termination

[3]

V_TERM

termination voltage for

3.0^[4]

-

3.6

V

upstream port pull-up (R_PU

)

[1] D+ is the USB positive data pin; D− is the USB negative data pin.

[2] Includes external resistors of 22 Ω ±1% on both D+ and D−.

[3] This voltage is available at pin V_reg(3.3)

.

[4] In ‘suspend’ mode the minimum voltage is 2.7 V.

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19. Dynamic characteristics

Table 56: Dynamic characteristics

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Reset

Parameter

Conditions

Min

Typ

Max

Unit

t_W(RESET)

pulse width on input RESET

crystal oscillator running

crystal oscillator stopped

<tbf>

-

µs

<tbf>^[1]

ms

Crystal oscillator

f_XTAL

crystal frequency

-

6

-

MHz

[1] Dependent on the crystal oscillator start-up time.

Table 57: Dynamic characteristics: analog I/O pins (D+, D−)

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; C_L= 50 pF; R_PU= 1.5 kΩ on D+ to V_TERM.; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_FR

rise time

C_L= 50 pF;

10 to 90% of |V_OH− V_OL

4

-

20

ns

%

V

|

t_FF

fall time

C_L= 50 pF;

90 to 10% of |V_OH− V_OL

4

20

|

[2]

FRFM

differential rise/fall time

matching (t_FR/t_FF

90

1.3

111.11

2.0

)

[2] [3]

V_CRS

output signal crossover voltage

Data source timing

t_FEOPTsource EOP width

t_FDEOP

[3]

see Figure 17

160

-

175

ns

source differential data-to-EOP see Figure 17

transition skew

Receiver timing

−2

+5

[3]

t_JR1

receiver data jitter tolerance for see Figure 18

consecutive transitions

−18.5

−9

-

+18.5

+9

ns

t_JR2

receiver data jitter tolerance for see Figure 18

paired transitions

t_FEOPR

t_FST

receiver SE0 width

accepted as EOP;

see Figure 17

82

-

width of SE0 during differential rejected as EOP;

transition see Figure 19

-

14

[1] Test circuit: see Figure 38.

[2] Excluding the ﬁrst transition from Idle state.

[3] Characterized only, not tested. Limits guaranteed by design.

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T

handbook, full pagewidth

PERIOD

+3.3 V

crossover point

extended

crossover point

differential

data lines

0 V

differential data to

SE0/EOP skew

N × T + t

source EOP width: t

EOPT

receiver EOP width: t

EOPR

PERIOD DEOP

MGR776

T_PERIODis the bit duration corresponding with the USB data rate.

Full-speed timing symbols have a subscript preﬁx ‘F’, low-speed timings a preﬁx ‘L’.

Fig 17. Source differential data-to-EOP transition skew and EOP width.

T

handbook, full pagewidth

PERIOD

+3.3 V

differential

data lines

0 V

MGR871

t

JR2

JR

JR1

consecutive

transitions

N × T

+ t

PERIOD JR1

paired

transitions

N × T

+ t

PERIOD JR2

T_PERIODis the bit duration corresponding with the USB data rate.

Fig 18. Receiver differential data jitter.

handbook, halfpage

t

FST

+3.3 V

V

differential

data lines

IH(min)

0 V

MGR872

Fig 19. Receiver SE0 width tolerance.

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ISP1181

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19.1 Timing symbols

Table 58: Legend for timing characteristics

Symbol

Description

Time symbols

t

time

T

cycle time (periodic signal)

Signal names

A

address;

DMA acknowledge (DACK)

clock;

C

D

command

data input;

data

E

G

I

chip enable

output enable

instruction (program memory content);

input (general)

L

address latch enable (ALE)

program store enable (PSEN, active LOW);

propagation delay

data output

P

Q

R

read signal (RD, active LOW);

read (action);

DMA request (DREQ)

chip select

S

W

write signal (WR, active LOW);

write (action);

pulse width

U

undeﬁned

Y

output (general)

Logic levels

H

L

logic HIGH

logic LOW

P

S

V

X

Z

stop, not active (OFF)

start, active (ON)

valid logic level

invalid logic level

high-impedance (ﬂoating, three-state)

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19.2 Parallel I/O timing

Table 59: Dynamic characteristics: parallel interface timing

Symbol Parameter Conditions

8-bit bus

Max

16-bit bus

Max

Unit

Min

Read timing (see Figure 20 and Figure 21)

t_RHAX

t_AVRL

t_SHDZ

address hold after RD HIGH

address setup before RD LOW

3

0

-

3

0

-

ns

-

data outputs high-impedance

after CS HIGH

3

t_RLRH

t_RLDV

RD pulse width

25

-

25

-

ns

data valid after RD LOW

22

-

22

-

t_SHRL1

t_SHRL2

t_YHRH

read interval after CS HIGH^[1]READY pulsing

read interval after CS HIGH^[1]READY = HIGH

22

90

0

22

180

0

-

output READY HIGH before

RD HIGH

-

t_RC

read cycle duration

-

90

-

180

ns

Write timing (see Figure 22 and Figure 23)

t_WHAX

t_AVWL

t_SHWL1

t_SHWL2

t_WLWH

t_WHSH

t_DVWH

t_WHDZ

t_WC

address hold after WR HIGH

address setup before WR LOW

write interval after CS HIGH^[2]READY pulsing

write interval after CS HIGH^[2]READY = HIGH

WR pulse width

3

-

3

-

ns

0

-

22

90/180^[3]

22

180

22

0

-

22

0

-

chip deselect after WR HIGH

data setup before WR HIGH

data hold after WR HIGH

-

5

-

5

-

3

-

3

-

write cycle duration

-

90/180^[3]

-

180

ALE timing (see Figure 24)

t_LH

ALE pulse width

20

10

-

20

10

-

ns

t_AVLL

address setup before ALE

LOW

t_LLAX

address hold after ALE LOW

reading

writing

0

10

-

0

10

-

ns

[1] Measured from CS going HIGH to CS and RD both going LOW.

[2] Measured from CS going HIGH to CS and WR both going LOW.

[3] Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Conﬁguration require 180 ns to complete.

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t

handbook, full pagewidth

RHAX

SHDZ

A0

t

AVRL

RLRH

CS/DACK

(1)

t

SHRL1

RD

t

RLDV

DATA

t

RC

YHRH

READY

MGS786

(1) For t_SHRLboth CS and RD must be LOW.

Fig 20. Parallel interface read timing (I/O and 8237 compatible DMA) with READY.

handbook, full pagewidth

t

RHAX

A0

t

AVRL

SHDZ

CS/DACK

(1)

t

SHRL2

RLRH

RD

t

RLDV

DATA

READY

MGS787

(1) For t_SHRLboth CS and RD must be LOW.

Fig 21. Parallel interface read timing (I/O and 8237 compatible DMA) without READY.

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handbook, full pagewidth

t

WHAX

A0

t

AVWL

CS/DACK

(1)

t

SHWL1

WLWH

t

WHSH

WR

t

DVWH

WHDZ

DATA

t

WC

READY

MGS788

(1) For t_SHRLboth CS and WR must be LOW.

Fig 22. Parallel interface write timing (I/O and 8237 compatible DMA) with READY.

t

WHAX

handbook, full pagewidth

A0

t

AVWL

CS/DACK

t

WLWH

(1)

t

SHWL2

t

WHSH

WR

t

DVWH

WHDZ

DATA

READY

MGS789

(1) For t_SHRLboth CS and WR must be LOW.

Fig 23. Parallel interface write timing (I/O and 8237 compatible DMA) without READY.

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t

LH

handbook, full pagewidth

ALE

t

LLAX

t

AVLL

AD

DATA

A0

D0

MGS790

Fig 24. ALE timing.

19.3 Access cycle timing

Table 60: Dynamic characteristics: access cycle timing

Symbol

Parameter

Conditions

8-bit bus

16-bit bus

Unit

Min^[1]

Max

Min^[1]

Max

Write command + write data (see Figure 25 and Figure 26)

T_cy(WC-WD)

cycle time for write command,

then write data

100^[2]

-

200

-

ns

T_cy(WD-WD)

T_cy(WD-WC)

cycle time for write data

90

-

180

-

ns

cycle time for write data, then

write command

Write command + read data (see Figure 27 and Figure 28)

T_cy(WC-RD)

cycle time for write command,

then read data

100^[2]

-

200

-

ns

T_cy(RD-RD)

T_cy(RD-WC)

cycle time for read data

90

-

180

-

ns

cycle time for read data, then

write command

[1] If the access cycle time is less than speciﬁed, the READY signal will be LOW until the internal processing has ﬁnished.

[2] Commands Acknowledge Setup, Clear Buffer, Validate Buffer and Write Endpoint Conﬁguration require 180 ns to complete.

handbook, full pagewidth

DATA

command

data

T

cy(WD-WD)

cy(WC-WD)

WR

CS

MGT022

Fig 25. Write command + write data cycle timing.

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handbook, full pagewidth

DATA

data

command

data

T

cy(WD-WC)

WR

(1)

RD

CS

MGT025

(1) Example: read data.

Fig 26. Write data + write command cycle timing.

handbook, full pagewidth

DATA

WR

command

data

T

cy(WC-RD)

RD

CS

T

cy(RD-RD)

MGT023

Fig 27. Write command + read data cycle timing.

handbook, full pagewidth

DATA

WR

data

command

data

T

cy(RD-WC)

(1)

RD

CS

MGT024

(1) Example: read data.

Fig 28. Read data + write command cycle timing.

19.4 DMA timing: single-cycle mode

Table 61: Dynamic characteristics: single-cycle DMA timing

Symbol

Parameter

Conditions

8-bit bus

Max

16-bit bus

Min Max

Unit

Min

8237 compatible mode (see Figure 29)

t_ASRP

t_APRS

DREQ off after DACK on

DREQ on after DACK off

-

40

22

-

40

22

ns

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Table 61: Dynamic characteristics: single-cycle DMA timing

Symbol

Parameter

Conditions

8-bit bus

Max

16-bit bus

Max

Unit

Min

Read in DACK-only mode (see Figure 30)

t_ASRP

t_APRS

t_ASDV

t_APDZ

DREQ off after DACK on

DREQ on after DACK off

data valid after DACK on

data hold after DACK off

-

22

3

-

22

3

ns

Write in DACK-only mode (see Figure 31)

t_ASRP

t_APRS

t_DVAP

t_APDZ

DREQ off after DACK on

DREQ on after DACK off

data setup before DACK off

data hold after DACK off

-

22

-

22

-

ns

-

5

3

5

3

-

Single-cycle EOT (see Figure 32)

t_RSIH

t_IHAP

t_EOT

input RD/WR HIGH after

DREQ on

22

0

-

22

0

-

ns

DACK off after input RD/WR

HIGH

EOT pulse width

EOT on;

22

DACK on;

RD/WR LOW

t

handbook, full pagewidth

ASRP

APRS

DREQ

DACK

MGS792

Fig 29. DMA timing in 8237 compatible mode.

t

handbook, full pagewidth

ASRP

APRS

DREQ

DACK

t

APDZ

ASDV

DATA

MGS793

Fig 30. DMA read timing in DACK-only mode.

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t

APRS

handbook, full pagewidth

ASRP

DREQ

t

DVAP

APDZ

DACK

DATA

MGS794

Fig 31. DMA write timing in DACK-only mode.

handbook, full pagewidth

t

RSIH

APRS

DREQ

t

ASRP

(1)

IHAP

DACK

RD/WR

(2)

t

EOT

(3)

EOT

MGS795

(1) t_ASRPstarts from DACK or RD/WR going LOW, whichever occurs later.

(2) The RD/WR signals are not used in 8237 compatible DMA mode.

(3) The EOT condition is considered valid if DACK, RD/WR and EOT are all active (= LOW).

Fig 32. EOT timing in single-cycle DMA mode.

19.5 DMA timing: burst mode

Table 62: Dynamic characteristics: burst mode DMA timing

Symbol

Parameter

Conditions

8-bit bus

Max

16-bit bus

Max

Unit

Min

Burst (see Figure 33)

t_RSIH

t_ILRP

t_IHAP

t_IHIL

input RD/WR HIGH after

DREQ on

22

-

22

-

ns

DREQ off after input RD/WR

LOW

60

-

60

-

DACK off after input RD/WR

HIGH

0

DMA burst repeat interval

90

-

180

-

(input RD/WR HIGH to LOW)

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Table 62: Dynamic characteristics: burst mode DMA timing

Symbol

Parameter

Conditions

8-bit bus

Max

16-bit bus

Max

Unit

Min

Burst EOT (see Figure 34)

t_EOT

EOT pulse width

EOT on;

DACK on;

RD/WR LOW

22

-

22

-

ns

t_ISRP

DREQ off after input EOT on

-

40

-

40

t

ILRP

RSIH

handbook, full pagewidth

DREQ

t

IHAP

DACK

t

IHIL

RD/WR

MGS796

Fig 33. Burst mode DMA timing.

t

handbook, full pagewidth

ISRP

DREQ

DACK

RD/WR

EOT

(1)

t

EOT

MGS797

(1) The EOT condition is considered valid if DACK, RD/WR and EOT are all active (= LOW).

Fig 34. EOT timing in burst mode DMA.

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20. Application information

20.1 Typical interface circuits

V

handbook, full pagewidth

CC

A0

AD

D0

D1

LINK LED

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

D2

V

reg(3.3)

D3

V

CC(5.0)

RESET

D4

0.1

µF

0.1

µF

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

USB

upstream

connector

H8S/2357

V

1

2

3

4

BUS

22 Ω

D+

D−

ISP1181

A0

CSn

RD

ALE

CS

WR

RD

IRQ

WR

P1.1

XTAL1

XTAL2

READY

INT

DREQ0

DACK

TEND

SUSPEND

WAKEUP

DREQ

>

330 Ω

GL

6 MHz

18 pF

DACK

EOT

18 pF

BUS_CONF1

BUS_CONF0

SDRD

SDWR

MGS769

Fig 35. Typical interface circuit for bus conﬁguration mode 0 (shared ports: 16-bit PIO, 8-bit or 16-bit DMA).

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V

handbook, full pagewidth

CC

AD

AD0

AD1

LINK LED

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

DATA8

DATA9

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

AD2

V

reg(3.3)

AD3

V

CC(5.0)

RESET

AD4

0.1

µF

0.1

µF

AD5

AD6

AD7

ALE

8051

PSEN

RD

USB

upstream

connector

WR

IRQ

V

1

2

3

4

BUS

22 Ω

D+

D−

ISP1181

A0

ALE

CS

P2.3

P2.0

P2.1

RD

WR

XTAL1

XTAL2

READY

INT

SUSPEND

WAKEUP

DREQ

>

330 Ω

GL

6 MHz

18 pF

DACK

EOT

D0

D1

D2

D3

D4

D5

D6

D7

18 pF

BUS_CONF1

BUS_CONF0

SDRD

SDWR

DMA CONTROLLER

or

MASTER DMA DEVICE

MGS770

DREQ

DACK

END of DMA

RD

WR

Fig 36. Typical interface circuit for bus conﬁguration mode 1 (separate ports: 8-bit PIO and 8-bit DMA)

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V

handbook, full pagewidth

CC

AD

D1

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

ALE

LINK LED

D2

V

ref(3.3)

D3

V

CC

D4

0.1

µF

RESET

D5

µF

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

PSEN

8051

USB

upstream

connector

RD

WR

IRQ

V

1

2

3

4

BUS

22 Ω

D+

D−

ISP1181

A0

ALE

CS

P2.3

P2.0

P2.1

RD

WR

XTAL1

XTAL2

READY

INT

SUSPEND

WAKEUP

DREQ

>

330 Ω

GL

6 MHz

DACK

EOT

18 pF

BUS_CONF1

BUS_CONF0

SDRD

SDWR

BUS_REQ

BUS_GNT

MCU_WR

MCU_RD

CS

RD

WR

CS1

CS2

D15

D14

D13

D12

D11

RD

WR

DREQ

DACK

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

16 BIT

DMA PORT

EOT

DMA

CONTROLLER

D7

D6

D5

D4

D3

D2

D1

D0

MGS771

Fig 37. Typical interface circuit for bus conﬁguration mode 2 (shared ports: 8-bit PIO, 8-bit or 16-bit DMA).

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20.2 Interfacing ISP1181 with an H8S/2357 microcontroller

This section gives a summary of the ISP1181 interface with a H8S/2357 (or

compatible) microcontroller. Aspects discussed are: interrupt handling, address

mapping, DMA and I/O port usage for suspend and remote wake-up control. A typical

interface circuit is shown in Figure 35.

20.2.1 Interrupt Handling

ISP1181: program the Hardware Conﬁguration register to select an active LOW

level for output INT (INTPOL = 0, see Table 22)

•

H8S/2357: program the IRQ Sense Control Register (ISCRH and ISCRL) to

specify low-level sensing for the IRQ input.

20.2.2 Address Mapping in H8S/2357

The H8S/2357 bus controller partitions its 16 Mbyte address space into eight areas

(0 to 7) of 2 Mbyte each. The bus controller will activate one of the outputs CS0 to

CS7 when external address space for the associated area is accessed.

The ISP1181 can be mapped to any address area, allowing easy interfacing when the

ISP1181 is the only device in that area. If in the example circuit for bus conﬁguration

mode 0 (see Figure 35) the ISP1181 is mapped to address FFFF08H (in area 7),

output CS7 of the H8S/2357 can be directly connected to input CS of the ISP1181.

The external bus speciﬁcations, bus width, number of access states and number of

program wait states can be programmed for each address area. The recommended

settings of H8S/2357 for interfacing the ISP1181 are:

8-bit bus in Bus Width Control Register (ABWCR)

•

enable wait states in Access State Control Register (ASTCR)

1 program wait state in the Wait Control Register (WCRH and WCRL).

20.2.3 Using DMA

The ISP1181 can be conﬁgured for several methods of DMA with the H8S/2357 and

other devices. The interface circuit in Figure 35 shows an example of the ISP1181

working with the H8S/2357 in single-address DACK-only DMA mode. External

devices are not shown.

For single-address DACK-only mode, ﬁrmware must program the following settings:

ISP1181:

•

– program the DMA Counter register with the total transfer byte count

– program the Hardware Conﬁguration Register to select active level LOW for

DREQ and DACK

– select the target endpoint and transfer direction

– select DACK-only mode and enable DMA transfer.

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20.2.4 Using H8S2357 I/O Ports

In the interface circuit of Figure 35 pin P1.1 of the H8S/2357 is conﬁgured as a

general purpose output port. This pin drives the ISP1181’s WAKEUP input to

generate a remote wake-up.

The H8S/2357 has 3 registers to conﬁgure port 1: Port 1 Data Direction Register

(P1DDR), Port 1 Data Register (P1DR) and Port 1 Register (PORT1). Only registers

P1DDR and P1DR must be conﬁgured, register PORT1 is only used to read the

actual levels on the port pins.

For single

H8S/2357:

•

– select pin P1.1 to be an output in register P1DDR

– program the desired bit value for P1.1 in register P1DR.

21. Test information

The dynamic characteristics of the analog I/O ports (D+ and D−) as listed in Table 57,

were determined using the circuit shown in Figure 38.

test point

handbook, halfpage

22 Ω

D.U.T

C

=

L

15 kΩ

50 pF

MGS784

Load capacitance:

C_L= 50 pF (full-speed mode)

Speed:

full-speed mode only: internal 1.5 kΩ pull-up resistor on D+

Fig 38. Load impedance for D+ and D− pins.

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22. Package outline

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

SOT362-1

E

D

A

X

c

H

v

M

A

y

E

Z

48

25

Q

A

2

(A )

3

A

1

pin 1 index

θ

L

p

L

detail X

1

24

w

M

b

e

p

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions).

A

(1)

(2)

UNIT

A

b

c

D

E

e

H

L

p

Q

v

w

y

Z

θ

1

2

3

p

E

max.

8^o

0^o

0.15

0.05

1.05

0.85

0.28

0.17

0.2

0.1

12.6

12.4

6.2

6.0

8.3

7.9

0.8

0.4

0.50

0.35

0.8

0.4

mm

1.2

0.5

1

0.25

0.08

0.1

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

EIAJ

95-02-10

99-12-27

SOT362-1

MO-153

Fig 39. TSSOP48 package outline.

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23. Soldering

23.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering is not always suitable for surface mount ICs, or for printed-circuit boards

with high population densities. In these situations reﬂow soldering is often used.

23.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement.

Several methods exist for reﬂowing; for example, infrared/convection heating in a

conveyor type oven. Throughput times (preheating, soldering and cooling) vary

between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 250 °C. The top-surface

temperature of the packages should preferable be kept below 230 °C.

23.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

•

For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

•

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

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Typical dwell time is 4 seconds at 250 °C. A mildly-activated ﬂux will eliminate the

need for removal of corrosive residues in most applications.

23.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

23.5 Package related soldering information

Table 63: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package

Soldering method

Wave

Reﬂow^[1]

suitable

BGA, LFBGA, SQFP, TFBGA

not suitable

not suitable^[2]

HBCC, HLQFP, HSQFP, HSOP, HTQFP,

HTSSOP, SMS

PLCC^[3], SO, SOJ

LQFP, QFP, TQFP

SSOP, TSSOP, VSO

suitable

not recommended ^{[3] [4]}

not recommended^[5]

[1] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

[2] These packages are not suitable for wave soldering as a solder joint between the printed-circuit board

and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top

version).

[3] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[4] Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger

than 0.8 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[5] Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

9397 750 06896

Objective speciﬁcation

Rev. 01 — 13 March 2000

65 of 69

ISP1181

Full-speed USB interface

Philips Semiconductors

24. Revision history

Table 64: Revision history

Rev Date

CPCN

Description

01 20000313

Objective speciﬁcation; initial version.

9397 750 06896

Objective speciﬁcation

Rev. 01 — 13 March 2000

66 of 69

ISP1181

Full-speed USB interface

Philips Semiconductors

25. Data sheet status

Datasheet status

Product status Deﬁnition^[1]

Objective speciﬁcation

Development

This data sheet contains the design target or goal speciﬁcations for product development. Speciﬁcation may

change in any manner without notice.

Preliminary speciﬁcation Qualiﬁcation

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips

Semiconductors reserves the right to make changes at any time without notice in order to improve design and

supply the best possible product.

Product speciﬁcation

Production

This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors reserves the right to make changes at any

time without notice in order to improve design and supply the best possible product.

[1]

Please consult the most recently issued data sheet before initiating or completing a design.

26. Deﬁnitions

27. Disclaimers

Short-form speciﬁcation — The data in

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

a

short-form speciﬁcation is

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Right to make changes — Philips Semiconductors reserves the right to

make changes, without notice, in the products, including circuits, standard

cells, and/or software, described or contained herein in order to improve

design and/or performance. Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products

are free from patent, copyright, or mask work right infringement, unless

otherwise speciﬁed.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

28. Trademarks

ACPI — is an open industry speciﬁcation for PC power management,

co-developed by Intel Corp., Microsoft Corp. and Toshiba

SMBus — is a bus speciﬁcation for PC power management, developed by

Intel Corp. based on the I²C-bus from Royal Philips Electronics

GoodLink — is a trademark of Royal Philips Electronics

OnNow — is a trademark of Microsoft Corp.

SoftConnect — is a trademark of Royal Philips Electronics

9397 750 06896

Objective speciﬁcation

Rev. 01 — 13 March 2000

67 of 69

ISP1181

Full-speed USB interface

Philips Semiconductors

Philips Semiconductors - a worldwide company

Argentina: see South America

Netherlands: Tel. +31 40 278 2785, Fax. +31 40 278 8399

Australia: Tel. +61 2 9704 8141, Fax. +61 2 9704 8139

Austria: Tel. +43 160 101, Fax. +43 160 101 1210

Belarus: Tel. +375 17 220 0733, Fax. +375 17 220 0773

Belgium: see The Netherlands

New Zealand: Tel. +64 98 49 4160, Fax. +64 98 49 7811

Norway: Tel. +47 22 74 8000, Fax. +47 22 74 8341

Philippines: Tel. +63 28 16 6380, Fax. +63 28 17 3474

Poland: Tel. +48 22 5710 000, Fax. +48 22 5710 001

Portugal: see Spain

Brazil: see South America

Bulgaria: Tel. +359 268 9211, Fax. +359 268 9102

Canada: Tel. +1 800 234 7381

Romania: see Italy

Russia: Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

China/Hong Kong: Tel. +852 2 319 7888, Fax. +852 2 319 7700

Colombia: see South America

Czech Republic: see Austria

Slovenia: see Italy

Denmark: Tel. +45 3 288 2636, Fax. +45 3 157 0044

Finland: Tel. +358 961 5800, Fax. +358 96 158 0920

France: Tel. +33 14 099 6161, Fax. +33 14 099 6427

Germany: Tel. +49 40 23 5360, Fax. +49 402 353 6300

Hungary: see Austria

South Africa: Tel. +27 11 471 5401, Fax. +27 11 471 5398

South America: Tel. +55 11 821 2333, Fax. +55 11 829 1849

Spain: Tel. +34 33 01 6312, Fax. +34 33 01 4107

Sweden: Tel. +46 86 32 2000, Fax. +46 86 32 2745

Switzerland: Tel. +41 14 88 2686, Fax. +41 14 81 7730

Taiwan: Tel. +886 22 134 2865, Fax. +886 22 134 2874

Thailand: Tel. +66 27 45 4090, Fax. +66 23 98 0793

Turkey: Tel. +90 216 522 1500, Fax. +90 216 522 1813

Ukraine: Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Tel. +44 208 730 5000, Fax. +44 208 754 8421

United States: Tel. +1 800 234 7381

India: Tel. +91 22 493 8541, Fax. +91 22 493 8722

Indonesia: see Singapore

Ireland: Tel. +353 17 64 0000, Fax. +353 17 64 0200

Israel: Tel. +972 36 45 0444, Fax. +972 36 49 1007

Italy: Tel. +39 039 203 6838, Fax +39 039 203 6800

Japan: Tel. +81 33 740 5130, Fax. +81 3 3740 5057

Korea: Tel. +82 27 09 1412, Fax. +82 27 09 1415

Malaysia: Tel. +60 37 50 5214, Fax. +60 37 57 4880

Mexico: Tel. +9-5 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: Tel. +381 11 3341 299, Fax. +381 11 3342 553

Middle East: see Italy

For all other countries apply to: Philips Semiconductors,

International Marketing & Sales Communications,

Building BE, P.O. Box 218, 5600 MD EINDHOVEN,

The Netherlands, Fax. +31 40 272 4825

Internet: http://www.semiconductors.philips.com

(SCA69)

9397 750 06896

Objective speciﬁcation

Rev. 01 — 13 March 2000

68 of 69

ISP1181

Full-speed USB interface

Philips Semiconductors

Contents

1

2

3

4

5

General description. . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

12.2.2

12.2.3

12.2.4

12.2.5

12.2.6

12.3

12.3.1

12.3.2

12.3.3

12.3.4

12.3.5

12.3.6

Write/Read Endpoint Status . . . . . . . . . . . . . . . . . . 33

Validate Endpoint Buffer . . . . . . . . . . . . . . . . . . . . . 34

Clear Endpoint Buffer . . . . . . . . . . . . . . . . . . . . . . . 35

Check Endpoint Status . . . . . . . . . . . . . . . . . . . . . . 35

Acknowledge Setup. . . . . . . . . . . . . . . . . . . . . . . . . 36

General commands . . . . . . . . . . . . . . . . . . . . . . . . . 36

Read Endpoint Error Code . . . . . . . . . . . . . . . . . . . 36

Unlock Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Write/Read Scratch Register . . . . . . . . . . . . . . . . . . 38

Read Frame Number. . . . . . . . . . . . . . . . . . . . . . . . 38

Read Chip ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Read Interrupt Register . . . . . . . . . . . . . . . . . . . . . . 39

6

Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

6.1

6.2

7

Functional description . . . . . . . . . . . . . . . . . . . . . . . . 7

Analog transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Philips Serial Interface Engine (SIE) . . . . . . . . . . . . . 8

Memory Management Unit (MMU) and integrated

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Bit clock recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PLL clock multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Parallel I/O (PIO) and Direct Memory Access (DMA)

interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

7.1

7.2

7.3

13

14

15

16

17

18

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Power supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Crystal oscillator and LazyClock. . . . . . . . . . . . . . . 42

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . 45

7.4

7.5

7.6

7.7

7.8

7.9

19

Dynamic characteristics. . . . . . . . . . . . . . . . . . . . . . 47

Timing symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Parallel I/O timing . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Access cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . 53

DMA timing: single-cycle mode . . . . . . . . . . . . . . . . 54

DMA timing: burst mode . . . . . . . . . . . . . . . . . . . . . 56

19.1

19.2

19.3

19.4

19.5

8

Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

9

Endpoint descriptions. . . . . . . . . . . . . . . . . . . . . . . . 10

Endpoint access. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Endpoint FIFO size . . . . . . . . . . . . . . . . . . . . . . . . . 11

Endpoint initialization . . . . . . . . . . . . . . . . . . . . . . . . 12

Endpoint I/O mode access. . . . . . . . . . . . . . . . . . . . 12

Special actions on control endpoints . . . . . . . . . . . . 12

9.1

9.2

9.3

9.4

9.5

20

Application information . . . . . . . . . . . . . . . . . . . . . . 58

Typical interface circuits . . . . . . . . . . . . . . . . . . . . . 58

Interfacing ISP1181 with an H8S/2357

20.1

20.2

microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Address Mapping in H8S/2357 . . . . . . . . . . . . . . . . 61

Using DMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Using H8S2357 I/O Ports . . . . . . . . . . . . . . . . . . . . 62

10

DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Selecting an endpoint for DMA transfer . . . . . . . . . . 13

8237 compatible mode. . . . . . . . . . . . . . . . . . . . . . . 14

DACK-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

End-Of-Transfer conditions . . . . . . . . . . . . . . . . . . . 16

Bulk endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Isochronous endpoints. . . . . . . . . . . . . . . . . . . . . . . 17

DMA auto-restart . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

20.2.1

20.2.2

20.2.3

20.2.4

10.1

10.2

10.3

10.4

10.4.1

10.4.2

10.4.3

21

22

Test information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

23

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Introduction to soldering surface mount packages . 64

Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Package related soldering information . . . . . . . . . . 65

11

Suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 18

Suspend conditions . . . . . . . . . . . . . . . . . . . . . . . . . 18

Powered-on application . . . . . . . . . . . . . . . . . . . . . . 19

Powered-off application . . . . . . . . . . . . . . . . . . . . . . 20

Resume conditions. . . . . . . . . . . . . . . . . . . . . . . . . . 22

Control bits in suspend and resume. . . . . . . . . . . . . 22

23.1

23.2

23.3

23.4

23.5

11.1

11.1.1

11.1.2

11.2

11.3

24

25

26

27

28

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

12

Commands and registers . . . . . . . . . . . . . . . . . . . . . 23

Initialization commands . . . . . . . . . . . . . . . . . . . . . . 25

Write/Read Endpoint Configuration . . . . . . . . . . . . . 25

Write/Read Device Address. . . . . . . . . . . . . . . . . . . 26

Write/Read Mode Register. . . . . . . . . . . . . . . . . . . . 26

Write/Read Hardware Configuration . . . . . . . . . . . . 27

Write/Read Interrupt Enable Register . . . . . . . . . . . 29

Write/Read DMA Configuration . . . . . . . . . . . . . . . . 30

Write/Read DMA Counter . . . . . . . . . . . . . . . . . . . . 31

Reset Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Data flow commands . . . . . . . . . . . . . . . . . . . . . . . . 32

Write/Read Endpoint Buffer . . . . . . . . . . . . . . . . . . . 32

12.1

12.1.1

12.1.2

12.1.3

12.1.4

12.1.5

12.1.6

12.1.7

12.1.8

12.2

12.2.1

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 13 March 2000

Document order number: 9397 750 06896


型号：	ISP1181
厂家：	NXP
描述：	Full-speed Universal Serial Bus interface device 全速通用串行总线接口设备
文件：	总69页 (文件大小：1501K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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