ISP1301BS,151 [NXP]
IC LINE TRANSCEIVER, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, LEAD FREE AND HALOGEN FREE, PLASTIC, MO-220, SOT-616-1, HVQFN-24, Line Driver or Receiver;
| 型号： | ISP1301BS,151 |
| 厂家： | 
NXP |
| 描述： | IC LINE TRANSCEIVER, PQCC24, 4 X 4 MM, 0.85 MM HEIGHT, LEAD FREE AND HALOGEN FREE, PLASTIC, MO-220, SOT-616-1, HVQFN-24, Line Driver or Receiver 驱动 接口集成电路 驱动器 |
| 文件： | 总52页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IMPORTANT NOTICE
Dear customer,
As from August 2nd 2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
●
Company name - Philips Semiconductors is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© Koninklijke Philips
Electronics N.V. 200x. All rights reserved”, shall now read: “© ST-NXP Wireless 200x -
All rights reserved”.
●
●
Web site - http://www.semiconductors.philips.com is replaced with
http://www.stnwireless.com
Contact information - the list of sales offices previously obtained by sending an email
to sales.addresses@www.semiconductors.philips.com, is now found at
http://www.stnwireless.com under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
34ꢀ.80 7IRELESS
www.stnwireless.com
ISP1301
Universal Serial Bus On-The-Go transceiver
Rev. 03 — 21 February 2006
Product data sheet
1. General description
The ISP1301 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device that is
fully compliant with Universal Serial Bus Specification Rev. 2.0 and On-The-Go
Supplement to the USB Specification Rev. 1.0a. The ISP1301 can transmit and receive
serial data at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data rates.
It is ideal for use in portable electronics devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) and any system chip set (with the USB host or device function
built-in but without the USB physical layer) to interface to the physical layer of the USB.
The ISP1301 can interface to devices with digital I/O voltages in the range of
1.65 V to 3.6 V.
The ISP1301 is available in HVQFN24 package.
2. Features
■ Fully complies with:
◆ Universal Serial Bus Specification Rev. 2.0
◆ On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a
◆ On-The-Go Transceiver Specification (CEA-2011) Rev. 1.0
■ Can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s) data rates
■ Ideal for system ASICs or chip sets with built-in USB OTG dual-role core
■ Supports mini USB analog carkit interface
■ Supports various serial data interface protocols; transparent general-purpose buffer
mode allows you to control the direction of data transfer
■ Supports data line and VBUS pulsing session request
■ Contains Host Negotiation Protocol (HNP) command and status registers
■ Supports serial I2C-bus interface for OTG status and command controls
■ 2.7 V to 4.5 V power supply input range for the ISP1301
■ Built-in charge pump regulator outputs 5 V at current greater than 8 mA
■ Supports external charge pump
■ Supports wide range interfacing I/O voltage (VCC(I/O) = 1.65 V to 3.6 V) for digital
control logics
ISP1301
Philips Semiconductors
USB OTG transceiver
■ 8 kV built-in ElectroStatic Discharge (ESD) protection on the DP, DM, VBUS and ID
lines
■ Full industrial grade operation from −40 °C to +85 °C
■ Available in a small HVQFN24 (4 × 4 mm2) halogen-free and lead-free package
3. Applications
■ Mobile phone
■ Digital camera
■ Personal digital assistant
■ Digital video recorder
4. Ordering information
Table 1:
Ordering information
Type number Package
Name
Description
Version
ISP1301BS
HVQFN24
plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; SOT616-1
body 4 × 4 × 0.85 mm
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
2 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
5. Block diagram
V
V
VREG3V3
7
C2
C1
CC(I/O)
24
CC
22
21
20
23
3.3 V DC-DC
REGULATOR
CGND
V
BUS
CHARGE PUMP
19
V
BUS
ISP1301BS
V
BUS
3
SCL
COMPARATORS
2
SDA
1
ADR/PSW
5
INT_N
SERIAL
CONTROLLER
18
ID DETECTOR
ID
9
OE_N/INT_N
14
DAT/VP
LEVEL
SHIFTER
13
SE0/VM
PULL-UP AND
PULL-DOWN
RESISTORS
12
RCV
11
VP
10
VM
CARKIT
INTERRUPT
DETECTOR
6
SPEED
8
SUSPEND
15
16
DM
DP
4
USB
TRANSCEIVER
RESET_N
exposed die pad
17
004aaa748
DGND
AGND
Fig 1. Block diagram
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
3 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
6. Pinning information
6.1 Pinning
terminal 1
index area
1
2
3
4
5
6
18
17
16
15
14
13
ADR/PSW
SDA
ID
AGND
DP
SCL
ISP1301BS
RESET_N
INT_N
DM
DAT/VP
SE0/VM
SPEED
004aaa542
Transparent top view
Fig 2. Pin configuration HVQFN24 (top view)
6
5
4
3
2
1
13
14
15
16
17
18
SPEED
INT_N
SE0/VM
DAT/VP
DM
DGND (exposed
die pad)
RESET_N
SCL
ISP1301BS
DP
SDA
AGND
ID
ADR/PSW
terminal 1
index area
004aaa196
Bottom view
Fig 3. Pin configuration HVQFN24 (bottom view)
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
4 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
6.2 Pin description
Table 2:
Pin description
Symbol[1]
Pin
Type [2] Reset
Description[3]
state
ADR/PSW
1
I/O
high-Z
ADR input — sets the least-significant I2C-bus
address bit of the ISP1301; latched-on reset
(including power-on reset)
PSW output — enables or disables the external
charge pump after reset
bidirectional; push-pull input; 3-state output
serial I2C-bus data input and output
bidirectional; push-pull input; open-drain output
serial I2C-bus clock input and output
bidirectional; push-pull input; open-drain output
asynchronous reset; active LOW
push-pull input
SDA
2
3
4
5
6
I/OD
high-Z
SCL
I/OD
high-Z
RESET_N
INT_N
SPEED
I
-
OD
I
high-Z
-
interrupt output; active LOW
open-drain output
speed selection input for the ATX; effective when
bit SPD_SUSP_CTRL = 0:
• LOW: low-speed
• HIGH: full-speed
push-pull input
VREG3V3
SUSPEND
7
8
P
I
-
-
output of the internal voltage regulator; an external
decoupling capacitor of 0.1 µF is required
suspend selection input for the ATX; effective when
bit SPD_SUSP_CTRL = 0:
• LOW: normal operating
• HIGH: suspend
push-pull input
OE_N/
INT_N
9
I/O
high-Z
OE_N input — enables driving DP and DM when in
USB mode
INT_N output — interrupt (push pull) when
suspended and bit OE_INT_EN = 1
bidirectional; push-pull input; 3-state output
single-ended DM receiver output
push-pull output
VM
VP
10
11
12
O
O
O
-
-
single-ended DP receiver output
push-pull output
RCV
0
differential receiver output; reflects the differential
value of DP and DM
push-pull output
[4]
SE0/VM
13
I/O
-
SE0 (input and output) — SE0 functions in
DAT_SE0 USB mode
VM (input and output) — VM functions in VP_VM
USB mode
bidirectional; push-pull input; 3-state output
ISP1301_3
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Product data sheet
Rev. 03 — 21 February 2006
5 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
Table 2:
Pin description…continued
Symbol[1]
Pin
Type [2] Reset
Description[3]
state
[4]
DAT/VP
14
I/O
-
DAT (input and output) — DAT functions in
DAT_SE0 USB mode
VP (input and output) — VP functions in VP_VM
USB mode
bidirectional; push-pull input; 3-state output
USB data minus pin (D−)
USB data plus pin (D+)
DM
DP
15
16
17
18
AI/O
AI/O
P
-
-
-
-
AGND
ID
analog ground
AI/O
identification detector input and output; connected
to the ID pin of the USB mini receptacle
VBUS
19
AI/O
-
VBUS line input and output of the USB interface;
place an external decoupling capacitor of 0.1 µF
close to this pin
VCC
C1
20
21
P
-
-
supply voltage (2.7 V to 4.5 V)
AI/O
charge pump capacitor pin 1; typically use a 100 nF
capacitor between pins C1 and C2
C2
22
AI/O
-
charge pump capacitor pin 2; typically use a 100 nF
capacitor between pins C1 and C2
CGND
23
24
P
P
-
-
ground for the charge pump
VCC(I/O)
supply voltage for the interface logic signals
(1.65 V to 3.6 V)
DGND
exposed
die pad
P
-
digital ground
[1] Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals.
[2] I = input; O = output; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output;
P = power or ground pin.
[3] A detailed description of these pins can be found in Section 7.10.
[4] High-Z when pin OE_N/INT_N is LOW. Driven LOW when pin OE_N/INT_N is HIGH.
ISP1301_3
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Product data sheet
Rev. 03 — 21 February 2006
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ISP1301
Philips Semiconductors
USB OTG transceiver
7. Functional description
7.1 Serial controller
The serial controller includes the following functions:
• I2C-bus slave interface
• Interrupt generator
• Mode Control registers
• OTG registers
• Interrupt related registers
• Device identification registers
The serial controller acts as an I2C-bus slave, and uses the SCL and SDA pins to
communicate with the OTG Controller.
For details on serial controller, see Section 10.
7.2 VBUS charge pump
The charge pump supplies current to the VBUS line. It can operate in any of the following
modes:
• Output 5 V at current greater than 8 mA
• Pull-up VBUS to 3.3 V through a resistor (RUP(VBUS)) to initiate VBUS pulsing SRP
• Pull-down VBUS to ground through a resistor (RDN(VBUS)) to discharge VBUS before
initiating SRP
7.3 VBUS comparators
VBUS comparators provide indications regarding the voltage level on VBUS
.
7.3.1 VBUS valid comparator
This comparator is used by an A-device to determine whether the voltage on VBUS is at a
valid level for operation. The minimum threshold for the VBUS valid comparator is 4.4 V.
Any voltage on VBUS below this threshold is considered to be a fault. During power-up, it is
expected that the comparator output will be ignored.
7.3.2 Session valid comparator
The session valid comparator is a TTL-level input that determines when VBUS is high
enough for a session to start. Both the A-device and the B-device use this comparator to
detect when a session is started. The A-device also uses this comparator to indicate when
a session is completed. The session valid threshold of the ISP1301 is between
0.8 V and 2.0 V.
7.3.3 Session end comparator
The session end comparator determines when VBUS is below the B-device session end
threshold of 0.2 V to 0.8 V.
ISP1301_3
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Product data sheet
Rev. 03 — 21 February 2006
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ISP1301
Philips Semiconductors
USB OTG transceiver
7.4 ID detector
In either active or suspended power mode, the ID detector senses the condition of the ID
line and differentiates between the following three conditions:
• Pin ID is floating; bit ID_FLOAT = 1
• Pin ID is shorted to ground; bit ID_GND = 1
• Pin ID is connected to ground through resistor RACC_ID; bit ID_FLOAT = 0 and bit
ID_GND = 0
The ID detector also has a switch that can be used to ground pin ID. This switch is
controlled by bit ID_PULLDOWN in the serial controller.
7.5 Pull-up and pull-down resistors
The pull-up and pull-down resistors include the following switchable resistors:
• Pin DP pull-up
• Pin DP pull-down
• Pin DM pull-up
• Pin DM pull-down
The pull-up resistor is a context variable as described in the ECN_27%_Resistor
document. The variable pull-up resistor hardware is implemented to meet the USB
ECN_27% specification.
7.6 Analog USB Transceiver (ATX)
The behavior of the USB transceiver depends on operation mode of the ISP1301:
• In USB mode, the USB transceiver block performs USB full-speed or low-speed
transceiver functions. This includes differential driver, differential receiver and
single-ended receivers.
• In transparent general purpose buffer mode or UART mode, USB transceiver block
functions as a level shifter between pins DAT/VP and SE0/VM and pins DP and DM.
7.7 3.3 V DC-DC regulator
The built-in 3.3 V DC-DC regulator conditions the supply voltage (VCC) for use in the
ISP1301:
• VCC = 3.6 V to 4.5 V: the regulator will output 3.3 V ± 10 %
• VCC < 3.6 V: the regulator will be bypassed
The output of the regulator can be monitored on the VREG3V3 pin.
7.8 Carkit interrupt detector
The carkit interrupt detector is a comparator that detects when the DP line is below the
carkit interrupt threshold VPH_CR_INT (0.4 V to 0.6 V). The carkit interrupt detector is
enabled in audio mode only (bit AUDIO_EN = 1).
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
8 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
7.9 Power-On Reset (POR)
When VCC is powered on, an internal POR is generated. The internal POR pulse width
(tPORP) will be typically 200 ns. The pulse is started when VCC rises above VPOR(trip)
.
The POR function can be explained by viewing dips at t2 to t3 and t4 to t5 on the VCC
curve (Figure 4).
t0 — The internal POR starts with a LOW level.
t1 — The detector will see the passing of the trip level and a delay element will add
another tPORP before it drops to LOW.
t2-t3 — The internal POR pulse will be generated whenever VCC drops below VPOR(trip) for
more than 11 µs.
t4-t5 — The dip is too short (< 11 µs) and the internal POR pulse will not react and will
remain LOW.
V
CC
V
POR(trip)
t0
t1
t
t2
t3
t4
t5
(1)
PORP
t
PORP
PORP
004aaa750
(1) PORP = Power-On Reset Pulse
Fig 4. Internal POR timing
7.10 Detailed description of pins
7.10.1 ADR/PSW
The ADR/PSW pin has two functions. On reset (including power-on reset), the level on
this pin is latched as ADR_REG, which represents the Least Significant Bit (LSB) of the
I2C-bus address of the ISP1301. If bit ADR_REG = 0, the I2C-bus address for the
ISP1301 is 010 1100 (2Ch); if bit ADR_REG = 1, the I2C-bus address for the ISP1301 is
010 1101 (2Dh).
After reset, the ADR/PSW pin can be programmed as an output. If in the Mode Control 2
register bit PSW_OE = 1, then the ADR/PSW output will be enabled. The logic level will
be determined by bit ADR_REG. If bit ADR_REG = 0, then the ADR/PSW pin will be
driven HIGH. If bit ADR_REG = 1, then the ADR/PSW pin will be driven LOW.
The ADR/PSW pin can be used to turn on or off the external charge pump. The ISP1301
built-in charge pump supports VBUS current at 8 mA. If the application needs more current
support (for example, 50 mA), an external charge pump may be needed. In this case, the
ADR/PSW pin can act as a power switch for the external charge pump. Figure 5 shows an
example of using external charge pump.
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
9 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
+3.3 V
100 kΩ
V
CC
ADR/PSW
V
OUT
V
V
BUS
IN
ID
4.7 µF
DM
ISP1301BS
CHARGE PUMP
ON/OFF
DP
V
BUS
GND
004aaa437
Fig 5. Using external charge pump
7.10.2 SCL and SDA
The SCL (serial clock) and SDA (serial data) signals implement a two-wire serial I2C-bus.
7.10.3 RESET_N
Active LOW asynchronous reset for all digital logic. Either connect this pin to VCC(I/O) for
power-on reset or apply a minimum of 10 µs LOW pulse for hardware reset.
7.10.4 INT_N
The INT_N (interrupt) pin is asserted while an interrupt condition exists. It is de-asserted
when the Interrupt Latch register is cleared. The INT_N pin is open-drain, and, therefore,
can be connected using a wired-AND with other interrupt signals.
7.10.5 OE_N/INT_N
Pin OE_N/INT_N is normally an input to the ISP1301.
When bit TRANSP_EN = 0 and bit UART_EN = 0, the OE_N/INT_N pin controls the
direction of DAT/VP, SE0/VM, DP and DM as indicated in Table 4.
When suspended (either pin SUSPEND = HIGH or bit SUSPEND_REG = 1) and bit
OE_INT_EN = 1, pin OE_N/INT_N becomes a push-pull output (active LOW) to indicate
the interrupt condition.
7.10.6 SE0/VM, DAT/VP, RCV, VM and VP
The ISP1301 transmits USB data on the USB line under the following conditions:
• Bit TRANSP_EN = 0
• Bit UART_EN = 0
• Pin OE_N/INT_N = LOW
Table 10 shows the operation of the SE0/VM and DAT/VP pins during the transmit
operation. The RCV pin is not used during transmit.
The ISP1301 receives USB data from the USB line under the following conditions:
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
10 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
• Bit TRANSP_EN = 0
• Bit UART_EN = 0
• Pin OE_N/INT_N = HIGH
Table 12 shows the operation of the SE0/VM, DAT/VP and RCV pins during the receive
operation.
The VP and VM pins are single-ended receiver outputs of the DP and DM pins,
respectively.
7.10.7 DP and DM
The DP (data plus) and DM (data minus) pins implement the USB data signals. When in
transparent general-purpose buffer mode, the ISP1301 operates as a level shifter
between the (DAT/VP, SE0/VM) and (DP, DM) pins.
7.10.8 ID
The ID (identification) pin is connected to the ID pin on the USB mini receptacle. An
internal pull-up resistor (to VREG3V3) is connected to this pin. When bit ID_PULLDOWN
is set, the ID pin will be shorted to ground.
7.10.9 VBUS
This pin acts as an input to the VBUS comparator or an output from the charge pump.
When the VBUS_DRV bit of the OTG Control register is asserted, the ISP1301 tries to
drive VBUS to a voltage of 4.4 V to 5.25 V, with an output current capability of at least
8 mA.
7.10.10 VCC
This pin is an input and supplies power to the ISP1301. The ISP1301 operates when VCC
is between 2.7 V and 4.5 V.
7.10.11 C1 and C2
The C1 and C2 pins are to connect the flying capacitor of the charge pump. The output
current capacity of the charge pump depends on the value of the capacitor. For maximum
efficiency, place capacitors as close as possible to the pins.
V
CC
C1
C2
C
ext
ISP1301BS
V
BUS
I
L
004aaa278
Fig 6. Charge pump capacitor
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
11 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
Table 3:
Cext
Recommended charge pump capacitor value
VCC
IL (max)[1]
47 nF
100 nF
2.7 V to 4.5 V
2.7 V to 4.5 V
3.0 V to 4.5 V
8 mA
8 mA
18 mA
[1] For output voltage VBUS > 4.7 V (bit VBUS_VLD = 1).
7.10.12 VCC(I/O)
This pin is an input and sets logic thresholds. It also powers the pads of the following logic
pins:
• ADR/PSW
• DAT/VP, SE0/VM and RCV
• VM and VP
• INT_N
• OE_N/INT_N
• RESET_N
• SPEED
• SUSPEND
• SCL and SDA
7.10.13 AGND, CGND and DGND
AGND, CGND and DGND are ground pins for analog, charge pump and digital circuits,
respectively. These pins can be connected separately or together depending on the
system performance requirements.
8. Modes of operation
There are four types of modes in the ISP1301:
• Power modes
• Direct I2C-bus mode
• USB modes
• Transparent modes
8.1 Power modes
Power modes of the ISP1301 are as follows:
• Active power mode: power is on.
• USB suspend mode: to reduce power consumption, the USB differential receiver is
powered down.
• Global power-down mode: set bit GLOBAL_PWR_DN = 1 of the Mode Control 2
register; the differential transmitter and receiver, clock generator, charge pump, and
all biasing circuits are turned off to reduce power consumption to the minimum
possible; for details on waking up the clock, see Section 11.
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
12 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
8.2 Direct I2C-bus mode
In direct I2C-bus mode, an external I2C-bus master (OTG Controller) directly
communicates with the serial controller through the SCL and SDA lines. The serial
controller has a built-in I2C-bus slave function.
In this mode, an external I2C-bus master can access the internal registers of the device
(Status, Control, Interrupt, and so on) through the I2C-bus interface.
The supported I2C-bus bit rate is 100 kbit/s (maximum).
The ISP1301 is in direct I2C-bus mode when either bit TRANSP_EN bit = 0 or pin
OE_N/INT_N is de-asserted.
8.3 USB modes
The four USB modes of the ISP1301 are:
• VP_VM unidirectional mode
• VP_VM bidirectional mode
• DAT_SE0 unidirectional mode
• DAT_SE0 bidirectional mode
In VP_VM USB mode, the DAT/VP pin is used for the VP function, the SE0/VM pin is used
for the VM function, and the RCV pin is used for the RCV function.
In DAT_SE0 USB mode, the DAT/VP pin is used for the DAT function, the SE0/VM pin is
used for the SE0 function, and the RCV pin is not used.
In unidirectional mode, the DAT/VP and SE0/VM pins are always inputs. In bidirectional
mode, the direction of these signals depends on the OE_N/INT_N input.
Table 6 specifies the functionality of the device during the four USB modes.
The ISP1301 is in USB mode when both the TRANSP_EN and UART_EN bits are
cleared.
8.4 Transparent modes
8.4.1 Transparent general-purpose buffer mode
In transparent general-purpose buffer mode, the DAT/VP and SE0/VM pins are connected
to the DP and DM pins, respectively. Using bits TRANSP_BDIR1 and TRANSP_BDIR0 of
the Mode Control 2 register as specified in Table 8, you can control the direction of data
transfer. The ISP1301 is in transparent general-purpose buffer mode if bit
TRANSP_EN = 1 and bit DAT_SE0 = 1.
8.4.2 Transparent UART mode
When in transparent UART mode, the ATX behaves as two logic level translator between
the following pins:
• For the TxD signal: from SE0/VM (VCC(I/O) level) to DM (+3.3 V level).
• For the RxD signal: from DP (+3.3 V level) to DAT/VP (VCC(I/O) level).
ISP1301_3
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Product data sheet
Rev. 03 — 21 February 2006
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ISP1301
Philips Semiconductors
USB OTG transceiver
In UART mode, the OTG Controller is allowed to connect a UART to the DAT/VP and
SE0/VM pins of the ISP1301.
UART mode is entered by setting the UART_EN bit in the Mode Control 1 register. UART
mode is equivalent to one of transparent general purpose buffer mode (bit
TRANSP_BDIR1 = 1, bit TRANSP_BDIR0 = 0).
8.4.3 Summary tables
Table 4:
Mode
Device operating modes
USB
Bit
Pin
Bit
Bit
Description
suspend
DAT
OE_N/ TRANSP UART
condition[1] _SE0
INT_N _EN
_ EN
Direct I2C-bus mode
Direct I2C-bus mode
X
X
X
X
X
1
X
0
1
1
X
X
X
-
HIGH
X
USB modes
USB suspend mode
USB functional mode
Transparent modes
1
0
X
X
X
X
0
0
0
0
see Table 5 and Table 7
ATX is fully functional; see Table 6
Transparent
general-purpose buffer
mode
X
X
1
X
X
1
0
1
ATX is not functional; see Table 8
Transparent UART mode
X
X
DAT/VP ← DP (RxD signal of UART)
SE0/VM → DM (TxD signal of UART);
ATX is not functional
[1] Conditions:
a) bit SPD_SUSP_CTRL = 0 and pin SUSPEND = HIGH, or
b) bit SPD_SUSP_CTRL = 1 and bit SUSPEND_REG = 0.
Table 5:
Pin
USB suspend mode: I/O
Function
DP as output
DM as output
VBUS
can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z[1]
can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z[1]
can be driven depending on bit VBUS_DRV
SCL
connected to SCL I/O of the I2C-bus slave
SDA
connected to SDA I/O of the I2C-bus slave
[1] In USB suspend mode, the ISP1301 can drive the DP and DM lines, if the OE_N/INT_N input (when the
OE_INT_EN bit is not set) is LOW. In such a case, these outputs are driven as in USB functional modes,
but with the full-speed characteristics, irrespective of the value of the SPEED input pin or the SPEED_REG
bit.
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Table 6:
USB functional modes: I/O values
USB mode[1]
Bit
Pin
DAT_SE0
BI_DI
OE_N/
INT_N
DAT/VP
SE0/VM VP
VM
RCV
VP_VM
unidirectional
bidirectional
0
0
0
1
1
1
0
1
1
0
1
1
X
TxD+[2]
TxD+[2]
RxD+[3]
TxD[4]
TxD[4]
RxD[6]
TxD− [2]
TxD− [2]
RxD− [3]
FSE0[5]
FSE0[5]
RSE0[7]
RxD+[3] RxD− [3]
RxD[6]
LOW
HIGH
X
DAT_SE0 unidirectional
bidirectional
LOW
HIGH
[1] Some of the modes and signals are provided to achieve backward compatibility with IP cores.
[2] TxD+ and TxD− are single-ended inputs to drive the DP and DM outputs, respectively, in single-ended mode.
[3] RxD+ and RxD− are the outputs of the single-ended receivers connected to DP and DM, respectively.
[4] TxD is the input to drive DP and DM in DAT_SE0 mode.
[5] FSE0 is to force an SE0 on the DP and DM lines in DAT_SE0 mode.
[6] RxD is the output of the differential receiver.
[7] RSE0 is an output indicating that an SE0 has been received on the DP and DM lines.
Table 7:
USB suspend mode: I/O values
USB suspend mode
Input pin
Output pin
DAT/VP
LOW
DP
DM
SE0/VM
HIGH
LOW
VP
VM
RCV
X
DAT_SE0
(bit DAT_SE0 = 1)
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
HIGH
X
LOW
LOW
X
HIGH
LOW
X
VP_VM
(bit DAT_SE0 = 0)
LOW
LOW
X
HIGH
LOW
X
LOW
HIGH
HIGH
X
HIGH
X
Table 8:
Bit
Transparent general-purpose buffer mode
Direction of the data flow
TRANSP_BDIR[1:0]
00
01
10
11
DAT/VP → DP
DAT/VP → DP
DAT/VP ← DP
DAT/VP ← DP
SE0/VM → DM
SE0/VM ← DM
SE0/VM → DM
SE0/VM ← DM
9. USB transceiver
9.1 Differential driver
The operation of the driver is described in Table 9. The register bits and the pins used in
the column heading are described in Section 10.1 and Section 7.10, respectively.
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Table 9:
Transceiver driver operation setting
Suspend[1] Bit
TRANSP_
Pin
OE_N/
INT_N
Bit
DAT_SE0
Differential driver
EN
0
0
0
LOW
0
1
output value from DAT/VP to DP and
SE0/VM to DM
0
LOW
output value from DAT/VP to DP and DM if
SE0/VM is 0; otherwise, drive both DP and
DM LOW
1
0
X
1
LOW
HIGH
X
X
X
X
output value from DAT/VP to DP and DM
X
X
high-Z
high-Z
[1] Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
Table 10: USB functional mode: transmit operation
USB mode
Input pin
DAT/VP
LOW
Output pin
DP
SE0/VM
LOW
DM
DAT_SE0
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
VP_VM
LOW
HIGH
LOW
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
9.2 Differential receiver
Table 11 describes the operation of the differential receiver. The register bits and the pins
used in the column heading are described in Section 10.1 and Section 7.10, respectively.
The detailed behavior of the receive transceiver operation is given in Table 12.
Table 11: Differential receiver operation settings
Suspend[1] Bit
TRANSP_EN
Pin
OE_N/INT_N
Bit
DAT_SE0
Differential receiver
1
X
X
0
X
X
X
X
X
1
X
0
0
X
1
0
LOW
X
HIGH
output differential value from DP
and DM to DAT/VP and RCV
0
0
HIGH
0
output differential value from DP
and DM to RCV
[1] Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
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Table 12: USB functional mode: receive operation
USB mode Suspend[1] Input pin
Output pin
DAT/VP
RCV
DP
DM
SE0/VM
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
RCV
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
VP_VM
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
last value of RCV
HIGH
LOW
HIGH
LOW
RCV
last value of RCV
LOW
X
HIGH
LOW
X
X
HIGH
LOW
X
last value of RCV
VP_VM
HIGH
LOW
HIGH
VP_VM
LOW
VP_VM
HIGH
LOW
last value of RCV
VP_VM
X
X
X
X
VP_VM
HIGH
LOW
VP_VM
VP_VM
HIGH
[1] Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
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10. Serial controller
10.1 Register map
Table 13 provides an overview of the serial controller registers.
Table 13: Serial controller registers
Register
Width Access[1] Memory address Functionality
Reference
(bits)
Vendor ID
16
R
00h to 01h
02h to 03h
14h to 15h
Set — 04h
Clear — 05h
Set — 12h
Clear — 13h
Set — 06h
Clear — 07h
10h
device identification registers Section 10.1.1 on page 18
Product ID
Version ID
16
R
16
R
Mode Control 1
8
R/S/C
mode control registers
Section 10.1.2 on page 19
Mode Control 2
OTG Control
8
8
R/S/C
R/S/C
OTG registers
Section 10.1.3 on page 20
Section 10.1.4 on page 21
OTG Status
8
8
8
R
Interrupt Source
Interrupt Latch
R
08h
interrupt related registers
R/S/C
Set — 0Ah
Clear — 0Bh
Set — 0Ch
Clear — 0Dh
Set — 0Eh
Clear — 0Fh
Interrupt Enable Low
Interrupt Enable High
8
8
R/S/C
R/S/C
[1] The R/S/C access type represents a field that can be read, set or cleared (set to 0). A register can be read from either of the indicated
addresses: set or clear. Writing logic 1 to the set address causes the associated bit to be set. Writing logic 1 to the clear address causes
the associated bit to be cleared. Writing logic 0 to an address has no effect.
10.1.1 Device identification registers
10.1.1.1 Vendor ID register (Read: 00h to 01h)
Table 14 provides the bit description of the Vendor ID register.
Table 14: Vendor ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
VENDORID[15:0]
R
04CCh
Philips Semiconductors’ Vendor ID
10.1.1.2 Product ID register (Read: 02h to 03h)
The bit description of this register is given in Table 15.
Table 15: Product ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0
PRODUCTID[15:0]
R
1301h
Product ID of the ISP1301
10.1.1.3 Version ID register (Read: 14h to 15h)
Table 16 shows the bit description of this register.
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Table 16: Version ID register: bit description
Bit
Symbol
Access
Value
Description
Version number of the ISP1301
15 to 0
VERSIONID[15:0] R
0210h
10.1.2 Mode control registers
10.1.2.1 Mode Control 1 register (Set/Clear: 04h/05h)
The bit allocation of the Mode Control 1 register is given in Table 17.
Table 17: Mode Control 1 register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
UART_EN
OE_INT_
EN
BDIS_
ACON_EN
TRANSP_
EN
DAT_SE0
SUSPEND
_REG
SPEED_
REG
Reset
-
0
0
0
0
0
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 18: Mode Control 1 register: bit description
Bit
7
Symbol
-
Description
reserved
6
UART_EN
OE_INT_EN
When set, the ATX is in transparent UART mode.
5
When set and when in suspend mode, pin OE_N/INT_N becomes
an output and is asserted when an interrupt occurs.
4
BDIS_ACON_EN
Enables the A-device to connect if the B-device disconnect is
detected; see Section 10.3.
3
2
TRANSP_EN
DAT_SE0
When set, the ATX is in transparent mode.
0 — VP_VM mode
1 — DAT_SE0 mode; see Table 6 and Table 7
Sets the ISP1301 in suspend mode, if bit SPD_SUSP_CTRL = 1.
0 — active-power mode
1
0
SUSPEND_REG
SPEED_REG
1 — USB suspend mode
Sets the rise time and the fall time of the transmit driver in USB
modes, if bit SPD_SUSP_CTRL = 1.
0 — USB low-speed mode
1 — USB full-speed mode
10.1.2.2 Mode Control 2 register (Set/Clear: 12h/13h)
For the bit allocation of this register, see Table 19.
Table 19: Mode Control 2 register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EN2V7
PSW_OE AUDIO_EN TRANSP_ TRANSP_
BI_DI
SPD_SUSP GLOBAL_
BDIR1
BDIR0
_CTRL
PWR_DN
Reset
0
0
0
0
0
1
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
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Table 20: Mode Control 2 register: bit description
Bit
Symbol
Description
7
EN2V7
0 — VCC = 3.0 V to 4.5 V
1 — VCC = 2.7 V to 4.5 V
0 — ADR/PSW pin acts as an input
1 — ADR/PSW pin is driven
6
5
PSW_OE
AUDIO_EN
0 — SE receiver is enabled; cr_int detector is disabled
1 — SE receiver is turned off (pin VP = LOW, pin VM = LOW);
cr_int detector is enabled
4 to 3
2
TRANSP_BDIR[1:0] controls the direction of data transfer in transparent
general-purpose buffer mode; see Table 8
BI_DI
0 — direction of DAT/VP and SE0/VM are fixed (transmit only)
1 — direction of DAT/VP and SE0/VM are controlled by
pin OE_N/INT_N; see Table 6
1
0
SPD_SUSP_CTRL
control of speed and suspend in USB modes:
0 — controlled by pins SPEED and SUSPEND
1 — controlled by bit SPEED_REG and bit SUSPEND_REG of
the Mode Control 1 register
GLOBAL_PWR_DN 0 — normal operation
1 — sets the ISP1301 to Power-down mode
Activities on the I2C-bus or any OTG event can wake-up the chip;
see Section 11
10.1.3 OTG registers
10.1.3.1 OTG Control register (Set/Clear: 06h/07h)
Table 21 provides the bit allocation of the OTG Control register.
Table 21: OTG Control register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
VBUS_
CHRG
VBUS_
DISCHRG
VBUS_
DRV
ID_PULL
DOWN
DM_PULL
DOWN
DP_PULL
DOWN
DM_PULL
UP
DP_PULL
UP
Reset
0
0
0
0
1
1
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 22: OTG Control register: bit description
Bit
7
Symbol
Description
VBUS_CHRG
VBUS_DISCHRG
VBUS_DRV
charge VBUS through a resistor to 3.3 V
discharge VBUS through a resistor to ground
drive VBUS to 5 V through the charge pump
connect the ID pin to ground
6
5
4
ID_PULLDOWN
DM_PULLDOWN
DP_PULLDOWN
DM_PULLUP
DP_PULLUP
3
connect the DM pull-down resistor to ground
connect the DP pull-down resistor to ground
connect the DM pull-up resistor to 3.3 V
connect the DP pull-up resistor to 3.3 V
2
1
0
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10.1.3.2 OTG Status register (Read: 10h)
Table 23 shows the bit allocation of the OTG Status register.
Table 23: OTG Status register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
B_SESS_
VLD
B_SESS_
END
reserved
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 24: OTG Status register: bit description
Bit
Symbol
Description
7
B_SESS_VLD
set when the VBUS voltage is above the B-device session valid
threshold (2.0 V to 4.0 V)
6
B_SESS_END
-
set when the VBUS voltage is below the B-device session end
threshold (0.2 V to 0.8 V)
5 to 0
reserved
10.1.4 Interrupt related registers
10.1.4.1 Interrupt Source register (Read: 08h)
This register indicates the current state of the signals that can generate an interrupt. The
bit allocation of the Interrupt Source register is given in Table 25.
Table 25: Interrupt Source register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD VBUS_VLD
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 26: Interrupt Source register: bit description
Bit
7
Symbol
Description
DP pin is above the carkit interrupt threshold (0.4 V to 0.6 V)
CR_INT
6
BDIS_ACON
set when bit BDIS_ACON_EN is set, and the ISP1301 asserts bit
DP_PULLUP after detecting the B-device disconnect
5
4
3
2
1
0
ID_FLOAT
DM_HI
ID pin is floating
DM pin is HIGH
ID_GND
DP_HI
ID pin is connected to ground
DP pin is HIGH
SESS_VLD
VBUS_VLD
session valid comparator; threshold = 0.8 V to 2.0 V
A-device VBUS valid comparator; threshold > 4.4 V
10.1.4.2 Interrupt Latch register (Set/Clear: 0Ah/0Bh)
This register indicates the source that generated the interrupt. The bit allocation of the
Interrupt Latch register is given in Table 27.
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Table 27: Interrupt Latch register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD VBUS_VLD
Reset
0
0
0
0
0
0
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 28: Interrupt Latch register: bit description
Bit
7
Symbol
Description
CR_INT
interrupt for CR_INT status change
interrupt for BDIS_ACON status change
interrupt for ID_FLOAT status change
interrupt for DM_HI status change
interrupt for ID_GND status change
interrupt for DP_HI status change
interrupt for SESS_VLD status change
interrupt for VBUS_VLD status change
6
BDIS_ACON
ID_FLOAT
DM_HI
5
4
3
ID_GND
2
DP_HI
1
SESS_VLD
VBUS_VLD
0
10.1.4.3 Interrupt Enable Low register (Set/Clear: 0Ch/0Dh)
This register enables interrupts on transition from true to false. For the bit allocation of this
register, see Table 29.
Table 29: Interrupt Enable Low register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD VBUS_VLD
Reset
0
0
0
0
0
0
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 30: Interrupt Enable Low register: bit description
Bit
7
Symbol
Description
CR_INT
interrupt enable for CR_INT status change from 1 to 0
interrupt enable for BDIS_ACON status change from 1 to 0
interrupt enable for ID_FLOAT status change from 1 to 0
interrupt enable for DM_HI status change from 1 to 0
interrupt enable for ID_GND status change from 1 to 0
interrupt enable for DP_HI status change from 1 to 0
interrupt enable for SESS_VLD status change from 1 to 0
interrupt enable for VBUS_VLD status change from 1 to 0
6
BDIS_ACON
ID_FLOAT
DM_HI
5
4
3
ID_GND
2
DP_HI
1
SESS_VLD
VBUS_VLD
0
10.1.4.4 Interrupt Enable High register (Set/Clear: 0Eh/0Fh)
The Interrupt Enable High register enables interrupts on transition from FALSE to TRUE.
Table 31 provides the bit allocation of this register.
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Table 31: Interrupt Enable High register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD VBUS_VLD
Reset
0
0
0
0
0
0
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 32: Interrupt Enable High register: bit description
Bit
7
Symbol
Description
CR_INT
interrupt enable for CR_INT status change from 0 to 1
interrupt enable for BDIS_ACON status change from 0 to 1
interrupt enable for ID_FLOAT status change from 0 to 1
interrupt enable for DM_HI status change from 0 to 1
interrupt enable for ID_GND status change from 0 to 1
interrupt enable for DP_HI status change from 0 to 1
interrupt enable for SESS_VLD status change from 0 to 1
interrupt enable for VBUS_VLD status change from 0 to 1
6
BDIS_ACON
ID_FLOAT
DM_HI
5
4
3
ID_GND
2
DP_HI
1
SESS_VLD
VBUS_VLD
0
10.2 Interrupts
Table 26 indicates the signals that can generate interrupts. Any of the signals given in
Table 26 can generate an interrupt when the signal becomes either LOW or HIGH. After
an interrupt has been generated, the OTG Controller should be able to read the status of
each signal and the bit that indicates whether that signal generated the interrupt.
A bit in the Interrupt Latch register is set when any of these occurs:
• Writing logic 1 to its set address causes the corresponding bit to be set.
• The corresponding bit in the Interrupt Enable High register is set, and the associated
signal changes from LOW to HIGH.
• The corresponding bit in the Interrupt Enable Low register is set, and the associated
signal changes from HIGH to LOW.
The Interrupt Latch register bit is cleared by writing logic 1 to its clear address.
10.3 Auto-connect
The Host Negotiation Protocol (HNP) in the OTG supplement specifies the following
sequence of events to transfer the role of the host from the A-device to the B-device:
1. The A-device puts the bus in the suspend state.
2. The B-device simulates a disconnect by de-asserting its DP pull-up.
3. The A-device detects SE0 on the bus, and asserts its DP pull-up.
4. The B-device detects that the DP line is HIGH, and takes the role of the host.
The OTG supplement specifies that the time between the B-device de-asserting its DP
pull-up and the A-device asserting its pull-up must be less than 3 ms. For an A-device with
a slow interrupt response time, 3 ms may not be enough time to write an I2C-bus
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command to the ISP1301 to assert the DP pull-up. An alternative method is for the
A-device transceiver to automatically assert the DP pull-up after detecting an SE0 from
the B-device.
The sequence of events is: After finishing data transfers between the A-device and the
B-device and before suspending the bus, the A-device sends SOFs. The B-device
receives these SOFs, and does not transmit any packet back to the A-device. During this
time, the A-device sets the BDIS_ACON_EN bit in the ISP1301. This enables the
ISP1301 to look for SE0 whenever the A-device is not transmitting (that is, whenever the
OE_N/INT_N pin of the ISP1301 is not asserted). After the BDIS_ACON_EN bit is set, the
A-device stops transmitting SOFs and allows the bus to go to the idle state. If the B-device
disconnects, the bus goes to SE0, and the ISP1301 logic automatically turns on the
A-device pull-up.
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11. Clock wake-up scheme
The following subsections explain the ISP1301 clock stop timing, events triggering the
clock to wake up, and the timing of the clock wake-up.
11.1 Power-down event
The clock is stopped when the GLOBAL_PWR_DN bit is set. It takes approximately 8 ms
for the clock to stop from the time the power-down condition is detected. The clock always
stops at its falling edge. The waveform is given in Figure 7.
SCL
GLOBAL_PWR_DN
CLOCK
8 ms
004aaa217
Fig 7. Clock stopped using the GLOBAL_PWR_DN bit
11.2 Clock wake-up events
The clock wakes up when any of the following events occur on the ISP1301 pins:
• SCL goes LOW.
• VBUS goes above the session valid threshold (0.8 V to 2.0 V), provided the
SESS_VLD bit in the Interrupt Enable High register is set.
• ID changes when mini-A plug is inserted, provided the ID_FLOAT bit in the Interrupt
Enable Low register is set.
• ID changes when mini-A plug is removed, provided the ID_FLOAT bit in the Interrupt
Enable High register is set.
• DP goes HIGH, provided the DP_HI bit in the Interrupt Enable High register is set.
• DM goes HIGH, provided the DM_HI bit in the Interrupt Enable High register is set.
The event triggers the clock to start and a stable clock is guaranteed after about six clock
periods, which is approximately 8 µs. The startup analog clock time is 10 µs. Therefore,
the total estimated start time after a triggered event is about 20 µs. The clock will always
start at its rising edge.
Waveforms of the clock wake-up because of different events are given in Figure 8,
Figure 9, Figure 10, Figure 11 and Figure 12.
SCL
CLOCK
004aaa218
20 µs
Fig 8. Clock wake-up using SCL
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SESS_VLD
CLOCK
004aaa219
20 µs
20 µs
20 µs
Fig 9. Clock wake-up by VBUS
ID_FLOAT
CLOCK
004aaa220
Fig 10. Clock wake-up by ID change (1)
ID_FLOAT
CLOCK
004aaa221
Fig 11. Clock wake-up by ID change (2)
DP_HI
or DM_HI
CLOCK
20 µs
004aaa434
Fig 12. Clock wake-up by data line SRP
When an event is triggered and the clock is started, it will remain active for 8 ms. If the
GLOBAL_PWR_DN bit is not cleared within this 8 ms period, the clock will stop. If the
clock wakes up because of any event other than SCL going LOW, an interrupt will be
generated once the clock is active.
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USB OTG transceiver
12. I2C-bus protocol
For detailed information, refer to The I2C-bus specification; version 2.1.
12.1 I2C-bus byte transfer format
Table 33: I2C-bus byte transfer format
S[1]
Byte 1
A[2]
Byte 2
A[2]
Byte 3
A[2]
..
A[2]
P[3]
8 bits
8 bits
8 bits
..
[1] S = Start.
[2] A = Acknowledge.
[3] P = Stop.
12.2 I2C-bus device address
Table 34: I2C-bus device address byte 1 bit allocation
Bit
7
A6
0
6
A5
1
5
A4
0
4
A3
1
3
A2
1
2
A1
0
1
0
R/W_N
X
Symbol
Value
A0
[1]
[1] The value of A0 (LSB) is loaded from pin ADR/PSW during reset (including power-on reset). If pin
ADR/PSW = HIGH, bit A0 = 1; otherwise bit A0 = 0.
Table 35: I2C-bus device address byte 1 bit description
Bit
7 to 1
0
Symbol Description
A[6:0]
Device address: The device address of the ISP1301 is: 01 0110 (A0).
R/W_N Read or write command.
0 — write
1 — read
12.3 Write format
A write operation can be performed as:
• One-byte write to the specified register address.
• Multi-byte write to N consecutive registers, starting from the specified start address. N
defines the number of registers to write. If N = 1, only the start register is written.
12.3.1 One-byte write
Figure 13 illustrates the byte sequence.
Table 36: Transfer format description for one-byte write
Byte
Description
S
master starts with a START condition
master transmits device address and write command bit R/W = 0
slave generates an acknowledgment
Device select
ACK
Register address K master transmits address of register K
ACK
slave generates an acknowledgment
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Table 36: Transfer format description for one-byte write…continued
Byte
Description
Write data K
master writes data to register K
slave generates an acknowledgment
master generates a STOP condition
ACK
P
12.3.2 Multiple-byte write
Figure 13 illustrates the byte sequence.
Table 37: Transfer format description for multiple-byte write
Byte
Description
S
master starts with a START condition
Device select
ACK
master transmits device address and write command bit R/W = 0
slave generates an acknowledgment
Register address K master transmits address of register K. This is the start address for writing
multiple data bytes to consecutive registers. After a byte is written, the
register address is automatically incremented by 1.
Remark: If the master writes to a non existent register, the slave must send
a 'not ACK' and also must not increment the index address.
ACK
slave generates an acknowledgment
master writes data to register K
slave generates an acknowledgment
master writes data to register K + 1
slave generates an acknowledgment
:
Write data K
ACK
Write data K + 1
ACK
:
Write data K + N − 1 master writes data to register K + N − 1. When the incremented address
K + N − 1 becomes > 255, the register address rolls over to 0. Therefore, it
is possible that some registers may be overwritten, if the transfer is not
stopped before the rollover.
ACK
P
slave generates an acknowledgment
master generates a STOP condition
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ACK
ACK
ACK
P
write data K
S
register address K
device select
wr
one-byte write
ACK
ACK
ACK
ACK
ACK
ACK
write data K
S
wr
write data K + 1
device select
register address K
write data K + 3
ACK
.... maximum, rollover to 0
ACK
P
write data K + N - 1
write data K + 2
004aaa569
multiple-byte write
Fig 13. Writing data to the ISP1301 registers
12.4 Read format
A read operation can be performed in two ways:
• Current address read: to read the register at the current address.
– Single register read
• Random address read: to read N registers starting at a specified address. N defines
the number of registers to be read. If N = 1, only the start register is read.
– Single register read
– Multiple register read
12.4.1 Current address read
Figure 14 illustrates the byte sequence.
Table 38: Transfer format description for current address read
Byte
Description
S
master starts with a START condition
master transmits device address and read command bit R/W = 1
slave generates an acknowledgment
Device select
ACK
Read data K
slave transmits and master reads data from register K. If the start address is
not specified, the read operation starts from where the index register is
pointing to because of a previous read or write operation.
No ACK
P
master terminates the read operation by generating a No Acknowledge
master generates a stop condition
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USB OTG transceiver
ACK
rd
current address read
no ACK
P
S
device select
read data K
004aaa570
Fig 14. Current address read
12.4.2 Random address read
12.4.2.1 Single read
Figure 15 illustrates the byte sequence.
Table 39: Transfer format description for single-byte read
SDA line
S
Description
master starts with a START condition
Device select
ACK
master transmits device address and writes command bit R/W = 0
slave generates an acknowledgment
Register address K master transmits (start) address of register K to be read from
ACK
slave generates an acknowledgment
Device select
master transmits device address and read command bit R/W = 1
slave generates an acknowledgment
ACK
S
master restarts with a START condition
Read data K
No ACK
P
slave transmits and master reads data from register K
master terminates the read operation by generating a No Acknowledge
master generates a STOP condition
12.4.2.2 Multiple read
Figure 15 illustrates the byte sequence.
Table 40: Transfer format description for multiple-byte read
SDA line
S
Description
master starts with a START condition
master transmits device address and write command bit R/W = 0
slave generates an acknowledgment
Device select
ACK
Register address K master transmits (start) address of register K to be read from
ACK
slave generates an acknowledgment
S
master restarts with a START condition
Device select
ACK
master transmits device address and read command bit R/W = 1
slave generates an acknowledgment
Read data K
slave transmits and master reads data from register K. After a byte is read,
the address is automatically incremented by 1.
ACK
master generates an acknowledgment
slave transmits and master reads data from register K + 1
master generates an acknowledgment
:
Read data K + 1
ACK
:
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Table 40: Transfer format description for multiple-byte read…continued
SDA line Description
Read data K + N − 1 slave transmits and master reads data register K + N − 1. This is the last
register to read. After incrementing, the address rolls over to 0. Here, N
represents the number of addresses available in the slave.
No ACK
P
master terminates the read operation by generating a No Acknowledge
master generates a STOP condition
ACK
ACK
no ACK
P
ACK
S
rd
S
wr
device select
device select
read data K
register address K
random address single read
ACK
S
ACK
ACK
ACK
ACK
wr
device select
rd
ACK
S
device select
register address K
read data K
ACK
.... maximum, rollover to 0
no ACK
P
write data K + N - 1
read data K + 1
read data K + 2
004aaa571
random access multiple read
Fig 15. Random address read
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13. Limiting values
Table 41: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
Parameter
Conditions
Min
−0.5
−0.5
−0.5
-
Max
Unit
V
supply voltage
+4.6
VCC(I/O)
VI
input/output supply voltage
input voltage
+4.6
V
VI = −1.8 V to +5.4 V
ILI < 1 µA
VCC(I/O) + 0.5 V
100
V
Ilu
latch-up current
mA
Vesd
electrostatic discharge voltage
[1]
pins DP, DM, ID,
VBUS, AGND, CGND
and DGND
−8
+8
kV
all other pins
−2
+2
kV
Tstg
storage temperature
−60
+125
°C
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model). A 4.7 µF capacitor is needed from
VREG3V3 and VBUS to ground.
14. Recommended operating conditions
Table 42: Recommended operating conditions
Symbol
VCC
Parameter
Conditions
Min
2.7
1.65
0
Typ
Max
3.6
Unit
V
supply voltage
-
-
-
-
-
-
[1]
VCC(I/O)
VI
input/output supply voltage
input voltage
3.6
V
VCC(I/O)
3.6
V
[2]
[3]
VIA(I/O)
V(pu)OD
Tamb
input voltage on analog I/O pins
open-drain pull-up voltage
ambient temperature
0
V
0
3.6
V
−40
+85
°C
[1] VCC(I/O) should be less than or equal to VCC
.
[2] Input voltage on analog I/O pins DP and DM.
[3] Open-drain output pull-up voltage on pins SCL, SDA and INT_N.
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USB OTG transceiver
15. Static characteristics
Table 43: Static characteristics: supply pins
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Charge pump disabled
[1]
[2]
VO(REG3V3) output voltage from internal 3.3 V VCC = 3.0 V to 4.5 V
3.0
2.7
1.5
-
-
3.6
3.0
2.5
8
V
regulator
VCC = 2.7 V to 3.0 V
-
V
VPOR(trip)
ICC
power-on reset trip voltage
supply current
-
V
transmitting and receiving at
12 Mbit/s; CL = 50 pF on
pins DP and DM
4
mA
[2]
[3]
ICC(I/O)
ICC(idle)
supply current on pin VCC(I/O)
idle and SE0 supply current
transmitting and receiving at
12 Mbit/s
-
-
1
-
2
mA
idle: VDP > 2.7 V, VDM < 0.3 V;
SE0: VDP < 0.3 V, VDM < 0.3 V
300
µA
ICC(I/O)(static) static supply current on pin VCC(I/O) idle, SE0 or suspend
ICC(pd) Power-down mode supply current bit GLOBAL_PWR_DN = 1
Charge pump enabled
-
-
-
-
20
20
µA
µA
[3]
ICC(cp)
charge pump supply current
Iload = 8 mA; ATX is idle
Iload = 0 mA; ATX is idle
-
-
-
-
20
mA
300
µA
[1] In suspend mode, the minimum voltage is 2.7 V.
[2] Maximum value characterized only, not tested in production.
[3] Excluding any load current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 µA typical).
Table 44: Static characteristics: digital pins
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Input levels
VIL
Parameter
Conditions
Min
Typ
Max
Unit
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.3VCC(I/O)
-
V
V
VIH
0.6VCC(I/O)
Output levels
VOL
LOW-level output voltage
HIGH-level output voltage
IOL = 2 mA
-
-
-
-
-
-
0.4
V
V
V
V
IOL = 100 µA
IOH = 2 mA
IOH = 100 µA
0.15
[1]
VOH
V
CC(I/O) − 0.4 V
CC(I/O) − 0.15 V
-
-
V
Leakage current
ILI
input leakage current
−1
−5
-
-
-
-
+1
+5
10
µA
µA
pF
Open-drain outputs
IOZ
off-state output current
Capacitance
Cin
input capacitance
pin to GND
[1] Not applicable for open-drain outputs.
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Table 45: Static characteristics: analog I/O pins DP and DM
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input levels
VDI
differential input sensitivity
|VI(DP) − VI(DM)
|
0.2
0.8
-
-
-
-
-
-
V
V
V
V
VCM
differential common-mode range includes VDI range
LOW-level input voltage
2.5
0.8
-
VIL
VIH
HIGH-level input voltage
2.0
Output levels
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
RL of 1.5 kΩ to +3.6 V
RL of 15 kΩ to GND
VCC = 3.0 V to 4.5 V
VCC = 2.7 V to 3.0 V
-
-
0.3
V
2.8
2.6
-
-
3.6
3.0
V
V
Leakage current
ILZ
off-state leakage current
−1
-
-
+1
10
µA
Capacitance
Cin
input capacitance
pin to GND
-
pF
Resistance
RDN(DP)
RDN(DM)
RUP(DP)
pull-down resistance on pin DP
pull-down resistance on pin DM
pull-up resistance on pin DP
14.25
14.25
900
-
-
-
-
-
-
-
-
24.8
24.8
1575
3090
1575
3090
44
kΩ
kΩ
Ω
bus idle
bus driven
bus idle
1425
900
Ω
RUP(DM)
pull-up resistance on pin DM
Ω
bus driven
steady-state drive
1425
34
Ω
[1]
ZDRV
driver output impedance
input impedance
Ω
ZINP
10
-
MΩ
Termination
VTERM
termination voltage
for the upstream port
3.0
-
3.6
V
pull-up resistor (RPU
)
[1] Includes external series resistors of 33 Ω ± 1 % each on DP and DM.
Table 46: Static characteristics: analog I/O pin ID
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Resistance
RUP(ID)
Parameter
Conditions
Min
Typ
Max
Unit
ID pull-up resistance
on pin ID to VREG3V3
77
-
-
-
-
130
10
1
kΩ
Ω
RDN(ID)
pull-down resistance on pin ID bit ID_PULLDOWN = 1
RA_ID
A-device ID impedance to
GND
bit ID_GND = 1
-
kΩ
RB_ID
B-device ID impedance to
GND
bit ID_FLOAT = 1
800
20
-
-
-
kΩ
kΩ
RACC_ID
accessory device ID
impedance to GND
bit ID_GND = 0;
bit ID_FLOAT = 0
200
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USB OTG transceiver
Table 47: Static characteristics: charge pump
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Current
Iload
Parameter
Conditions
Min
Typ
Max
Unit
load current
Cext = 100 nF;
8.0
-
-
mA
VBUS = 4.65 V
Voltage
VO(VBUS)
output voltage on pin VBUS Iload = 8 mA;
ext = 100 nF
4.65
-
5
-
5.25
0.2
V
V
C
VL(VBUS)
leakage voltage on
pin VBUS
charge pump disabled
VA_VBUS_VLD
VB_SESS_END
A-device VBUS valid voltage
4.4
0.2
-
-
4.65
0.8
V
V
B-device session end
voltage
Vhys(B_SESS_END) B-device session end
hysteresis voltage
-
150
-
-
mV
V
VA_SESS_VLD
A-device session valid
voltage
0.8
2.0
Vhys(A_SESS_VLD) A-device session valid
hysteresis voltage
-
200
-
-
mV
V
VB_SESS_VLD
B-device session valid
voltage
2.0
4.0
Vhys(B_SESS_VLD) B-device session valid
hysteresis voltage
-
-
200
75
-
-
mV
%
ηcp
charge pump efficiency
Iload = 8 mA; VCC = 3 V
Resistance
RUP(VBUS)
pull-up resistance on
pin VBUS
connect to VREG3V3
when VBUS_CHRG = 1
460
660
40
-
-
-
1000
1200
100
Ω
RDN(VBUS)
pull-down resistance on
pin VBUS
connect to GND when
VBUS_DISCHRG = 1
Ω
RI(idle)(VBUS)(A)
idle input resistance on
pin VBUS (A-device)
ID pin connected to
GND
kΩ
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USB OTG transceiver
16. Dynamic characteristics
Table 48: Dynamic characteristics: reset and clock
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Reset
Parameter
Conditions
Min
Typ
Max
-
Unit
µs
tW(RESET_N) external RESET_N pulse width
10
-
Internal clock
fclk
clock frequency
bit GLOBAL_PWR_DN = 0
700
1000
1300
kHz
Table 49: Dynamic characteristics: digital I/O pins
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tTOI
bus turnaround time (O/I) OE_N/INT_N to DAT/VP and
SE0/VM; see Figure 20
0
-
5
ns
tTIO
bus turnaround time (I/O) OE_N/INT_N to DAT/VP and
SE0/VM; see Figure 20
0
-
5
ns
Table 50: Dynamic characteristics: analog I/O pins DP and DM
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
tFR
rise time
fall time
CL = 50 pF to 125 pF;
10 % to 90 % of
|VOH − VOL|; see Figure 16
4
-
20
ns
tFF
CL = 50 pF to 125 pF;
90 % to 10 % of
4
-
20
ns
|VOH − VOL|; see Figure 16
[1]
[2]
FRFM
VCRS
differential rise time/fall time
matching
excluding the first transition
from idle state
90
-
-
111.1
2.0
%
V
output signal crossover voltage excluding the first transition
1.3
from idle state; see
Figure 17
Driver timing
tPLH(drv)
tPHL(drv)
tPHZ
driver propagation delay
(LOW to HIGH)
DAT/VP, SE0/VM to
DP, DM; see Figure 17 and
Figure 21
-
-
-
-
-
-
-
-
18
18
15
15
ns
ns
ns
ns
driver propagation delay
(HIGH to LOW)
DAT/VP, SE0/VM to
DP, DM; see Figure 17 and
Figure 21
driver disable delay from HIGH OE_N/INT_N to DP, DM;
level
see Figure 18 and
Figure 22
tPLZ
driver disable delay from LOW
level
OE_N/INT_N to DP, DM;
see Figure 18 and
Figure 22
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USB OTG transceiver
Table 50: Dynamic characteristics: analog I/O pins DP and DM…continued
VCC = 2.7 V to 4.5 V; VCC(I/O) = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPZH
driver enable delay to HIGH
level
OE_N/INT_N to DP, DM;
see Figure 18 and
Figure 22
-
-
15
ns
tPZL
driver enable delay to LOW level OE_N/INT_N to DP, DM;
-
-
15
ns
see Figure 18 and
Figure 22
Receiver timing
Differential receiver
tPLH(rcv)
receiver propagation delay
(LOW to HIGH)
DP, DM to RCV; see
Figure 19 and Figure 23
-
-
-
-
15
15
ns
ns
tPHL(rcv)
receiver propagation delay
(HIGH to LOW)
DP, DM to RCV; see
Figure 19 and Figure 23
Single-ended receiver
tPLH(se) single-ended propagation delay DP, DM to VP and DAT/VP,
-
-
-
-
18
18
ns
ns
(LOW to HIGH)
VM and SE0/VM; see
Figure 19 and Figure 23
tPHL(se)
single-ended propagation delay DP, DM to VP and DAT/VP,
(HIGH to LOW)
VM and SE0/VM; see
Figure 19 and Figure 23
[1] tFR / tFF
.
[2] Characterized only; not tested. Limits guaranteed by design.
1.8 V
logic input 0.9 V
0 V
0.9 V
t
, t
FR LR
t
, t
FF LF
V
t
t
OH
PLH(drv)
PHL(drv)
90 %
90 %
V
OH
differential
data lines
V
V
CRS
CRS
10 %
10 %
V
OL
V
OL
004aaa572
004aaa573
Fig 16. Rise time and fall time
Fig 17. Timing of DAT/VP and SE0/VM to DP and DM
2.0 V
1.8 V
differential
data lines
V
V
CRS
CRS
logic
input
0.9 V
PHZ
0.9 V
0.8 V
0 V
t
t
PLH(rcv)
PHL(rcv)
t
t
t
PZH
t
PHL(se)
t
PLH(se)
t
PLZ
PZL
V
OH
V
OH
V
− 0.3 V
OH
0.9 V
0.9 V
logic output
differential
data lines
V
CRS
V
+ 0.3 V
OL
V
OL
V
004aaa574
004aaa575
OL
Fig 18. Timing of OE_N/INT_N to DP and DM
Fig 19. Timing of DP and DM to RCV, VP or DAT/VP and
VM or SE0/VM
ISP1301_3
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Product data sheet
Rev. 03 — 21 February 2006
37 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
OE_N/INT_N
t
t
TOI
TIO
DAT/VP
SE0/VM
input
output
output
004aaa439
Fig 20. SIE interface bus turnaround timing
V
TERM
VREG3V3
1.5 kΩ
33 Ω
DUT
test point
DP or DM
15 kΩ
C
L
004aaa448
Load capacitance CL = 50 pF (minimum or maximum timing).
Fig 21. Load on pins DP and DM
test point
33 Ω
500 Ω
D.U.T.
DP or
DM
50 pF
V
004aaa517
V = 0 V for tPZH and tPHZ
.
V = VREG3V3 for tPZL and tPLZ
.
Fig 22. Load on pins DP and DM for enable time and disable time
test point
D.U.T.
25 pF
004aaa709
Fig 23. Load on pins VM, SE0/VM, VP, DAT/VP and RCV
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
38 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
Table 51: Characteristics of I/O stages of I2C-bus lines (SDA, SCL)
Symbol Parameter
Conditions
Standard mode Unit
Min
-
Max
fSCL
SCL clock frequency
100
kHz
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
tHD;STA
t(SCL)L
t(SCL)H
tSU;STA
tSU;DAT
tHD;DAT
tr
hold time for the START condition
LOW period of the SCL clock
HIGH period of the SCL clock
setup time for the START condition
data setup time
4.0
4.7
4.0
4.7
250
0
-
-
-
-
-
data hold time
-
rise time
SDA and SCL signals
SDA and SCL signals
-
1000
tf
fall time
-
300
tSU;STO
tBUF
STOP condition setup time
4.0
4.7
-
-
bus free time between a STOP and START
condition
SDA
t
t
r
f
t
t
t
BUF
t
t
t
SU;DAT
t
r
HD;STA
SP
f
t
(SCL)L
SCL
t
HD;STA
t
SU;STA
Sr
SU;STO
P
S
S
t
t
(SCL)H
HD;DAT
004aaa577
Fig 24. Definition of timing for standard-mode devices on the I2C-bus
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
39 of 51
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
V
CC(I/O)
R1
V
CC(I/O)
V
10 kΩ
SW1
CC
SW-PB
V
CC(I/O)
C1
C2
1 µF
C10
0.1 µF
0.1 µF
V
R9
CC(I/O)
100 kΩ
R3
R5
R2
R4
R8
100
kΩ
3.3
kΩ
3.3
kΩ
10 kΩ
10 kΩ
V
ADR/PSW
CC(I/O)
1
24
SDA
SCL
CGND
C2
2
3
4
SDA
SCL
23
22
21
C4
RESET_N
C1
0.1 µF
INT_N
INT_N
SPEED
V
V
CC
5
6
7
20
19
18
OTG
GND
ID
BUS
CONTROLLER
OE_N
5
4
3
ISP1301BS
VREG3V3
SUSPEND
ID
R6
AGND
DP
D+
8
9
17
16
33 Ω
OE_N/INT_N
VM
D−
USB MINI-AB
RECEPTACLE
2
1
SE0
DAT
R7
33 Ω
DM
V
BUS
10
11
12
15
14
13
VP
DAT/VP
SE0/VM
C5
0.1 µF
RCV
C7
C9
C6
C8
DGND
4.7
µF
0.1
µF
22
pF
22
pF
004aaa348
Fig 25. Application diagram for the OTG Controller with the DAT_SE0 SIE interface
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
V
CC(I/O)
V
CC
R1
10 kΩ
SW1
V
SW-PB
CC(I/O)
C1
1 µF
V
CC(I/O)
C3
C10
0.1 µF
0.1 µF
R9
V
CC(I/O)
100 kΩ
R5
R2
R4
R3
R8
3.3
kΩ
3.3
kΩ
10 kΩ
10 kΩ
100
kΩ
V
ADR/PSW
CC(I/O)
24
1
SDA
SCL
CGND
SDA
SCL
23
22
2
3
4
C2
C1
V
C4
RESET_N
0.1 µF
INT_N
21
INT_N
CC
5
6
7
20
19
18
OTG
V
GND
ID
SPEED
BUS
CONTROLLER
OE_N
5
4
3
ISP1301BS
VREG3V3
ID
R6
D+
SUSPEND
AGND
DP
17
16
15
8
33 Ω
OE_N/INT_N
D−
USB MINI-AB
RECEPTACLE
9
2
1
RCV
VM
VP
R7
33 Ω
VM
VP
DM
V
BUS
10
DAT/VP
SE0/VM
14
13
11
12
C5
RCV
0.1 µF
C7
C9
4.7 µF
C6
C8
DGND
22 pF
0.1 µF
22 pF
004aaa438
Fig 26. Application diagram for the OTG Controller with the VP_VM SIE interface
ISP1301
Philips Semiconductors
USB OTG transceiver
18. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
SOT616-1
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
e
1
C
1/2 e
y
y
C
1
e
v
M
M
C
C
A
B
b
7
12
w
L
13
6
e
e
E
h
2
1/2 e
1
18
terminal 1
index area
24
19
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
mm
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
h
1
h
1
max.
0.05 0.30
0.00 0.18
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
0.3
0.05
0.1
1
0.2
0.5
2.5
2.5
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT616-1
- - -
MO-220
- - -
Fig 27. Package outline SOT616-1 (HVQFN24)
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
42 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
19. Soldering
19.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of
soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is recommended.
19.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and cooling)
vary between 100 seconds and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 °C to 270 °C depending on solder paste
material. The top-surface temperature of the packages should preferably be kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
19.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
ISP1301_3
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Product data sheet
Rev. 03 — 21 February 2006
43 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to
the transport direction of the printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 °C
or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most
applications.
19.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage
(24 V or less) soldering iron applied to the flat part of the lead. Contact time must be
limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 seconds to 5 seconds between 270 °C and 320 °C.
19.5 Package related soldering information
Table 52: Suitability of surface mount IC packages for wave and reflow soldering methods
Package [1]
Soldering method
Wave
Reflow[2]
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, VFBGA, XSON
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP,
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable[4]
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5] [6]
not recommended[7]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[8], PMFP[9], WQCCN..L[8]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026);
order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal or
external package cracks may occur due to vaporization of the moisture in them (the so called popcorn
effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit
Packages; Section: Packing Methods.
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no
account be processed through more than one soldering cycle or subjected to infrared reflow soldering with
peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package
body peak temperature must be kept as low as possible.
ISP1301_3
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Product data sheet
Rev. 03 — 21 February 2006
44 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the
solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink
on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger
than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by
using a hot bar soldering process. The appropriate soldering profile can be provided on request.
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.
20. Abbreviations
Table 53: Abbreviations
Acronym
ASIC
ATX
Description
Application-Specific Integrated Circuit
Analog USB Transceiver
Host Negotiation Protocol
ElectroStatic Discharge
Inter IC-bus
HNP
ESD
I2C-bus
IC
Integrated Circuit
LSB
Least Significant Bit
On-The-Go
OTG
PDA
Personal Digital Assistant
Programmable Logic Device
Power-On Reset
PLD
POR
PORP
SE0
Power-On Reset Pulse
Single-Ended Zero
SOF
Start-Of-Frame
SRP
Session Request Protocol
Universal Serial Bus
USB Implementers Forum
USB
USB-IF
21. References
[1] ECN_27%_Resistor (Pull-up/pull-down Resistors ECN)
[2] Universal Serial Bus Specification Rev. 2.0
[3] On-The-Go Supplement to the USB Specification Rev. 1.0a
[4] On-The-Go Transceiver Specification (CEA-2011) Rev. 1.0
[5] The I2C-bus specification; version 2.1
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
45 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
22. Revision history
Table 54: Revision history
Document ID
ISP1301_3
Release date Data sheet status
20060221 Product data sheet
Change notice
Doc. number
Supersedes
-
-
ISP1301-02
Modifications:
• The format of this data sheet has been redesigned to comply with the new presentation and
information standard of Philips Semiconductors.
• Updated symbols and pin names according to the latest Philips Semiconductors standards.
• Table 41 “Limiting values”: updated the maximum value of VCC
.
• Table 42 “Recommended operating conditions”: updated the maximum value of VCC
.
ISP1301-02
ISP1301-01
20050104
20040414
Product data
Product data
-
-
9397 750 14337 ISP1301-01
9397 750 11355
-
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
46 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
23. Data sheet status
Level Data sheet status[1] Product status[2] [3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
24. Definitions
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
makes no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
26. Trademarks
Notice — All referenced brands, product names, service names and
trademarks are the property of their respective owners.
I2C-bus — logo is a trademark of Koninklijke Philips Electronics N.V.
25. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
27. Contact information
For additional information, please visit: http://www.semiconductors.philips.com
For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
47 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
28. Tables
Table 1: Ordering information . . . . . . . . . . . . . . . . . . . . .2
Table 2: Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Table 3: Recommended charge pump capacitor value .12
Table 4: Device operating modes . . . . . . . . . . . . . . . . .14
Table 5: USB suspend mode: I/O . . . . . . . . . . . . . . . . .14
Table 6: USB functional modes: I/O values . . . . . . . . . .15
Table 7: USB suspend mode: I/O values . . . . . . . . . . . .15
Table 8: Transparent general-purpose buffer mode . . . .15
Table 9: Transceiver driver operation setting . . . . . . . . .16
Table 10: USB functional mode: transmit operation . . . .16
Table 11: Differential receiver operation settings . . . . . . .16
Table 12: USB functional mode: receive operation . . . . .17
Table 13: Serial controller registers . . . . . . . . . . . . . . . . .18
Table 14: Vendor ID register: bit description . . . . . . . . . .18
Table 15: Product ID register: bit description . . . . . . . . .18
Table 16: Version ID register: bit description . . . . . . . . . .19
Table 17: Mode Control 1 register: bit allocation . . . . . . .19
Table 18: Mode Control 1 register: bit description . . . . . .19
Table 19: Mode Control 2 register: bit allocation . . . . . . .19
Table 20: Mode Control 2 register: bit description . . . . . .20
Table 21: OTG Control register: bit allocation . . . . . . . . .20
Table 22: OTG Control register: bit description . . . . . . . .20
Table 23: OTG Status register: bit allocation . . . . . . . . . .21
Table 24: OTG Status register: bit description . . . . . . . . .21
Table 25: Interrupt Source register: bit allocation . . . . . .21
Table 26: Interrupt Source register: bit description . . . . .21
Table 27: Interrupt Latch register: bit allocation . . . . . . .22
Table 28: Interrupt Latch register: bit description . . . . . .22
Table 29: Interrupt Enable Low register: bit allocation . . .22
Table 30: Interrupt Enable Low register: bit description .22
Table 31: Interrupt Enable High register: bit allocation . .23
Table 32: Interrupt Enable High register: bit description .23
Table 33: I2C-bus byte transfer format . . . . . . . . . . . . . . .27
Table 34: I2C-bus device address byte 1 bit allocation . .27
Table 35: I2C-bus device address byte 1 bit description .27
Table 36: Transfer format description for one-byte write .27
Table 37: Transfer format description for multiple-byte
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 45: Static characteristics: analog I/O pins DP
and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 46: Static characteristics: analog I/O pin ID . . . . . 34
Table 47: Static characteristics: charge pump . . . . . . . . 35
Table 48: Dynamic characteristics: reset and clock . . . . 36
Table 49: Dynamic characteristics: digital I/O pins . . . . . 36
Table 50: Dynamic characteristics: analog I/O pins DP
and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 51: Characteristics of I/O stages of I2C-bus lines
(SDA, SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 52: Suitability of surface mount IC packages for
wave and reflow soldering methods . . . . . . . . 44
Table 53: Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 54: Revision history . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 38: Transfer format description for current address
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 39: Transfer format description for single-byte
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 40: Transfer format description for multiple-byte
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 41: Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 42: Recommended operating conditions . . . . . . . .32
Table 43: Static characteristics: supply pins . . . . . . . . . .33
Table 44: Static characteristics: digital pins . . . . . . . . . . .33
continued >>
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
48 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
29. Figures
Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Fig 2. Pin configuration HVQFN24 (top view) . . . . . . . . .4
Fig 3. Pin configuration HVQFN24 (bottom view) . . . . . .4
Fig 4. Internal POR timing . . . . . . . . . . . . . . . . . . . . . . . .9
Fig 5. Using external charge pump . . . . . . . . . . . . . . . .10
Fig 6. Charge pump capacitor . . . . . . . . . . . . . . . . . . . .11
Fig 7. Clock stopped using the GLOBAL_PWR_DN bit.25
Fig 8. Clock wake-up using SCL . . . . . . . . . . . . . . . . . .25
Fig 9. Clock wake-up by VBUS . . . . . . . . . . . . . . . . . . . .26
Fig 10. Clock wake-up by ID change (1) . . . . . . . . . . . . .26
Fig 11. Clock wake-up by ID change (2) . . . . . . . . . . . . .26
Fig 12. Clock wake-up by data line SRP . . . . . . . . . . . . .26
Fig 13. Writing data to the ISP1301 registers . . . . . . . . .29
Fig 14. Current address read. . . . . . . . . . . . . . . . . . . . . .30
Fig 15. Random address read . . . . . . . . . . . . . . . . . . . . .31
Fig 16. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .37
Fig 17. Timing of DAT/VP and SE0/VM to DP and DM . .37
Fig 18. Timing of OE_N/INT_N to DP and DM . . . . . . . .37
Fig 19. Timing of DP and DM to RCV, VP or DAT/VP
and VM or SE0/VM . . . . . . . . . . . . . . . . . . . . . . .37
Fig 20. SIE interface bus turnaround timing. . . . . . . . . . .38
Fig 21. Load on pins DP and DM. . . . . . . . . . . . . . . . . . .38
Fig 22. Load on pins DP and DM for enable time and
disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Fig 23. Load on pins VM, SE0/VM, VP, DAT/VP and
RCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Fig 24. Definition of timing for standard-mode devices
on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Fig 25. Application diagram for the OTG Controller with
the DAT_SE0 SIE interface . . . . . . . . . . . . . . . . .40
Fig 26. Application diagram for the OTG Controller with
the VP_VM SIE interface . . . . . . . . . . . . . . . . . . .41
Fig 27. Package outline SOT616-1 (HVQFN24) . . . . . . .42
continued >>
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
49 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
30. Contents
1
2
3
4
5
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
10
10.1
10.1.1
Serial controller. . . . . . . . . . . . . . . . . . . . . . . . 18
Register map . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device identification registers. . . . . . . . . . . . . 18
10.1.1.1 Vendor ID register (Read: 00h to 01h) . . . . . . 18
10.1.1.2 Product ID register (Read: 02h to 03h) . . . . . 18
10.1.1.3 Version ID register (Read: 14h to 15h). . . . . . 18
6
6.1
6.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
10.1.2
Mode control registers . . . . . . . . . . . . . . . . . . 19
10.1.2.1 Mode Control 1 register (Set/Clear: 04h/05h) 19
10.1.2.2 Mode Control 2 register (Set/Clear: 12h/13h) 19
10.1.3
OTG registers. . . . . . . . . . . . . . . . . . . . . . . . . 20
7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.4
7.5
7.6
Functional description . . . . . . . . . . . . . . . . . . . 7
Serial controller. . . . . . . . . . . . . . . . . . . . . . . . . 7
VBUS charge pump . . . . . . . . . . . . . . . . . . . . . . 7
10.1.3.1 OTG Control register (Set/Clear: 06h/07h) . . 20
10.1.3.2 OTG Status register (Read: 10h) . . . . . . . . . . 21
10.1.4
10.1.4.1 Interrupt Source register (Read: 08h) . . . . . . 21
10.1.4.2 Interrupt Latch register (Set/Clear: 0Ah/0Bh). 21
10.1.4.3 Interrupt Enable Low register (Set/Clear:
0Ch/0Dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10.1.4.4 Interrupt Enable High register (Set/Clear:
0Eh/0Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Interrupt related registers. . . . . . . . . . . . . . . . 21
V
V
BUS comparators. . . . . . . . . . . . . . . . . . . . . . . 7
BUS valid comparator . . . . . . . . . . . . . . . . . . . 7
Session valid comparator . . . . . . . . . . . . . . . . . 7
Session end comparator. . . . . . . . . . . . . . . . . . 7
ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pull-up and pull-down resistors. . . . . . . . . . . . . 8
Analog USB Transceiver (ATX). . . . . . . . . . . . . 8
3.3 V DC-DC regulator . . . . . . . . . . . . . . . . . . . 8
Carkit interrupt detector . . . . . . . . . . . . . . . . . . 8
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 9
Detailed description of pins . . . . . . . . . . . . . . . 9
ADR/PSW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . 10
RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
INT_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
OE_N/INT_N. . . . . . . . . . . . . . . . . . . . . . . . . . 10
SE0/VM, DAT/VP, RCV, VM and VP . . . . . . . . 10
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
10.2
10.3
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Auto-connect . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.7
7.8
7.9
11
11.1
11.2
Clock wake-up scheme. . . . . . . . . . . . . . . . . . 25
Power-down event . . . . . . . . . . . . . . . . . . . . . 25
Clock wake-up events . . . . . . . . . . . . . . . . . . 25
7.10
7.10.1
7.10.2
7.10.3
7.10.4
7.10.5
7.10.6
7.10.7
7.10.8
7.10.9
7.10.10
12
12.1
12.2
12.3
12.3.1
12.3.2
12.4
12.4.1
12.4.2
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 27
I2C-bus byte transfer format . . . . . . . . . . . . . . 27
I2C-bus device address . . . . . . . . . . . . . . . . . 27
Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 27
One-byte write . . . . . . . . . . . . . . . . . . . . . . . . 27
Multiple-byte write . . . . . . . . . . . . . . . . . . . . . 28
Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Current address read . . . . . . . . . . . . . . . . . . . 29
Random address read . . . . . . . . . . . . . . . . . . 30
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.10.11 C1 and C2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.10.12 VCC(I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.10.13 AGND, CGND and DGND. . . . . . . . . . . . . . . . 12
12.4.2.1 Single read. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
12.4.2.2 Multiple read. . . . . . . . . . . . . . . . . . . . . . . . . . 30
13
14
15
16
17
18
19
19.1
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 32
Recommended operating conditions . . . . . . 32
Static characteristics . . . . . . . . . . . . . . . . . . . 33
Dynamic characteristics. . . . . . . . . . . . . . . . . 36
Application information . . . . . . . . . . . . . . . . . 40
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 42
8
8.1
8.2
8.3
Modes of operation . . . . . . . . . . . . . . . . . . . . . 12
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 12
Direct I2C-bus mode . . . . . . . . . . . . . . . . . . . . 13
USB modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Transparent modes. . . . . . . . . . . . . . . . . . . . . 13
Transparent general-purpose buffer mode . . . 13
Transparent UART mode . . . . . . . . . . . . . . . . 13
Summary tables . . . . . . . . . . . . . . . . . . . . . . . 14
8.4
8.4.1
8.4.2
8.4.3
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 43
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 43
9
9.1
9.2
USB transceiver . . . . . . . . . . . . . . . . . . . . . . . . 15
Differential driver. . . . . . . . . . . . . . . . . . . . . . . 15
Differential receiver. . . . . . . . . . . . . . . . . . . . . 16
19.2
19.3
continued >>
ISP1301_3
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 21 February 2006
50 of 51
ISP1301
Philips Semiconductors
USB OTG transceiver
19.4
19.5
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 44
Package related soldering information . . . . . . 44
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 45
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 46
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 47
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Contact information . . . . . . . . . . . . . . . . . . . . 47
20
21
22
23
24
25
26
27
© Koninklijke Philips Electronics N.V. 2006
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner. The information presented in this document does
not form part of any quotation or contract, is believed to be accurate and reliable and may
be changed without notice. No liability will be accepted by the publisher for any
consequence of its use. Publication thereof does not convey nor imply any license under
patent- or other industrial or intellectual property rights.
Date of release: 21 February 2006
Document number: ISP1301_3
Published in The Netherlands
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