ISP1301BS [NXP]
Universal Serial Bus On-The-Go transceiver; 通用串行总线的On-the - Go收发器
| 型号： | ISP1301BS |
| 厂家： | 
NXP |
| 描述： | Universal Serial Bus On-The-Go transceiver |
| 文件： | 总46页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISP1301
Universal Serial Bus On-The-Go transceiver
Rev. 01 — 14 April 2004
Product data
1. General description
The ISP1301 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device
that is fully compliant with Universal Serial Bus Specification Rev. 2.0 and On-The-Go
Supplement to the USB Specification Rev. 1.0a. The ISP1301 can transmit and
receive serial data at both full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) data
rates.
It is ideal for use in portable electronics devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application Specific Integrated Circuits (ASICs),
Programmable Logic Devices (PLDs) and any system chip set (with the USB host or
device function built-in but without the USB physical layer) to interface to the physical
layer of the USB.
The ISP1301 can interface to devices with digital I/O voltages in the range of
1.65 V to 3.6 V.
The ISP1301 is available in HVQFN24 package.
2. Features
■ Fully complies with:
◆ Universal Serial Bus Specification Rev. 2.0
◆ On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a
◆ On-The-Go Transceiver Specification (CEA–2011) Rev. 1.0
■ Can transmit and receive serial data at both full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s) data rates
■ Ideal for system ASICs or chip sets with built-in USB OTG dual-role core
■ Supports mini USB analog car kit interface
■ Supports various serial data interface protocols; transparent general-purpose
buffer mode allows you to control the direction of data transfer
■ Supports data line and VBUS pulsing session request
■ Contains Host Negotiation Protocol (HNP) command and status registers
■ Supports serial I2C-bus™ interface for OTG status and command controls
■ 2.7 V to 4.5 V power supply input range for the ISP1301
■ Built-in charge pump regulator outputs 5 V at current greater than 8 mA
■ Supports external charge pump
■ Supports wide range interfacing I/O voltage (VDD_LGC = 1.65 V to 3.6 V) for digital
control logics
ISP1301
USB OTG transceiver
Philips Semiconductors
■ 8 kV built-in electrostatic discharge (ESD) protection on the DP, DM, VBUS and ID
lines
■ Full industrial grade operation from −40 °C to +85 °C
■ Available in a small HVQFN24 (4 × 4 mm2) halogen-free and lead-free package.
3. Applications
4. Abbreviations
■ Mobile phone
■ Digital camera
■ Personal digital assistant
■ Digital video recorder.
ASIC — Application-Specific Integrated Circuit
ATX — Analog USB transceiver
HNP — Host Negotiation Protocol
ESD — ElectroStatic Discharge
I2C-bus — Inter IC-bus
IC — Integrated Circuit
OTG — On-The-Go
PDA — Personal Digital Assistant
SE0 — Single-Ended zero
SOF — Start-of-Frame
SRP — Session Request Protocol
USB — Universal Serial Bus
USB-IF — USB Implementers Forum.
5. Ordering information
Table 1:
Ordering information
Package
Type
number
Name
Description
Version
ISP1301BS HVQFN24 plastic thermal enhanced very thin quad flat package; SOT616-1
no leads; 24 terminals; body 4 × 4 × 0.85 mm
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Product data
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ISP1301
USB OTG transceiver
Philips Semiconductors
6. Block diagram
V
V
V
C2
C1
DD_LGC
24
REG(3V3)
7
BAT
22
V
21
20
23
3.3 V DC-DC
REGULATOR
CGND
BUS
CHARGE PUMP
19
V
BUS
ISP1301
V
BUS
3
SCL
COMPARATORS
2
SDA
1
ADR/PSW
5
INT_N
SERIAL
CONTROLLER
18
ID DETECTOR
ID
9
OE_N/INT_N
LEVEL
14
13
DAT/VP
SHIFTER
PULL-UP AND
PULL-DOWN
RESISTORS
SE0/VM
12
RCV
11
VP
10
VM
6
SPEED
8
CARKIT
INTERRUPT
DETECTOR
SUSPEND
15
DM
4
USB
TRANSCEIVER
RESET_N
16
DP
exposed die pad
17
004aaa195
DGND
AGND
Fig 1. Block diagram.
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Product data
Rev. 01 — 14 April 2004
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ISP1301
USB OTG transceiver
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7. Pinning information
7.1 Pinning
24
23
19
22
21
20
ID
1
18
ADR/PSW
SDA
AGND
2
3
4
5
6
17
16
15
14
13
SCL
RESET_N
INT_N
DP
ISP1301BS
DM
DAT/VP
SE0/VM
004aaa542
SPEED
7
8
12
9
10
11
Fig 2. Pin configuration HVQFN24 (top view).
7
8
12
9
10
11
SE0/VM
DAT/VP
6
13
SPEED
INT_N
DGND
(exposed die pad)
5
4
3
2
1
14
15
16
17
18
RESET_N
SCL
DM
DP
ISP1301BS
terminal 1
AGND
ID
SDA
ADR/PSW
24
23
19
22
21
20
004aaa196
Bottom view
Fig 3. Pin configuration HVQFN24 (bottom view).
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ISP1301
USB OTG transceiver
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7.2 Pin description
Table 2:
Symbol[2] Pin
Pin description[1]
Type[3] Reset
value
Description
ADR/PSW
1
I/O
high-Z ADR input — sets the least-significant I2C-bus
address bit of the ISP1301; latched-on reset
(including power-on reset)
PSW output — enables or disables the external
charge pump after reset
bidirectional; push-pull input; three-state output
high-Z serial I2C-bus data input and output
bidirectional; push-pull input; open-drain output
high-Z serial I2C-bus clock input and output
bidirectional; push-pull input; open-drain output
SDA
2
3
4
5
6
I/OD
SCL
I/OD
RESET_N
INT_N
SPEED
I
-
asynchronous reset; active LOW
push-pull input
OD
I
high-Z interrupt output; active LOW
open-drain output
-
speed selection input for the ATX; effective when
bit SPD_SUSP_CTRL = 0:
• LOW: low-speed
• HIGH: full-speed.
push-pull input
VREG(3V3)
7
8
P
I
-
-
output of the internal voltage regulator; an
external decoupling capacitor of 0.1 µF is
required
SUSPEND
suspend selection input for ATX; effective when
bit SPD_SUSP_CTRL = 0:
• LOW: normal operating
• HIGH: suspend.
push-pull input
OE_N/
INT_N
9
I/O
high-Z OE_N input — enable driving DP and DM when
in the USB mode
INT_N output — interrupt (push pull) when
suspended and bit OE_INT_EN = 1
bidirectional; push-pull input; three-state output
VM
VP
10
11
12
O
O
O
-
single-ended DM receiver output
push-pull output
-
single-ended DP receiver output
push-pull output
RCV
0
differential receiver output; reflects the
differential value of DP and DM
push-pull output
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ISP1301
USB OTG transceiver
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Table 2:
Symbol[2] Pin
Pin description[1]…continued
Type[3] Reset
Description
value
[4]
SE0/VM
13
I/O
-
SE0 (input and output) — SE0 function in
DAT_SE0 USB mode
VM (input and output) — VM function in
VP_VM USB mode
bidirectional; push-pull input; three-state output
[4]
DAT/VP
14
I/O
-
DAT (input and output) — DAT function in
DAT_SE0 USB mode
VP (input and output) — VP function in VP_VM
USB mode
bidirectional; push-pull input; three-state output
USB data minus pin (D−)
USB data plus pin (D+)
DM
DP
15
16
17
18
AI/O
AI/O
P
-
-
-
-
AGND
ID
analog ground
AI/O
identification detector input and output;
connected to the ID pin of the USB mini
receptacle
VBUS
19
AI/O
-
VBUS line input and output of the USB interface;
place an external decoupling capacitor of 0.1 µF
close to this pin
VBAT
C1
20
21
P
-
-
supply voltage (2.7 V to 4.5 V)
AI/O
charge pump capacitor pin 1; typically use a
100 nF capacitor between pins C1 and C2
C2
22
AI/O
-
charge pump capacitor pin 2; typically use a
100 nF capacitor between pins C1 and C2
CGND
23
24
P
P
-
-
ground for the charge pump
VDD_LGC
supply voltage for the interface logic signals
(1.65 V to 3.6 V)
DGND
exposed
die pad
P
-
digital ground
[1] A detailed description of these pins can be found in Section 8.9.
[2] Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals.
[3] I = input; O = output; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output;
P = power or ground pin.
[4] High-Z when pin OE_N/INT_N is LOW. Driven LOW when pin OE_N/INT_N is HIGH.
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USB OTG transceiver
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8. Functional description
8.1 Serial controller
The serial controller includes the following functions:
• I2C-bus slave interface
• Interrupt generator
• Mode Control registers
• OTG registers
• Interrupt related registers
• Device identification registers.
The serial controller acts as an I2C-bus slave, and uses the SCL and SDA pins to
communicate with the OTG controller.
For more details on serial controller, see Section 11.
8.2 VBUS charge pump
The charge pump supplies current to the VBUS line. It can operate in any of the
following modes:
• Output 5 V at current greater than 8 mA
• Pull-up VBUS to 3.3 V through a resistor (RVBUS(PU)) for initiating VBUS pulsing SRP
• Pull-down VBUS to ground through a resistor (RVBUS(PD)) for discharging VBUS
before initiating SRP.
8.3 VBUS comparators
VBUS comparators provide indications regarding the voltage level on VBUS
.
8.3.1 VBUS valid comparator
This comparator is used by an A-device to determine whether or not the voltage on
VBUS is at a valid level for operation. The minimum threshold for the VBUS valid
comparator is 4.4 V. Any voltage on VBUS below this threshold is considered to be a
fault. During power up, it is expected that the comparator output will be ignored.
8.3.2 Session valid comparator
The session valid comparator is a TTL-level input that determines when VBUS is high
enough for a session to start. Both the A-device and the B-device use this comparator
to detect when a session is being started. The A-device also uses this comparator to
indicate when a session is completed. The session valid threshold of the ISP1301 is
between 0.8 V and 2.0 V.
8.3.3 Session end comparator
The session end comparator determines when VBUS is below the B-device session
end threshold of 0.2 V to 0.8 V.
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USB OTG transceiver
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8.4 ID detector
In either the active or suspended power mode, the ID detector senses the condition of
the ID line and differentiates between the following three conditions:
• Pin ID is floating; bit ID_FLOAT = 1
• Pin ID is shorted to ground; bit ID_GND = 1
• Pin ID is connected to ground through resistor RACC_ID; bit ID_FLOAT = 0 and bit
ID_GND = 0.
The ID detector also has a switch that can be used to ground pin ID. This switch is
controlled by bit ID_PULLDOWN in the serial controller.
8.5 Pull-up and pull-down resistors
The pull-up and pull-down resistors include the following switchable resistors:
• Pin DP pull-up
• Pin DP pull-down
• Pin DM pull-up
• Pin DM pull-down.
The pull-up resistor is a context variable as described in the ECN_27%_Resistor
document. The variable pull-up resistor hardware is implemented to meet the USB
ECN_27% specification.
8.6 USB transceiver (ATX)
The behavior of the USB transceiver depends on the operation mode of the ISP1301:
• In the USB mode, the USB transceiver block performs USB full-speed or
low-speed transceiver functions. This includes differential driver, differential
receiver and single-ended receivers.
• In the transparent general purpose buffer mode or the UART mode, the USB
transceiver block functions as a level shifter between the pins DAT/VP and SE0/VM
and the pins DP and DM.
8.7 3.3 V DC-DC regulator
The built-in 3.3 V DC-DC regulator conditions the supply voltage (VBAT) for use in the
ISP1301:
• VBAT = 3.6 V to 4.5 V: the regulator will output 3.3 V ± 10 %
• VBAT < 3.6 V: the regulator will be bypassed.
The output of the regulator can be monitored on the VREG(3V3) pin.
8.8 Car kit interrupt detector
The car kit interrupt detector is a comparator that detects when the DP line is below
the car kit interrupt threshold VPH_CR_INT (0.4 V to 0.6 V). The car kit interrupt
detector is enabled in the audio mode only (bit AUDIO_EN = 1).
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ISP1301
USB OTG transceiver
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8.9 Detailed description of pins
8.9.1 ADR/PSW
The ADR/PSW pin has two functions. On reset (including power-on reset), the level
on this pin is latched as ADR_REG, which represents the least significant bit (LSB) of
the I2C address of the ISP1301. If bit ADR_REG = 0, the I2C-bus address for the
ISP1301 is 0101100 (0x2C); if bit ADR_REG = 1, the I2C-bus address for the
ISP1301 is 0101101 (0x2D).
After reset, the ADR/PSW pin can be programmed as an output. If in the Mode
Control 2 register bit PSW_OE = 1, then the ADR/PSW output will be enabled. The
logic level will be determined by bit ADR_REG. If bit ADR_REG = 0, then the
ADR/PSW pin will drive HIGH. If bit ADR_REG = 1, then the ADR/PSW pin will drive
LOW.
The ADR/PSW pin can be used to turn on or off the external charge pump. The
ISP1301 built-in charge pump supports VBUS current at 8 mA. If the application needs
more current support (for example, 50 mA), an external charge pump may be
needed. In this case, the ADR/PSW pin can act as a power switch for the external
charge pump. Figure 4 shows an example of using external charge pump.
+3.3 V
100 kΩ
V
BAT
ADR/PSW
V
V
V
OUT
BUS
IN
ID
4.7 µF
DM
CHARGE PUMP
ON/OFF
ISP1301
DP
V
BUS
GND
004aaa437
Fig 4. Using external charge pump.
8.9.2 SCL and SDA
The SCL (serial clock) and SDA (serial data) signals implement a two-wire serial
I2C-bus.
8.9.3 RESET_N
Active LOW asynchronous reset for all digital logic. Either connect this pin to VDD_LGC
for power-on reset or apply a minimum of 10 µs LOW pulse for hardware reset.
8.9.4 INT_N
The INT_N (interrupt) pin is asserted while an interrupt condition exists. It is
deasserted when the Interrupt Latch register is cleared. The INT_N pin is open-drain,
and, therefore, can be connected using a wired-AND with other interrupt signals.
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ISP1301
USB OTG transceiver
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8.9.5 OE_N/INT_N
Pin OE_N/INT_N is normally an input to the ISP1301.
When bit TRANSP_EN = 0 and bit UART_EN = 0, the OE_N/INT_N pin controls the
direction of DAT/VP, SE0/VM, DP and DM as indicated in Table 4.
When suspended (either pin SUSPEND = HIGH or bit SUSPEND_REG = 1) and bit
OE_INT_EN = 1, pin OE_N/INT_N becomes a push-pull output (active LOW) to
indicate the interrupt condition.
8.9.6 SE0/VM, DAT/VP, RCV, VM and VP
The ISP1301 transmits USB data on the USB line under the following conditions:
• Bit TRANSP_EN = 0
• Bit UART_EN = 0
• Pin OE_N/INT_N = LOW.
Table 10 shows the operation of the SE0/VM and DAT/VP pins during the transmit
operation. The RCV pin is not used during transmit.
The ISP1301 receives USB data from the USB line under the following conditions:
• Bit TRANSP_EN = 0
• Bit UART_EN = 0
• Pin OE_N/INT_N = HIGH.
Table 12 shows the operation of the SE0/VM, DAT/VP and RCV pins during the
receive operation.
The VP and VM pins are single-ended receiver outputs of the DP and DM pins,
respectively.
8.9.7 DP and DM
The DP (data plus) and DM (data minus) pins implement the USB data signals. When
in the transparent general-purpose buffer mode, the ISP1301 operates as a level
shifter between the (DAT/VP, SE0/VM) and (DP, DM) pins.
8.9.8 ID
The ID (identification) pin is connected to the ID pin on the USB mini receptacle. An
internal pull-up resistor (to VREG(3V3)) is connected to this pin. When bit
ID_PULLDOWN is set, the ID pin will be shorted to ground.
8.9.9 VBUS
This pin acts as an input to the VBUS comparator or an output from the charge pump.
When the VBUS_DRV bit of the OTG Control register is asserted, the ISP1301 tries
to drive VBUS to a voltage of 4.4 V to 5.25 V with an output current capability of at
least 8 mA.
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ISP1301
USB OTG transceiver
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8.9.10 VBAT
This pin is an input and supplies power to the ISP1301. The ISP1301 operates when
VBAT is between 2.7 V and 4.5 V.
8.9.11 C1 and C2
The C1 and C2 pins are for connecting the flying capacitor of the charge pump. The
output current capacity of the charge pump depends on the value of the capacitor.
For maximum efficiency, place capacitors as close as possible to the pins.
C1
C
ext
C2
ISP1301
V
BUS
I
L
004aaa278
Fig 5. Charge pump capacitor.
Table 3:
Cext
Recommended charge pump capacitor value
IL (max)[1]
47 nF
100 nF
8 mA
18 mA[2]
[1] For output voltage VBUS > 4.7 V (bit VBUS_VLD = 1).
[2] For VBAT = 3.0 V to 4.5 V.
8.9.12 VDD_LGC
This pin is an input and sets logic thresholds. It also powers the pads of the following
logic pins:
• ADR/PSW
• DAT/VP, SE0/VM and RCV
• VM and VP
• INT_N
• OE_N/INT_N
• RESET_N
• SPEED
• SUSPEND
• SCL and SDA.
8.9.13 AGND, CGND and DGND
AGND, CGND and DGND are ground pins for analog, charge pump and digital
circuits, respectively. These pins can be connected separately or together depending
on the system performance requirements.
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ISP1301
USB OTG transceiver
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9. Modes of operation
There are four types of modes in the ISP1301:
• Power modes
• Direct I2C-bus mode
• USB modes
• Transparent modes.
9.1 Power modes
The power modes of the ISP1301 are as follows:
• Active power mode: power is on.
• USB suspend mode: to reduce power consumption, the USB differential receiver is
powered down.
• Global power-down mode: set bit GLOBAL_PWR_DN = 1 of the Mode Control 2
register; the differential transmitter and receiver, clock generator, charge pump,
and all biasing circuits are turned off to reduce power consumption to the minimum
possible; for details on waking up the clock, see Section 12.
9.2 Direct I2C-bus mode
In the direct I2C-bus mode, an external I2C-bus master (OTG controller) directly
communicates with the serial controller through the SCL and SDA lines. The serial
controller has a built-in I2C-bus slave function.
In this mode, an external I2C-bus master can access the internal registers of the
device (Status, Control, Interrupt, and so on) through the I2C-bus interface.
The supported I2C-bus bit rate is 100 kbit/s (maximum).
The ISP1301 is in the direct I2C-bus mode when either bit TRANSP_EN bit = 0 or pin
OE_N/INT_N is deasserted.
9.3 USB modes
The four USB modes of the ISP1301 are:
• VP_VM unidirectional mode
• VP_VM bidirectional mode
• DAT_SE0 unidirectional mode
• DAT_SE0 bidirectional mode.
In the VP_VM USB mode, the DAT/VP pin is used for the VP function, the SE0/VM
pin is used for the VM function, and the RCV pin is used for the RCV function.
In the DAT_SE0 USB mode, the DAT/VP pin is used for the DAT function, the SE0/VM
pin is used for the SE0 function, and the RCV pin is not used.
In the unidirectional mode, the DAT/VP and SE0/VM pins are always inputs. In the
bidirectional mode, the direction of these signals depends on the OE_N/INT_N input.
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USB OTG transceiver
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Table 6 specifies the functionality of the device during the four USB modes.
The ISP1301 is in the USB mode when both the TRANSP_EN and UART_EN bits
are cleared.
9.4 Transparent modes
9.4.1 Transparent general-purpose buffer mode
In the transparent general-purpose buffer mode, the DAT/VP and SE0/VM pins are
connected to the DP and DM pins, respectively. Using bits TRANSP_BDIR1 and
TRANSP_BDIR0 of the Mode Control 2 register as specified in Table 8, you can
control the direction of data transfer. The ISP1301 is in the transparent
general-purpose buffer mode if bit TRANSP_EN = 1 and bit DAT_SE0 = 1.
9.4.2 Transparent UART mode
When in the transparent UART mode, the ATX behaves as two logic level translator
between the following pins:
• For TxD signal: from SE0/VM (VDD_LGC level) to DM (+3.3 V level)
• For RxD signal: from DP (+3.3 V level) to DAT/VP (VDD_LGC level).
In the UART mode, the OTG controller is allowed to connect a UART to the DAT/VP
and SE0/VM pins of the ISP1301.
The UART mode is entered by setting the UART_EN bit in the Mode Control 1
register. The UART mode is equivalent to one of the transparent general purpose
buffer mode (bit TRANSP_BDIR1 = 1, bit TRANSP_BDIR0 = 0).
9.4.3 Summary tables
Table 4:
Mode
Device operating modes
USB
suspend
Bit
DAT
Pin
Bit
Bit
Description
OE_N/ TRANSP UART
INT_N _EN
condition[1] _SE0
_ EN
Direct I2C-bus mode
Direct I2C-bus mode
X
X
X
X
X
1
X
0
1
1
X
X
X
HIGH
X
USB modes
USB suspend mode
USB functional mode
Transparent modes
1
0
X
X
X
X
0
0
0
0
see Table 5 and Table 7
ATX is fully functional; see Table 6
Transparent general-purpose
buffer mode
X
X
1
X
X
1
0
1
ATX is not functional; see Table 8
Transparent UART mode
X
X
DAT/VP <= DP (RxD signal of UART)
SE0/VM => DM (TxD signal of UART);
ATX is not functional
[1] Conditions:
a) bit SPD_SUSP_CTRL = 0 and pin SUSPEND = HIGH, or
b) bit SPD_SUSP_CTRL = 1 and bit SUSPEND_REG = 0.
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ISP1301
USB OTG transceiver
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Table 5:
Pin
USB suspend mode: I/O
Function
DP as output
DM as output
VBUS
can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z[1]
can be driven if pin OE_N/INT_N is active LOW, otherwise high-Z[1]
can be driven depending on bit VBUS_DRV
SCL
connected to SCL I/O of the I2C-bus slave
SDA
connected to SDA I/O of the I2C-bus slave
[1] In the USB suspend mode, the ISP1301 can drive the DP and DM lines, if the OE_N/INT_N input
(when the OE_INT_EN bit is not set) is LOW. In such a case, these outputs are driven as in the USB
functional modes, but with the full-speed characteristics, irrespective of the value of the SPEED input
pin or the SPEED_REG bit.
Table 6:
USB functional modes: I/O values[1]
USB mode
Bit
Pin
DAT_SE0
BI_DI
OE_N/
INT_N
DAT/VP
SE0/VM VP
VM
RCV
VP_VM
unidirectional
bidirectional
0
0
0
1
1
1
0
1
1
0
1
1
X
TxD+[2]
TxD+[2]
RxD+[3]
TxD[4]
TxD[4]
RxD[6]
TxD−[2]
TxD−[2]
RxD−[3]
FSE0[5]
FSE0[5]
RSE0[7]
RxD+[3]
RxD−[3]
RxD[3]
LOW
HIGH
X
DAT_SE0 unidirectional
bidirectional
LOW
HIGH
[1] Some of the modes and signals are provided to achieve backward compatibility with IP cores.
[2] TxD+ and TxD− are single-ended inputs for driving the DP and DM outputs, respectively, in the single-ended mode.
[3] RxD+ and RxD− are the outputs of the single-ended receivers connected to DP and DM, respectively.
[4] TxD is the input for driving DP and DM in the DAT_SE0 mode.
[5] FSE0 is for forcing an SE0 on the DP and DM lines in the DAT_SE0 mode.
[6] RxD is the output of the differential receiver.
[7] RSE0 is an output indicating that an SE0 has been received on the DP and DM lines.
Table 7:
USB suspend mode: I/O values
USB suspend mode Input pin
Output pin
DAT/VP
LOW
DP
DM
LOW
SE0/VM VP
VM
RCV
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
DAT_SE0
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
(bit DAT_SE0 = 1)
HIGH LOW
LOW
HIGH HIGH HIGH
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH LOW
VP_VM
(bit DAT_SE0 = 0)
LOW
HIGH LOW
LOW
LOW
LOW
HIGH
HIGH LOW
HIGH HIGH HIGH
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Table 8:
Bit
Transparent general-purpose buffer mode
Direction of the data flow
TRANSP_BDIR[1:0]
00
01
10
11
DAT/VP => DP
DAT/VP => DP
DAT/VP <= DP
DAT/VP <= DP
SE0/VM => DM
SE0/VM <= DM
SE0/VM => DM
SE0/VM <= DM
10. USB transceiver
10.1 Differential driver
The operation of the driver is described in Table 9. The register bits and the pins used
in the column heading are described in Section 11.1 and Section 8.9, respectively.
Table 9:
Suspend[1] Bit
TRANSP_ OE_N/
Transceiver driver operation setting
Pin
Bit
Differential driver
DAT_SE0
EN
INT_N
0
0
0
LOW
0
1
output value from DAT/VP to DP and
SE0/VM to DM
0
LOW
output value from DAT/VP to DP and DM
if SE0/VM is 0; otherwise, drive both DP
and DM LOW
1
0
X
1
LOW
HIGH
X
X
X
X
output value from DAT/VP to DP and DM
X
X
high-Z
high-Z
[1] Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
Table 10: USB functional mode: transmit operation
USB mode
Input pin
DAT/VP
LOW
Output pin
DP
SE0/VM
LOW
DM
DAT_SE0
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
HIGH
LOW
HIGH
HIGH
LOW
HIGH
LOW
LOW
VP_VM
LOW
HIGH
LOW
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
10.2 Differential receiver
Table 11 describes the operation of the differential receiver. The register bits and the
pins used in the column heading are described in Section 11.1 and Section 8.9,
respectively.
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The detailed behavior of the receive transceiver operation is given in Table 12.
Table 11: Differential receiver operation settings
Suspend[1] Bit
TRANSP_EN OE_N/INT_N
Pin
Bit
DAT_SE0
Differential receiver
1
X
X
0
X
X
1
0
X
X
X
X
1
0
0
0
LOW
X
HIGH
output differential value from DP
and DM to DAT/VP and RCV
0
0
HIGH
0
output differential value from DP
and DM to RCV
[1] Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
Table 12: USB functional mode: receive operation
USB mode Suspend[1] Input pin
Output pin
DP
DM
DAT/VP SE0/VM RCV
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
DAT_SE0
VP_VM
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
RCV
HIGH
LOW
LOW
LOW
HIGH
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
last value of RCV
HIGH
HIGH
LOW
RCV
LOW
last value of RCV
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
last value of RCV
HIGH
VP_VM
VP_VM
LOW
VP_VM
last value of RCV
LOW
VP_VM
VP_VM
LOW
VP_VM
LOW
VP_VM
LOW
[1] Can be controlled by using either the SUSPEND pin or the SUSPEND_REG bit.
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11. Serial controller
11.1 Register map
Table 13 provides an overview of the serial controller registers.
Table 13: Serial controller registers
Register
Width Access[1] Memory address Functionality
Reference
(bits)
Vendor ID
16
R
00–01H
device identification registers Section 11.1.1 on page 17
Product ID
Version ID
16
R
02–03H
16
R
14–15H
Mode Control 1
8
R/S/C
Set — 04H
Clear — 05H
Set — 12H
Clear — 13H
Set — 06H
Clear — 07H
10H
mode control registers
Section 11.1.2 on page 18
Mode Control 2
OTG Control
8
8
R/S/C
R/S/C
OTG registers
Section 11.1.3 on page 19
Section 11.1.4 on page 20
OTG Status
8
8
8
R
Interrupt Source
Interrupt Latch
R
08H
interrupt related registers
R/S/C
Set — 0AH
Clear — 0BH
Set — 0CH
Clear — 0DH
Set — 0EH
Clear — 0FH
Interrupt Enable Low
Interrupt Enable High
8
8
R/S/C
R/S/C
[1] The R/S/C access type represents a field that can be read, set or cleared (set to 0). A register can be read from either of the indicated
addresses—set or clear. Writing logic 1 to the set address causes the associated bit to be set. Writing logic 1 to the clear address
causes the associated bit to be cleared. Writing logic 0 to an address has no effect.
11.1.1 Device identification registers
Vendor ID register (Read: 00H–01H): Table 14 provides the bit allocation of the
Vendor ID register.
Table 14: Vendor ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0 VENDORID
[15:0]
R
04CCH
Philips Semiconductors’ Vendor ID
Product ID register (Read: 02H–03H): The bit allocation of this register is given in
Table 15.
Table 15: Product ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0 PRODUCTID
[15:0]
R
1301H
Product ID of the ISP1301
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Version ID register (Read: 14H–15H): Table 16 shows the bit allocation of this
register.
Table 16: Version ID register: bit description
Bit
Symbol
Access
Value
Description
15 to 0 VERSIONID
[15:0]
R
0210H
Version number of the ISP1301
11.1.2 Mode control registers
Mode Control 1 register (Set/Clear: 04H/05H): The bit allocation of the Mode
Control 1 register is given in Table 17.
Table 17: Mode Control 1 register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
UART_EN
OE_INT_
EN
BDIS_
ACON_EN
TRANSP_
EN
DAT_SE0
SUSPEND
_REG
SPEED_
REG
Reset
-
0
0
0
0
0
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 18: Mode Control 1 register: bit description
Bit
7
Symbol
-
Description
reserved
6
UART_EN
OE_INT_EN
When set, the ATX is in the transparent UART mode.
5
When set and when in the suspend mode, pin OE_N/INT_N
becomes an output and is asserted when an interrupt occurs.
4
BDIS_ACON_EN Enables the A-device to connect if the B-device disconnect is
detected; see Section 11.3
3
2
TRANSP_EN
DAT_SE0
When set, the ATX is in the transparent mode.
0 — VP_VM mode
1 — DAT_SE0 mode; see Table 6 and Table 7
1
SUSPEND_REG Sets the ISP1301 in the suspend mode, if bit
SPD_SUSP_CTRL = 1.
0 — active-power mode
1 — USB suspend mode
0
SPEED_REG
Sets the rise time and the fall time of the transmit driver in
USB modes, if bit SPD_SUSP_CTRL = 1.
0 — USB low-speed mode
1 — USB full-speed mode
Mode Control 2 register (Set/Clear: 12H/13H): For the bit allocation of this register,
see Table 19.
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Table 19: Mode Control 2 register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
EN2V7
PSW_OE AUDIO_EN TRANSP_ TRANSP_
BI_DI
SPD_SUSP GLOBAL_
BDIR1
BDIR0
_CTRL
PWR_DN
Reset
0
0
0
0
0
1
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 20: Mode Control 2 register: bit description
Bit
Symbol
Description
7
EN2V7
0 — VBAT = 3.0 V to 4.5 V
1 — VBAT = 2.7 V to 4.5 V
6
5
PSW_OE
0 — ADR/PSW pin acts as an input
1 — ADR/PSW pin is driven
AUDIO_EN
0 — SE receiver is enabled; cr_int detector is disabled
1 — SE receiver is turned off (pin VP = LOW, pin VM = LOW);
cr_int detector is enabled
4 to 3
2
TRANSP_BDIR[1:0] controls the direction of data transfer in the transparent
general-purpose buffer mode; see Table 8
BI_DI
0 — direction of DAT/VP and SE0/VM are fixed (transmit only)
1 — direction of DAT/VP and SE0/VM are controlled by
pin OE_N/INT_N; see Table 6
1
0
SPD_SUSP_CTRL control of speed and suspend in USB modes:
0 — controlled by pins SPEED and SUSPEND
1 — controlled by bit SPEED_REG and bit SUSPEND_REG
of the Mode Control 1 register
GLOBAL_PWR_DN 0 — normal operation
1 — sets the ISP1301 to the power down mode
Activities on the I2C-bus or any OTG event can wake up the
chip; see Section 12
11.1.3 OTG registers
OTG Control register (Set/Clear: 06H/07H): Table 21 provides the bit allocation of
the OTG Control register.
Table 21: OTG Control register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
VBUS_
CHRG
VBUS_
DISCHRG
VBUS_
DRV
ID_PULL
DOWN
DM_PULL
DOWN
DP_PULL
DOWN
DM_PULL
UP
DP_PULL
UP
Reset
0
0
0
0
1
1
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
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Table 22: OTG Control register: bit description
Bit
7
Symbol
Description
VBUS_CHRG
charge VBUS through a resistor to 3.3 V
6
VBUS_DISCHRG discharge VBUS through a resistor to ground
5
VBUS_DRV
drive VBUS to 5 V through the charge pump
connect the ID pin to ground
4
ID_PULLDOWN
DM_PULLDOWN
DP_PULLDOWN
DM_PULLUP
3
connect DM pull-down resistor to ground
connect DP pull-down resistor to ground
connect DM pull-up resistor to 3.3 V
connect DP pull-up resistor to 3.3 V
2
1
0
DP_PULLUP
OTG Status register (Read: 10H): Table 23 shows the bit allocation of the OTG
Status register.
Table 23: OTG Status register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
B_SESS_
VLD
B_SESS_
END
reserved
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 24: OTG Status register: bit description
Bit
Symbol
Description
7
B_SESS_VLD set when the VBUS voltage is above the B-device session valid
threshold (2.0 V to 4.0 V)
6
B_SESS_END set when the VBUS voltage is below the B-device session end
threshold (0.2 V to 0.8 V)
5 to 0
-
reserved
11.1.4 Interrupt related registers
Interrupt Source register (Read: 08H): This register indicates the current state of
the signals that can generate an interrupt. The bit allocation of the Interrupt Source
register is given in Table 25.
Table 25: Interrupt Source register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD VBUS_VLD
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
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Table 26: Interrupt Source register: bit description
Bit
7
Symbol
Description
CR_INT
DP pin is above the car kit interrupt threshold (0.4 V to 0.6 V)
6
BDIS_ACON
set when bit BDIS_ACON_EN is set, and the ISP1301 asserts bit
DP_PULLUP after detecting the B-device disconnect
5
4
3
2
1
0
ID_FLOAT
DM_HI
ID pin is floating
DM pin is HIGH
ID_GND
DP_HI
ID pin is connected to ground
DP pin is HIGH
SESS_VLD
VBUS_VLD
session valid comparator; threshold = 0.8 V to 2.0 V
A-device VBUS valid comparator; threshold > 4.4 V
Interrupt Latch register (Set/Clear: 0AH/0BH): This register indicates the source
that generated the interrupt. The bit allocation of the Interrupt Latch register is given
in Table 27.
Table 27: Interrupt Latch register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD VBUS_VLD
Reset
0
0
0
0
0
0
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 28: Interrupt Latch register: bit description
Bit
7
Symbol
Description
CR_INT
interrupt for CR_INT status change
interrupt for BDIS_ACON status change
interrupt for ID_FLOAT status change
interrupt for DM_HI status change
interrupt for ID_GND status change
interrupt for DP_HI status change
interrupt for SESS_VLD status change
interrupt for VBUS_VLD status change
6
BDIS_ACON
ID_FLOAT
DM_HI
5
4
3
ID_GND
2
DP_HI
1
SESS_VLD
VBUS_VLD
0
Interrupt Enable Low register (Set/Clear: 0CH/0DH): This register enables
interrupts on transition from true to false. For the bit allocation of this register, see
Table 29.
Table 29: Interrupt Enable Low register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD VBUS_VLD
Reset
0
0
0
0
0
0
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
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Table 30: Interrupt Enable Low register: bit description
Bit
7
Symbol
Description
CR_INT
interrupt enable for CR_INT status change from 1 to 0
interrupt enable for BDIS_ACON status change from 1 to 0
interrupt enable for ID_FLOAT status change from 1 to 0
interrupt enable for DM_HI status change from 1 to 0
interrupt enable for ID_GND status change from 1 to 0
interrupt enable for DP_HI status change from 1 to 0
interrupt enable for SESS_VLD status change from 1 to 0
interrupt enable for VBUS_VLD status change from 1 to 0
6
BDIS_ACON
ID_FLOAT
DM_HI
5
4
3
ID_GND
2
DP_HI
1
SESS_VLD
VBUS_VLD
0
Interrupt Enable High register (Set/Clear: 0EH/0FH): The Interrupt Enable High
register enables interrupts on transition from FALSE to TRUE. Table 31 provides the
bit allocation of this register.
Table 31: Interrupt Enable High register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
CR_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
SESS_VLD VBUS_VLD
Reset
0
0
0
0
0
0
0
0
Access
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 32: Interrupt Enable High register: bit description
Bit
7
Symbol
Description
interrupt enable for CR_INT status change from 0 to 1
CR_INT
6
BDIS_ACON
ID_FLOAT
DM_HI
interrupt enable for BDIS_ACON status change from 0 to 1
interrupt enable for ID_FLOAT status change from 0 to 1
interrupt enable for DM_HI status change from 0 to 1
interrupt enable for ID_GND status change from 0 to 1
interrupt enable for DP_HI status change from 0 to 1
interrupt enable for SESS_VLD status change from 0 to 1
interrupt enable for VBUS_VLD status change from 0 to 1
5
4
3
ID_GND
2
DP_HI
1
SESS_VLD
VBUS_VLD
0
11.2 Interrupts
Table 26 indicates the signals that can generate interrupts. Any of the signals given in
Table 26 can generate an interrupt when the signal becomes either LOW or HIGH.
After an interrupt has been generated, the OTG controller should be able to read the
status of each signal and the bit that indicates whether or not that signal generated
the interrupt.
A bit in the Interrupt Latch register is set when any of these occurs:
• Writing logic 1 to its set address causes the corresponding bit to be set
• The corresponding bit in the Interrupt Enable High register is set, and the
associated signal changes from LOW to HIGH
• The corresponding bit in the Interrupt Enable Low register is set, and the
associated signal changes from HIGH to LOW.
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The Interrupt Latch register bit is cleared by writing logic 1 to its clear address.
11.3 Autoconnect
The Host Negotiation Protocol (HNP) in the OTG supplement specifies the following
sequence of events to transfer the role of the host from the A-device to the B-device:
1. The A-device puts the bus in the suspend state
2. The B-device simulates a disconnect by deasserting its DP pull-up
3. The A-device detects SE0 on the bus, and asserts its DP pull-up
4. The B-device detects that the DP line is HIGH, and takes the role of the host.
The OTG supplement specifies that the time between the B-device deasserting its DP
pull-up and the A-device asserting its pull-up must be less than 3 ms. For an A-device
with a slow interrupt response time, 3 ms may not be enough time to write an I2C-bus
command to the ISP1301 to assert the DP pull-up. An alternative method is for the
A-device transceiver to automatically assert the DP pull-up after detecting an SE0
from the B-device.
The sequence of events is as follows:
After finishing data transfers between the A-device and the B-device and before
suspending the bus, the A-device sends SOFs. The B-device receives these SOFs,
and does not transmit any packet back to the A-device. During this time, the A-device
sets the BDIS_ACON_EN bit in the ISP1301. This enables the ISP1301 to look for
SE0 whenever the A-device is not transmitting (that is, whenever the OE_N/INT_N
pin of the ISP1301 is not asserted). After the BDIS_ACON_EN bit is set, the A-device
stops transmitting SOFs and allows the bus to go to the idle state. If the B-device
disconnects, the bus goes to SE0, and the ISP1301 logic automatically turns on the
A-device pull-up.
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12. Clock wake up scheme
This section explains the ISP1301 clock stop timing, events triggering the clock to
wake up, and the timing of the clock wake up.
12.1 Power down event
The clock is stopped when the GLOBAL_PWR_DN bit is set. It takes approximately
8 ms for the clock to stop from the time the power down condition is detected. The
clock always stops at its falling edge. The waveform is given in Figure 6.
SCL
GLOBAL_PWR_DN
CLOCK
8 ms
004aaa217
Fig 6. Clock stopped using the GLOBAL_PWR_DN bit.
12.2 Clock wake up events
The clock wakes up when any of the following events occur on the ISP1301 pins:
• SCL goes LOW
• VBUS goes above the session valid threshold (0.8 V to 2.0 V), provided the
SESS_VLD bit in the Interrupt Enable High register is set.
• ID changes when mini-A plug is inserted, provided the ID_FLOAT bit in the
Interrupt Enable Low register is set.
• ID changes when mini-A plug is removed, provided the ID_FLOAT bit in the
Interrupt Enable High register is set.
• DP goes HIGH, provided the DP_HI bit in the Interrupt Enable High register is set.
• DM goes HIGH, provided the DM_HI bit in the Interrupt Enable High register is set.
The event triggers the clock to start and a stable clock is guaranteed after about six
clock periods, which is approximately 8 µs. The startup analog clock time is 10 µs.
Therefore, the total estimated start time after a triggered event is about 20 µs. The
clock will always start at its rising edge.
Waveforms of the clock wake up because of different events are given in Figure 7,
Figure 8, Figure 9, Figure 10 and Figure 11.
SCL
CLOCK
004aaa218
20 µs
Fig 7. Clock wake up using SCL.
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SESS_VLD
CLOCK
004aaa219
20 µs
Fig 8. Clock wake up by VBUS
.
ID_FLOAT
CLOCK
20 µs
004aaa220
Fig 9. Clock wake up by ID change (1).
ID_FLOAT
CLOCK
004aaa221
20 µs
Fig 10. Clock wake up by ID change (2).
DP_HI
or DM_HI
CLOCK
004aaa434
20 µs
Fig 11. Clock wake up by data line SRP.
When an event is triggered and the clock is started, it will remain active for 8 ms. If
the GLOBAL_PWR_DN bit is not cleared within this 8 ms period, the clock will stop. If
the clock wakes up because of any event other than SCL going LOW, an interrupt will
be generated once the clock is active.
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13. I2C-bus protocol
For detailed information, refer to The I2C-bus specification; version 2.1.
13.1 I2C-bus byte transfer format
Table 33: I2C-bus byte transfer format[1]
S
Byte 1
A
Byte 2
A
Byte 3
A
…
…
A
P
8 bits
8 bits
8 bits
[1] S = Start; A = Acknowledge; P = Stop.
13.2 I2C-bus device address
Table 34: Device address byte 1
Bit
7
6
5
4
3
2
1
0
device address
-
R/W
X
Name
Value
A6
0
A5
1
A4
0
A3
1
A2
1
A1
0
A0
X
Table 35: Bit description
Bit
Symbol Description
7 to 1
A[6:0]
Device address: The device address of the ISP1301 is: 0101 10 (A0).
The value of A0 (LSB) is loaded from pin ADR/PSW during reset
(including power-on reset). If pin ADR/PSW = HIGH, bit A0 = 1;
otherwise bit A0 = 0.
0
R/W
Read/write command.
0 — write
1 — read.
13.3 Write format
A write operation can be performed as:
• One-byte write to the specified register address
• Multi-byte write to N consecutive registers, starting from the specified start
address. N defines the number of registers to write. If N = 1, only the start register
is written.
13.3.1 One-byte write
Figure 12 illustrates the byte sequence.
Table 36: Transfer format description for one-byte write
Byte
Description
S
master starts with a START condition
master transmits device address and write command bit R/W = 0
slave generates an acknowledgment
Device select
ACK
Register address K master transmits address of register K
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Table 36: Transfer format description for one-byte write…continued
Byte
Description
ACK
slave generates an acknowledgment
master writes data to register K
slave generates an acknowledgment
master generates a STOP condition
Write data K
ACK
P
13.3.2 Multiple-byte write
Figure 12 illustrates the byte sequence.
Table 37: Transfer format description for multiple-byte write
Byte
Description
S
master starts with a START condition
Device select
ACK
master transmits device address and write command bit R/W = 0
slave generates an acknowledgment
Register address K master transmits address of register K. This is the start address for
writing multiple data bytes to consecutive registers. After a byte is
written, the register address is automatically incremented by 1.
Remark: If the master writes to a non existent register, the slave must
send a 'not ACK' and also must not increment the index address.
ACK
slave generates an acknowledgment
master writes data to register K
slave generates an acknowledgment
master writes data to register K + 1
slave generates an acknowledgment
:
Write data K
ACK
Write data K + 1
ACK
:
Write data
K + N − 1
master writes data to register K + N − 1. When the incremented
address K + N − 1 becomes > 255, the register address rolls over to 0.
Therefore, it is possible that some registers may be overwritten, if the
transfer is not stopped before the rollover.
ACK
P
slave generates an acknowledgment
master generates a STOP condition
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ACK
ACK
ACK
P
write data K
S
WR
deviceselect
register address K
One-byte write
ACK
ACK
ACK
ACK
ACK
ACK
ACK
write data K
S
WR
deviceselect
writedataK+2
register address K
write data K + 3
write data K + 1
ACK
P
write data K + N - 1
.... maximum, rollover to 0
004aaa213
Multiple-byte write
Fig 12. Writing data to the ISP1301 registers.
13.4 Read format
A read operation can be performed in two ways:
• Current address read: to read the register at the current address.
– Single register read.
• Random address read: to read N registers starting at a specified address.
N defines the number of registers to be read. If N = 1, only the start register is
read.
– Single register read
– Multiple register read.
13.4.1 Current address read
Figure 13 illustrates the byte sequence.
Table 38: Transfer format description for current address read
Byte
Description
S
master starts with a START condition
master transmits device address and read command bit R/W = 1
slave generates an acknowledgment
Device select
ACK
Read data K
slave transmits and master reads data from register K. If the start
address is not specified, the read operation starts from where the index
register is pointing to because of a previous read or write operation.
No ACK
P
master terminates the read operation by generating a No Acknowledge
master generates a stop condition
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ACK
No ACK
S
RD
P
device select
read data K
004aaa215
Current address read
Fig 13. Current address read.
13.4.2 Random address read
Single read: Figure 14 illustrates the byte sequence.
Table 39: Transfer format description for single-byte read
SDA line
S
Description
master starts with a START condition
Device select
ACK
master transmits device address and writes command bit R/W = 0
slave generates an acknowledgment
Register address K master transmits (start) address of register K to be read from
ACK
slave generates an acknowledgment
Device select
ACK
master transmits device address and read command bit R/W = 1
slave generates an acknowledgment
Read data K
No ACK
P
slave transmits and master reads data from register K
master terminates the read operation by generating a No Acknowledge
master generates a STOP condition
Multiple read: Figure 14 illustrates the byte sequence.
Table 40: Transfer format description for multiple-byte read
SDA line
S
Description
master starts with a START condition
master transmits device address and write command bit R/W = 0
slave generates an acknowledgment
Device select
ACK
Register address K master transmits (start) address of register K to be read from
ACK
slave generates an acknowledgment
Device select
ACK
master transmits device address and read command bit R/W = 1
slave generates an acknowledgment
Read data K
slave transmits and master reads data from register K. After a byte is
read, the address is automatically incremented by 1.
ACK
slave generates an acknowledgment
slave transmits and master reads data from register K + 1
slave generates an acknowledgment
:
Read data K + 1
ACK
:
Read data
K + N − 1
slave transmits and master reads data register K + N − 1. This is the
last register to read. After incrementing, the address rolls over to 0.
Here, N represents the number of addresses available in the slave.
No ACK
P
master terminates the read operation by generating a No Acknowledge
master generates a STOP condition
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ACK
ACK
No ACK
ACK
device select
register address K
S
P
S
WR
deviceselect
RD
read data K
Random address single read
ACK
ACK
ACK
ACK
device select
S
RD
S
WR
deviceselect
readdataK+1
register address K
read data K + 2
read data K
ACK
ACK
ACK
No ACK
P
write data K + N - 1
.... maximum, rollover to 0
004aaa214
Random access multiple read
Fig 14. Random address read.
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14. Limiting values
Table 41: Absolute maximum ratings
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VBAT
VDD_LGC
VI
Parameter
Conditions
Min
−0.5
−0.5
−0.5
-
Max
Unit
V
supply voltage
+5.5
I/O supply voltage
input voltage
+4.6
V
VI = −1.8 V to +5.4 V
ILI < 1 µA
VDD_LGC + 0.5
100
V
Ilu
latch-up current
electrostatic discharge voltage
mA
Vesd
[1]
pins DP, DM, ID,
VBUS, AGND, CGND
and DGND
−8
+8
kV
all other pins
−2
+2
kV
Tstg
storage temperature
−60
+125
°C
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model). A 4.7 µF capacitor is needed from
VREG(3V3) and VBUS to ground.
15. Recommended operating conditions
Table 42: Recommended operating conditions
Symbol
VBAT
Parameter
Conditions
Min
2.7
1.65
0
Typ
Max
4.5
Unit
V
supply voltage
I/O supply voltage
input voltage
-
-
-
-
[1]
VDD_LGC
VI
3.6
V
VDD_LGC
3.6
V
VI(AI/O)
input voltage on analog I/O pins DP
and DM
0
V
VO(OD)
Tamb
open-drain output pull-up voltage on
pins SCL, SDA and INT_N
0
-
-
3.6
V
ambient temperature
−40
+85
°C
[1] VDD_LGC should be less than or equal to VBAT
.
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16. Static characteristics
Table 43: Static characteristics: supply pins
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Charge pump disabled
Conditions
Min
Typ
Max
Unit
[1]
[2]
VREG(3V3)
regulated supply voltage output VBAT = 3.0 V to 4.5 V
VBAT = 2.7 V to 3.0 V
3.0
2.7
-
-
3.6
3.0
8
V
-
V
IBAT
operating supply current
transmitting and receiving at
4
mA
12 Mbit/s; CL = 50 pF on
pins DP and DM
[2]
[3]
IDD_LGC
IBAT(idle)
operating I/O supply current
transmitting and receiving at
12 Mbit/s
-
-
1
-
2
mA
supply current during full-speed idle: VDP > 2.7 V, VDM < 0.3 V;
300
µA
idle and SE0
IDD_LGC(static) static I/O supply current
IBAT(pd)
Charge pump enabled
IBAT(cp) operating supply current for the
charge pump
SE0: VDP < 0.3 V, VDM < 0.3 V
idle, SE0 or suspend
-
-
-
-
20
20
µA
µA
[3]
power down mode supply current bit GLOBAL_PWR_DN = 1
I
LOAD = 8 mA; ATX is idle
LOAD = 0 mA; ATX is idle
-
-
-
-
20
mA
I
300
µA
[1] In the suspend mode, the minimum voltage is 2.7 V.
[2] Maximum value characterized only, not tested in production.
[3] Excluding any load current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 µA typical).
Table 44: Static characteristics: digital pins
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input levels
VIL
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.3VDD_LGC
-
V
V
VIH
0.6VDD_LGC
Output levels
VOL
LOW-level output voltage
HIGH-level output voltage
I
I
I
I
OL = 2 mA
-
-
-
-
-
-
0.4
V
V
V
V
OL = 100 µA
OH = 2 mA
OH = 100 µA
0.15
[1]
VOH
V
DD_LGC − 0.4
-
-
V
DD_LGC − 0.15
Leakage current
ILI
input leakage current
−1
−5
-
-
-
-
+1
+5
10
µA
µA
pF
Open-drain outputs
IOZ
OFF-state output current
Capacitance
CIN
input capacitance
pin to GND
[1] Not applicable for open-drain outputs.
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Table 45: Static characteristics: analog I/O pins DP and DM
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input levels
VDI
differential input sensitivity
|VI(DP) − VI(DM)
|
0.2
0.8
-
-
-
V
V
VCM
differential common mode
voltage
includes VDI range
2.5
VIL
LOW-level input voltage
HIGH-level input voltage
-
-
-
0.8
-
V
V
VIH
2.0
Output levels
VOL
VOH
LOW-level output voltage
HIGH-level output voltage
RL of 1.5 kΩ to +3.6 V
RL of 15 kΩ to GND
VBAT = 3.0 V to 4.5 V
VBAT = 2.7 V to 3.0 V
-
-
0.3
V
2.8
2.6
-
-
3.6
3.0
V
V
Leakage current
ILZ
OFF-state leakage current
−1
-
-
-
+1
µA
pF
kΩ
Capacitance
CIN
transceiver capacitance
pin to GND
-
10
Resistance
RPD
pull-down resistor on pins
DP and DM
14.25
24.8
RPU_DP
pull-up resistor on pin DP
bus idle
900
1425
900
1425
34
-
-
-
-
-
-
1575
3090
1575
3090
44
Ω
bus driven
bus idle
Ω
RPU_DM
pull-up resistor on pin DM
Ω
bus driven
steady-state drive
Ω
[1]
ZDRV
driver output impedance
input impedance
Ω
ZINP
10
-
MΩ
Termination
VTERM
termination voltage for the
upstream port pull-up
3.0
-
3.6
V
resistor (RPU
)
[1] Includes external series resistors of 33 Ω ± 1 % each on DP and DM.
Table 46: Static characteristics: analog I/O pin ID
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resistance
RPU_ID
pull-up resistor on pin ID to
VREG(3V3)
77
-
-
-
130
10
kΩ
RPD_ID
impedance to GND
bit ID_PULLDOWN = 1
Ω
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Table 46: Static characteristics: analog I/O pin ID…continued
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RA_ID
A-device ID impedance to
GND
bit ID_GND = 1
-
-
1
kΩ
RB_ID
B-device ID impedance to
GND
bit ID_FLOAT = 1
800
20
-
-
-
kΩ
kΩ
RACC_ID
Accessory device ID
impedance to GND
bit ID_GND = 0;
bit ID_FLOAT = 0
200
Table 47: Static characteristics: charge pump
BAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
V
Symbol
Parameter
Conditions
Min
Typ
Max
8.0
Unit
mA
V
Current
ILOAD
maximum load current
C
ext = 100 nF; VBUS = 4.7 V
-
-
Voltage
VBUS
regulated VBUS output
voltage
ILOAD = 8 mA; Cext = 100 nF
4.65
5
5.25
VBUS(LEAK)
VBUS leakage voltage
VBUS valid threshold
charge pump disabled
-
-
-
-
0.2
V
V
V
Vth(VBUSVLD)
Vth(SESSEND)
4.4
0.2
4.65
0.8
VBUS session end
comparator threshold
Vhys(SESSEND) VBUS session end
comparator hysteresis
-
150
-
-
mV
V
Vth(SESSVLD)
VBUS session valid
0.8
2.0
comparator threshold
Vhys(SESSVLD) VBUS session valid
comparator hysteresis
-
200
-
-
mV
V
Vth(BSESSVLD) VBUS session valid
comparator threshold
for the B-device
for the B-device
2.0
4.0
Vhys(BSESSVLD) VBUS session valid
comparator hysteresis
-
-
200
75
-
-
mV
%
E
efficiency when loaded
ILOAD = 8 mA; VBAT = 3 V
Resistance
RVBUS(PU)
VBUS pull-up resistor
connect to VREG(3V3) when
VBUS_CHRG = 1
460
660
40
-
-
-
1000
1200
100
Ω
RVBUS(PD)
VBUS pull-down resistor
connect to GND when
VBUS_DISCHRG = 1
Ω
RVBUS(IDLE_A) VBUS idle impedance for
A-device
ID pin connected to GND
kΩ
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17. Dynamic characteristics
Table 48: Dynamic characteristics: reset and clock
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol
Reset
Parameter
Conditions
Min
Typ
Max
-
Unit
µs
tW(RESET_N) pulse width on input RESET_N
10
-
Internal clock
fclk
clock frequency
bit GLOBAL_PWR_DN = 0
700
1000
1300
kHz
Table 49: Dynamic characteristics: digital I/O pins
BAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40°C to +85 °C; unless
otherwise specified.
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tTOI
bus turnaround time
(OE_N/INT_N to DAT/VP and
SE0/VM)
output-to-input; see
Figure 19
0
-
5
ns
tTIO
bus turnaround time
(OE_N/INT_N to DAT/VP and
SE0/VM)
input-to-output; see
Figure 19
0
-
5
ns
Table 50: Dynamic characteristics: analog I/O pins DP and DM
BAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics
tFR
rise time
CL = 50 pF to 125 pF;
10 % to 90 % of
4
-
20
ns
|VOH − VOL|; see Figure 15
tFF
fall time
CL = 50 pF to 125 pF;
90 % to 10 % of
4
-
20
ns
|VOH − VOL|; see Figure 15
FRFM
VCRS
differential rise/fall time
excluding the first transition
from idle state
90
-
-
111.1
2.0
%
V
matching (tFR/tFF
)
[1]
output signal crossover voltage excluding the first transition
1.3
from idle state; see
Figure 16
Driver timing
tPLH(drv)
tPHL(drv)
tPHZ
driver propagation delay
(DAT/VP, SE0/VM to DP, DM)
LOW-to-HIGH; see
Figure 16 and Figure 20
-
-
-
-
-
-
-
-
-
-
18
18
15
15
15
ns
ns
ns
ns
ns
driver propagation delay
(DAT/VP, SE0/VM to DP, DM)
HIGH-to-LOW; see
Figure 16 and Figure 20
driver disable delay
(OE_N/INT_N to DP, DM)
HIGH-to-OFF; see
Figure 17 and Figure 21
tPLZ
driver disable delay
(OE_N/INT_N to DP, DM)
LOW-to-OFF; see
Figure 17 and Figure 21
tPZH
driver enable delay
OFF-to-HIGH; see
(OE_N/INT_N to DP, DM)
Figure 17 and Figure 21
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Table 50: Dynamic characteristics: analog I/O pins DP and DM…continued
VBAT = 2.7 V to 4.5 V; VDD_LGC = 1.65 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tPZL
driver enable delay
OFF-to-LOW; see
-
-
15
ns
(OE_N/INT_N to DP, DM)
Figure 17 and Figure 21
Receiver timing
Differential receiver
tPLH(rcv)
propagation delay (DP, DM to
RCV)
LOW-to-HIGH; see
Figure 18 and Figure 22
-
-
-
-
15
15
ns
ns
tPHL(rcv)
propagation delay (DP, DM to
RCV)
HIGH-to-LOW; see
Figure 18 and Figure 22
Single-ended receiver
tPLH(se) propagation delay (DP, DM to
LOW-to-HIGH; see
Figure 18 and Figure 22
-
-
-
-
18
18
ns
ns
VP and DAT/VP, VM and
SE0/VM)
tPHL(se)
propagation delay (DP, DM to
VP and DAT/VP, VM and
SE0/VM)
HIGH-to-LOW; see
Figure 18 and Figure 22
[1] Characterized only; not tested. Limits guaranteed by design.
1.8 V
logic input 0.9 V
0.9 V
0 V
OH
t
, t
t
, t
FR LR
FF LF
t
t
PHL(drv)
PLH(drv)
V
OH
90 %
V
90 %
differential
data lines
V
V
CRS
CRS
10 %
10 %
V
V
OL
OL
MGS964
MGS963
Fig 15. Rise and fall times.
Fig 16. Timing of DAT/VP and SE0/VM to DP and DM.
2.0 V
1.8 V
differential
data lines
V
V
CRS
CRS
0.9 V
logic input 0.9 V
0 V
0.8 V
t
t
PLH(rcv)
PHL(rcv)
t
t
t
t
PHZ
PLZ
PZH
PZL
t
t
PHL(se)
PLH(se)
V
OH
V
OH
V
−0.3 V
OH
0.9 V
0.9 V
differential
data lines
logic output
V
CRS
V
+0.3 V
OL
V
OL
V
MGS965
MGS966
OL
Fig 17. Timing of OE_N/INT_N to DP and DM.
Fig 18. Timing of DP and DM to RCV, VP or DAT/VP and
VM or SE0/VM.
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OE_N/INT_N
t
t
TOI
TIO
DAT/VP
SE0/VM
output
input
output
004aaa439
Fig 19. SIE interface bus turnaround timing.
V
TERM
V
REG(3V3)
test point
1.5 kΩ
DP or DM
D.U.T.
33 Ω
004aaa448
15 kΩ
C
L
Load capacitance CL = 50 pF (minimum or maximum timing).
Fig 20. Load on pins DP and DM.
test point
33 Ω
500 Ω
D.U.T.
50 pF
V
MBL142
V = 0 V for tPZH and tPHZ
.
V = VREG(3V3) for tPZL and tPLZ
.
Fig 21. Load on pins DP and DM for enable and disable times.
test point
D.U.T.
25 pF
MGS968
Fig 22. Load on pins VM, SE0/VM, VP, DAT/VP and RCV.
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USB OTG transceiver
Philips Semiconductors
Table 51: Characteristics of I/O stages of I2C-bus lines (SDA, SCL)
Symbol
Parameter
Standard mode
Unit
Min
-
Max
fSCL
SCL clock frequency
100
kHz
µs
µs
µs
µs
ns
µs
ns
ns
µs
µs
tHD;STA
tLOW
tHIGH
tSU;STA
tSU;DAT
tHD:DAT
tr
hold time for the START condition
LOW period of the SCL clock
HIGH period of the SCL clock
set-up time for the START condition
data set-up time
4.0
4.7
4.0
4.7
250
0
-
-
-
-
-
data hold time
-
rise time of SDA and SCL signals
fall time of SDA and SCL signals
set-up time for the STOP condition
-
1000
tf
-
300
tSU;STO
tBUF
4.0
4.7
-
-
bus free time between a STOP and START
condition
SDA
SCL
t
f
t
t
t
t
t
t
t
t
BUF
SU;DAT
LOW
f
r
HD;STA
SP
r
t
t
SU;STA
t
HD;STA
SU;STO
t
t
HIGH
HD;DAT
P
S
S
Sr
004aaa216
Fig 23. Definition of timing for standard-mode devices on the I2C-bus.
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Product data
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38 of 46
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
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xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
V
DD_LGC
V
BAT
R1
10 kΩ
SW1
V
DD_LGC
SW-PB
C1
1 µF
V
DD_LGC
C2
C10
0.1 µF
0.1 µF
V
R9
100 kΩ
DD_LGC
R3
R5
10
kΩ
R8
100
kΩ
R2
3.3
kΩ
R4
10
kΩ
3.3
kΩ
1
24
23
22
21
V
DD_LGC
ADR/PSW
2
3
4
SDA
SCL
CGND
C2
SDA
SCL
C4
0.1
µF
C1
INT_N
RESET_N
5
6
7
20
19
18
OTG
V
BAT
INT_N
CONTROLLER
5
4
3
V
SPEED
BUS
GND
ID
ISP1301
V
ID
REG(3V3)
R6
8
9
17
16
15
14
13
AGND
DP
SUSPEND
D+
OE_N
SE0
USB MINI-AB
RECEPTACLE
33 Ω
2
OE_N/INT_N
VM
D-
V
R7
33 Ω
10
11
12
1
DM
DAT/VP
SE0/VM
DAT
BUS
VP
C5
0.1 µF
RCV
C9
4.7
µF
C6
0.1
µF
C8
22
pF
C7
22
pF
004aaa348
Fig 24. Application diagram for the OTG controller with DAT_SE0 SIE interface.
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
V
DD_LGC
V
BAT
R1
10 kΩ
SW1
V
DD_LGC
SW-PB
C1
1 µF
V
DD_LGC
C3
C10
0.1 µF
0.1 µF
V
R9
100 kΩ
DD_LGC
R3
R5
10
kΩ
R8
100
kΩ
R2
3.3
kΩ
R4
10
kΩ
3.3
kΩ
1
24
V
DD_LGC
ADR/PSW
2
3
4
23
22
21
SDA
SCL
CGND
C2
SDA
SCL
C4
0.1 µF
C1
INT_N
RESET_N
5
6
7
20
19
18
OTG
CONTROLLER
V
BAT
INT_N
5
4
3
V
SPEED
BUS
GND
ID
ISP1301
V
ID
REG(3V3)
R6
8
9
17
16
15
14
13
AGND
DP
SUSPEND
D+
USB MINI-AB
RECEPTACLE
OE_N
33 Ω
2
OE_N/INT_N
VM
D-
V
RCV
VM
VP
R7
33 Ω
10
11
12
1
DM
DAT/VP
SE0/VM
BUS
VP
C5
0.1 µF
RCV
C9
4.7
µF
C6
0.1
µF
C8
22
pF
C7
22
pF
004aaa438
Fig 25. Application diagram for the OTG controller with VP_VM SIE interface.
ISP1301
USB OTG transceiver
Philips Semiconductors
19. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
SOT616-1
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
e
1
C
1/2 e
y
y
C
1
e
v
M
M
C
C
A
B
b
7
12
w
L
13
6
e
e
E
h
2
1/2 e
1
18
terminal 1
index area
24
19
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
mm
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
h
1
h
1
max.
0.05 0.30
0.00 0.18
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
0.3
0.05
0.1
1
0.2
0.5
2.5
2.5
0.1 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-22
SOT616-1
- - -
MO-220
- - -
Fig 26. HVQFN24 package outline.
9397 750 11355
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 14 April 2004
41 of 46
ISP1301
USB OTG transceiver
Philips Semiconductors
20. Soldering
20.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave
soldering can still be used for certain surface mount ICs, but it is not suitable for fine
pitch SMDs. In these situations reflow soldering is recommended. In these situations
reflow soldering is recommended.
20.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA, HTSSON..T and SSOP..T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
20.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 11355
Product data
Rev. 01 — 14 April 2004
42 of 46
ISP1301
USB OTG transceiver
Philips Semiconductors
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
20.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
20.5 Package related soldering information
Table 52: Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
Wave
Reflow[2]
BGA, HTSSON..T[3], LBGA, LFBGA, SQFP,
SSOP..T[3], TFBGA, USON, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4]
HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5][6]
not recommended[7]
not suitable
suitable
SSOP, TSSOP, VSO, VSSOP
CWQCCN..L[8], PMFP[9], WQCCN..L[8]
suitable
not suitable
[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
9397 750 11355
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 14 April 2004
43 of 46
ISP1301
USB OTG transceiver
Philips Semiconductors
[3] These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or
larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than
0.5 mm.
[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered
pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex
foil by using a hot bar soldering process. The appropriate soldering profile can be provided on
request.
[9] Hot bar soldering or manual soldering is suitable for PMFP packages.
21. Revision history
Table 53: Revision history
Rev Date
CPCN
-
Description
01 20040414
Product data (9397 750 11355).
9397 750 11355
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 01 — 14 April 2004
44 of 46
ISP1301
USB OTG transceiver
Philips Semiconductors
22. Data sheet status
Level Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
[2]
Please consult the most recently issued data sheet before initiating or completing a design.
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Right to make changes — Philips Semiconductors reserves the right to
23. Definitions
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
25. Licenses
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Purchase of Philips I2C components
Purchase of Philips I2C components conveys a license
under the Philips’ I2C patent to use the components in the
I2C system provided the system conforms to the I2C
specification defined by Philips. This specification can be
ordered using the code 9398 393 40011.
24. Disclaimers
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
26. Trademarks
I2C-bus — is a trademark of Koninklijke Philips Electronics N.V.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
45 of 46
9397 750 11355
Product data
Rev. 01 — 14 April 2004
ISP1301
USB OTG transceiver
Philips Semiconductors
Contents
1
2
3
4
5
6
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
11.1.1
11.1.2
11.1.3
11.1.4
11.2
Device identification registers. . . . . . . . . . . . . 17
Mode control registers . . . . . . . . . . . . . . . . . . 18
OTG registers. . . . . . . . . . . . . . . . . . . . . . . . . 19
Interrupt related registers. . . . . . . . . . . . . . . . 20
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Autoconnect . . . . . . . . . . . . . . . . . . . . . . . . . . 23
11.3
12
12.1
12.2
Clock wake up scheme . . . . . . . . . . . . . . . . . . 24
Power down event . . . . . . . . . . . . . . . . . . . . . 24
Clock wake up events. . . . . . . . . . . . . . . . . . . 24
7
7.1
7.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
13
13.1
13.2
13.3
13.3.1
13.3.2
13.4
13.4.1
13.4.2
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 26
I2C-bus byte transfer format . . . . . . . . . . . . . . 26
I2C-bus device address . . . . . . . . . . . . . . . . . 26
Write format . . . . . . . . . . . . . . . . . . . . . . . . . . 26
One-byte write . . . . . . . . . . . . . . . . . . . . . . . . 26
Multiple-byte write . . . . . . . . . . . . . . . . . . . . . 27
Read format . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Current address read . . . . . . . . . . . . . . . . . . . 28
Random address read . . . . . . . . . . . . . . . . . . 29
8
8.1
8.2
8.3
8.3.1
8.3.2
8.3.3
8.4
8.5
8.6
Functional description . . . . . . . . . . . . . . . . . . . 7
Serial controller. . . . . . . . . . . . . . . . . . . . . . . . . 7
VBUS charge pump . . . . . . . . . . . . . . . . . . . . . . 7
V
V
BUS comparators. . . . . . . . . . . . . . . . . . . . . . . 7
BUS valid comparator . . . . . . . . . . . . . . . . . . . 7
Session valid comparator . . . . . . . . . . . . . . . . . 7
Session end comparator. . . . . . . . . . . . . . . . . . 7
ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Pull-up and pull-down resistors. . . . . . . . . . . . . 8
USB transceiver (ATX) . . . . . . . . . . . . . . . . . . . 8
3.3 V DC-DC regulator . . . . . . . . . . . . . . . . . . . 8
Car kit interrupt detector. . . . . . . . . . . . . . . . . . 8
Detailed description of pins . . . . . . . . . . . . . . . 9
ADR/PSW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SCL and SDA . . . . . . . . . . . . . . . . . . . . . . . . . . 9
RESET_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
INT_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
OE_N/INT_N. . . . . . . . . . . . . . . . . . . . . . . . . . 10
SE0/VM, DAT/VP, RCV, VM and VP . . . . . . . . 10
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
C1 and C2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VDD_LGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AGND, CGND and DGND. . . . . . . . . . . . . . . . 11
14
15
16
17
18
19
20
20.1
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 31
Recommended operating conditions . . . . . . 31
Static characteristics . . . . . . . . . . . . . . . . . . . 32
Dynamic characteristics. . . . . . . . . . . . . . . . . 35
Application information . . . . . . . . . . . . . . . . . 39
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 41
8.7
8.8
8.9
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
8.9.9
8.9.10
8.9.11
8.9.12
8.9.13
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Introduction to soldering surface mount
packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 42
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 42
Manual soldering . . . . . . . . . . . . . . . . . . . . . . 43
Package related soldering information. . . . . . 43
20.2
20.3
20.4
20.5
21
22
23
24
25
26
Revision history . . . . . . . . . . . . . . . . . . . . . . . 44
Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 45
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9
9.1
9.2
9.3
Modes of operation . . . . . . . . . . . . . . . . . . . . . 12
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 12
Direct I2C-bus mode . . . . . . . . . . . . . . . . . . . . 12
USB modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transparent modes. . . . . . . . . . . . . . . . . . . . . 13
Transparent general-purpose buffer mode . . . 13
Transparent UART mode . . . . . . . . . . . . . . . . 13
Summary tables . . . . . . . . . . . . . . . . . . . . . . . 13
9.4
9.4.1
9.4.2
9.4.3
10
10.1
10.2
USB transceiver . . . . . . . . . . . . . . . . . . . . . . . . 15
Differential driver. . . . . . . . . . . . . . . . . . . . . . . 15
Differential receiver. . . . . . . . . . . . . . . . . . . . . 15
11
Serial controller . . . . . . . . . . . . . . . . . . . . . . . . 17
11.1
Register map . . . . . . . . . . . . . . . . . . . . . . . . . 17
© Koninklijke Philips Electronics N.V. 2004.
Printed in The Netherlands
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 14 April 2004
Document order number: 9397 750 11355
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