ISP1561BM,551_技术文档

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IMPORTANT NOTICE

Dear customer,

As from August 2^nd2008, the wireless operations of NXP have moved to a new company,

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As a result, the following changes are applicable to the attached document.

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If you have any questions related to the document, please contact our nearest sales office.

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ISP1561

Hi-Speed Universal Serial Bus PCI Host Controller

Rev. 02 — 5 March 2007

Product data sheet

1. General description

The ISP1561 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal

Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller

Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI)

core, and four transceivers that are compliant with Hi-Speed USB and Original USB. The

functional parts of the ISP1561 are fully compliant with Ref. 8 “Universal Serial Bus

Speciﬁcation”, Ref. 4 “Open Host Controller Interface Speciﬁcation for USB”, Ref. 2

“Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus”, Ref. 6 “PCI

Local Bus Speciﬁcation”, and Ref. 5 “PCI Bus Power Management Interface

Speciﬁcation”.

Integrated high performance USB transceivers allow the ISP1561 to handle all Hi-Speed

USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s). The ISP1561 provides four downstream ports, allowing simultaneous

connection of USB devices at different speeds.

The ISP1561 provides three downstream port status indicators, GoodLink along with

green and amber LEDs, to allow user-rich messages of the root hub downstream ports

status, without requiring detailed port information to be reﬂected in internal registers.

The ISP1561 is fully compatible with various operating system drivers, such as Microsoft

Windows standard OHCI and EHCI drivers that are present in Windows 98 Second

Edition (SE), Windows Millennium Edition (Me), Windows XP and Windows 2000.

The ISP1561 directly interfaces to any 32-bit, 33 MHz PCI bus. It has 5 V tolerant PCI pins

that can source 3.3 V. The PCI interface fully complies with Ref. 6 “PCI Local Bus

Speciﬁcation”.

The ISP1561 is ideally suited for use in Hi-Speed USB host-enabled motherboards,

Hi-Speed USB host PCI add-on card applications, mobile applications, and embedded

solutions.

To facilitate motherboard development, the ISP1561 can use the available 48 MHz clock

signal to reduce the total cost of a solution. To reduce the ElectroMagnetic Interference

(EMI), however, it is recommended that the 12 MHz clock is used in PCI add-on card

designs.

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

2. Features

I Complies with Ref. 8 “Universal Serial Bus Speciﬁcation”

I Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and

low-speed (1.5 Mbit/s)

I Two Original USB OHCI cores are compliant with Ref. 4 “Open Host Controller

Interface Speciﬁcation for USB”

I One Hi-Speed USB EHCI core is compliant with Ref. 2 “Enhanced Host Controller

Interface Speciﬁcation for Universal Serial Bus”

I Supports PCI 32-bit, 33 MHz interface compliant with Ref. 6 “PCI Local Bus

Speciﬁcation”, with support for D3_coldstandby and wake-up modes; all I/O pins are

3.3 V standard, but 5 V tolerant

I Compliant with Ref. 5 “PCI Bus Power Management Interface Speciﬁcation” for all

hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3_hotand D3_cold

I Four downstream ports with support for three types of downstream port indicator

LEDs: GoodLink, amber and green LEDs

I CLKRUN support for mobile applications, such as internal notebook design

I Conﬁgurable subsystem ID and subsystem vendor ID through external EEPROM

I Conﬁgurable two or four port root hub

I Digital and analog power separation

I Supports hot Plug and Play and remote wake-up of peripherals

I Supports individual power switching and individual overcurrent protection for

downstream ports

I Supports partial dynamic port-routing capability for downstream ports that allows

sharing of the same physical downstream ports between the Original USB Host

Controller and the Hi-Speed USB Host Controller

I Supports legacy PS/2 keyboards and mice

I Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions

I Operates at +3.3 V power supply input

I Full industrial operating temperature range from −40 °C to +85 °C

I Full-scan design with high fault coverage (93 % to 95 %) ensures high quality

I LQFP128 package available

3. Applications

I PC motherboard

I Notebook

I PCI add-on card

I Set-Top Box (STB)

I Web appliance

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

2 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

plastic low proﬁle quad ﬂat package; 128 leads; body 14 × 14 × 1.4 mm

Version

ISP1561BM

LQFP128

SOT420-1

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

3 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

6. Pinning information

6.1 Pinning

1

96

65

ISP1561BM

32

004aaa931

Fig 2. Pin conﬁguration

6.2 Pin description

Table 2.

Pin description

Symbol^[1]

Type Description

SEL48M

1

I

selection between 12 MHz crystal and 48 MHz oscillator

0 — 12 MHz crystal is used

1 — 48 MHz oscillator is used

push-pull; TTL with hysteresis; 5 V tolerant

I²C-bus clock (open-drain)^[2]

I²C-bus data (open-drain)^[2]

SCL

2

3

4

O

SDA

I/O

O

PME#

PCI power management event; used by a device to request a

change in the device or system power state

push-pull, open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

V_AUX

5

6

7

-

auxiliary voltage (3.3 V)

digital ground

DGND

IRQ1

-

O

system keyboard interrupt

push-pull; open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

IRQ12

8

9

O

I

system mouse interrupt

push-pull; open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

SEL2PORTS

active downstream port selection

0 — all the four ports are active

1 — only port 1 and port 2 are active; port 3 and port 4 are

inactive

push-pull; TTL with hysteresis; 5 V tolerant

supply voltage (3.3 V)

V_DD

10

-

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

5 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 2.

Pin description …continued

Symbol^[1]

Type Description

A20OUT

11

O

legacy gate 20 output

push-pull; open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

KBIRQ1

12

13

I

legacy keyboard interrupt input

push-pull; TTL with hysteresis; 5 V tolerant^[3]

legacy mouse interrupt input

MUIRQ12

push-pull; TTL with hysteresis; 5 V tolerant^[3]

DGND

SMI#

14

15

-

digital ground

O

system management interrupt

open-drain; push-pull; 10 ns slew rate control; CMOS; 5 V

tolerant

INTA#

16

O

PCI interrupt

push-pull, open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

V_DD

17

18

-

I

supply voltage (3.3 V)

RST#

PCI reset; used to bring PCI-speciﬁc registers, sequencers and

signals to a consistent state

push-pull; TTL with hysteresis; 5 V tolerant

PCI system clock (33 MHz)

CLK

19

20

I

GNT#

PCI grant; indicates to the agent that access to the bus has been

granted

DGND

REQ#

21

22

-

digital ground

O

PCI request; indicates to the arbitrator that the agent wants to

use the bus

AD[31]

AD[30]

V_DD

23

24

25

26

27

28

29

30

31

32

33

34

35

I/O

-

bit 31 of multiplexed PCI address and data

bit 30 of multiplexed PCI address and data

supply voltage (3.3 V)

AD[29]

AD[28]

AD[27]

DGND

AD[26]

AD[25]

AD[24]

V_DD

I/O

-

bit 29 of multiplexed PCI address and data

bit 28 of multiplexed PCI address and data

bit 27 of multiplexed PCI address and data

digital ground

I/O

-

bit 26 of multiplexed PCI address and data

bit 25 of multiplexed PCI address and data

bit 24 of multiplexed PCI address and data

supply voltage (3.3 V)

C/BE#[3]

IDSEL

I/O

I

byte 3 of multiplexed PCI bus command and byte enable

PCI initialization device select; used as a chip select during

conﬁguration read and write transactions

AD[23]

DGND

AD[22]

AD[21]

AD[20]

36

37

38

39

40

I/O

-

bit 23 of multiplexed PCI address and data

digital ground

I/O

bit 22 of multiplexed PCI address and data

bit 21 of multiplexed PCI address and data

bit 20 of multiplexed PCI address and data

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

6 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 2.

Pin description …continued

Symbol^[1]

41

42

43

44

45

46

47

48

Type Description

V_DD

-

supply voltage (3.3 V)

AD[19]

AD[18]

AD[17]

DGND

I/O

-

bit 19 of multiplexed PCI address and data

bit 18 of multiplexed PCI address and data

bit 17 of multiplexed PCI address and data

digital ground

AD[16]

C/BE#[2]

FRAME#

I/O

bit 16 of multiplexed PCI address and data

byte 2 of multiplexed PCI bus command and byte enable

PCI cycle frame; driven by the master to indicate the beginning

and duration of an access

V_DD

49

50

-

supply voltage (3.3 V)

IRDY#

I/O

PCI initiator ready; indicates ability of the initiating agent to

complete the current data phase of a transaction

TRDY#

51

52

I/O

PCI target ready; indicates ability of the target agent to complete

the current data phase of a transaction

DEVSEL#

PCI device select; indicates if any device has been selected on

the bus

DGND

53

54

-

digital ground

STOP#

I/O

PCI stop; indicates that the current target is requesting the

master to stop the current transaction

CLKRUN#

PERR#

55

56

I/O

PCI CLKRUN signal

push-pull input; 3-state output; 5 ns slew rate control; TTL with

hysteresis; 5 V tolerant

PCI parity error; used to report data parity errors during all PCI

transactions, except a special cycle

V_DD

57

58

-

supply voltage (3.3 V)

SERR#

O

PCI system error; used to report address parity errors, data parity

errors on the Special Cycle command, or any other system error

where the result will be catastrophic

push-pull; open-drain; 10 ns slew rate control; CMOS; 5 V

tolerant

PAR

59

60

61

62

63

64

65

66

67

68

69

70

71

72

I/O

-

PCI parity

C/BE#[1]

DGND

AD[15]

AD[14]

AD[13]

V_DD

byte 1 of multiplexed PCI bus command and byte enable

digital ground

I/O

-

bit 15 of multiplexed PCI address and data

bit 14 of multiplexed PCI address and data

bit 13 of multiplexed PCI address and data

supply voltage (3.3 V)

AD[12]

AD[11]

AD[10]

DGND

AD[9]

I/O

-

bit 12 of multiplexed PCI address and data

bit 11 of multiplexed PCI address and data

bit 10 of multiplexed PCI address and data

digital ground

I/O

bit 9 of multiplexed PCI address and data

bit 8 of multiplexed PCI address and data

byte 0 of multiplexed PCI bus command and byte enable

AD[8]

C/BE#[0]

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

7 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 2.

Symbol^[1]

Pin description …continued

Type Description

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

V_DD

-

supply voltage (3.3 V)

AD[7]

AD[6]

DGND

AD[5]

AD[4]

AD[3]

V_DD

I/O

-

bit 7 of multiplexed PCI address and data

bit 6 of multiplexed PCI address and data

digital ground

I/O

-

bit 5 of multiplexed PCI address and data

bit 4 of multiplexed PCI address and data

bit 3 of multiplexed PCI address and data

supply voltage (3.3 V)

AD[2]

AD[1]

DGND

AD[0]

V_AUX

I/O

-

bit 2 of multiplexed PCI address and data

bit 1 of multiplexed PCI address and data

digital ground

I/O

-

bit 0 of multiplexed PCI address and data

auxiliary voltage (3.3 V)

DGND

XTAL1

-

digital ground

I

crystal input; directly connected to a 12 MHz crystal; when this

pin is connected to an external 48 MHz oscillator source,

pin XTAL2 must be left open

Remark: This pin works in conjunction with pin SEL48M.

XTAL2

88

O

crystal output; directly connected to a 12 MHz crystal; when

XTAL1 is connected to an external 48 MHz oscillator source, this

pin must be left open

Remark: This pin works in conjunction with pin SEL48M.

overcurrent sense input for the USB downstream port 1 (digital)

push-pull; TTL with hysteresis; 5 V tolerant

OC1

PWE1

GL1

89

90

91

I

O

power enable for USB downstream port 1 (open-drain)

10 ns slew rate control; TTL; 5 V tolerant

GoodLink LED indicator output for USB downstream port 1

(open-drain); the LED is off by default, blinks on at USB trafﬁc

10 ns slew rate control; TTL; 5 V tolerant

AMB1

92

O

amber LED indicator output for USB downstream port 1

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

AV_AUX

93

94

95

-

analog auxiliary voltage (3.3 V); supply voltage

reference ground; RREF resistor must be connected to this pin

GND_RREF

GRN1

-

O

green LED indicator output for USB downstream port 1

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

OC2

96

97

I

overcurrent sense input for USB downstream port 2 (digital)

push-pull; TTL with hysteresis; 5 V tolerant

PWE2

O

power enable for USB downstream port 2 (open-drain)

10 ns slew rate control; TTL; 5 V tolerant

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

8 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 2.

Pin description …continued

Symbol^[1]

Type Description

GL2

98

O

GoodLink LED indicator output for USB downstream port 2

(open-drain); the LED is off by default, blinks on at USB trafﬁc

10 ns slew rate control; TTL; 5 V tolerant

AMB2

GRN2

99

O

amber LED indicator output for USB downstream port 2

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

100

O

green LED indicator output for USB downstream port 2

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

AV_{AUX_PLL}

DM1

101

102

103

104

105

-

analog auxiliary voltage (3.3 V); supply voltage for PLL

D−; analog connection for USB downstream port 1

D+; analog connection for USB downstream port 1

analog ground

AI/O

DP1

AI/O

AGND

OC3

-

I

overcurrent sense input for USB downstream port 3 (digital)

push-pull; TTL with hysteresis; 5 V tolerant

power enable for USB downstream port 3 (open-drain)

10 ns slew rate control; TTL; 5 V tolerant

PWE3

106

O

RREF

AV_AUX

DM2

107

108

109

110

111

112

AI/O

-

analog connection for the external resistor (12 kΩ ± 1 %)

analog auxiliary voltage (3.3 V); supply voltage

D−; analog connection for USB downstream port 2

D+; analog connection for USB downstream port 2

analog ground

AI/O

-

DP2

AGND

GL3

O

GoodLink LED indicator output for USB downstream port 3

(open-drain); the LED is off by default, blinks on at USB trafﬁc

10 ns slew rate control; TTL; 5 V tolerant

AMB3

GRN3

113

I/O

amber LED indicator output for USB downstream port 3

(open-drain); the LED is off by default and can be programmed to

enable it to blink; input as port indicator enable during reset; by

default, pull up is enabled; if no LEDs are used, then connect this

pin to ground, that is, no port indicator support

bidirectional pin; push-pull input; 3-state output; 10 ns slew rate

control; TTL; 5 V tolerant

114

O

green LED indicator output for USB downstream port 3

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

analog auxiliary voltage (3.3 V); supply voltage

D−; analog connection for USB downstream port 3

D+; analog connection for USB downstream port 3

analog ground

AV_AUX

DM3

115

116

117

118

119

-

AI/O

DP3

AI/O

AGND

OC4

-

I

overcurrent sense input for USB downstream port 4 (digital)

push-pull; TTL with hysteresis; 5 V tolerant

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

9 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 2.

Pin description …continued

Symbol^[1]

Type Description

PWE4

120

O

power enable for USB downstream port 4 (open-drain)

10 ns slew rate control; TTL; 5 V tolerant

analog auxiliary voltage (3.3 V); supply voltage

D−; analog connection for USB downstream port 4

D+; analog connection for USB downstream port 4

analog ground

AV_AUX

DM4

DP4

121

122

123

124

125

-

AI/O

-

AGND

GL4

O

GoodLink LED indicator output for USB downstream port 4

(open-drain); the LED is off by default, blinks on at USB trafﬁc

10 ns slew rate control; TTL; 5 V tolerant

AMB4

126

I/O

amber LED indicator output for USB downstream port 4

(open-drain); this pin acts as an input only during the power-up

sequence and thereafter, acts as an output

1 — FF in the PMC register; supports D3_cold

0 — EF in the PMC register; does not support D3_cold

bidirectional pin; push-pull input; 3-state output; 10 ns slew rate

control; TTL; 5 V tolerant

GRN4

DGND

127

128

O

-

green LED indicator output for USB downstream port 4

(open-drain); the LED is off by default; the LED can be

programmed to enable it to blink

10 ns slew rate control; TTL; 5 V tolerant

digital ground

[1] Symbol names ending with a ‘#’ (for example, NAME#) represent active LOW signals for PCI pins. Symbol

names with an overscore (for example, NAME) represent active LOW signals for USB pins.

[2] The pull-up resistor must always be present even if I²C EEPROM is not used.

[3] If legacy support is not used, connect this pin to ground.

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

10 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

7. Functional description

7.1 OHCI Host Controller

An OHCI Host Controller transfers data to devices at the Original USB deﬁned bit rate of

12 Mbit/s or 1.5 Mbit/s.

7.2 EHCI Host Controller

The EHCI Host Controller transfers data to a Hi-Speed USB compliant device at the

Hi-Speed USB deﬁned bit rate of 480 Mbit/s. When the EHCI Host Controller has the

ownership of a port, OHCI Host Controllers are not allowed to modify the port register. All

additional port bit deﬁnitions required for the enhanced Host Controller are not visible to

the OHCI Host Controller.

7.3 Dynamic port-routing logic

The port-routing feature allows sharing of the same physical downstream ports between

the Original USB Host Controller and the Hi-Speed USB Host Controller. This requirement

of Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus”

provides four downstream ports that are multiplexed with the ports of the two OHCIs. The

ﬁrst and third downstream ports are always connected to the ﬁrst OHCI, and the second

and fourth downstream ports are always connected to the second OHCI.

The EHCI is responsible for the port-routing switching mechanism. Two register bits are

used for ownership switching. During power-on and system reset, the default ownership of

all downstream ports is OHCIs. The enhanced Host Controller Driver (HCD) controls the

ownership during normal functionality.

7.4 Hi-Speed USB analog transceivers

The Hi-Speed USB analog transceivers directly interface to the USB cables through

integrated termination resistors. These transceivers can transmit and receive serial data

at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s).

7.5 LED indicators for downstream ports

Indication of a good USB connection is provided through the GoodLink technology

(open-drain, a maximum current of 20 mA). During enumeration, LED indicators blink on

momentarily corresponding to the enumeration trafﬁc of ISP1561 downstream ports. The

LED also blinks on whenever there is valid trafﬁc to the downstream port. In suspend

mode, the LED is off.

The GoodLink feature provides a user-friendly indication on the status of the USB trafﬁc

between the host and downstream hubs and devices. It is a useful diagnostics tool to

isolate faulty equipment and helps to reduce ﬁeld support and hotline costs.

The system designer can also program two optional port indicators, a green LED and an

amber LED, to indicate the status of the Host Controller. These port indicators are

implemented as per the USB speciﬁcation.

All LED indicators are open-drain output.

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

11 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

7.6 Power management

The ISP1561 provides an advanced power management capabilities interface that is

compliant with Ref. 5 “PCI Bus Power Management Interface Speciﬁcation”. Power is

controlled and managed by the interaction between drivers and PCI registers. For a

detailed description on power management, see Section 10.

7.7 Legacy support

The ISP1561 provides legacy support for a USB keyboard and mouse. This means that

the keyboard and mouse must be able to work even before the OS boot-up, with the

necessary support in the system’s BIOS. Section 11.2 provides detailed description on

legacy support in the ISP1561.

7.8 Phase-Locked Loop (PLL)

A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows

the use of a low-cost 12 MHz crystal, which also minimizes EMI. No external components

are required for the PLL to operate.

8. PCI

8.1 PCI interface

The PCI interface has three functions. The ﬁrst function (#0) and the second function (#1)

are for OHCI Host Controllers, and the third function (#2) is for the EHCI Host Controller.

All functions supports both master and target accesses and share the same PCI interrupt

signal INTA#. These functions provide memory-mapped, addressable operational

registers as required in Ref. 4 “Open Host Controller Interface Speciﬁcation for USB” and

Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus”.

Additionally, function #0 provides legacy keyboard and mouse support to comply with Ref.

4 “Open Host Controller Interface Speciﬁcation for USB”.

Each function has its own conﬁguration space. The PCI enumerator must allocate the

memory address space for each of these functions. Power management is implemented

in each PCI function and all power states are provided. This allows the system to achieve

low power consumption by switching off the functions which are not required.

8.1.1 PCI conﬁguration space

Ref. 6 “PCI Local Bus Speciﬁcation” requires that each of the three PCI functions of the

ISP1561 provides its own PCI conﬁguration registers, which can vary in size. In addition to

the basic PCI conﬁguration header registers, these functions implement the capability

registers to support power management.

The registers of each of these functions are accessed by the respective driver. Section 8.2

provides a detailed description of various PCI conﬁguration registers.

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

12 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

8.1.2 PCI initiator and target

A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI

transactions as a slave. In the ISP1561, the two open Host Controllers and the enhanced

Host Controller function as both initiators or targets of PCI transactions issued by the host

CPU.

All USB Host Controllers have their own operational registers that can be accessed by the

system driver software. Drivers use these registers to conﬁgure the Host Controller

hardware system, issue commands to it and/or monitor the status of the current hardware

operation. The Host Controller plays the role of a PCI target. All operational registers of

the Host Controllers are the PCI transaction targets of the CPU.

Normal USB transfers require the Host Controller to access system memory ﬁelds, which

are allocated by USB HCDs and PCI drivers. The Host Controller hardware interacts with

the HCD by accessing these buffers. The Host Controller works as an initiator in this case,

and becomes a PCI master.

8.2 PCI conﬁguration registers

OHCI USB Host Controllers and the EHCI USB Host Controller contain two sets of

software-accessible hardware registers: PCI conﬁguration registers and memory-mapped

Host Controller registers.

A set of conﬁguration registers is implemented for each of the three PCI functions of the

ISP1561, see Table 3.

Remark: In addition to the normal PCI header (from offset index 00h to 3Fh),

implementation-speciﬁc registers are deﬁned to support power management and

function-speciﬁc features.

Table 3.

PCI conﬁguration space registers of OHCI1, OHCI2 and EHCI

Address Bits 31 to 24 Bits 23 to 16 Bits 15 to 8

Bits 7 to 0

Reset Hex Value^[1]

(Hex)

Func0 OHCI1 Func1 OHCI2 Func2 EHCI

00

04

08

0C

DID[15:0]

VID[15:0]

Command[15:0]

1561 1131

0210 0000

0C03 1030

0080 0000

1562 1131

0210 0000

0C03 2030

0080 0000

Status[15:0]

0210 0000

Class Code[23:0]

REVID[7:0] 0C03 1030

BIST[7:0]

Header

LT[7:0]

CLS[7:0]

0080 0000

Type[7:0]

10

14

18

1C

20

24

28

2C

30

34

38

BAR0[31:0]

0000 0000

Base Address Register 1, 2, 3, 4, 5 (Not conﬁgurable to

prevent setting by the driver)

0000 0000

Cardbus CIS Pointer[31:0]

0000 0000

1561 1131

0000 0000

0000 00DC

0000 0000

1561 1131

0000 0000

0000 00DC

0000 0000

1562 1131

0000 0000

0000 00DC

0000 0000

SID[15:0]

SVID[15:0]

Expansion ROM Base Address[31:0]

Reserved

CP[7:0]

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 3.

PCI conﬁguration space registers of OHCI1, OHCI2 and EHCI …continued

Address Bits 31 to 24 Bits 23 to 16 Bits 15 to 8

(Hex)

Bits 7 to 0

Reset Hex Value^[1]

Func0 OHCI1 Func1 OHCI2 Func2 EHCI

3C

40

MAX_LAT

[7:0]

MIN_GNT

[7:0]

Interrupt

Pin[7:0]

IL[7:0]

2A01 0100

1002 0100

Reserved

Retry Timeout

TRDY

0000 8000

Timeout

Enhanced Host Controller-speciﬁc PCI registers

60 PORTWAKECAP[15:0] FLADJ[7:0]

Power management registers

SBRN[7:0]

-

XX1F 2020^[2]

DC

PMC[15:0]

NEXT_ITEM_ CAP_ID[7:0]

PTR[7:0]

5202 0001

FF02 0001

E0

DATA[7:0]

PMCSR_BSE

[7:0]

PMCSR[15:0]

0000 0000

0000 XX00^[2]

[1] Reset values that are highlighted (for example, 0) indicate read and write accesses; and reset values that are not highlighted (for

example, 0) indicate read-only.

[2] XX is 1Fh for four ports or 07h for two ports.

The HCD does not usually interact with the PCI conﬁguration space. The conﬁguration

space is used only by the PCI enumerator to identify the USB Host Controller and assign

appropriate system resources by reading the Vendor ID (VID) and the Device ID (DID).

8.2.1 PCI conﬁguration header registers

The enhanced Host Controller implements normal PCI header register values, except the

values for the memory-mapping base address register, serial bus number and device ID.

8.2.1.1 Vendor ID register (address: 00h)

This read-only register identiﬁes the manufacturer of the device. PCI Special Interest

Group (PCI-SIG) assigns valid vendor identiﬁers to ensure the uniqueness of the

identiﬁer. The bit description is shown in Table 4.

Table 4.

Bit

Vendor ID register: bit description

Symbol

Access

Value

Description

15 to 0

VID[15:0]

R

1131h

Vendor ID: This read-only register value is assigned to NXP Semiconductors

by PCI-SIG as 1131h.

8.2.1.2 Device ID register (address: 02h)

Device ID is a 2-byte read-only register that identiﬁes a particular device. This identiﬁer is

allocated by NXP Semiconductors. Table 5 shows the bit description of the register.

Table 5.

Bit

Device ID register: bit description

Symbol

Access

Value

Description

15 to 0

DID[15:0]

R

X^[1]

Device ID: This register value is deﬁned by NXP Semiconductors to

identify the USB Host Controller IC product. For the ISP1561, NXP

Semiconductors has deﬁned OHCI functions as 1561h, and the EHCI

function as 1562h.

[1] X is 1561h for OHCI1 and OHCI2 and X is 1562h for EHCI.

ISP1561_2

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

8.2.1.3 Command register (address: 04h)

This is a 2-byte register that provides coarse control over the ability of a device to

generate and respond to PCI cycles. The bit allocation of the Command register is given

in Table 6. When logic 0 is written to this register, the device is logically disconnected from

the PCI bus for all accesses, except conﬁguration accesses. All devices are required to

support this base level of functionality. Individual bits in the Command register may or may

not support this base level of functionality.

Table 6.

Bit

Command register: bit allocation

15

14

13

12

11

10

9

FBBE

0

8

SERRE

0

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

4

R/W

1

R/W

0

7

6

5

3

2

Symbol

Reset

Access

SCTRL

PER

0

VGAPS

MWIE

0

SC

0

BM

0

MS

0

IOS

0

R

R/W

R

R/W

R

R/W

Table 7.

Command register: bit description

Bit

Symbol

-

Description

15 to 10

9

reserved

FBBE

Fast Back-to-Back Enable: This bit controls whether a master can do

fast back-to-back transactions to various devices. The initialization

software must set this bit if all targets are fast back-to-back capable.

0 — Fast back-to-back transactions are only allowed to the same

agent (value after RST#).

1 — The master is allowed to generate fast back-to-back transactions

to different agents.

8

SERRE

SERR# Enable: This bit is an enable bit for the SERR# driver. All

devices that have an SERR# pin must implement this bit. Address

parity errors are reported only if this bit and the PER bit are logic 1.

0 — Disable the SERR# driver.

1 — Enable the SERR# driver.

7

6

SCTRL

PER

Stepping Control: This bit controls whether a device does address

and data stepping. Devices that never do stepping must clear this bit.

Devices that always do stepping must set this bit. Devices that can do

either, must make this bit read/write and initialize it to logic 1 after

RST#.

Parity Error Response: This bit controls the response of a device to

parity errors. When the bit is set, the device must take its normal

action when a parity error is detected. When the bit is logic 0, the

device sets its Detected Parity Error status bit (bit 15 in the Status

register) when an error is detected, but does not assert PERR# and

continues normal operation. The state of this bit after RST# is logic 0.

Devices that check parity must implement this bit. Devices are

required to generate parity, even if parity checking is disabled.

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 7.

Command register: bit description …continued

Bit

Symbol

Description

5

VGAPS

VGA Palette Snoop: This bit controls how VGA compatible and

graphics devices handle accesses to VGA palette registers. When this

bit is logic 1, palette snooping is enabled (that is, the device does not

respond to palette register writes and snoops data). When the bit is

logic 0, the device must treat palette write accesses like all other

accesses. VGA compatible devices should implement this bit.

4

MWIE

Memory Write and Invalidate Enable: This is an enable bit for using

the Memory Write and Invalidate command. When this bit is logic 1,

masters may generate the command. When it is logic 0, Memory

Writes must be used instead. State after RST# is logic 0. This bit must

be implemented by master devices that can generate the Memory

Write and Invalidate command.

3

2

1

0

SC

BM

MS

IOS

Special Cycles: Controls the action of a device on special cycle

operations. A value of logic 0 causes the device to ignore all special

cycle operations. A value of logic 1 allows the device to monitor

special cycle operations. State after RST# is logic 0.

Bus Master: Controls the ability of a device to act as a master on the

PCI bus. A value of logic 0 disables the device from generating PCI

accesses. A value of logic 1 allows the device to behave as a bus

master. State after RST# is logic 0.

Memory Space: Controls the response of a device to memory space

accesses. A value of logic 0 disables the device response. A value of

logic 1 allows the device to respond to memory space accesses. State

after RST# is logic 0.

IO Space: Controls the response of a device to I/O space accesses. A

value of logic 0 disables the device response. A value of logic 1 allows

the device to respond to I/O space accesses. State after RST# is

logic 0.

8.2.1.4 Status register (address: 06h)

The Status register is a 2-byte read-only register used to record status information on PCI

bus-related events (bit allocation: see Table 8).

Table 8.

Bit

Status register: bit allocation

15

14

13

12

RTA

0

11

STA

0

10

9

8

Symbol

Reset

Access

Bit

DPE

SSE

RMA

DEVSELT[1:0]

MDPE

0

R

2

1

R

1

0

R

0

R

7

FBBC

0

6

5

66MC

0

4

3

Symbol

Reset

Access

reserved

CL

1

reserved

0

-

0

-

0

-

0

-

0

-

R

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 9.

Status register: bit description

Bit

Symbol

Description

15

DPE

Detected Parity Error: This bit must be set by the device whenever

it detects a parity error, even if the parity error handling is disabled.

14

SSE

Signaled System Error: This bit must be set whenever the device

asserts SERR#. Devices that never assert SERR# do not need to

implement this bit.

13

RMA

Received Master Abort: This bit must be set by a master device

whenever its transaction, except for special cycle, is terminated with

master abort. All master devices must implement this bit.

12

RTA

Received Target Abort: This bit must be set by a master device

whenever its transaction is terminated with target abort. All master

devices must implement this bit.

11

STA

Signaled Target Abort: This bit must be set by a target device

whenever it terminates a transaction with target abort. Devices that

never signal target abort do not need to implement this bit.

10 to 9

DEVSELT[1:0]

DEVSEL Timing: These bits encode the timing of DEVSEL#. There

are three allowable timing for assertion of DEVSEL#:

00b — for fast

01b — for medium

10b — for slow

11b — is reserved

These bits are read-only and must indicate the slowest time that a

device asserts DEVSEL# for any bus command, except

Conﬁguration Read and Conﬁguration Write.

8

7

MDPE

Master Data Parity Error: This bit is implemented by bus masters.

It is set when the following three conditions are met:

• The bus agent asserted PERR# itself, on a read; or observed

PERR# asserted, on a write.

• The agent setting the bit acted as the bus master for the

operation in which error occurred.

• The Parity Error Response bit (in the Command register) is set.

FBBC

Fast Back-to-Back Capable: This read-only bit indicates whether

the target is capable of accepting fast back-to-back transactions

when the transactions are not to the same agent. This bit can be set

to logic 1 if the device can accept these transactions; and must be

set to logic 0 otherwise.

6

5

-

reserved

66MC

66 MHz Capable: This read-only bit indicates whether this device is

capable of running at 66 MHz. A value of logic 0 indicates 33 MHz,

and a value of logic 1 indicates 66 MHz.

4

CL

Capabilities List: This read-only bit indicates whether this device

implements the pointer for a new capabilities linked list at offset 34h.

A value of logic 0 indicates that no new capabilities linked list is

available. A value of logic 1 indicates that the value read at offset

34h is a pointer in conﬁguration space to a linked list of new

capabilities.

3 to 0

-

reserved

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

8.2.1.5 Revision ID register (address: 08h)

This 1-byte read-only register indicates a device-speciﬁc revision identiﬁer. The value is

chosen by the vendor. This ﬁeld is a vendor-deﬁned extension of the device ID. The

Revision ID register bit description is given in Table 10.

Table 10. Revision ID register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

REVID[7:0]

R

30h

Revision ID: This byte speciﬁes the design revision number of functions.

8.2.1.6 Class Code register (address: 09h)

Class Code is a 24-bit read-only register used to identify the generic function of the

device, and in some cases, a speciﬁc register-level programming interface. Table 11

shows the bit allocation of the register.

The Class Code register is divided into three byte-size ﬁelds. The upper byte is a base

class code that broadly classiﬁes the type of function the device performs. The middle

byte is a sub-class code that identiﬁes more speciﬁcally the function of the device. The

lower byte identiﬁes a speciﬁc register-level programming interface, if any, so that

device-independent software can interact with the device.

Table 11. Class Code register: bit allocation

Bit

23

15

7

22

14

6

21

13

5

20

12

4

19

11

3

18

10

2

17

16

Symbol

Reset

Access

Bit

BCC[7:0]

0Ch

R

9

8

Symbol

Reset

Access

Bit

SCC[7:0]

03h

R

1

0

Symbol

Reset

Access

RLPI[7:0]

X^[1]

R

[1] X is 10h for OHCI1 and OHCI2; X is 20h for EHCI.

Table 12. Class Code register: bit description

Bit

Symbol

Description

23 to 16

BCC[7:0]

Base Class Code: 0Ch is the base class code assigned to this byte,

and it implies a serial bus controller.

15 to 8

7 to 0

SCC[7:0]

RLPI[7:0]

Sub-Class Code: 03h is the sub-class code assigned to this byte, and

it implies the USB Host Controller.

Register-Level Programming Interface: 10h is the programming

interface code assigned to OHCI, which is USB 1.1 speciﬁcation

compliant. 20h is the programming interface code assigned to EHCI,

which is USB 2.0 speciﬁcation compliant.

ISP1561_2

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

8.2.1.7 CacheLine Size register (address: 0Ch)

The CacheLine Size register is a read/write single-byte register that speciﬁes the system

cacheline size in units of DWORDs. This register must be implemented by master devices

that can generate the Memory Write and Invalidate command. The value in this register is

also used by master devices to determine whether to use the Read, Read Line, or Read

Multiple command to access memory.

Slave devices that want to allow memory bursting using cacheline-wrap addressing mode

must implement this register to know when a burst sequence wraps to the beginning of the

cacheline.

This ﬁeld must be initialized to logic 0 on activation of RST#. Table 13 shows the bit

description of the CacheLine Size register.

Table 13. CacheLine Size register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

CLS[7:0]

R/W

00h

CacheLine Size: This byte identiﬁes the system cacheline size.

8.2.1.8 Latency Timer register (address: 0Dh)

This 1-byte register speciﬁes, in units of PCI bus clocks, the value of the latency timer for

the PCI bus master. The Latency Time register bit description is given in Table 14.

This register must be implemented as writable by any master that can burst more than two

data phases. This register may be implemented as read-only for devices that burst two or

fewer data phases, but the ﬁxed value must be limited to 16 or less. The register must be

initialized to logic 0 at RST#, if programmable.

Table 14. Latency Timer register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

LT[7:0]

R/W

00h

Latency Timer: This byte identiﬁes the latency timer.

8.2.1.9 Header Type register (address: 0Eh)

The Header Type register identiﬁes the layout of the second part of the predeﬁned header,

beginning at byte 10h in conﬁguration space. It also identiﬁes whether the device contains

multiple functions (bit allocation: see Table 15).

Table 15. Header Type register: bit allocation

Bit

7

MFD

1

6

5

4

3

2

1

0

Symbol

Reset

Access

HT[6:0]

0

R

Table 16. Header Type register: bit description

Bit

Symbol

Description

7

MFD

Multi-Function Device: This bit identiﬁes a multifunction device. If the

bit is logic 0, then the device has a single function. If the bit is logic 1,

then the device has multiple functions.

6 to 0

HT[6:0]

Header Type: These bits identify the layout of the part of the

predeﬁned header, beginning at byte 10h in conﬁguration space.

ISP1561_2

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HS USB PCI Host Controller

8.2.1.10 BIST register (address: 0Fh)

This register is used for control and status of Built In Self Test (BIST). Devices that do not

support BIST must always return logic 0, that is, treat it as a reserved register. A device

whose BIST is invoked must not prevent normal operation of the PCI bus. The BIST

register is not used in the ISP1561. Therefore, the logic value returned is always zero.

8.2.1.11 Base Address registers

Power-up software must build a consistent address map before booting the machine to an

operating system. This means it must determine how much memory is in the system, and

how much address space the I/O controllers in the system require. After determining this

information, power-up software can map the I/O controllers into reasonable locations and

proceed with system boot. To do this mapping in a device-independent manner, base

registers for this mapping are placed in the predeﬁned header portion of conﬁguration

space.

Bit 0 in all Base Address registers is read-only and used to determine whether the register

maps into memory or I/O space. Base Address registers that map to memory space must

return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in

bit 0.

The bit description of the BAR0 register is given in Table 17.

Base Address register 0 (BAR0) — (address: 10h)

Table 17. BAR0 register: bit description

Bit

Symbol

Access

Value

Description

31 to 0 BAR0[31:0]

R/W

0000 0000h Base Address to Memory-Mapped Host Controller Register

Space: The memory size required by OHCI and EHCI are 4 kB and

256 bytes, respectively. Therefore, BAR0[31:12] is assigned to the two

OHCI ports, and BAR0[31:8] is assigned to the EHCI port.

Base Address register 1, 2, 3, 4, 5 (BAR1, 2, 3, 4, 5) — (address: 14h, 18h, 1Ch, 20h

and 24h): The BAR1, 2, 3, 4, 5 register spaces are not used in the ISP1561.

8.2.1.12 CardBus CIS Pointer register (address: 28h)

This 4-byte register is used by devices that want to share silicon between CardBus and

PCI. The CardBus CIS Pointer register is used to point to the Card Information Structure

(CIS) for the CardBus card. This register is not implemented in the ISP1561.

8.2.1.13 Subsystem Vendor ID register (address: 2Ch)

The Subsystem Vendor ID register is used to uniquely identify the expansion board or

subsystem where the PCI device resides. This register allows expansion board vendors to

distinguish their boards, even though the boards may have the same vendor ID and device

ID.

Subsystem vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit

description of the Subsystem Vendor ID register is given in Table 18.

Table 18. Subsystem Vendor ID register: bit description

Bit

Symbol

Access

Value

Description

15 to 0 SVID[15:0]

R

1131h

Subsystem Vendor ID: 1131h is the subsystem vendor ID assigned to NXP

Semiconductors.

ISP1561_2

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HS USB PCI Host Controller

8.2.1.14 Subsystem ID register (address: 2Eh)

Subsystem ID values are vendor-speciﬁc. The bit description of the Subsystem ID register

is given in Table 19.

Table 19. Subsystem ID register: bit description

Bit

Symbol

Access Value

X^[1]

Description

15 to 0 SID[15:0]

R

Subsystem ID: For the ISP1561, NXP Semiconductors has deﬁned OHCI

functions as 1561h, and the EHCI function as 1562h.

[1] X is 1561h for OHCI1 and OHCI2; X is 1562h for EHCI.

8.2.1.15 Expansion ROM Base Address register (address: 30h)

Some PCI devices, especially those intended for use on expansion boards in the PC

architecture, require local EPROMs for expansion ROM. This 4-byte register at offset 30h

in a type 00h predeﬁned header is deﬁned to handle the base address and size

information for this expansion ROM. The ISP1561 does not support expansion EPROM.

8.2.1.16 Capabilities Pointer register (address: 34h)

The Capabilities Pointer register is used to point to a linked list of new capabilities

implemented by the device. This register is only valid if the CL bit in the Status register is

set. If implemented, bit 1 and bit 0 are reserved and should be set to 00b. Software must

mask these bits off before using this register as a pointer in conﬁguration space to the ﬁrst

entry of a linked list of new capabilities. The bit description of the register is given in

Table 20.

Table 20. Capabilities Pointer register: bit description

Bit

Symbol

Access Value

DCh

Description

7 to 0

CP[7:0]

R

Capabilities Pointer: EHCI manages power efﬁciently using this register. This

power management register is allocated at offset DCh. Only one Host

Controller is needed to manage power in the ISP1561.

8.2.1.17 Interrupt Line register (address: 3Ch)

The Interrupt Line register is a 1-byte read/write register used to communicate interrupt

line routing information. This register must be implemented by any device or device

function that uses an interrupt pin. The interrupt allocation is done by the BIOS. The

POST software needs to write the routing information into this register because it

initializes and conﬁgures the system. The bit description of the Interrupt Line register is

given in Table 21.

The value in this register speciﬁes which input of the system interrupt controller(s) the

interrupt pin of the device is connected. The device itself does not use this value, rather it

is used by device drivers and operating systems to determine priority and vector

information. Values in this register are system architecture speciﬁc.

Table 21. Interrupt Line register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

IL[7:0]

R/W

00h

Interrupt Line: Indicates which IRQ is used to report interrupt from the

ISP1561.

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HS USB PCI Host Controller

8.2.1.18 Interrupt Pin register (address: 3Dh)

This 1-byte register is use to specify which interrupt pin the device or device function uses.

The bit description is given in Table 22.

Devices or functions that do not use an interrupt pin must put a logic 0 in this register.

Table 22. Interrupt Pin register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

IP[7:0]

R/W

01h

Interrupt Pin: INTA# is the default interrupt pin used by the ISP1561.

8.2.1.19 MIN_GNT and MAX_LAT registers (address: 3Eh and 3Fh)

The Minimum Grant (MIN_GNT) and Maximum Latency (MAX_LAT) registers are used to

specify the desired settings of the device for latency timer values. For both registers, the

value speciﬁes a period of time in units of 250 ns. Values of 0 indicates that the device has

no major requirements for the settings of latency timers.The MIN_GNT register bit

description is given in Table 23.

Table 23. MIN_GNT register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

MIN_GNT[7:0]

R

X^[1]

MIN_GNT: It is used to specify how long a burst period the device needs,

assuming a clock rate of 33 MHz.

[1] X is 01h for OHCI1 and OHCI2; X is 02h for EHCI.

The MAX_LAT register bit description is given in Table 24.

Table 24. MAX_LAT register: but description

Bit

Symbol

Access

Value

Description

7 to 0

MAX_LAT[7:0]

R

X^[1]

MAX_LAT: It is used to specify how often the device needs to gain

access to the PCI bus.

[1] X is 2Ah for OHCI1 and OHCI2; X is 10h for EHCI.

8.2.1.20 TRDY Timeout register (R/W: 40h)

The default and recommended value is 00h, TRDY time-out disabled. This value can,

however, be modiﬁed. It is an implementation-speciﬁc register, and not a standard PCI

conﬁguration register.

The TRDY timer is 13 bits: the lower 5 bits are ﬁxed as logic 0 and the upper 8 bits are

determined by the TRDY time-out register value. The time-out is calculated by multiplying

the 13-bit timer with the PCICLK cycle time.

This register determines the delay for the UE bit setting if a target does not assert its

TDRY signal.

8.2.1.21 Retry Timeout register (R/W: 41h)

The default value is 80h. This value can, however, be modiﬁed. Programming this register

as 00h means that retry time-out is disabled. This is an implementation-speciﬁc register,

and not a standard PCI conﬁguration register.

The time-out is determined by multiplying the register value with the PCICLK cycle time.

This register determines the delay to set the UE bit if a RETRY time-out occurs.

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

8.2.2 Enhanced Host Controller-speciﬁc PCI registers

In addition to the PCI conﬁguration header registers, EHCI needs some additional PCI

conﬁguration space registers to indicate the serial bus release number, downstream port

wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF).

The EHCI-speciﬁc PCI registers are given in Table 25.

Table 25. EHCI-speciﬁc PCI registers

Offset

60h

Register

Serial Bus Release Number (SBRN)

Frame Length Adjustment (FLADJ)

Port Wake Capability (PORTWAKECAP)

61h

62h to 63h

8.2.2.1 SBRN register (address: 60h)

The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit

description is given in Table 26. This register contains the release number of the USB

speciﬁcation with which this USB Host Controller module is compliant.

Table 26. SBRN register: bit description

Bit Symbol Access Value Description

7 to 0 SBRN[7:0] R

20h

Serial Bus Speciﬁcation Release Number: This register value is to identify Ref. 8

“Universal Serial Bus Speciﬁcation”. All other combinations are reserved.

8.2.2.2 FLADJ register (address: 61h)

This feature is used to adjust any offset from the clock source that generates the clock that

drives the SOF counter. When a new value is written to these six bits, the length of the

frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is

given in Table 27.

Table 27. FLADJ register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

FLADJ[5:0]

0

-

0

-

1

0

R/W

Table 28. FLADJ register: bit description

Bit

Symbol

Description

7 to 6

5 to 0

-

reserved

FLADJ[5:0] Frame Length Timing Value: Each decimal value change to this register

corresponds to 16 high-speed bit times. The SOF cycle time, number of

SOF counter clock periods to generate a SOF micro frame length, is equal

to 59488 + value in this ﬁeld. The default value is decimal 32 (20h), which

gives a SOF cycle time of 60000. See Table 29.

Table 29. FLADJ value as a function of SOF cycle time

FLADJ value

0 (00h)

SOF cycle time (480 MHz)

59488

59504

59520

1 (01h)

2 (02h)

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Table 29. FLADJ value as a function of SOF cycle time …continued

FLADJ value

:

SOF cycle time (480 MHz)

:

31(1Fh)

32 (20h)

:

59984

60000

:

62 (3Eh)

63 (3Fh)

60480

60496

8.2.2.3 PORTWAKECAP register (address: 62h)

The PORTWAKECAP register is a 2-byte register, and the bit description is given in

Table 30. This register is used to establish a policy about which ports are for wake events.

Bit positions 1 to 15 in the mask correspond to a physical port implemented on the current

EHCI controller. Logic 1 in a bit position indicates that a device connected below the port

can be enabled as a wake-up device and the port may be enabled for disconnect or

connect, or overcurrent events as wake-up events. This is an information only mask

register. The bits in this register do not affect the actual operation of the EHCI Host

Controller. The system-speciﬁc policy can be established by BIOS initializing this register

to a system-speciﬁc value. The system software uses the information in this register when

enabling devices and ports for remote wake-up.

Table 30. PORTWAKECAP register: bit description

Bit

Symbol

Access

Value

Description

15 to 0 PORTWAKE R/W

CAP[15:0]

001Fh

Port Wake Up Capability Mask: EHCI does not implement this feature.

8.2.3 Power management registers

Table 31. Power management registers

Offset

Register

value read from address 34h + 0h

value read from address 34h + 1h

value read from address 34h + 2h

value read from address 34h + 4h

value read from address 34h + 6h

Capability Identiﬁer (CAP_ID)

Next Item Pointer (NEXT_ITEM_PTR)

Power Management Capabilities (PMC)

Power Management Control/Status (PMCSR)

Power Management Control/Status PCI-to-PCI Bridge

Support Extensions (PMCSR_BSE)

value read from address 34h + 7h

Data

8.2.3.1 CAP_ID register (address: value read from address 34h + 0h)

The Capability Identiﬁer (CAP_ID) register when read by the system software as 01h

indicates that the data structure currently being pointed to is the PCI power management

data structure. Each function of a PCI device may have only one item in its capability list

with CAP_ID set to 01h. The bit description of the register is given in Table 32.

Table 32. CAP_ID register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

CAP_ID[7:0]

R

01h

ID: This ﬁeld when 01h identiﬁes the linked list item as being PCI power

management registers.

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8.2.3.2 NEXT_ITEM_PTR register (address: value read from address 34h + 1h)

The Next Item Pointer (NEXT_ITEM_PTR) register (see Table 33) describes the location

of the next item in the function’s capability list. The value given is an offset into the

function’s PCI conﬁguration space. If the function does not implement any other

capabilities deﬁned by the PCI-SIG for inclusion in the capabilities list, or if power

management is the last item in the list, then this register must be set to 00h.

Table 33. NEXT_ITEM_PTR register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

NEXT_ITEM_

PTR[7:0]

R

00h

Next Item Pointer: This ﬁeld provides an offset into the function’s

PCI conﬁguration space pointing to the location of the next item in the

function’s capability list. If there are no additional items in the

capabilities list, this register is set to 00h.

8.2.3.3 PMC register (address: value read from address 34h + 2h)

The Power Management Capabilities (PMC) register is a 2-byte register, and the bit

allocation is given in Table 34. This read-only register provides information on the

capabilities of the function related to power management.

Table 34. PMC register: bit allocation

Bit

15

14

13

12

11

10

D2_S

X^[2]

R

9

8

Symbol

Reset

Access

Bit

PME_S[4:0]

D1_S

AUX_C[2:0]

X^[1]

R

1

R

6

X^[2]

1

X^[2]

R

1

X^[2]

R

7

5

4

3

2

1

0

Symbol

Reset

Access

AUX_C[2:0]

DSI

0

reserved

PMI

0

VER[2:0]

0

-

0

1

0

R

[1] X is 0 for OHCI1, OHCI2 and EHCI S1; X is 1 for EHCI S3.

[2] X is 0 for OHCI1 and OHCI2; X is 1 for EHCI.

Table 35. PMC register: bit description

Bit

Symbol

Description

15 to 11

PME_S[4:0]

PME Support: This 5-bit ﬁeld indicates the power states in which

the function may assert PME#. Logic 0 for any bit indicates that

the function is not capable of asserting the PME# signal while in

that power state.

PME_S[0] — PME# can be asserted from D0

PME_S[1] — PME# can be asserted from D1

PME_S[2] — PME# can be asserted from D2

PME_S[3] — PME# can be asserted from D3_hot

PME_S[4] — PME# can be asserted from D3_cold

10

9

D2_S

D1_S

D2 Support: If this bit is logic 1, this function supports the D2

power management state. Functions that do not support D2 must

always return a value of logic 0 for this bit.

D1 Support: If this bit is logic 1, this function supports the D1

power management state. Functions that do not support D1 must

always return a value of logic 0 for this bit.

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Table 35. PMC register: bit description …continued

Bit

Symbol

Description

8 to 6

AUX_C[2:0]

Auxiliary Current: This three-bit ﬁeld reports the V_AUXauxiliary

current requirements for the PCI function.

If the Data register is implemented by this function:

• A read from this ﬁeld needs to return a value of 000b.

• The Data register takes precedence over this ﬁeld for V_AUX

current requirement reporting.

If the PME# generation from D3_coldis not supported by the

function (PMC[15] = 0), this ﬁeld must return a value of 000b when

read.

For functions that support PME# from D3_coldand do not implement

the Data register, bit assignments correspond to the maximum

current required for V_AUXare:

111b — 375 mA

110b — 320 mA

101b — 270 mA

100b — 220 mA

011b — 160 mA

010b — 100 mA

001b — 55 mA

000b — 0 (self-powered)

5

DSI

Device Speciﬁc Initialization: This bit indicates whether special

initialization of this function is required, beyond the standard PCI

conﬁguration header, before the generic class device driver can

use it.

Remark: This bit is not used by some operating systems. For

example, Microsoft Windows and Windows NT do not use this bit

to determine whether to use D3. Instead, it is determined using

the capabilities of the driver.

Logic 1 indicates that the function requires a device-speciﬁc

initialization sequence, following transition to D0 uninitialized state.

4

3

-

reserved

PMI

PME Clock: When this bit is logic 1, it indicates that the function

relies on the presence of the PCI clock for the PME# operation.

When this bit is logic 0, it indicates that no PCI clock is required for

the function to generate PME#. Functions that do not support the

PME# generation in any state must return logic 0 for this ﬁeld.

2 to 0

VER[2:0]

Version: A value of 010b indicates that this function complies with

Ref. 5 “PCI Bus Power Management Interface Speciﬁcation”.

The logic level of the AMB4 pin at power-on determines the default value of PMC

registers. If this pin is connected to V_DDas a pull-up, then the ISP1561 supports D3_cold(in

the case of notebook design). If this pin is left open or is pulled down, then the ISP1561

does not support D3_cold(in the case of PCI add-on card design).

8.2.3.4 PMCSR register (address: value read from address 34h + 4h)

The Power Management Control/Status (PMCSR) register is a 2-byte register used to

manage the power management state of the PCI function, as well as to allow and monitor

Power Management Events (PMEs). The bit allocation of the register is given in Table 36.

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Table 36. PMCSR register: bit allocation

Bit

15

PMES

X^[1]

14

13

12

11

10

9

8

PMEE

X^[1]

Symbol

Reset

Access

Bit

DS[1:0]

D_S[3:0]

0

R

6

0

R

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

R/W

7

R/W

0

Symbol

Reset

Access

reserved

PS[1:0]

0

-

0

-

0

-

0

-

0

-

0

-

0

R/W

[1] Sticky bit, if the function supports PME# from D3_cold, then X is indeterminate at the time of initial operating system boot; X is 0 if the

function does not support PME# from D3_cold

.

Table 37. PMCSR register: bit description

Bit

Symbol

Description

15

PMES

PME Status: This bit is set when the function normally asserts the

PME# signal independent of the state of the PME_EN bit. Writing

logic 1 to this bit clears it and causes the function to stop asserting

PME#, if enabled. Writing logic 0 has no effect. This bit defaults to

logic 0, if the function does not support the PME# generation from

D3_cold. If the function supports the PME# generation from D3_cold, then

this bit is sticky and must be explicitly cleared by the operating system

each time the operating system is initially loaded.

14 to 13

DS[1:0]

Data Scale: This two-bit read-only ﬁeld indicates the scaling factor

when interpreting the value of the Data register. The value and

meaning of this ﬁeld vary, depending on which data value is selected by

the D_S ﬁeld. This ﬁeld is a required component of the Data register

(offset 7) and must be implemented, if the Data register is

implemented. If the Data register is not implemented, this ﬁeld must

return 00b when PMCSR is read.

12 to 9

D_S[3:0]

PMEE

Data Select: This four-bit ﬁeld selects the data that is reported through

the Data register and the D_S ﬁeld. This ﬁeld is a required component

of the Data register (offset 7) and must be implemented if the Data

register is implemented. If the Data register is not implemented, this

ﬁeld must return 00b when PMCSR is read.

8

PME Enabled: Logic 1 allows the function to assert PME#. When it is

logic 0, PME# assertion is disabled. This bit defaults to logic 0 if the

function does not support the PME# generation from D3_cold. If the

function supports PME# from D3_cold, then this bit is sticky and must

explicitly be cleared by the operating system each time the operating

system is initially loaded. Functions that do not support the PME#

generation from any D-state (that is, PMC[15:11] = 0 0000b), may

hardwire this bit to be read-only always returning logic 0 when read by

system software.

7 to 2

-

reserved

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Table 37. PMCSR register: bit description …continued

Bit

Symbol

Description

1 to 0

PS[1:0]

Power State: This two-bit ﬁeld is used to determine the current power

state of the EHCI function and to set the function into a new power

state. The deﬁnition of the ﬁeld values is given as:

00b — for D0

01b — for D1

10b — for D2

11b — for D3_hot

If the software attempts to write an unsupported, optional state to this

ﬁeld, the write operation must complete normally on the bus; however,

the data is discarded and no status change occurs.

8.2.3.5 PMCSR_BSE register (address: value read from address 34h + 6h)

The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI

bridge-speciﬁc functionality and is required for all PCI-to-PCI bridges. The bit allocation of

this register is given in Table 38.

Table 38. PMCSR_BSE register: bit allocation

Bit

7

BPCC_EN

R

6

B2_B3#

R

5

4

3

2

1

0

Symbol

Reset

Access

reserved

R

0

R

0

R

0

R

0

R

0

R

0

0^[1]

[1] Internally hardwired.

Table 39. PMCSR_BSE register: bit description

Bit

Symbol

Description

7

BPCC_EN Bus Power or Clock Control Enable

1 — Indicates that the bus power or clock control mechanism as deﬁned in

Table 40 is enabled.

0 — Indicates that the bus power or control policies as deﬁned in Table 40

are disabled.

When the bus power or clock control mechanism is disabled, the bridge’s

PMCSR PS (Power State) ﬁeld cannot be used by the system software to

control the power or clock of the bridge’s secondary bus.

6

B2_B3#

B2 or B3 support for D3_hot: The state of this bit determines the action that

is to occur as a direct result of programming the function to D3_hot

.

1 — Indicates that when the bridge function is programmed to D3_hot, its

secondary bus’s PCI clock will be stopped (B2).

0 — Indicates that when the bridge function is programmed to D3_hot, its

secondary bus will have its power removed (B3).

This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.

reserved

5 to 0

-

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Table 40. PCI bus power and clock control

Originating device’s Secondary bus

Resultant actions by bridge (either direct or

indirect)

bridge PM state

PM state

D0

B0

none

D1

B1

none

D2

B2

clock stopped on secondary bus

D3_hot

B2, B3

clock stopped and V_CCremoved from secondary bus

(B3 only); for deﬁnition of B2_B3#, see Table 39

D3_cold

B3

none

8.2.3.6 Data register (address: value read from address 34h + 7h)

The Data register is an optional, 1-byte register that provides a mechanism for the

function to report state dependent operating data, such as power consumed or heat

dissipated. Table 41 shows the bit description of the register.

Table 41. Data register: bit description

Bit

Symbol

Access

Value

Description

7 to 0

DATA[7:0]

R

00h

DATA: This register is used to report the state dependent data requested by

the D_S (Data Select) ﬁeld. The value of this register is scaled by the value

reported by the DS (Data Scale) ﬁeld.

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9. I²C-bus interface

A simple I²C-bus interface is provided in the ISP1561 to read customized vendor ID,

product ID and some other conﬁguration bits from an external EEPROM.

The I²C-bus interface is for bidirectional communication between ICs using two serial bus

wires: SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must

be connected to the positive supply voltage through pull-up resistors.

9.1 Protocol

The I²C-bus protocol deﬁnes the following conditions:

• Bus free: both SDA and SCL are HIGH

• START: a HIGH-to-LOW transition on SDA, while SCL is HIGH

• STOP: a LOW-to-HIGH transition on SDA, while SCL is HIGH

• Data valid: after a START condition, data on SDA is stable during the HIGH period of

SCL; data on SDA may only change while SCL is LOW

Each device on the I²C-bus has a unique slave address, which the master uses to select a

device for access.

The master starts a data transfer using a START condition and ends it by generating a

STOP condition. Transfers can only be initiated when the bus is free. The receiver must

acknowledge each byte by means of a LOW level on SDA during the ninth clock pulse on

SCL.

For detailed information, refer to Ref. 7 “The I²C-bus Speciﬁcation”.

9.2 Hardware connections

The ISP1561 can be connected to an external EEPROM through the I²C-bus interface.

The hardware connections are shown in Figure 3.

DV

AUX

DV

AUX

R

P

R

P

SCL

SDA

SCL

SDA

A0

A1

A2

2

I C-bus

ISP1561

USB HOST

24C01

EEPROM

or

equivalent

004aaa163

Fig 3. EEPROM connection diagram

The slave address that the ISP1561 uses to access the EEPROM is 101 0000b. Page

mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must

be connected to ground (logic 0).

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9.3 Information loading from EEPROM

Figure 4 shows the content of the EEPROM memory. If the EEPROM is not present, the

default values of Device ID (DID), Vendor ID (VID), subsystem VID and subsystem DID

assigned to NXP Semiconductors by PCI-SIG will be loaded. See Table 3 for these default

value. For instructions on programming the EEPROM, refer to application note Ref. 1

“Designing a Hi-Speed USB Host PCI Adapter Using the ISP1561” and user manual Ref.

3 “ISP1561 Evaluation Board User’s Guide”.

address

0

1

2

3

4

5

6

7

subsystem vendor ID (L)

subsystem vendor ID (H)

subsystem device ID (L) - OHCI

subsystem device ID (H) - OHCI

subsystem device ID (L) - EHCI

subsystem device ID (H) - EHCI

reserved - FFh

15h - loads subsystem vendor ID, device ID

signature

1Ah - loads default values defined by NXP Semiconductors

004aaa930

L = LOW; H = HIGH.

Fig 4. Information loading from EEPROM

10. Power management

10.1 PCI bus power states

The PCI bus can be characterized by one of the four power management states: B0, B1,

B2 and B3.

B0 state (PCI clock = 33 MHz, PCI bus power = on) — This corresponds to the bus

being fully operational.

B1 state (PCI clock = intermittent clock operation mode, PCI bus power = on) —

When a PCI bus is in B1, V_DDis still applied to all devices on the bus. No bus transactions,

however, are allowed to take place on the bus. The B1 state indicates a perpetual idle

state on the PCI bus.

B2 state (PCI clock = stop, PCI bus power = on) — V_DDis still applied on the bus, but

the clock is stopped and held in the LOW state.

B3 state (PCI clock = stop, PCI bus power = off) — V_DDis removed from all devices on

the PCI bus segment.

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10.2 USB bus states

Reset state — When the USB bus is in the reset state, the USB system is stopped.

Operational state — When the USB bus is in the active state, the USB system is

operating normally.

Suspend state — When the USB bus is in the suspend state, the USB system is

stopped.

Resume state — When the USB bus is in the resume state, the USB system is operating

normally.

11. USB Host Controller registers

Each Host Controller contains a set of on-chip operational registers that are mapped into

uncached memory of the system addressable space. This memory space must begin on a

DWORD (32-bit) boundary. The size of the allocated space is deﬁned by the initial value in

the BAR0 register. HCDs must interact with these registers to implement USB and legacy

support functionality.

After the PCI enumeration driver ﬁnishes the PCI device conﬁguration, the new base

address of these memory-mapped operational registers is deﬁned in BAR0. The HCD can

access these registers by using the address of base address value + offset. Table 42

contains a list of Host Controller registers.

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For the OHCI Host Controller, these registers are divided into two types: one set of

operational registers for the USB operation and one set of legacy support registers for the

legacy keyboard and mouse operation.

For the enhanced Host Controller, there are two types of registers: one set of read-only

capability registers and one set of read/write operational registers.

11.1 OHCI USB Host Controller operational registers

OHCI HCDs must communicate with these registers to implement USB data transfers.

Based on their functions, these registers are classiﬁed into four partitions:

• Control and status

• Memory pointer

• Frame counter

• Root hub

11.1.1 HcRevision register (address: content of the base address register + 00h)

Table 43. HcRevision register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

L

0

-

0

-

0

-

0

-

0

-

0

-

0

-

X^[1]

R

0

7

6

5

4

3

2

1

Symbol

Reset

Access

REV[7:0]

0

1

0

R

[1] X is 1 for OHCI1 (2P) and OHCI1 (1P); X is 0 for OHCI2 (2P) and OHCI2 (1P).

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Table 44. HcRevision register: bit description

Bit

Symbol

Description

31 to 9

8

-

reserved

L

Legacy:

0 — Does not support legacy devices

1 — Supports legacy keyboard and mouse

7 to 0

REV[7:0]

Revision: This read-only ﬁeld contains the BCD representation of the

version of the HCI speciﬁcation that is implemented by this Host

Controller. For example, a value of 11h corresponds to version 1.1. All

of the Host Controller implementations that are compliant with this

speciﬁcation must have a value of 10h.

11.1.2 HcControl register (address: content of the base address register + 04h)

The HcControl register deﬁnes the operating modes for the Host Controller. All the ﬁelds

in this register, except HCFS and RWC, are modiﬁed only by the HCD. The bit allocation is

given in Table 45.

Table 45. HcControl register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

9

15

14

13

12

11

10

8

Symbol

Reset

Access

Bit

reserved

RWE

0

RWC

0

IR

0

-

0

-

0

-

0

-

0

-

R/W

2

R/W

1

R/W

0

7

6

5

4

3

Symbol

Reset

Access

HCFS[1:0]

BLE

0

CLE

0

IE

0

PLE

0

CBSR[1:0]

0

R/W

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Table 46. HcControl register: bit description

Bit

Symbol

-

Description

31 to 11

10

reserved

RWE

Remote Wake-up Enable: This bit is used by the HCD to enable or

disable the remote wake-up feature on detecting upstream resume

signaling. When this bit and the RD bit in HcInterruptStatus are set, a

remote wake-up is signaled to the host system. Setting this bit has no

impact on the generation of hardware interrupt.

9

RWC

Remote Wake-up Connected: This bit indicates whether the Host

Controller supports remote wake-up signaling. If remote wake-up is

supported and used by the system, it is the responsibility of the system

ﬁrmware to set this bit during POST. The Host Controller clears the bit on

a hardware reset but does not alter it on a software reset. Remote

wake-up signaling of the host system is host-bus-speciﬁc and is not

described in this speciﬁcation.

8

IR

Interrupt Routing: This bit determines the routing of interrupts

generated by events registered in HcInterruptStatus. If clear, all

interrupts are routed to the normal host bus interrupt mechanism. If set,

interrupts are routed to the system management interrupt. The HCD

clears this bit on a hardware reset, but it does not alter this bit on a

software reset. The HCD uses this bit as a tag to indicate the ownership

of the Host Controller.

7 to 6

HCFS[1:0] Host Controller Functional State for USB:

00b — USBRESET

01b — USBRESUME

10b — USBOPERATIONAL

11b — USBSUSPEND

A transition to USBOPERATIONAL from another state causes SOF

generation to begin 1 ms later. The HCD may determine whether the

Host Controller has begun sending SOFs by reading the SF ﬁeld of

HcInterruptStatus.

This ﬁeld may be changed by the Host Controller only when in the

USBSUSPEND state. The Host Controller may move from the

USBSUSPEND state to the USBRESUME state after detecting the

resume signaling from a downstream port.

The Host Controller enters USBSUSPEND after a software reset; it

enters USBRESET after a hardware reset. The latter also resets the root

hub and asserts subsequent reset signaling to downstream ports.

5

BLE

Bulk List Enable: This bit is set to enable the processing of the bulk list

in the next frame. If cleared by the HCD, processing of the bulk list does

not occur after the next SOF. The Host Controller checks this bit

whenever it wants to process the list. When disabled, the HCD may

modify the list. If HcBulkCurrentED is pointing to an Endpoint Descriptor

(ED) to be removed, the HCD must advance the pointer by updating

HcBulkCurrentED before re-enabling processing of the list.

ISP1561_2

Product data sheet

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 46. HcControl register: bit description …continued

Bit

Symbol

Description

4

CLE

Control List Enable: This bit is set to enable the processing of the

control list in the next frame. If cleared by the HCD, processing of the

control list does not occur after the next SOF. The Host Controller must

check this bit whenever it wants to process the list. When disabled, the

HCD may modify the list. If HcControlCurrentED is pointing to an ED to

be removed, the HCD must advance the pointer by updating

HcControlCurrentED before re-enabling processing of the list.

3

IE

Isochronous Enable: This bit is used by the HCD to enable or disable

processing of isochronous EDs. While processing the periodic list in a

frame, the Host Controller checks the status of this bit when it ﬁnds an

isochronous ED (that is, the Format bit of ED is logic 1; for details, refer

to Ref. 4 “Open Host Controller Interface Speciﬁcation for USB”). If set

(enabled), the Host Controller continues processing EDs. If cleared

(disabled), the Host Controller halts processing of the periodic list, which

now contains only isochronous EDs, and begins processing the bulk or

control lists. Setting this bit is guaranteed to take effect in the next frame

and not the current frame.

2

PLE

Periodic List Enable: This bit is set to enable the processing of the

periodic list in the next frame. If cleared by the HCD, processing of the

periodic list does not occur after the next SOF. The Host Controller must

check this bit before it starts processing the list.

1 to 0

CBSR[1:0] Control Bulk Service Ratio: This speciﬁes the service ratio of control

EDs over bulk EDs. Before processing any of the nonperiodic lists, the

Host Controller must compare the ratio speciﬁed with its internal count

on how many nonempty control EDs are processed, in determining

whether to continue serving another control ED or switching to bulk EDs.

The internal count must be retained when crossing the frame boundary.

After a reset, the HCD is responsible for restoring this value.

00b — 1 : 1

01b — 2 : 1

10b — 3 : 1

11b — 4 : 1

11.1.3 HcCommandStatus register (address: content of the base address

register + 08h)

The HcCommandStatus register is used by the Host Controller to receive commands

issued by the HCD. It also reﬂects the current status of the Host Controller. To the HCD, it

appears as a “write to set” register. The Host Controller must ensure that bits written as

logic 1 become set in the register while bits written as logic 0 remain unchanged in the

register. The HCD may issue multiple distinct commands to the Host Controller without

concern for corrupting previously issued commands. The HCD has normal read access to

all bits.

The SOC[1:0] (Scheduling Overrun Count) ﬁeld indicates the number of frames with which

the Host Controller has detected the scheduling overrun error. This occurs when the

periodic list does not complete before EOF. When a scheduling overrun error is detected,

the Host Controller increments the counter and sets the SO (Scheduling Overrun) ﬁeld in

the HcInterruptStatus register. Table 47 shows the bit allocation of the HcCommandStatus

register.

ISP1561_2

Product data sheet

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38 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 47. HcCommandStatus register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

SOC[1:0]

0

-

0

-

0

-

0

-

0

-

0

-

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

OCR

0

BLF

0

CLF

0

HCR

0

-

0

-

0

-

0

-

R/W

Table 48. HcCommandStatus register: bit description

Bit

Symbol

Description

31 to 18

17 to 16

-

reserved

SOC[1:0] Scheduling Overrun Count: The bit is incremented on each scheduling

overrun error. It is initialized to 00b and wraps around at 11b. It must be

incremented when a scheduling overrun is detected, even if the SO bit in

HcInterruptStatus is already set. This is used by the HCD to monitor any

persistent scheduling problems.

15 to 4

3

-

reserved

OCR

Ownership Change Request: This bit is set by an OS HCD to request a

change of control of the Host Controller. When set, the Host Controller

must set the OC (Ownership Change) ﬁeld in HcInterruptStatus. After the

changeover, this bit is cleared and remains so until the next request from

the OS HCD.

2

BLF

Bulk List Filled: This bit is used to indicate whether there are any

Transfer Descriptors (TDs) on the bulk list. It is set by the HCD whenever

it adds a TD to an ED in the bulk list. When the Host Controller begins to

process the head of the bulk list, it checks Bulk-Filled (BF). If BLF (Bulk

List Filled) is logic 0, the Host Controller does not need to process the

bulk list. If BLF is logic 1, the Host Controller must start processing the

bulk list and set BF to logic 0. If the Host Controller ﬁnds a TD on the list,

then the Host Controller must set BLF to logic 1, causing the bulk list

processing to continue. If no TD is found on the bulk list, and if the HCD

does not set BLF, then BLF is still logic 0 when the Host Controller

completes processing the bulk list and the bulk list processing stops.

ISP1561_2

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39 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 48. HcCommandStatus register: bit description …continued

Bit

Symbol

Description

1

CLF

Control List Filled: This bit is used to indicate whether there are any TDs

on the control list. It is set by the HCD whenever it adds a TD to an ED in

the control list.

When the Host Controller begins to process the head of the control list, it

checks CLF. If CLF is logic 0, the Host Controller does not need to

process the control list. If Control-Filled (CF) is logic 1, the Host Controller

must start processing the control list and set CLF to logic 0. If the Host

Controller ﬁnds a TD on the list, then the Host Controller must set CLF to

logic 1, causing the control list processing to continue. If no TD is found

on the control list, and if the HCD does not set CLF, then CLF is still

logic 0 when the Host Controller completes processing the control list and

the control list processing stops.

0

HCR

Host Controller Reset: This bit is set by the HCD to initiate a software

reset of the Host Controller. Regardless of the functional state of the Host

Controller, it moves to the USBSUSPEND state in which most of the

operational registers are reset, except those stated otherwise; for

example, the IR (Interrupt Routing) ﬁeld of HcControl, and no host bus

accesses are allowed. This bit is cleared by the Host Controller on

completing the reset operation. The reset operation must be completed

within 10 µs. This bit, when set, must not cause a reset to the root hub

and no subsequent reset signaling must be asserted to its downstream

ports.

11.1.4 HcInterruptStatus register (address: content of the base address register +

0Ch)

This is a 4-byte register that provides the status of the events that cause hardware

interrupts. The bit allocation of the register is given in Table 49. When an event occurs, the

Host Controller sets the corresponding bit in this register. When a bit becomes set, a

hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register

(see Table 51) and the MIE (Master Interrupt Enable) bit is set. The HCD may clear

speciﬁc bits in this register by writing logic 1 to the bit positions to be cleared. The HCD

may not set any of these bits. The Host Controller does not clear the bit.

Table 49. HcInterruptStatus register: bit allocation

Bit

31

30

OC

0

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

R/W

22

23

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

ISP1561_2

Product data sheet

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40 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Bit

7

6

RHSC

0

5

4

UE

0

3

RD

0

2

SF

0

1

WDH

0

SO

0

Symbol

Reset

Access

reserved

FNO

0

-

R/W

Table 50. HcInterruptStatus register: bit description

Bit

31

30

Symbol

Description

-

reserved

OC

Ownership Change: This bit is set by the Host Controller when HCD

sets the OCR (Ownership Change Request) ﬁeld in

HcCommandStatus. This event, when unmasked, will always

immediately generate a System Management Interrupt (SMI). This bit

is forced to logic 0 when the SMI# pin is not implemented.

29 to 7

6

-

reserved

RHSC

Root Hub Status Change: This bit is set when the content of

HcRhStatus or the content of any of

HcRhPortStatus[NumberofDownstreamPort] has changed.

5

4

FNO

UE

Frame Number Overﬂow: This bit is set when the Most Signiﬁcant Bit

(MSB) of HcFmNumber (bit 15) changes value, or after the

HccaFrameNumber is updated.

Unrecoverable Error: This bit is set when the Host Controller detects

a system error not related to USB. The Host Controller must not

proceed with any processing nor signaling before the system error is

corrected. The HCD clears this bit after the Host Controller is reset.

3

RD

Resume Detected: This bit is set when the Host Controller detects

that a device on the USB is asserting resume signaling. It is the

transition from no resume signaling to resume signaling causing this

bit to be set. This bit is not set when the HCD sets the USBRESUME

state.

2

1

SF

Start-of-Frame: At the start of each frame, this bit is set by the Host

Controller and an SOF token is generated at the same time.

WDH

Write-back Done Head: This bit is immediately set after the Host

Controller has written HcDoneHead to HccaDoneHead. Further,

updates of HccaDoneHead occur only after this bit is cleared. The

HCD must only clear this bit after it has saved the content of

HccaDoneHead.

0

SO

Scheduling Overrun: This bit is set when USB schedules for current

frame overruns and after the update of HccaFrameNumber. A

scheduling overrun causes the SOC (Scheduling Overrun Count) of

HcCommandStatus to be incremented.

11.1.5 HcInterruptEnable register (address: content of the base address register +

10h)

Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt

bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control

which events generate a hardware interrupt. If the following conditions occur:

• A bit is set in the HcInterruptStatus register.

• The corresponding bit in the HcInterruptEnable register is set.

• The MIE (Master Interrupt Enable) bit is set.

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Then, a hardware interrupt is requested on the host bus.

Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to

a bit in this register leaves the corresponding bit unchanged. On a read, the current value

of this register is returned.

The bit allocation is given in Table 51.

Table 51. HcInterruptEnable register: bit allocation

Bit

31

MIE

0

30

OC

0

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

R/W

23

R/W

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

6

7

5

4

3

2

1

0

Symbol

Reset

Access

reserved

RHSC

0

FNO

0

UE

0

RD

0

SF

0

WDH

0

SO

0

-

R/W

Table 52. HcInterruptEnable register: bit description

Bit

Symbol

Description

31

MIE

Master Interrupt Enable:

0 — Ignore

1 — Enables interrupt generation by events speciﬁed in other bits of

this register

30

OC

Ownership Change:

0 — Ignore

1 — Enables interrupt generation because of ownership change

29 to 7

6

-

reserved

RHSC

Root Hub Status Change:

0 — Ignore

1 — Enables interrupt generation because of root hub status change

Frame Number Overﬂow:

5

4

FNO

UE

0 — Ignore

1 — Enables interrupt generation because of frame number overﬂow

Unrecoverable Error:

0 — Ignore

1 — Enables interrupt generation because of unrecoverable error

ISP1561_2

Product data sheet

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42 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 52. HcInterruptEnable register: bit description …continued

Bit

Symbol

Description

Resume Detect:

0 — Ignore

3

RD

1 — Enables interrupt generation because of resume detect

2

1

0

SF

Start-of-Frame:

0 — Ignore

1 — Enables interrupt generation because of Start-of-Frame

HcDoneHead Write-back:

WDH

SO

0 — Ignore

1 — Enables interrupt generation because of HcDoneHead write-back

Scheduling Overrun:

0 — Ignore

1 — Enables interrupt generation because of scheduling overrun

11.1.6 HcInterruptDisable register (address: content of the base address register +

14h)

Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt

bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the

HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the

corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this

register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a

read, the current value of the HcInterruptEnable register is returned. The register contains

4 bytes, and the bit allocation is given in Table 53.

Table 53. HcInterruptDisable register: bit allocation

Bit

31

MIE

0

30

OC

0

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

R/W

23

R/W

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

6

7

5

4

3

2

1

0

Symbol

Reset

Access

reserved

RHSC

0

FNO

0

UE

0

RD

0

SF

0

WDH

0

SO

0

-

R/W

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 54. HcInterruptDisable register: bit description

Bit

Symbol

Description

31

MIE

Master Interrupt Enable:

0 — Ignore

1 — Disables interrupt generation because of events speciﬁed in other

bits of this register.

This ﬁeld is set after a hardware or software reset. Interrupts are

disabled.

30

OC

Ownership Change:

0 — Ignore

1 — Disables interrupt generation because of ownership change

29 to 7

6

-

reserved

RHSC

Root Hub Status Change:

0 — Ignore

1 — Disables interrupt generation because of root hub status change

5

4

3

2

1

FNO

UE

Frame Number Overﬂow:

0 — Ignore

1 — Disables interrupt generation because of frame number overﬂow

Unrecoverable Error:

0 — Ignore

1 — Disables interrupt generation because of unrecoverable error

RD

Resume Detect:

0 — Ignore

1 — Disables interrupt generation because of resume detect

SF

Start-of-Frame:

0 — Ignore

1 — Disables interrupt generation because of Start-of-Frame

HcDoneHead Write-back:

WDH

0 — Ignore

1 — Disables interrupt generation because of HcDoneHead

write-back

0

SO

Scheduling Overrun:

0 — Ignore

1 — Disables interrupt generation because of scheduling overrun

11.1.7 HcHCCA register (address: content of the base address register + 18h)

The HcHCCA register contains the physical address of Host Controller Communication

Area (HCCA). The bit allocation is given in Table 55. The HCD determines alignment

restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The

alignment is evaluated by examining the number of zeroes in the lower order bits. The

minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0

when read. This area is used to hold control structures and the Interrupt table that are

accessed by both the Host Controller and the HCD.

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 55. HcHCCA register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

HCCA[23:16]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

HCCA[15:8]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

HCCA[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

Table 56. HcHCCA register: bit description

Bit Symbol Description

31 to 8 HCCA[23:0] Host Controller Communication Area Base Address: This is the base

address of the HCCA.

7 to 0

-

reserved

11.1.8 HcPeriodCurrentED register (address: content of the base address

register + 1Ch)

The HcPeriodCurrentED register contains the physical address of the current isochronous

or interrupt ED. Table 57 gives the bit allocation of the register.

Table 57. HcPeriodCurrentED register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

PCED[27:20]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

PCED[19:12]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

PCED[11:4]

0

R

ISP1561_2

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

PCED[3:0]

reserved

0

-

0

-

0

-

0

-

R

Table 58. HcPeriodCurrentED register: bit description

Bit

Symbol

Description

31 to 4

PCED[27:0] Period Current ED: This is used by the Host Controller to point to the

head of one of the periodic lists that must be processed in the current

Frame. The content of this register is updated by the Host Controller after

a periodic ED has been processed. The HCD may read the content in

determining which ED is currently being processed at the time of reading.

3 to 0

-

reserved

11.1.9 HcControlHeadED register (address: content of the base address register +

20h)

The HcControlHeadED register contains the physical address of the ﬁrst ED of the control

list. The bit allocation is given in Table 59.

Table 59. HcControlHeadED register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

CHED[27:20]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

CHED[19:12]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

CHED[11:4]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

CHED[3:0]

reserved

0

-

0

-

0

-

0

-

R

Table 60. HcControlHeadED register: bit description

Bit

Symbol

Description

31 to 4

CHED[27:0]

Control Head ED: The Host Controller traverses the control list,

starting with the HcControlHeadED pointer. The content is loaded

from HCCA during the initialization of the Host Controller.

3 to 0

-

reserved

ISP1561_2

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HS USB PCI Host Controller

11.1.10 HcControlCurrentED register (address: content of the base address

register + 24h)

The HcControlCurrentED register contains the physical address of the current ED of the

control list. The bit allocation is given in Table 61.

Table 61. HcControlCurrentED register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

CCED[27:20]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

CCED[19:12]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

CCED[11:4]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

CCED[3:0]

reserved

0

-

0

-

0

-

0

-

R

Table 62. HcControlCurrentED register: bit description

Bit Symbol Description

31 to 4 CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving

the present. The Host Controller must continue processing the list from

where it left off in the last frame. When it reaches the end of the control list,

the Host Controller checks the CLF (Control List Filled) bit of

HcCommandStatus. If set, it copies the content of HcControlHeadED to

HcControlCurrentED and clears the bit. If not set, it does nothing. The

HCD is allowed to modify this register only when the CLE (Control List

Enable) bit of HcControl is cleared. When set, the HCD only reads the

instantaneous value of this register. Initially, this is set to logic 0 to indicate

the end of the control list.

3 to 0

-

reserved

11.1.11 HcBulkHeadED register (address: content of the base address register +

28h)

This is a 4-byte register, and the bit allocation is given in Table 63. The register contains

the physical address of the ﬁrst ED of the bulk list.

Table 63. HcBulkHeadED register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

BHED[27:20]

0

R/W

ISP1561_2

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HS USB PCI Host Controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

BHED[19:12]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

BHED[11:4]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

BHED[3:0]

reserved

0

-

0

-

0

-

0

-

R/W

Table 64. HcBulkHeadED register: bit description

Bit

Symbol

Description

31 to 4

BHED[27:0] Bulk Head ED: The Host Controller traverses the bulk list starting

with the HcBulkHeadED pointer. The content is loaded from HCCA

during the initialization of the Host Controller.

3 to 0

-

reserved

11.1.12 HcBulkCurrentED register (address: content of the base address register +

2Ch)

This register contains the physical address of the current endpoint of the bulk list.

Endpoints are ordered according to their insertion to the list because the bulk list must be

served in a round-robin fashion. The bit allocation is given in Table 65.

Table 65. HcBulkCurrentED register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

BCED[27:20]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

BCED[19:12]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

BCED[11:4]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

BCED[3:0]

reserved

0

-

0

-

0

-

0

-

R/W

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

48 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 66. HcBulkCurrentED register: bit description

Bit Symbol Description

31 to 4 BCED[27:0] Bulk Current ED: This is advanced to the next ED after the Host

Controller has served the present ED. The Host Controller continues

processing the list from where it left off in the last frame. When it reaches

the end of the bulk list, the Host Controller checks the CLF (Control List

Filled) bit of HcControl. If the CLF bit is not set, nothing is done. If the CLF

bit is set, it copies the content of HcBulkHeadED to HcBulkCurrentED and

clears the CLF bit. The HCD can only modify this register when the BLE

(Bulk List Enable) bit of HcControl is cleared. When HcControl is set, the

HCD reads the instantaneous value of this register. This is initially set to

logic 0 to indicate the end of the bulk list.

3 to 0

-

reserved

11.1.13 HcDoneHead register (address: content of the base address register + 30h)

The HcDoneHead register contains the physical address of the last completed TD that

was added to the done queue. In a normal operation, the HCD need not read this register

because its content is periodically written to the HCCA. Table 67 contains the bit allocation

of the register.

Table 67. HcDoneHead register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

DH[27:20]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

DH[19:12]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

DH[11:4]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

DH[3:0]

reserved

0

-

0

-

0

-

0

-

R/W

Table 68. HcDoneHead register: bit description

Bit

Symbol

Description

31 to 4

DH[27:0]

Done Head: When a TD is completed, the Host Controller writes the

content of HcDoneHead to the NextTD ﬁeld of the TD. The Host

Controller then overwrites the content of HcDoneHead with the

address of this TD. This is set to logic 0 whenever the Host Controller

writes the content of this register to HCCA.

3 to 0

-

reserved

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

49 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

11.1.14 HcFmInterval register (address: content of the base address register + 34h)

The HcFmInterval register contains a 14-bit value that indicates the bit time interval in a

frame, that is, between two consecutive SOFs, and a 15-bit value indicating the full-speed

maximum packet size that the Host Controller may transmit or receive, without causing a

scheduling overrun. The HCD may carry out minor adjustment on the FI (Frame Interval)

by writing a new value over the present at each SOF. This provides the possibility for the

Host Controller to synchronize with an external clocking resource and to adjust any

unknown local clock offset. The bit allocation of the register is given in Table 69.

Table 69. HcFmInterval register: bit allocation

Bit

31

FIT

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

FSMPS[14:8]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

FSMPS[7:0]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved

FI[13:8]

0

-

0

-

1

R/W

5

0

R/W

4

1

R/W

3

1

R/W

2

1

R/W

1

0

R/W

0

7

6

Symbol

Reset

Access

FI[7:0]

1

0

1

R/W

Table 70. HcFmInterval register: bit description

Bit

Symbol

Description

31

FIT

Frame Interval Toggle: The HCD toggles this bit whenever it loads

a new value to Frame Interval.

30 to 16

FSMPS[14:0]

FS Largest Data Packet: This ﬁeld speciﬁes a value that is loaded

into the largest data packet counter at the beginning of each frame.

The counter value represents the largest amount of data in bits that

can be sent or received by the Host Controller in a single

transaction at any given time, without causing a scheduling

overrun. The ﬁeld value is calculated by the HCD.

15 to 14

13 to 0

-

reserved

FI[13:0]

Frame Interval: This speciﬁes the interval between two

consecutive SOFs in bit times. The nominal value is set to 11,999.

The HCD must store the current value of this ﬁeld before resetting

the Host Controller because this causes the ﬁeld to be reset the

nominal value. The HCD can then restore the stored value on

completing the reset sequence.

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

50 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

11.1.15 HcFmRemaining register (address: content of the base address register +

38h)

The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in

the current frame. Table 71 contains the bit allocation of this four-byte register.

Table 71. HcFmRemaining register: bit allocation

Bit

31

FRT

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

FR[13:8]

0

-

0

-

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

6

Symbol

Reset

Access

FR[7:0]

0

R/W

Table 72. HcFmRemaining register: bit description

Bit

Symbol

Description

31

FRT

Frame Remaining Toggle: This bit is loaded from the FIT (Frame Interval

Toggle) ﬁeld of HcFmInterval whenever FR (Frame Remaining) reaches 0.

This bit is used by the HCD for the synchronization between FI (Frame

Interval) and FR.

30 to 14

13 to 0

-

reserved

FR[13:0] Frame Remaining: This counter is decremented at each bit time. When it

reaches 0, it is reset by loading the FI value speciﬁed in HcFmInterval at

the next bit time boundary. When entering the USBOPERATIONAL state,

the Host Controller reloads the content with the FI of HcFmInterval and

uses the updated value from the next SOF.

11.1.16 HcFmNumber register (address: content of the base address register + 3Ch)

This register is a 16-bit counter, and the bit allocation is given in Table 73. It provides a

timing reference among events happening in the Host Controller and the HCD. The HCD

may use the 16-bit value speciﬁed in this register and generate a 32-bit frame number

without requiring frequent access to the register.

Table 73. HcFmNumber register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

51 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

FN[13:8]

0

-

0

-

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

6

Symbol

Reset

Access

FN[7:0]

0

R/W

Table 74. HcFmNumber register: bit description

Bit

Symbol Description

reserved

31 to 14

13 to 0

-

FN[13:0] Frame Number: Incremented when HcFmRemaining is re-loaded. It

must be rolled over to 0h after FFFFh. Automatically incremented when

entering the USBOPERATIONAL state. The content is written to HCCA

after the Host Controller has incremented Frame Number at each frame

boundary and sent a SOF but before the Host Controller reads the ﬁrst

ED in that frame. After writing to HCCA, the Host Controller sets the SF

(Start-of-Frame) in HcInterruptStatus.

11.1.17 HcPeriodicStart register (address: content of the base address register +

40h)

The HcPeriodicStart register has a 14-bit programmable value that determines when is

the earliest time for the Host Controller to start processing the periodic list. The bit

allocation is given in Table 75.

Table 75. HcPeriodicStart register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

reserved

P_S[13:8]

0

-

0

-

0

R/W

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

52 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

P_S[7:0]

0

R/W

Table 76. HcPeriodicStart register: bit description

Bit

Symbol

Description

31 to 14

13 to 0

-

reserved

P_S[13:0] Periodic Start: After a hardware reset, this ﬁeld is cleared. It is then set

by the HCD during the Host Controller initialization. The value is

calculated roughly as 10 % of the HcFmInterval. A typical value is 3E67h.

When HcFmRemaining reaches the value speciﬁed, processing of the

periodic lists have priority over control or bulk processing. The Host

Controller, therefore, starts processing the interrupt list after completing

the current control or bulk transaction that is in progress.

11.1.18 HcLSThreshold register (address: content of the base address register +

44h)

This register contains an 11-bit value used by the Host Controller to determine whether to

commit to the transfer of a maximum of 8-byte low-speed packet before EOF. Neither the

Host Controller nor the HCD can change this value. The bit allocation of the

HcLSThreshold register is given in Table 77.

Table 77. HcLSThreshold register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

LST[11:8]

0

-

0

-

0

-

0

-

0

R/W

3

1

R/W

2

1

R/W

1

0

R/W

0

7

6

5

4

Symbol

Reset

Access

LST[7:0]

0

1

0

1

0

R/W

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

53 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 78. HcLSThreshold register: bit description

Bit

Symbol

-

Description

31 to 12

11 to 0

reserved

LST[11:0]

LS Threshold: This ﬁeld contains a value that is compared to the FR

(Frame Remaining) ﬁeld prior to initiating a low-speed transaction.

The transaction is started only if FR ≥ this ﬁeld. The value is

calculated by the HCD, considering the transmission and set-up

overhead.

11.1.19 HcRhDescriptorA register (address: content of the base address register +

48h)

The HcRhDescriptorA register is the ﬁrst of two registers describing the characteristics of

the root hub. Reset values are implementation-speciﬁc.

Table 79 contains the bit allocation of the HcRhDescriptorA register.

Table 79. HcRhDescriptorA register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

POTPGT[7:0]

1

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

12

-

8

15

14

13

11

10

DT

0

9

Symbol

Reset

Access

Bit

reserved

NOCP

0

OCPM

NPS

0

PSM

1

0

-

0

-

0

-

1

R/W

3

R/W

4

R

2

R/W

1

R/W

0

7

6

5

Symbol

Reset

Access

NDP[7:0]

0

X^[1]

R

X^[2]

R

[1] X is 1 for OHCI1 (2P) and OHCI2 (2P); X is 0 for OHCI1 (1P) and OHCI2 (1P).

[2] X is 0 for OHCI1 (2P) and OHCI2 (2P); X is 1 for OHCI1 (1P) and OHCI2 (1P).

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

54 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 80. HcRhDescriptorA register: bit description

Bit Symbol Description

31 to 24 POTPGT[7:0] Power On To Power Good Time: This byte speciﬁes the duration the

HCD must wait before accessing a powered-on port of the root hub. It is

implementation-speciﬁc. The unit of time is 2 ms. The duration is

calculated as POTPGT × 2 ms.

23 to 13

12

-

reserved

NOCP

No Overcurrent Protection: This bit describes how the overcurrent

status for root hub ports are reported. When this bit is cleared, the

OCPM (Overcurrent Protection Mode) ﬁeld speciﬁes global or per-port

reporting.

0 — Overcurrent status is reported collectively for all downstream ports

1 — No overcurrent protection supported

11

OCPM

Overcurrent Protection Mode: This bit describes how the overcurrent

status for root hub ports are reported. At reset, this ﬁelds reﬂects the

same mode as Power Switching Mode. This ﬁeld is valid only if the

NOCP ﬁeld is cleared.

0 — Overcurrent status is collectively reported for all downstream ports

1 — Overcurrent status is reported on a per-port basis

10

9

DT

Device Type: This bit speciﬁes that the root hub is not a compound

device. The root hub is not permitted to be a compound device. This

ﬁeld must always read 0.

NPS

No Power Switching: This bit is used to specify whether power

switching is supported or ports are always powered. It is

implementation-speciﬁc. When this bit is cleared, the PSM (Power

Switching Mode) ﬁeld speciﬁes global or per-port switching.

0 — Ports are power switched

1 — Ports are always powered on when the Host Controller is powered

on

8

PSM

Power Switching Mode: This bit is used to specify how the power

switching of root hub ports is controlled. It is implementation-speciﬁc.

This ﬁeld is only valid if the NPS ﬁeld is cleared.

0 — All ports are powered at the same time.

1 — Each port is powered individually. This mode allows port power to

be controlled by either the global switch or per-port switching. If the

PPCM (Port Power Control Mask) bit is set, the port responds only to

port power commands (Set/Clear Port Power). If the port mask is

cleared, then the port is controlled only by the global power switch

(Set/Clear Global Power).

7 to 0

NDP[7:0]

Number Downstream Ports: These bits specify the number of

downstream ports supported by the root hub. It is

implementation-speciﬁc. The minimum number of ports is 1. The

maximum number of ports supported by OHCI is 15.

11.1.20 HcRhDescriptorB register (address: content of the base address register +

4Ch)

The HcRhDescriptorB register is the second of two registers describing the characteristics

of the root hub. The bit allocation is given in Table 81. These ﬁelds are written during

initialization to correspond with the system implementation. Reset values are

implementation-speciﬁc.

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

55 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 81. HcRhDescriptorB register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

PPCM[15:8]

0

R

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

18

R/W

17

R/W

16

19

Symbol

Reset

Access

Bit

PPCM[7:0]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

DR[15:8]

DR[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

0

R/W

Table 82. HcRhDescriptorB register: bit description

Bit

Symbol

Description

31 to 16

PPCM[15:0]

Port Power Control Mask: Each bit indicates whether a port is

affected by a global power control command when Power Switching

Mode is set. When set, the power state of the port is only affected

by per-port power control (Set/Clear Port Power). When cleared, the

port is controlled by the global power switch (Set/Clear Global

Power). If the device is conﬁgured to global switching mode (Power

Switching Mode = 0), this ﬁeld is not valid.

Bit 0 — reserved

Bit 1 — Ganged-power mask on port #1

Bit 2 — Ganged-power mask on port #2

15 to 0

DR[15:0]

Device Removable: Each bit is dedicated to a port of the root hub.

When cleared, the attached device is removable. When set, the

attached device is not removable.

Bit 0 — reserved

Bit 1 — Device attached to port #1

Bit 2 — Device attached to port #2

11.1.21 HcRhStatus register (address: content of the base address register + 50h)

The HcRhStatus register is divided into two parts. The lower word of a DWORD

represents the Hub Status ﬁeld and the upper word represents the Hub Status Change

ﬁeld. Reserved bits must always be written as logic 0. Table 83 contains the bit allocation

of the register.

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

56 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 83. HcRhStatus register: bit allocation

Bit

31

CRWE

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

R/W

23

22

21

20

19

18

17

CCIC

0

16

Symbol

Reset

Access

Bit

reserved

LPSC

0

-

0

-

0

-

0

-

15

-

R/W

9

R/W

8

14

13

12

11

10

Symbol

Reset

Access

Bit

DRWE

0

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

R/W

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

OCI

0

LPS

0

-

0

-

0

-

0

-

0

-

0

-

R

RW

Table 84. HcRhStatus register: bit description

Bit

Symbol Description

31

CRWE On write Clear Remote Wake-up Enable: Writing logic 1 clears DRWE

(Device Remote Wake-up Enable). Writing logic 0 has no effect.

30 to 18

17

-

reserved

CCIC

Overcurrent Indicator Change: This bit is set by hardware when a change

has occurred to the OCI (Overcurrent Indicator) ﬁeld of this register. The HCD

clears this bit by writing logic 1. Writing logic 0 has no effect.

16

LPSC

On read Local Power Status Change: The root hub does not support the

local power status feature. Therefore, this bit is always logic 0.

On write Set Global Power: In global power mode (Power Switching Mode =

0), logic 1 is written to this bit to turn on power to all ports (clear Port Power

Status). In per-port power mode, it sets Port Power Status only on ports

whose Port Power Control Mask bit is not set. Writing logic 0 has no effect.

15

DRWE On read Device Remote Wake-up Enable: This bit enables the Connect

Status Change bit as a resume event, causing a state transition

USBSUSPEND to USBRESUME and setting the Resume Detected interrupt.

0 — Connect Status Change is not a remote wake-up event

1 — Connect Status Change is a remote wake-up event

On write Set Remote Wake-up Enable: Writing logic 1 sets DRWE (Device

Remote Wake-up Enable). Writing logic 0 has no effect.

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

57 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 84. HcRhStatus register: bit description …continued

Bit

Symbol Description

14 to 2

1

-

reserved

OCI

Overcurrent Indicator: This bit reports overcurrent conditions when global

reporting is implemented. When set, an overcurrent condition exists. When

cleared, all power operations are normal. If the per-port overcurrent protection

is implemented, this bit is always logic 0.

0

LPS

On read Local Power Status: The root hub does not support the local power

status feature. Therefore, this bit is always read as logic 0.

On write Clear Global Power: In global power mode (Power Switching

Mode = 0), logic 1 is written to this bit to turn off power to all ports (clear Port

Power Status). In per-port power mode, it clears Port Power Status only on

ports whose Port Power Control Mask bit is not set. Writing logic 0 has no

effect.

11.1.22 HcRhPortStatus[1:4] register (address: content of the base address

register + 54h)

The HcRhPortStatus[1:4] register is used to control and report port events on a per-port

basis. NumberofDownstreamPort represents the number of HcRhPortStatus registers that

are implemented in hardware. The lower word reﬂects the port status. The upper word

reﬂects status change bits. Some status bits are implemented with special write behavior.

If a transaction, token through handshake, is in progress when a write to change port

status occurs, the resulting port status change is postponed until the transaction

completes. Always write logic 0 to the reserved bits. The bit allocation of the register is

given in Table 85.

Table 85. HcRhPortStatus[1:4] register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

PRSC

0

OCIC

0

PSSC

0

PESC

0

CSC

0

-

0

-

0

-

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

15

14

13

Symbol

Reset

Access

Bit

reserved

LSDA

0

PPS

0

-

0

-

0

-

0

-

0

-

R/W

1

R/W

0

7

6

5

4

3

2

Symbol

Reset

Access

reserved

PRS

0

POCI

0

PSS

0

PES

0

CCS

0

-

0

-

0

-

R/W

ISP1561_2

Product data sheet

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58 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 86. HCRhPortStatus[1:4] register: bit description

Bit

Symbol Description

31 to 21

20

-

reserved

PRSC

Port Reset Status Change: This bit is set at the end of the 10 ms port reset

signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no

effect.

0 — Port reset is not complete

1 — Port reset is complete

19

18

OCIC

PSSC

Port Overcurrent Indicator Change: This bit is valid only if overcurrent

conditions are reported on a per-port basis. This bit is set when the root hub

changes the POCI (Port Overcurrent Indicator) bit. The HCD can write logic 1

to clear this bit. Writing logic 0 has no effect.

0 — No change in Port Overcurrent Indicator

1 — POCI has changed

Port Suspend Status Change: This bit is set when the full resume

sequence is completed. This sequence includes the 20 ms resume pulse, LS

EOP and 3 ms re-synchronization delay. The HCD can write logic 1 to clear

this bit. Writing logic 0 has no effect. This bit is also cleared when Reset

Status Change is set.

0 — Resume is not completed

1 — Resume is completed

17

16

PESC

CSC

Port Enable Status Change: This bit is set when hardware events cause the

PES (Port Enable Status) bit to be cleared. Changes from the HCD writes do

not set this bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has

no effect.

0 — No change in PES

1 — Change in PES

Connect Status Change: This bit is set whenever a connect or disconnect

event occurs. The HCD can write logic 1 to clear this bit. Writing logic 0 has

no effect. If CCS (Current Connect Status) is cleared when a Set Port Reset,

Set Port Enable or Set Port Suspend write occurs, this bit is set to force the

driver to re-evaluate the connection status because these writes must not

occur if the port is disconnected.

0 — No change in CCS

1 — Change in CCS

Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a

root hub reset to inform the system that the device is attached.

15 to 10

9

-

reserved

LSDA

On read Low-speed Device Attached: This bit indicates the speed of the

device attached to this port. When set, a low-speed device is attached to this

port. When cleared, a full-speed device is attached to this port. This ﬁeld is

valid only when the CCS is set.

0 — Port is not suspended

1 — Port is suspended

On write Clear Port Power: The HCD can clear the PPS (Port Power Status)

bit by writing logic 1 to this bit. Writing logic 0 has no effect.

ISP1561_2

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 86. HCRhPortStatus[1:4] register: bit description …continued

Bit

Symbol Description

8

PPS

On read Port Power Status: This bit reﬂects the port power status,

regardless of the type of power switching implemented. This bit is cleared if

an overcurrent condition is detected. The HCD can set this bit by writing Set

Port Power or Set Global Power. The HCD can clear this bit by writing Clear

Port Power or Clear Global Power. Power Switching Mode and

PortPowerControlMask[NDP] determine which power control switches are

enabled. In Global Switching mode (Power Switching Mode = 0), only

Set/Clear Global Power controls this bit. In the per-port power switching

(Power Switching Mode = 1), if the PortPowerControlMask[NDP] bit for the

port is set, only Set/Clear Port Power commands are enabled. If the mask is

not set, only Set/Clear Global Power commands are enabled.

When port power is disabled, CCS (Current Connect Status), PES (Port

Enable Status), PSS (Port Suspend Status) and PRS (Port Reset Status)

must be reset.

0 — Port power is off

1 — Port power is on

On write Set Port Power: The HCD can write logic 1 to set the PPS (Port

Power Status) bit. Writing logic 0 has no effect.

Remark: This bit always reads logic1 if power switching is not supported.

7 to 5

4

-

reserved

PRS

On read Port Reset Status: When this bit is set by a write to Set Port Reset,

port reset signaling is asserted. When reset is completed and PRSC (Port

Reset Status Change) is set, this bit is cleared.

0 — Port reset signal is not active

1 — Port reset signal is active

On write Set Port Reset: The HCD can set the port reset signaling by writing

logic 1 to this bit. Writing logic 0 has no effect. If CCS is cleared, this write

does not set PRS (Port Reset Status) but instead sets CCS. This informs the

driver that it attempted to reset a disconnected port.

3

POCI

On read Port Overcurrent Indicator: This bit is valid only when the root hub

is conﬁgured to show overcurrent conditions are reported on a per-port basis.

If the per-port overcurrent reporting is not supported, this bit is set to logic 0.

If cleared, all power operations are normal for this port. If set, an overcurrent

condition exists on this port.

0 — No overcurrent condition

1 — Overcurrent condition detected

On write Clear Suspend Status: The HCD can write logic 1 to initiate a

resume. Writing logic 0 has no effect. A resume is initiated only if PSS (Port

Suspend Status) is set.

ISP1561_2

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 86. HCRhPortStatus[1:4] register: bit description …continued

Bit

Symbol Description

PSS On read Port Suspend Status: This bit indicates whether the port is

2

suspended or is in the resume sequence. It is set by a Set Suspend State

write and cleared when PSSC (Port Suspend Status Change) is set at the

end of the resume interval. This bit is not set if CCS (Current Connect Status)

is cleared. This bit is also cleared when PRSC (Port Reset Status Change) is

set at the end of the port reset or when the Host Controller is placed in the

USBRESUME state. If an upstream resume is in progress, it will propagate to

the Host Controller.

0 — Port is not suspended

1 — Port is suspended

On write Set Port Suspend: The HCD can set the PSS (Port Suspend

Status) bit by writing logic 1 to this bit. Writing logic 0 has no effect. If CCS is

cleared, this write does not set PSS; instead it sets CSS. This informs the

driver that it attempted to suspend a disconnected port.

1

PES

On read Port Enable Status: This bit indicates whether the port is enabled

or disabled. The root hub may clear this bit when an overcurrent condition,

disconnect event, switched-off power or operational bus error is detected.

This change also causes Port Enabled Status Change to be set. The HCD

can set this bit by writing Set Port Enable and clear it by writing Clear Port

Enable. This bit cannot be set when CCS (Current Connect Status) is

cleared. This bit is also set on completing a port reset when Reset Status

Change is set or on completing a port suspend when Suspend Status

Change is set.

0 — Port is disabled

1 — Port is enabled

On write Set Port Enable: The HCD can set PES (Port Enable Status) by

writing logic 1. Writing logic 0 has no effect. If CCS is cleared, this write does

not set PES, but instead sets CSC (Connect Status Change). This informs

the driver that it attempted to enable a disconnected port.

0

CCS

On read Current Connect Status: This bit reﬂects the current state of the

downstream port.

0 — No device connected

1 — Device connected

On write Clear Port Enable: The HCD can write logic 1 to this bit to clear the

PES (Port Enable Status) bit. Writing logic 0 has no effect. The CCS (Current

Connect Status) bit, on read, is not affected by any write to Clear Port

Enable.

Remark: This bit always reads logic 1 when the attached device is

nonremovable (DeviceRemoveable[NDP]).

11.2 USB legacy support registers

The ISP1561 supports legacy keyboard and mouse. Four operational registers are used

to provide the legacy support. Each of these registers is located on a 32-bit boundary. The

offset of these registers is relative to the base address of the Host Controller operational

registers with HceControl located at offset 100h.

ISP1561_2

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61 of 103

ISP1561

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HS USB PCI Host Controller

Table 87. Legacy support registers

Offset

Register

Description

100h

HceControl

used to enable and control the emulation hardware and report various

status information

104h

108h

HceInput

emulation of the legacy Input Buffer register

HceOutput

emulation of the legacy Output Buffer register in which the software

writes keyboard and mouse data

10Ch

HceStatus

emulation of the legacy Status register

Table 88. Emulated registers

I/O Cycle Register Contents

address type accessed or modiﬁed

Side effects

60h

64h

IN

OUT HceInput

IN HceStatus

OUT HceInput

HceOutput

IN from port 60h sets OUT_FULL (bit 0) in HceStatus

to logic 0

OUT to port 60h sets IN_FULL (bit 1) to logic 1 and

CMD_DATA (bit 3) to logic 0 in HceStatus

IN from port 64h returns current value of HceStatus

with no other side effect

OUT to port 64h sets IN_FULL to logic 0 and

CMD_DATA to logic 1 in HceStatus

11.2.1 HceControl register (address: content of the base address register + 100h)

Table 89 shows the bit allocation of the register.

Table 89. HceControl register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

A20S

0

-

0

-

7

-

6

-

5

-

3

R/W

0

4

EIRQEN

0

2

1

Symbol

Reset

Access

IRQ12A

0

IRQ1A

0

GA20S

0

IRQEN

0

C_P

0

EI

0

EE

0

R/W

R

R/W

ISP1561_2

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62 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 90. HceControl register: bit description

Bit

Symbol

-

Description

31 to 9

8

reserved

A20S

A20 State: This bit indicates the current state of gate A20 on the keyboard

controller. It is used to compare against value written to 60h when GA20S

(Gate A20 Sequence) is active.

7

6

5

4

3

IRQ12A

IRQ1A

IRQ12 Active: This bit indicates that a positive transition on IRQ12 from

the keyboard controller has occurred. Writing logic 1 sets IRQ12 to logic 0

(inactive). Writing logic 0 to this bit has no effect.

IRQ1 Active: This bit indicates that a positive transition on IRQ1 from the

keyboard controller has occurred. Writing logic 1 sets IRQ1 to logic 0

(inactive). Writing logic 0 to this bit has no effect.

GA20S

EIRQEN

IRQEN

Gate A20 Sequence: This bit is set by the Host Controller when a data

value of D1h is written to I/O port 64h and cleared, on a write to I/O port

64h of any value other than D1h.

External IRQ Enable: When this bit is set to logic 1, IRQ1 and IRQ12 from

the keyboard controller cause an emulation interrupt. This bit is

independent of the setting of the EE (Emulation Enable) bit in this register.

IRQ Enable: When this bit is set, the Host Controller generates IRQ1 or

IRQ12 as long as the OUT_FULL (Output Full) bit in HceStatus is set to

logic 1. If the AUX_OUT_FULL (Auxiliary Output Full) bit of HceStatus is

logic 0, then IRQ1 is generated; if it is logic 1, then an IRQ12 is generated.

2

1

C_P

EI

Character Pending: When this bit is set, an emulation interrupt is

generated when the OUT_FULL (Output Full) bit of the HceStatus register

is set to logic 0.

Emulation Interrupt: This bit shows the emulation interrupt condition.

0 — Legacy emulation enabled

1 — Legacy emulation disabled

0

EE

Emulation Enable: When this bit is set to logic 1, the Host Controller is

enabled for legacy emulation. The Host Controller decodes accesses to

I/O registers 60h and 64h, and enables interrupts on IRQ1 or IRQ12, or

both. The Host Controller also generates an emulation interrupt at

appropriate times to invoke the emulation software.

11.2.2 HceInput register (address: content of the base address register + 104h)

The HceInput register is a 4-byte register, and the bit allocation is given in Table 91. The

I/O data that is written to ports 60h and 64h is captured in this register, when emulation is

enabled. This register may directly be read or written by accessing it in the Host

Controller’s operational register space. When directly accessed in a memory cycle, reads

and writes of this register have no side effects.

Table 91. HceInput register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

ISP1561_2

Product data sheet

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63 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

IN_DATA[7:0]

0

R/W

Table 92. HceInput register: bit description

Bit

Symbol

Description

31 to 8

7 to 0

-

reserved

IN_DATA[7:0] Input Data: This register holds data that is written to I/O ports 60h or 64h.

11.2.3 HceOutput register (address: content of the base address register + 108h)

Data placed in this register by the emulation software is returned when I/O port 60h is

read and emulation is enabled. On a read of this location, the OUT_FULL (Output Full) bit

in HceStatus is set to logic 0. The bit allocation is given in Table 93.

Table 93. HceOutput register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

OUT_DATA[7:0]

0

R/W

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 94. HceOutput register: bit description

Bit

Symbol

Description

31 to 8

7 to 0

-

reserved

OUT_DATA[7:0] Output Data: This register holds the data that is returned when an I/O

read of port 60h is requested by application software.

11.2.4 HceStatus register (address: content of the base address register + 10Ch)

The contents of the HceStatus register are returned on an I/O read of port 64h when

emulation is enabled. Reads and writes of port 60h, and writes to port 64h can cause

changes in this register. Emulation software can directly access this register through its

memory address in the Host Controller’s operational register space. Accessing this

register through its memory address produces no side effects. Table 95 contains the bit

allocation.

Table 95. HceStatus register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

0

-

0

-

0

-

7

-

6

-

2

-

1

-

5

4

3

0

Symbol

PARITY

TIMEOUT

AUX_OUT

_FULL

INH_SW

CMD_DATA

FLAG

IN_FULL

OUT_FULL

Reset

0

Access

R/W

Table 96. HceStatus register: bit description

Bit

Symbol

-

Description

31 to 8

reserved

7

6

5

PARITY

TIMEOUT

Parity: This bit indicates parity error on keyboard and mouse data.

Time-out: This bit indicates a time-out.

AUX_OUT_ Auxiliary Output Full: IRQ12 is asserted whenever this bit is set to

FULL

logic 1, OUT_FULL (Output Full) is set to logic 1, and the IRQEN bit is set.

4

3

INH_SW

Inhibit Switch: This bit reﬂects the state of the keyboard inhibit switch. If

set, the keyboard is active.

CMD_DATA Cmd Data: The Host Controller sets this bit to logic 0 on an I/O write to

port 60h and to logic 1 on an I/O write to port 64h.

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 96. HceStatus register: bit description …continued

Bit

Symbol

Description

2

FLAG

Flag: Nominally used as a system ﬂag by software to indicate a warm or

cold boot.

1

0

IN_FULL

Input Full: Except for the case of a gate A20 sequence, this bit is set to

logic 1 on an I/O write to address 60h or 64h. While this bit is set to logic 1

and emulation is enabled, an emulation interrupt condition exists.

OUT_FULL Output Full: The Host Controller sets this bit to logic 0 on a read of I/O

port 60h. If IRQEN is set, AUX_OUT_FULL (Auxiliary Output Full)

determines which IRQ is activated. While this bit is logic 0 and C_P

(Character Pending) in HceControl is set to logic 1, an emulation interrupt

condition exists.

11.3 EHCI controller capability registers

Other than the OHCI Host Controller, there are some registers in EHCI that deﬁne the

capability of EHCI. The address range of these registers is located before the operational

registers.

11.3.1 CAPLENGTH/HCIVERSION register (address: content of the base address

register + 00h)

The bit allocation of this 4-byte register is given in Table 97.

Table 97. CAPLENGTH/HCIVERSION register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

HCIVERSION[15:8]

1

R

0

R

0

R

1

R

0

R

1

R

0

R

9

1

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

HCIVERSION[7:0]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

CAPLENGTH[7:0]

0

1

0

R

ISP1561_2

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66 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 98. CAPLENGTH/HCIVERSION register: bit description

Bit

Symbol

Description

31 to 24 -

reserved

23 to 8 HCIVERSION Host Controller Interface Version Number: It contains a BCD

[15:0]

encoded version number of the interface to which the Host Controller

interface conforms.

7 to 0

CAPLENGTH Capability Register Length: This is used as an offset. It is added to the

[7:0] register base to ﬁnd the beginning of the operational register space.

11.3.2 HCSPARAMS register (address: content of the base address register + 04h)

The Host Controller Structural Parameters (HCSPARAMS) register is a set of ﬁelds that

are structural parameters. The bit allocation is given in Table 99.

Table 99. HCSPARAMS register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

DPN[3:0]

reserved

P_INDI

CATOR

Reset

Access

Bit

0

R

0

R

0

R

0

R

0

-

0

-

0

-

0

R

8

15

14

13

12

11

10

9

Symbol

Reset

Access

Bit

N_CC[3:0]

reserved

N_PCC[3:0]

0

R

0

R

6

1

R

5

0

R

0

R

3

0

R

2

1

R

1

0

R

0

7

4

Symbol

Reset

Access

PRR

0

PPC

1

N_PORTS[3:0]

0

-

0

-

0

1

0

R

Table 100. HCSPARAMS register: bit description

Bit

Symbol

Description

31 to 24

-

reserved

23 to 20 DPN[3:0]

Debug Port Number: This ﬁeld identiﬁes which of the Host Controller

ports is the debug port. A nonzero value in this ﬁeld indicates the

presence of a debug port. The value in this register must not be greater

than N_PORTS.

19 to 17

16

reserved

P_

Port Indicators: This bit indicates whether the ports support port

INDICATOR indicator control. When this bit is logic 1, the port status and control

registers include a read/writable ﬁeld to control the state of the port

indicator.

ISP1561_2

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 100. HCSPARAMS register: bit description …continued

Bit Symbol Description

15 to 12 N_CC

[3:0]

Number of Companion Controller: This ﬁeld indicates the number of

companion controllers associated with this Hi-Speed USB Host

Controller. A value of zero in this ﬁeld indicates there are no companion

Host Controllers. Port-ownership hand-off is not supported. Only

high-speed devices are supported on the Host Controller root ports. A

value larger than zero in this ﬁeld indicates there are companion Original

USB Host Controller(s). Port-ownership hand-offs are supported.

11 to 8

N_PCC

[3:0]

Number of Ports per Companion Controller: This ﬁeld indicates the

number of ports supported per companion Host Controller. It is used to

indicate the port routing conﬁguration to system software. For example, if

N_PORTS has a value of 6 and N_CC has a value of 2, then N_PCC can

have a value of 3. The convention is that the ﬁrst N_PCC ports are

assumed to be routed to companion controller 1, the next N_PCC ports

to companion controller 2, and so on. In the previous example, N_PCC

could have been 4, in which case the ﬁrst four are routed to companion

controller 1 and the last two are routed to companion controller 2.

The number in this ﬁeld must be consistent with N_PORTS and N_CC.

7

PRR

Port Routing Rules: This ﬁeld indicates the method used to map ports

to companion controllers.

0 — The ﬁrst N_PCC ports are routed to the lowest numbered function

companion Host Controller, the next N_PCC ports are routed to the next

lowest function companion controller, and so on.

1 — The port routing is explicitly enumerated by the ﬁrst N_PORTS

elements of the HCSP-PORTROUTE array.

6 to 5

4

-

reserved

PPC

Port Power Control: This ﬁeld indicates whether the Host Controller

implementation includes port power control. Logic 1 indicates the port

has port power switches. Logic 0 indicates the port does not have port

power switches. The value of this ﬁeld affects the functionality of the Port

Power ﬁeld in each port status and control register.

3 to 0

N_PORTS

[3:0]

N_Ports: This ﬁeld speciﬁes the number of physical downstream ports

implemented on this Host Controller. The value of this ﬁeld determines

how many port registers are addressable in the operational register

space. Valid values are in the range of 1h to Fh. Logic 0 in this ﬁeld is

undeﬁned.

11.3.3 HCCPARAMS register (address: content of the base address register + 08h)

The Host Controller Capability Parameters (HCCPARAMS) register is a 4-byte register,

and the bit allocation is given in Table 101.

Table 101. HCCPARAMS register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

1

-

0

7

6

5

4

3

2

Symbol

Reset

Access

IST[3:0]

reserved

PFLF

1

64AC

0

1

0

-

0

-

R

Table 102. HCCPARAMS register: bit description

Bit

Symbol

-

Description

31 to 8

7 to 4

reserved

IST[3:0]

Isochronous Scheduling Threshold: Default = implementation

dependent. This ﬁeld indicates, relative to the current position of the

executing Host Controller, where software can reliably update the

isochronous schedule. When IST[3] is logic 0, the value of the least

signiﬁcant three bits indicates the number of micro frames a Host

Controller can hold a set of isochronous data structures, one or more,

before ﬂushing the state. When IST[3] is logic 1, then host software

assumes the Host Controller may cache an isochronous data structure

for an entire frame.

3 to 2

1

-

reserved

PFLF

Programmable Frame List Flag: Default = implementation

dependent. If this bit is cleared, the system software must use a frame

list length of 1024 elements with this Host Controller. The USBCMD

register FLS (Frame List Size) ﬁeld is a read-only register and must be

cleared. If PFLF is set, the system software can specify and use a

smaller frame list and conﬁgure the host through the USBCMD register

FLS ﬁeld. The frame list must always be aligned on a 4 kB page

boundary to ensure that the frame list is always physically contiguous.

0

64AC

64-bit Addressing Capability: This ﬁeld documents the addressing

range capability.

0 — Data structures using 32-bit address memory pointers

1 — Data structures using 64-bit address memory pointers

11.4 Operational registers of enhanced USB Host Controller

11.4.1 USBCMD register (address: content of the base address register + 0Ch)

The USB Command (USBCMD) register indicates the command to be executed by the

serial Host Controller. Writing to this register causes a command to be executed.

Table 103 shows the USBCMD register bit allocation.

Table 103. USBCMD register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

ISP1561_2

Product data sheet

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69 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

ITC[7:0]

reserved

0

1

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

7

-

6

5

4

3

2

1

0

Symbol

LHCR

IAAD

ASE

PSE

FLS[1:0]

HC

RS

RESET

Reset

0

Access

R/W

Table 104. USBCMD register: bit description

Bit

Symbol Description

- reserved

31 to

24

23 to

16

ITC[7:0] Interrupt Threshold Control: Default 08h. This ﬁeld is used by system

software to select the maximum rate at which the Host Controller will issue

interrupts. If software writes an invalid value to this register, the results are

undeﬁned. Valid values are:

00h — reserved

01h — 1 micro frame

02h — 2 micro frames

04h — 4 micro frames

08h — 8 micro frames (equals 1 ms)

10h — 16 micro frames (equals 2 ms)

20h — 32 micro frames (equals 4 ms)

40h — 64 micro frames (equals 8 ms)

Software modiﬁcations to this ﬁeld while HCH (HC Halted) bit is zero results in

undeﬁned behavior.

15 to 8

7

-

reserved

LHCR

Light Host Controller Reset: This control bit is not required. It allows the

driver software to reset the EHCI controller, without affecting the state of the

ports or the relationship to the companion Host Controllers. If not

implemented, a read of this ﬁeld will always return zero. If implemented, on

read:

Logic 0 — Indicates the Light Host Controller Reset has completed and it is

ready for the host software to re-initialize the Host Controller

Logic 1 — Indicates the Light Host Controller Reset has not yet completed

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 104. USBCMD register: bit description …continued

Bit

Symbol Description

6

IAAD

Interrupt on Asynchronous Advance Doorbell: This bit is used as a

doorbell by software to notify the Host Controller to issue an interrupt the next

time it advances the asynchronous schedule. Software must write logic 1 to

this bit to ring the doorbell. When the Host Controller has evicted all

appropriate cached schedule states, it sets the IAA (Interrupt on

Asynchronous Advance) status bit in the USBSTS register. If the IAAE

(Interrupt on Asynchronous Advance Enable) bit in the USBINTR register is

logic 1, then the Host Controller will assert an interrupt at the next interrupt

threshold. The Host Controller sets this bit to logic 0 after it sets IAA (Interrupt

on Asynchronous Advance) status bit in the USBSTS register. Software must

not set this bit when the asynchronous schedule is inactive because this

results in an undeﬁned value.

5

ASE

PSE

Asynchronous Schedule Enable: Default = 0. This bit controls whether the

Host Controller skips processing the asynchronous schedule.

0 — Do not process the asynchronous schedule

1 — Use the ASYNCLISTADDR register to access the asynchronous

schedule

4

Periodic Schedule Enable: Default = 0. This bit controls whether the Host

Controller skips processing the periodic schedule.

0 — Do not process the periodic schedule

1 — Use the PERIODICLISTBASE register to access the periodic schedule

3 to 2

FLS[1:0] Frame List Size: Default = 00b. This ﬁeld is read and write only if PFLF (bit 1)

in the HCCPARAMS register is set to logic 1. This ﬁeld speciﬁes the size of the

frame list. The size the frame list controls which bits in the Frame Index

register must be used for the frame list current index.

00b — 1024 elements (4096 bytes)

01b — 512 elements (2048 bytes)

10b — 256 elements (1024 bytes) for small environments

11b — reserved

1

HC

Host Controller Reset: This control bit is used by the software to reset the

RESET Host Controller. The effects of this on Root Hub registers are similar to a chip

hardware reset. Setting this bit causes the Host Controller to reset its internal

pipelines, timers, counters, state machines, and so on, to their initial values.

Any transaction currently in progress on USB is immediately terminated. A

USB reset is not driven on downstream ports. This reset does not affect PCI

Conﬁguration registers. All operational registers, including port registers and

port state machines, are set to their initial values. Port ownership reverts to the

companion Host Controller(s). The software must re-initialize the Host

Controller to return it to an operational state. This bit is cleared by the Host

Controller when the reset process is complete. Software cannot terminate the

reset process early by writing logic 0 to this register. Software must check the

HCH (HC Halted) bit in the USBSTS register is logic 0 before setting this bit.

Attempting to reset an actively running Host Controller results in undeﬁned

behavior.

0

RS

Run/Stop: 1 = Run. 0 = Stop. When set, the Host Controller executes the

schedule. The Host Controller continues execution as long as this bit is set.

When this bit is cleared, the Host Controller completes the current and active

transactions in the USB pipeline, and then halts. The HCH (HC Halted) bit in

the USBSTS register indicates when the Host Controller has ﬁnished the

transaction and has entered the stopped state. Software must check HCH (HC

Halted) in the USBSTS register is logic 1, before setting this bit.

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

11.4.2 USBSTS register (address: content of the base address register + 10h)

The USB Status (USBSTS) register indicates pending interrupts and various states of the

Host Controller. The status resulting from a transaction on the serial bus is not indicated in

this register. Software clears the register bits by writing ones to them. The bit allocation is

given in Table 105.

Table 105. USBSTS register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

ASS

0

14

13

RECL

0

12

HCH

1

11

10

9

8

Symbol

Reset

Access

Bit

PSSTAT

reserved

0

R

6

0

-

0

-

0

-

0

R

-

0

7

5

4

3

2

1

Symbol

reserved

IAA

HSE

FLR

PCD

USB

USBINT

ERRINT

Reset

0

-

0

-

0

Access

R

R/W

Table 106. USBSTS register: bit description

Bit

Symbol

Description

31 to 16

15

-

reserved

ASS

Asynchronous Schedule Status: 0 = Default. The bit reports the

current real status of the asynchronous schedule. If this bit is logic 0,

the status of the asynchronous schedule is disabled. If this bit is

logic 1, the status of the asynchronous schedule is enabled. The

Host Controller is not required to immediately disable or enable the

asynchronous schedule when software changes the ASE

(Asynchronous Schedule Enable) bit in the USBCMD register. When

this bit and the ASE (Asynchronous Schedule Enable) bit have the

same value, the asynchronous schedule is either enabled (1) or

disabled (0).

14

PSSTAT

Periodic Schedule Status: 0 = Default. This bit reports the current

status of the periodic schedule. If this bit is logic 0, the status of the

periodic schedule is disabled. If this bit is logic 1, the status of the

periodic schedule is enabled. The Host Controller is not required to

immediately disable or enable the periodic schedule when software

changes the PSE (Periodic Schedule Enable) bit in the USBCMD

register. When this bit and the PSE bit have the same value, the

periodic schedule is either enabled (1) or disabled (0).

13

RECL

Reclamation: 0 = Default. This is a read-only status bit that is used

to detect an empty asynchronous schedule.

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 106. USBSTS register: bit description …continued

Bit

Symbol

Description

12

HCH

HC Halted: 1 = Default. This bit is logic 0 when the Run/Stop bit of

the USBCMD register is logic 1. The Host Controller sets this bit to

logic 1 after it has stopped executing because the Run/Stop bit is set

to logic 0, either by software or by the Host Controller hardware. For

example, on an internal error.

11 to 6

5

-

reserved

IAA

Interrupt on Asynchronous Advance: Default = 0. The system

software can force the Host Controller to issue an interrupt the next

time the Host Controller advances the asynchronous schedule by

writing logic 1 to the IAAD (Interrupt on Asynchronous Advance

Doorbell) bit in the USBCMD register. This status bit indicates the

assertion of that interrupt source.

4

3

HSE

FLR

Host System Error: The Host Controller sets this bit when a serious

error occurs during a host system access, involving the Host

Controller module. In a PCI system, conditions that set this bit

include PCI parity error, PCI master abort and PCI target abort.

When this error occurs, the Host Controller clears the RS (Run/Stop)

bit in the USBCMD register to prevent further execution of the

scheduled TDs.

Frame List Rollover: The Host Controller sets this bit to logic 1

when the frame list index rolls over from its maximum value to zero.

The exact value at which the rollover occurs depends on the frame

list size. For example, if the frame list size (as programmed in the

FLS (Frame List Size) ﬁeld of the USBCMD register) is 1024

elements (see Table 111), the Frame Index register rolls over every

time bit 13 of the FRINDEX register toggles. Similarly, if the size is

512 elements, the Host Controller sets this bit to logic 1 every time

bit 12 of the FRINDEX register toggles.

2

PCD

Port Change Detect: The Host Controller sets this bit to logic 1

when any port, where the PO (Port Owner) bit is cleared, changes to

logic 1, or a Force Port Resume bit changes to logic 1 as a result of

a J-K transition detected on a suspended port. This bit is allowed to

be maintained in the auxiliary power well. Alternatively, it is also

acceptable that, on a D3-to-D0 transition of the EHCI Host Controller

device, this bit is loaded with the logical OR of all of the PORTSC

change bits, including force port resume, overcurrent change,

enable or disable change, and connect status change.

1

0

USBERRINT USB Error Interrupt: The Host Controller sets this bit when an error

condition occurs because of completing a USB transaction. For

example, error counter underﬂow. If the Transfer Descriptor (TD) on

which the error interrupt occurred also had its IOC bit set, both this

bit and USBINT bit are set.

USBINT

USB Interrupt: The Host Controller sets this bit on completing a

USB transaction, which results in the retirement of a TD that had its

IOC bit set. The Host Controller also sets this bit when a short

packet is detected, that is, the actual number of bytes received was

less than the expected number of bytes.

ISP1561_2

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HS USB PCI Host Controller

11.4.3 USBINTR register (address: content of the base address register + 14h)

The USB Interrupt Enable (USBINTR) register enables and disables reporting of the

corresponding interrupt to the software. When a bit is set and the corresponding interrupt

is active, an interrupt is generated to the host. Interrupt sources that are disabled in this

register still appear in the USBSTS to allow the software to poll for events. The USBSTS

register bit allocation is give in Table 107.

Table 107. USBINTR register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

5

-

3

-

2

-

0

7

6

4

1

Symbol

reserved

IAAE

HSEE

FLRE

PCIE

USBERR

INTE

USBINTE

Reset

0

-

0

-

0

Access

R/W

Table 108. USBINTR register: bit description

Bit

Symbol

-

Description

31 to 6

5

reserved

IAAE

Interrupt on Asynchronous Advance Enable: When this bit and the

IAA (Interrupt on Asynchronous Advance) bit in the USBSTS register

are set, the Host Controller issues an interrupt at the next interrupt

threshold. The interrupt is acknowledged by software clearing bit IAA.

4

3

HSEE

FLRE

Host System Error Enable: When this bit and the Host System Error

Status bit in the USBSTS register are set, the Host Controller issues

an interrupt. The interrupt is acknowledged by software clearing the

HSE (Host System Error) bit.

Frame List Rollover Enable: When this bit and the FLR (Frame List

Rollover) bit in the USBSTS register are set, the Host Controller

issues an interrupt. The interrupt is acknowledged by software

clearing the FLR (Frame List Rollover) bit.

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Table 108. USBINTR register: bit description …continued

Bit

Symbol

Description

2

PCIE

Port Change Interrupt Enable: When this bit and the PCD (Port

Change Detect) bit in the USBSTS register are set, the Host Controller

issues an interrupt. The interrupt is acknowledged by software

clearing the PCD (Port Change Detect) bit.

1

0

USB

ERRINTE

USB Error Interrupt Enable: When this bit and the USBERRINT bit in

the USBSTS register are set, the Host Controller issues an interrupt at

the next interrupt threshold. The interrupt is acknowledged by software

clearing the USBERRINT bit.

USBINTE

USB Interrupt Enable: When this bit and the USBINT bit in the

USBSTS register are set, the Host Controller issues an interrupt at the

next interrupt threshold. The interrupt is acknowledged by software

clearing the USBINT bit.

11.4.4 FRINDEX register (address: content of the base address register + 18h)

The Frame Index (FRINDEX) register is used by the Host Controller to index into the

periodic frame list. The register updates every 125 µs, once each microframe. Bits N to 3

are used to select a particular entry in the periodic frame list during periodic schedule

execution. The number of bits used for the index depends on the size of the frame list as

set by system software in the FLS (Frame List Size) ﬁeld in the USBCMD register. This

register must be written as a DWORD. Byte writes produce undeﬁned results. This

register cannot be written unless the Host Controller is in the halted state, as indicated by

the HCH (HC Halted) bit. A write to this register while the RS (Run/Stop) bit is set

produces undeﬁned results. Writes to this register also affect the SOF value. The bit

allocation is given in Table 109.

Table 109. FRINDEX register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved

FRINDEX[13:8]

0

-

0

-

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

6

Symbol

Reset

Access

FRINDEX[7:0]

0

R/W

ISP1561_2

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HS USB PCI Host Controller

Table 110. FRINDEX register: bit description

Bit

Symbol

Description

31 to 14

13 to 0

-

reserved

FRINDEX [13:0] Frame Index: Bits in this register are used for the frame number in

the SOF packet and as the index into the frame list. The value in this

register increments at the end of each time frame. For example,

micro frame. The bits used for the frame number in the SOF token

are taken from bits 13 to 3 of this register. Bits N to 3 are used for the

frame list current index. This means that each location of the frame

list is accessed eight times, frames or micro frames, before moving

to the next index. Table 111 illustrates N based on the value of the

FLS (Frame List Size) ﬁeld in the USBCMD register.

Table 111. N based value of FLS[1:0]

FLS[1:0]

00b

Number elements

N

1024

512

12

11

10

-

01b

10b

256

11b

reserved

11.4.5 CTRLDSSEGMENT register (address: content of the base address register +

1Ch)

The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to the

most signiﬁcant address bits (bits 63 to 32) for all EHCI data structures. If the 64AC (64-bit

Addressing Capability) ﬁeld in HCCPARAMS is cleared, then this register is not used and

software cannot write to it (reading from this register returns zero).

If the 64AC (64-bit Addressing Capability) ﬁeld in HCCPARAMS is set, this register is used

with link pointers to construct 64-bit addresses to EHCI control data structures. This

register is concatenated with the link pointer from either the PERIODICLISTBASE,

ASYNCLISTADDR, or any control data structure link ﬁeld to construct a 64-bit address.

This register allows the host software to locate all control data structures within the same

4 GB memory segment.

11.4.6 PERIODICLISTBASE register (address: content of the base address

register + 20h)

The Periodic Frame List Base Address (PERIODICLISTBASE) register contains the

beginning address of the periodic frame list in the system memory. If the Host Controller is

in 64-bit mode, as indicated by logic 1 in the 64AC (64-bit Addressing Capability) ﬁeld in

the HCCPARAMS register, the most signiﬁcant 32 bits of every control data structure

address comes from the CTRLDSSEGMENT register. The system software loads this

register before starting the schedule execution by the Host Controller. The memory

structure referenced by this physical memory pointer is assumed as 4 kB aligned. The

contents of this register are combined with the FRINDEX register to enable the Host

Controller to step through the periodic frame list in sequence. The bit allocation is given in

Table 112.

ISP1561_2

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HS USB PCI Host Controller

Table 112. PERIODICLISTBASE register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

BA[19:12]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

BA[11:4]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

BA[3:0]

reserved

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

-

0

-

0

-

0

-

3

2

1

0

Symbol

Reset

Access

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

Table 113. PERIODICLISTBASE register: bit description

Bit Symbol Description

31 to 12 BA[19:0] Base Address: These bits correspond to memory address signals 31 to 12,

respectively.

11 to 0

-

reserved

11.4.7 ASYNCLISTADDR register (address: content of the base address register +

24h)

This 32-bit register (bit allocation: Table 114) contains the address of the next

asynchronous queue head to be executed. If the Host Controller is in 64-bit mode, as

indicated by logic 1 in 64AC (64-bit Addressing Capability) ﬁeld in the HCCPARAMS

register, the most signiﬁcant 32 bits of every control data structure address comes from

the CTRLDSSEGMENT register. Bits 4 to 0 of this register always return zeros when read.

The memory structure referenced by the physical memory pointer is assumed to be

32 bytes (cache aligned).

Table 114. ASYNCLISTADDR register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

LPL[26:19]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

LPL[18:11]

0

R/W

ISP1561_2

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ISP1561

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HS USB PCI Host Controller

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

LPL[10:3]

0

R/W

7

0

R/W

5

0

R/W

4

0

-

0

-

0

-

R/W

-

6

3

2

1

0

Symbol

Reset

Access

LPL[2:0]

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

Table 115. ASYNCLISTADDR register: bit description

Bit Symbol Description

31 to 5 LPL[26:0] Link Pointer List: These bits correspond to memory address signals 31 to

5, respectively. This ﬁeld may only reference a Queue Head (QH).

4 to 0

-

reserved

11.4.8 CONFIGFLAG register (address: content of the base address register + 4Ch)

The bit allocation of the Conﬁgure Flag (CONFIGFLAG) register is given in Table 116.

Table 116. CONFIGFLAG register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved

CF

0

-

0

-

0

-

0

-

0

-

0

-

0

-

R/W

Table 117. CONFIGFLAG register: bit description

Bit

Symbol

Description

31 to 1

0

-

reserved

CF

Conﬁgure Flag: The host software sets this bit as the last action in its

process of conﬁguring the Host Controller. This bit controls the default

port-routing control logic.

0 — Port routing control logic default-routes each port to an implementation

dependent classic Host Controller

1 — Port routing control logic default-routes all ports to this Host Controller

ISP1561_2

Product data sheet

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78 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

11.4.9 PORTSC registers 1, 2, 3, 4 (address: content of the base address register +

50h + (4 times Port Number − 1)) where Port Number is 1, 2, 3,...N_Ports

The Port Status and Control (PORTSC) register (bit allocation: Table 118) is in the

auxiliary power well. It is only reset by hardware when the auxiliary power is initially

applied or in response to a Host Controller reset. The initial conditions of a port are:

• No device connected

• Port disabled

If the port has power control, software cannot change the state of the port until it sets port

power bits. Software must not attempt to change the state of the port until power is stable

on the port; maximum delay is 20 ms from the transition.

Table 118. PORTSC 1, 2, 3, 4 register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

-

0

-

0

-

0

-

0

-

0

-

23

22

21

20

19

18

17

16

Symbol

reserved

WKOC_E

WKDS

CNNT_E

WKCNNT_

E

PTC[3:0]

Reset

Access

Bit

0

-

0

R/W

13

0

R/W

12

0

R/W

9

0

R/W

8

R/W

14

R/W

11

R/W

10

15

Symbol

Reset

Access

Bit

PIC[1:0]

PO

1

PP

0

LS[1:0]

reserved

PR

0

R

0

R

0

R/W

3

0

R/W

2

0

R/W

5

R/W

4

-

1

R

7

6

0

Symbol

Reset

Access

SUSP

0

FPR

0

OCC

0

OCA

0

PEDC

0

PED

0

ECSC

0

ECCS

0

R/W

R

R/W

R

Table 119. PORTSC 1, 2, 3, 4 register: bit description

Bit

Symbol

Description

31 to 23 -

reserved

22

21

20

WKOC_E Wake on Overcurrent Enable: Default = 0. Setting this bit enables the port

to be sensitive to overcurrent conditions as wake-up events.^[1]

WKDS

Wake on Disconnect Enable: Default = 0. Setting this bit enables the port

CNNT_E to be sensitive to device disconnects as wake-up events.^[1]

WKCNNT Wake on Connect Enable: Default = 0. Setting this bit enables the port to

_E

be sensitive to device connects as wake-up events.^[1]

ISP1561_2

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 119. PORTSC 1, 2, 3, 4 register: bit description …continued

Bit Symbol Description

19 to 16 PTC[3:0] Port Test Control: Default = 0000b. When this ﬁeld is logic 0, the port is not

operating in test mode. A nonzero value indicates that it is operating in test

mode and test mode is indicated by the value. The encoding of test mode

bits are:

0000b — test mode disabled

0001b — test J_STATE

0010b — test K_STATE

0011b — test SE0_NAK

0100b — test packet

0101b — test FORCE_ENABLE

0110b to 1111b — reserved

15 to 14 PIC[1:0]

Port Indicator Control: Default = 0. Writing to this ﬁeld has no effect if the

P_INDICATOR bit in the HCSPARAMS register is logic 0. If P_INDICATOR

bit is logic 1, then the bit encoding is:

00b — Port indicators are off

01b — amber

10b — green

11b — undeﬁned

For a description on how these bits are implemented, refer to Ref. 8

“Universal Serial Bus Speciﬁcation”.^[1]

13

PO

Port Owner: Default = 1. This bit unconditionally goes to logic 0 when the

Conﬁgured bit in the CONFIGFLAG register makes logic 0 to logic 1

transition. This bit unconditionally goes to logic 1 whenever the Conﬁgured

bit is logic 0. The system software uses this ﬁeld to release ownership of the

port to a selected Host Controller, if the attached device is not a high-speed

device. Software writes logic 1 to this bit when the attached device is not a

high-speed device. Logic 1 in this bit means that a companion Host

Controller owns and controls the port.

12

PP

Port Power: The function of this bit depends on the value of the Port Power

Control (PPC) ﬁeld in the HCSPARAMS register.

If PPC = 0 and PP = 1 — The Host Controller does not have port power

control switches. Each port is hardwired to power.

If PPC = 1 and PP = 1 or 0 — The Host Controller has port power control

switches. This bit represents the current setting of the switch: logic 0 = off,

logic 1 = on. When PP is logic 0, the port is nonfunctional and will not report

any status

When an overcurrent condition is detected on a powered port and PPC is

logic 1, the PP bit in each affected port may be changed by the Host

Controller from logic 1 to logic 0, removing power from the port.

11 to 10 LS[1:0]

Line Status: This ﬁeld reﬂect the current logical levels of the DP (bit 11) and

DM (bit 10) signal lines. These bits are used to detect low-speed USB

devices before the port reset and enable sequence. This ﬁeld is valid only

when the Port Enable bit is logic 0, and the current connect status bit is set

to logic 1.

00b — SE0: Not a low-speed device, perform EHCI reset

01b — K-state: Low-speed device, release ownership of port

10b — J-state: Not a low-speed device, perform EHCI reset

11b — undeﬁned: Not a low-speed device, perform EHCI reset.

If Port Power (PP) is logic 0, this ﬁeld is undeﬁned.

ISP1561_2

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 119. PORTSC 1, 2, 3, 4 register: bit description …continued

Bit

9

Symbol

Description

-

reserved

8

PR

Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not

in reset. Default = 0. When software sets this bit from logic 0, the bus reset

sequence as deﬁned in Ref. 8 “Universal Serial Bus Speciﬁcation” is started.

Software clears this bit to terminate the bus reset sequence. Software must

hold this bit at logic 1 until the reset sequence, as speciﬁed in Ref. 8

“Universal Serial Bus Speciﬁcation”, is completed.

Remark: When software sets this bit, it must also clear the Port Enable bit.

Remark: When software clears this bit, there may be a delay before the bit

status changes to logic 0 because it will not read logic 0 until the reset is

completed. If the port is in high-speed mode after reset is completed, the

Host Controller will automatically enable this port; it can set the Port Enable

bit. A Host Controller must terminate the reset and stabilize the state of the

port within 2 ms of software changing this bit from logic 1 to logic 0. For

example, if the port detects that the attached device is high-speed during a

reset, then the Host Controller must enable the port within 2 ms of software

clearing this bit.

The HCH (HC Halted) bit in the USBSTS register must be logic 0 before

software attempts to use this bit. The Host Controller may hold Port Reset

asserted when the HCH (HC Halted) bit is set.^[1]

7

SUSP

Suspend: Default = 0. A logic 1 means the port is in the suspend state. A

logic 0 means the Port is not suspended. The Port Enabled bit and the

Suspend bit of this register deﬁne the port states as follows:

PED = 0 and SUSP = x — Port is disabled

PED = 1 and SUSP = 0 — Port is enabled

PED = 1 and SUSP = 1 — Port is suspended

When in the suspend state, downstream propagation of data is blocked on

this port, except for the port reset. If a transaction was in progress when this

bit was set, blocking occurs at the end of the current transaction. In the

suspend state, the port is sensitive to resume detection. The bit status does

not change until the port is suspended and there may be a delay in

suspending a port, if there is a transaction currently in progress on USB.

Attempts to clear this bit are ignored by the Host Controller. The Host

Controller will unconditionally set this bit to logic 0 when:

• Software changes the FPR (Force Port Resume) bit to logic 0.

• Software changes the PR (Port Reset) bit to logic 1.

If the host software sets this bit when the Port Enabled bit is logic 0, the

results are undeﬁned.^[1]

ISP1561_2

Product data sheet

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ISP1561

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HS USB PCI Host Controller

Table 119. PORTSC 1, 2, 3, 4 register: bit description …continued

Bit

Symbol

Description

6

FPR

Force Port Resume: Logic 1 means resume detected or driven on the port.

Logic 0 means no resume (K-state) detected or driven on the port. Default =

0. Software sets this bit to drive the resume signaling. The Host Controller

sets this bit if a J-to-K transition is detected while the port is in the suspend

state. When this bit changes to logic 1 because a J-to-K transition is

detected, the PCD (Port Change Detect) bit in the USBSTS register is also

set to logic 1. If software sets this bit to logic 1, the Host Controller must not

set the PCD (Port Change Detect) bit. When the EHCI controller owns the

port, the resume sequence follows the sequence speciﬁed in Ref. 8

“Universal Serial Bus Speciﬁcation”. The resume signaling (full-speed ‘K’) is

driven on the port as long as this bit remains set. Software must time the

resume and clear this bit after the correct amount of time has elapsed.

Clearing this bit causes the port to return to high-speed mode, forcing the

bus below the port into a high-speed idle. This bit will remain at logic 1, until

the port has switched to the high-speed idle. The Host Controller must

complete this transition within 2 ms of software clearing this bit.^[1]

5

4

OCC

OCA

Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a

change in overcurrent active. Software clears this bit by setting this bit to

logic 1.

Overcurrent Active: Default = 0. If set to logic 1, this port has an

overcurrent condition. If set to logic 0, this port does not have an overcurrent

condition. This bit will automatically change from logic 1 to logic 0 when the

overcurrent condition is removed.

3

2

PEDC

PED

Port Enable/Disable Change: Logic 1 means the port enabled/disabled

status has changed. Logic 0 means no change. Default = 0. For the root

hub, this bit gets set only when a port is disabled because of appropriate

conditions existing at the EOF2 point. For deﬁnition of port error, refer to

Chapter 11 of Ref. 8 “Universal Serial Bus Speciﬁcation”. Software clears

this bit by setting it.^[1]

Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable.

Default = 0. Ports can only be enabled by the Host Controller as a part of the

reset and enable sequence. Software cannot enable a port by writing logic 1

to this ﬁeld. The Host Controller will only set this bit when the reset

sequence determines that the attached device is a high-speed device. Ports

can be disabled by either a fault condition or by host software. The bit status

does not change until the port state has actually changed. There may be a

delay in disabling or enabling a port because of other Host Controller and

bus events. When the port is disabled, downstream propagation of data is

blocked on this port, except for reset.^[1]

1

ECSC

Connect Status Change: Logic 1 means change in ECCS (Current

Connect Status). Logic 0 means no change. Default = 0. This bit indicates a

change has occurred in the port’s ECCS (Current Connect Status). The

Host Controller sets this bit for all changes to the port device connect status,

even if system software has not cleared an existing connect status change.

For example, the insertion status changes twice before system software has

cleared the changed condition, hub hardware will be “setting” an already-set

bit, that is, the bit will remain set. Software clears this bit setting it.^[1]

0

ECCS

Current Connect Status: Logic 1 indicates a device is present on port.

Logic 0 indicates no device is present. Default = 0. This value reﬂects the

current state of the port and may not correspond directly to the event that

caused the ECSC (Connect Status Change) bit to be set.^[1]

[1] These ﬁelds read logic 0, if the Port Power (PP) (bit 12 in register PORTSC 1,2,3,4) is logic 0.

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

82 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

12. Current consumption

Table 120 shows the current consumption when two ports are active, that is, the

SEL2PORTS pin is connected to V_DD

.

Table 120. Current consumption when SEL2PORTS is HIGH

Cumulative current

Conditions

no devices connected to the ISP1561^[1]

Typ

151

181

209

98

Unit

mA

Total current on pins V_AUXplus AV_AUX

plus AV_{AUX_PLL}plus V_DD

one high-speed device connected to the ISP1561

two high-speed devices connected to the ISP1561

no devices connected to the ISP1561^[1]

Auxiliary current on pins V_AUXplus

AV_AUXplus AV_{AUX_PLL}

one high-speed device connected to the ISP1561

two high-speed devices connected to the ISP1561

no devices connected to the ISP1561^[1]

124

153

53

On pin V_DD

one high-speed device connected to the ISP1561

two high-speed devices connected to the ISP1561

56

[1] When one or two full-speed or low-speed power devices are connected, the current consumption is comparable with the current

consumption when no high-speed devices are connected. There is a difference of approximately 1 mA.

Table 121 shows the current consumption when four ports are active, that is, the

SEL2PORTS pin is connected to ground.

Table 121. Current consumption when SEL2PORTS is LOW

Cumulative current

Conditions

Typ

207

236

261

288

314

151

178

206

232

259

7

Unit

mA

Total current on pins V_AUXplus

AV_AUXplus AV_{AUX_PLL}plus V_DD

no devices connected to the ISP1561^[1]

one high-speed device connected to the ISP1561

two high-speed devices connected to the ISP1561

three high-speed devices connected to the ISP1561

four high-speed devices connected to the ISP1561

Auxiliary current on pins V_AUXplus no devices connected to the ISP1561^[1]

AV_AUXplus AV_{AUX_PLL}

one high-speed device connected to the ISP1561

two high-speed devices connected to the ISP1561

three high-speed devices connected to the ISP1561

four high-speed devices connected to the ISP1561

On pin AV_AUX

no devices connected to the ISP1561^[1]

one high-speed device connected to the ISP1561

two high-speed devices connected to the ISP1561

three high-speed devices connected to the ISP1561

four high-speed devices connected to the ISP1561

no devices connected to the ISP1561

33

58

84

108

3

On pin AV_{AUX_PLL}

one high-speed device connected to the ISP1561

two high-speed devices connected to the ISP1561

three high-speed devices connected to the ISP1561

four high-speed devices connected to the ISP1561

3

ISP1561_2

Product data sheet

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83 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 121. Current consumption when SEL2PORTS is LOW …continued

Cumulative current

Conditions

Typ

56

57

Unit

mA

On pin V_DD

no devices connected to the ISP1561

one high-speed device connected to the ISP1561

two high-speed devices connected to the ISP1561

three high-speed devices connected to the ISP1561

four high-speed devices connected to the ISP1561

[1] When one to four full-speed or low-speed power devices are connected, the current consumption is comparable with the current

consumption when no high-speed devices are connected. There is a difference of only about 3 mA.

Table 122. Current consumption: S1 and S3

Current consumption

Typ

Unit

mA

S1^[1]

S3^[2]

130

1.5^[3]

0.52^[4]

[1] S1 represents the system state that will determine the B1 and D1 states. For details, refer to Ref. 5 “PCI

Bus Power Management Interface Speciﬁcation”.

[2] S3 represents the system state that will determine the B3 and D3 states. For details, refer to Ref. 5 “PCI

Bus Power Management Interface Speciﬁcation”.

[3] When I²C-bus and legacy support are present.

[4] When I²C-bus and legacy support are not present.

ISP1561_2

Product data sheet

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84 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

13. Limiting values

Table 123. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_DD

Parameter

Conditions

Min

−0.5

Max

+4.6

Unit

V

supply voltage

auxiliary voltage

V_AUX

V

AV_AUX

analog auxiliary voltage (3.3 V);

supply voltage

V

AV_{AUX_PLL}analog auxiliary voltage (3.3 V);

supply voltage for PLL

−0.5

+4.6

V

[1]

[2]

V_I(5V)

V_I(3.3V)

I_lu

input voltage on 5 V buffers

input voltage on 3.3 V buffers

latch-up current

3.0 V < V_DD< 3.6 V

V_I< 0 V or V_I> V_CC

all pins (I_LI< 1 µA)

−0.5

-

+6.0

V

+4.6

V

100

mA

V

V_esd

electrostatic discharge voltage

−1000

−4000

+1000

+4000

on pins DM1 to DM4, DP1

to DP4, and all GND pins

(I_LI< 1 µA)

V

T_stg

storage temperature

−40

+125

°C

[1] Valid only when the supply voltage is present.

[2] Test method available on request.

14. Recommended operating conditions

Table 124. Recommended operating conditions

Symbol

V_DD

Parameter

Conditions

Min

3.0

Typ

3.3

Max

3.6

Unit

V

supply voltage

auxiliary voltage

V_AUX

V

AV_AUX

analog auxiliary voltage (3.3 V);

supply voltage

V

AV_{AUX_PLL}

analog auxiliary voltage (3.3 V);

supply voltage for PLL

3.0

3.3

3.6

V

[1]

V_I(5V)

V_I(3.3V)

T_amb

T_j

input voltage on 5 V buffers

input voltage on 3.3 V buffers

ambient temperature

0

-

5.5

V

0

V_DD

+85

+125

V

−40

°C

junction temperature

[1] Valid only when the supply voltage is present.

ISP1561_2

Product data sheet

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85 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

15. Static characteristics

Table 125. Static characteristics: I²C-bus interface (SDA and SCL)

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

V_IH

Parameter

Conditions

Min

2.1

-

Typ

Max

-

Unit

V

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

-

V_IL

0.9

-

V

V_hys

V_OL

0.15

-

V

LOW-level output voltage

I_OL= 3 mA

0.4

V

Table 126. Static characteristics: digital pins

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.^[1]

Symbol

V_IH

Parameter

Conditions

Min

2.0

-

Typ

Max

-

Unit

V

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

-

V_IL

0.8

0.7

0.4

-

V

V_hys

V_OL

0.4

-

V

LOW-level output voltage I_OL= 3 mA

HIGH-level output voltage

V

V_OH

2.4

V

[1] All pins are 5 V tolerant.

Table 127. Static characteristics: PCI interface block

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.^[1]

Symbol

V_IH

Parameter

Conditions

Min

2.0

0

Typ

Max

5.5

0.9

-

Unit

V

HIGH-level input voltage

LOW-level input voltage

input pull-up voltage

input leakage current

HIGH-level output voltage

LOW-level output voltage

input pin capacitance

CLK pin capacitance

IDSEL pin capacitance

-

V_IL

V

V_IPU

I_LI

2.1

−10

2.7

-

V

0 V < V_IN< V_DD

I_OUT= 500 µA

I_OUT= 1500 µA

+10

-

µA

V

V_OH

V_OL

0.3

10

12

8

V

C_IN

-

pF

C_CLK

C_IDSEL

5

-

[1] All pins are 5 V tolerant.

Table 128. Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4)

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input levels for high-speed

V_HSSQ

high-speed squelch detection

threshold voltage (differential signal

amplitude)

squelch detected

-

100

-

mV

no squelch

detected

150

ISP1561_2

Product data sheet

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ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 128. Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4) …continued

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_HSDSC

high-speed disconnect detection

disconnect

625

-

mV

threshold voltage (differential signal detected

amplitude)

disconnect not

-

525

mV

detected

V_HSCM

high-speed data signaling common

mode voltage range (guideline for

receiver)

−50

+500

Output levels for high-speed

V_HSOI

high-speed idle level voltage

−10

-

+10

440

mV

V_HSOH

high-speed data signaling

HIGH-level voltage

360

V_HSOL

high-speed data signaling LOW-level

voltage

−10

-

+10

mV

V_CHIRPJ

V_CHIRPK

chirp J level (differential voltage)

chirp K level (differential voltage)

700^[1]

−900^[1]

-

1100

mV

−500

Input levels for full-speed and low-speed

V_IH

HIGH-level input voltage

drive

2.0

2.7

-

V

V_IHZ

V_IL

HIGH-level input voltage (ﬂoating)

LOW-level input voltage

3.6

0.8

-

V_DI

differential input sensitivity

|V_DP− V_DM

|

0.2

0.8

V_CM

differential common mode voltage

range

2.5

Output levels for full-speed and low-speed

V_OH

HIGH-level output voltage

LOW-level output voltage

SE1 output voltage

2.8

0

-

3.6

0.3

-

V

V_OL

V_OSE1

V_CRS

0.8

1.3

output signal crossover voltage

2.0

[1] HS termination resistor disabled, pull-up resistor connected. Only during reset, when both hub and device are capable of high-speed

operation.

ISP1561_2

Product data sheet

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87 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

16. Dynamic characteristics

Table 129. Dynamic characteristics: system clock timing

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Crystal oscillator

[2]

f_clk

clock frequency

crystal^[1]

oscillator

-

12

48

-

MHz

External clock input

δ

clock duty cycle

-

50

-

%

External clock input

J

external clock jitter

-

50

3

ppm

ns

t_CR

t_CF

δ_clk

t_s

rise time

-

fall time

-

3

ns

clock duty factor

start-up time

50

5

-

%

10

ms

[1] Suggested values for external capacitors when using a crystal are 22 pF to 27 pF.

[2] Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. The oscillator should have 3.3 V power supply.

Table 130. Dynamic characteristics: I²C-bus interface (SDA and SCL)

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[3]

t_f

fall time

10 pF < C_B< 400 pF^[2]

-

0

250

ns

[1] All pins are 5 V tolerant.

[2] The bus capacitance (C_B) is speciﬁed in pF. To meet the speciﬁcation for V_OLand the maximum rise time (300 ns), use an external

pull-up resistor with R_max= 850 / C_BkΩ and R_min= (V_DD− 0.4) / 3 kΩ.

[3] Output fall time V_IHto V_IL.

Table 131. Dynamic characteristics: PCI interface block

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[3]

SR

slew rate

standard load^[2]

1

-

4

V/ns

[1] All pins are 5 V tolerant.

[2] Standard load is 10 pF together with a pull-up and pull-down resistor of 10 kΩ.

[3] Output slew rate (rise, fall).

Table 132. Dynamic characteristics: high-speed source electrical characteristics

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Driver characteristics

t_HSRrise time (10 % to 90 %)

t_HSFfall time (10 % to 90 %)

Parameter

Conditions

Min

Typ

Max

Unit

500

-

ps

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Table 132. Dynamic characteristics: high-speed source electrical characteristics …continued

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Z_HSDRV

driver output impedance

(which also serves as

high-speed termination)

includes the R_S

resistor

40.5

45

49.5

Ω

Clock timing

t_HSDRAT

high-speed data rate

microframe interval

479.76

124.9375

1

-

480.24

Mb/s

µs

t_HSFRAM

125.0625

t_HSRFI

consecutive microframe

interval difference

four

high-speed

bit times

ns

Table 133. Dynamic characteristics: full-speed source electrical characteristics

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_FR

rise time

fall time

C_L= 50 pF; 10 % to

4

-

20

ns

%

Ω

90 % of |V_OH− V_OL

|

t_FF

C_L= 50 pF; 90 % to

4

20

10 % of |V_OH− V_OL

|

t_FRFM

Z_DRV

differential rise and fall time

matching

90

28

111.1

44

driver output impedance for

driver which is not high-speed

capable

Data timing: see Figure 8

t_FDEOP

source jitter for differential

full-speed timing

low-speed timing

−2

-

5

ns

transition to SE0 transition

source SE0 interval of EOP

receiver SE0 interval of EOP

t_FEOPT

t_FEOPR

t_LDEOP

160

82

-

175

-

ns

upstream facing port source

jitter for differential transition to

SE0 transition

−40

100

t_LEOPT

t_LEOPR

t_FST

source SE0 interval of EOP

receiver SE0 interval of EOP

1.25

670

-

1.5

-

µs

ns

width of SE0 interval during

differential transition

14

Table 134. Dynamic characteristics: low-speed source electrical characteristics

V_DD= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_LR

transition time: rise time

75

90

-

300

125

ns

%

t_LF

transition time: fall time

t_LRFM

rise and fall time matching

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16.1 Timing

Table 135. PCI clock and IO timing

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

PCI clock timing; see Figure 5

T_cyc

CLK cycle time

CLK HIGH time

CLK LOW time

CLK slew rate

RST# slew rate

30

11

1

-

32

-

ns

t_high

ns

t_low

-

ns

SR_CLK

SR_RST#

4

-

V/ns

mV/ns

50

PCI input timing; see Figure 6

t_su

input set-up time to CLK - bused signals

7

-

ns

[1]

t_su(ptp)

t_h

input set-up time to CLK - point-to-point

input hold time from CLK

10

0

PCI output timing; see Figure 7

t_val

CLK to signal valid delay time - bused signals

2

-

11

12

-

ns

t_val(ptp)

t_on

CLK to signal valid delay time - point-to-point

ﬂoat to active delay time

t_off

active to ﬂoat delay time

28

PCI reset timing

t_rst-clkreset active time after CLK stable

t_rstreset active time after power stable

100

1

-

µs

ms

[1] REQ# and GNT# are point-to-point signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All others are bus signals.

T

cyc

t

LOW

HIGH

0.6V

0.5V

DD

minimum value

0.4V

0.3V

0.2V

DD

mbl341

Fig 5. PCI clock

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0.6V

DD

0.4V

CLK

DD

0.2V

DD

t

; t

su su(ptp)

t

h

0.6V

0.4V

0.2V

DD

input

delay

inputs valid

mbl344

Fig 6. PCI input timing

0.6V

DD

0.4V

0.2V

CLK

t

; t

val val(ptp)

0.615V

(falling edge)

(rising edge)

DD

output

delay

0.285V

DD

output

t

on

t

off

mbl345

Fig 7. PCI output timing

T

PERIOD

+3.3 V

crossover point

extended

crossover point

differential

data lines

0 V

differential data to

SE0/EOP skew

source EOP width: t

EOPT

receiver EOP width: t

N × T

+ t

EOPR

mgr776

PERIOD

DEOP

T_PERIODis the bit duration corresponding with the USB data rate.

Full-speed timing symbols have a subscript preﬁx ‘F’, low-speed timings a preﬁx ‘L’.

Fig 8. USB source differential data-to-EOP transition skew and EOP width

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17. Package outline

LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 14 x 1.4 mm

SOT420-1

y

X

A

96

97

65

64

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

pin 1 index

detail X

33

32

128

1

v

M

B

Z

A

w M

D

b

p

e

D

B

H

v

M

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.23 0.20 14.1 14.1

0.13 0.09 13.9 13.9

16.15 16.15

15.85 15.85

0.75

0.45

0.95 0.95

0.65 0.65

mm

1.6

0.25

1

0.2 0.07 0.08

0.4

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

99-11-03

03-02-20

SOT420-1

MS-026

Fig 9. Package outline SOT420-1 (LQFP128)

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18. Soldering

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

18.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

18.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus PbSn soldering

18.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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18.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 10) than a PbSn process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 136 and 137

Table 136. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 137. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 10.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 10. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

19. Abbreviations

Table 138. Abbreviations

Acronym

DID

Description

Device ID

EHCI

EMI

Enhanced Host Controller Interface

ElectroMagnetic interference

End-Of-Frame

EOF

HC

Host Controller

HCCA

HCD

HCI

Host Controller Communication Area

Host Controller Driver

Host Controller Interface

Open Host Controller Interface

Power Management Capabilities

Power Management Event

Power Management Control/Status

Universal Serial Bus

OHCI

PMC

PME

PMCSR

USB

VID

Vendor ID

20. References

[1] Designing a Hi-Speed USB Host PCI Adapter Using the ISP1561 — AN10006

[2] Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus —

Rev. 095

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[3] ISP1561 Evaluation Board User’s Guide — UM10005

[4] Open Host Controller Interface Speciﬁcation for USB — Rev. 1.0a

[5] PCI Bus Power Management Interface Speciﬁcation — Rev. 1.1

[6] PCI Local Bus Speciﬁcation — Rev. 2.2

[7] The I²C-bus Speciﬁcation — Version 2.1

[8] Universal Serial Bus Speciﬁcation — Rev. 2.0

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21. Revision history

Table 139. Revision history

Document ID

ISP1561_2

Release date

Data sheet status

Change notice

Supersedes

20070305

Product data sheet

-

ISP1561-01

Modiﬁcations:

• The format of this data sheet has been redesigned to comply with the new identity guidelines of

NXP Semiconductors.

• Legal texts have been adapted to the new company name where appropriate.

• Symbols and descriptions have been updated, wherever applicable, to comply with the new

identity guidelines of NXP Semiconductors.

• Updated Figure 1 “Block diagram”.

• Table 2 “Pin description”: updated description for XTAL1, XTAL2, GLn, PWEn, AMBn and GRNn.

Updated I/O detail of pin SERR#.

• Section 8.2.1.20 “TRDY Timeout register (R/W: 40h)” and Section 8.2.1.21 “Retry Timeout

register (R/W: 41h)”: added description.

• Table 23 “MIN_GNT register: bit description” and Table 24 “MAX_LAT register: but description”:

updated the access type from R/W to R.

• Section 11.4.8 “CONFIGFLAG register (address: content of the base address register + 4Ch)”:

corrected the address in the title from 5Ch to 4Ch.

• Table 119 “PORTSC 1, 2, 3, 4 register: bit description”: updated description for ﬁeld LS[1:0].

• Section 12 “Current consumption”: updated.

• Table 114 “ASYNCLISTADDR register: bit allocation” and Table 115 “ASYNCLISTADDR register:

bit description”: changed LPL[19:0] to LPL[26:0].

• Table 124 “Recommended operating conditions”: added T_j.

• Table 125 “Static characteristics: I²C-bus interface (SDA and SCL)” and Table 130 “Dynamic

characteristics: I²C-bus interface (SDA and SCL)”: updated table title.

• Table 129 “Dynamic characteristics: system clock timing”: updated.

• Table 135 “PCI clock and IO timing”: updated t_hand added the max value for T_cyc

.

ISP1561-01

20030206

Product data sheet

-

(9397 750 10015)

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22. Legal information

22.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

result in personal injury, death or severe property or environmental damage.

22.2 Deﬁnitions

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

22.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

22.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

GoodLink — is a trademark of NXP B.V.

I²C-bus — logo is a trademark of NXP B.V.

23. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

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24. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3. PCI conﬁguration space registers of OHCI1,

OHCI2 and EHCI . . . . . . . . . . . . . . . . . . . . . . .13

Table 48. HcCommandStatus register: bit description . . 39

Table 49. HcInterruptStatus register: bit allocation . . . . . 40

Table 50. HcInterruptStatus register: bit description . . . . 41

Table 51. HcInterruptEnable register: bit allocation . . . . 42

Table 52. HcInterruptEnable register: bit description . . . 42

Table 53. HcInterruptDisable register: bit allocation . . . . 43

Table 54. HcInterruptDisable register: bit description . . . 44

Table 55. HcHCCA register: bit allocation . . . . . . . . . . . . 45

Table 56. HcHCCA register: bit description . . . . . . . . . . 45

Table 57. HcPeriodCurrentED register: bit allocation . . . 45

Table 58. HcPeriodCurrentED register: bit description . . 46

Table 59. HcControlHeadED register: bit allocation . . . . 46

Table 60. HcControlHeadED register: bit description . . . 46

Table 61. HcControlCurrentED register: bit allocation . . 47

Table 62. HcControlCurrentED register: bit description . 47

Table 63. HcBulkHeadED register: bit allocation . . . . . . 47

Table 64. HcBulkHeadED register: bit description . . . . . 48

Table 65. HcBulkCurrentED register: bit allocation . . . . . 48

Table 66. HcBulkCurrentED register: bit description . . . 49

Table 67. HcDoneHead register: bit allocation . . . . . . . . 49

Table 68. HcDoneHead register: bit description . . . . . . . 49

Table 69. HcFmInterval register: bit allocation . . . . . . . . 50

Table 70. HcFmInterval register: bit description . . . . . . . 50

Table 71. HcFmRemaining register: bit allocation . . . . . 51

Table 72. HcFmRemaining register: bit description . . . . 51

Table 73. HcFmNumber register: bit allocation . . . . . . . . 51

Table 74. HcFmNumber register: bit description . . . . . . 52

Table 75. HcPeriodicStart register: bit allocation . . . . . . 52

Table 76. HcPeriodicStart register: bit description . . . . . 53

Table 77. HcLSThreshold register: bit allocation . . . . . . 53

Table 78. HcLSThreshold register: bit description . . . . . 54

Table 79. HcRhDescriptorA register: bit allocation . . . . . 54

Table 80. HcRhDescriptorA register: bit description . . . . 55

Table 81. HcRhDescriptorB register: bit allocation . . . . . 56

Table 82. HcRhDescriptorB register: bit description . . . . 56

Table 83. HcRhStatus register: bit allocation . . . . . . . . . 57

Table 84. HcRhStatus register: bit description . . . . . . . . 57

Table 85. HcRhPortStatus[1:4] register: bit allocation . . 58

Table 86. HCRhPortStatus[1:4] register: bit description . 59

Table 87. Legacy support registers . . . . . . . . . . . . . . . . . 62

Table 88. Emulated registers . . . . . . . . . . . . . . . . . . . . . 62

Table 89. HceControl register: bit allocation . . . . . . . . . . 62

Table 90. HceControl register: bit description . . . . . . . . . 63

Table 91. HceInput register: bit allocation . . . . . . . . . . . . 63

Table 92. HceInput register: bit description . . . . . . . . . . 64

Table 93. HceOutput register: bit allocation . . . . . . . . . . 64

Table 94. HceOutput register: bit description . . . . . . . . . 65

Table 95. HceStatus register: bit allocation . . . . . . . . . . . 65

Table 4. Vendor ID register: bit description . . . . . . . . . .14

Table 5. Device ID register: bit description . . . . . . . . . .14

Table 6. Command register: bit allocation . . . . . . . . . . .15

Table 7. Command register: bit description . . . . . . . . . .15

Table 8. Status register: bit allocation . . . . . . . . . . . . . .16

Table 9. Status register: bit description . . . . . . . . . . . . .17

Table 10. Revision ID register: bit description . . . . . . . . .18

Table 11. Class Code register: bit allocation . . . . . . . . . .18

Table 12. Class Code register: bit description . . . . . . . . .18

Table 13. CacheLine Size register: bit description . . . . .19

Table 14. Latency Timer register: bit description . . . . . . .19

Table 15. Header Type register: bit allocation . . . . . . . . .19

Table 16. Header Type register: bit description . . . . . . . .19

Table 17. BAR0 register: bit description . . . . . . . . . . . . .20

Table 18. Subsystem Vendor ID register: bit description .20

Table 19. Subsystem ID register: bit description . . . . . . .21

Table 20. Capabilities Pointer register: bit description . . .21

Table 21. Interrupt Line register: bit description . . . . . . .21

Table 22. Interrupt Pin register: bit description . . . . . . . .22

Table 23. MIN_GNT register: bit description . . . . . . . . . .22

Table 24. MAX_LAT register: but description . . . . . . . . .22

Table 25. EHCI-speciﬁc PCI registers . . . . . . . . . . . . . . .23

Table 26. SBRN register: bit description . . . . . . . . . . . . .23

Table 27. FLADJ register: bit allocation . . . . . . . . . . . . . .23

Table 28. FLADJ register: bit description . . . . . . . . . . . .23

Table 29. FLADJ value as a function of SOF cycle time .23

Table 30. PORTWAKECAP register: bit description . . . .24

Table 31. Power management registers . . . . . . . . . . . . .24

Table 32. CAP_ID register: bit description . . . . . . . . . . .24

Table 33. NEXT_ITEM_PTR register: bit description . . .25

Table 34. PMC register: bit allocation . . . . . . . . . . . . . . .25

Table 35. PMC register: bit description . . . . . . . . . . . . . .25

Table 36. PMCSR register: bit allocation . . . . . . . . . . . . .27

Table 37. PMCSR register: bit description . . . . . . . . . . .27

Table 38. PMCSR_BSE register: bit allocation . . . . . . . .28

Table 39. PMCSR_BSE register: bit description . . . . . . .28

Table 40. PCI bus power and clock control . . . . . . . . . . .29

Table 41. Data register: bit description . . . . . . . . . . . . . .29

Table 42. USB Host Controller registers . . . . . . . . . . . . .33

Table 43. HcRevision register: bit allocation . . . . . . . . . .35

Table 44. HcRevision register: bit description . . . . . . . . .36

Table 45. HcControl register: bit allocation . . . . . . . . . . .36

Table 46. HcControl register: bit description . . . . . . . . . .37

Table 47. HcCommandStatus register: bit allocation . . .39

continued >>

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

99 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

Table 96. HceStatus register: bit description . . . . . . . . . .65

Table 97. CAPLENGTH/HCIVERSION register: bit

Table 137.Lead-free process (from J-STD-020C) . . . . . . 94

Table 138.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Table 139.Revision history . . . . . . . . . . . . . . . . . . . . . . . . 97

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 98. CAPLENGTH/HCIVERSION register: bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 99. HCSPARAMS register: bit allocation . . . . . . . .67

Table 100.HCSPARAMS register: bit description . . . . . . .67

Table 101.HCCPARAMS register: bit allocation . . . . . . . .68

Table 102.HCCPARAMS register: bit description . . . . . . .69

Table 103.USBCMD register: bit allocation . . . . . . . . . . .69

Table 104.USBCMD register: bit description . . . . . . . . . .70

Table 105.USBSTS register: bit allocation . . . . . . . . . . . .72

Table 106.USBSTS register: bit description . . . . . . . . . . .72

Table 107.USBINTR register: bit allocation . . . . . . . . . . .74

Table 108.USBINTR register: bit description . . . . . . . . . .74

Table 109.FRINDEX register: bit allocation . . . . . . . . . . .75

Table 110.FRINDEX register: bit description . . . . . . . . . .76

Table 111.N based value of FLS[1:0] . . . . . . . . . . . . . . . .76

Table 112.PERIODICLISTBASE register: bit allocation . .77

Table 113.PERIODICLISTBASE register: bit description .77

Table 114.ASYNCLISTADDR register: bit allocation . . . .77

Table 115.ASYNCLISTADDR register: bit description . . .78

Table 116.CONFIGFLAG register: bit allocation . . . . . . .78

Table 117.CONFIGFLAG register: bit description . . . . . .78

Table 118.PORTSC 1, 2, 3, 4 register: bit allocation . . . .79

Table 119.PORTSC 1, 2, 3, 4 register: bit description . . .79

Table 120.Current consumption when SEL2PORTS is

HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 121.Current consumption when SEL2PORTS is

LOW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 122.Current consumption: S1 and S3 . . . . . . . . . . .84

Table 123.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 124.Recommended operating conditions . . . . . . . .85

Table 125.Static characteristics: I²C-bus interface (SDA

and SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 126.Static characteristics: digital pins . . . . . . . . . . .86

Table 127.Static characteristics: PCI interface block . . . .86

Table 128.Static characteristics: USB interface block

(pins DM1 to DM4 and DP1 to DP4) . . . . . . . .86

Table 129.Dynamic characteristics: system clock timing .88

Table 130.Dynamic characteristics: I²C-bus interface

(SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .88

Table 131.Dynamic characteristics: PCI interface block . .88

Table 132.Dynamic characteristics: high-speed source

electrical characteristics . . . . . . . . . . . . . . . . .88

Table 133.Dynamic characteristics: full-speed source

electrical characteristics . . . . . . . . . . . . . . . . .89

Table 134.Dynamic characteristics: low-speed source

electrical characteristics . . . . . . . . . . . . . . . . .89

Table 135.PCI clock and IO timing . . . . . . . . . . . . . . . . . .90

Table 136.SnPb eutectic process (from J-STD-020C) . . .94

continued >>

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

100 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

25. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin conﬁguration . . . . . . . . . . . . . . . . . . . . . . . . . .5

Fig 3. EEPROM connection diagram. . . . . . . . . . . . . . .30

Fig 4. Information loading from EEPROM . . . . . . . . . . .31

Fig 5. PCI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

Fig 6. PCI input timing . . . . . . . . . . . . . . . . . . . . . . . . . .91

Fig 7. PCI output timing . . . . . . . . . . . . . . . . . . . . . . . . .91

Fig 8. USB source differential data-to-EOP transition

skew and EOP width . . . . . . . . . . . . . . . . . . . . . .91

Fig 9. Package outline SOT420-1 (LQFP128) . . . . . . . .92

Fig 10. Temperature proﬁles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

continued >>

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

101 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

26. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.2.2

Enhanced Host Controller-speciﬁc PCI

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SBRN register (address: 60h) . . . . . . . . . . . . 23

FLADJ register (address: 61h). . . . . . . . . . . . 23

PORTWAKECAP register (address: 62h) . . . 24

Power management registers. . . . . . . . . . . . . 24

CAP_ID register (address: value read from

address 34h + 0h) . . . . . . . . . . . . . . . . . . . . . 24

NEXT_ITEM_PTR register (address: value

read from address 34h + 1h) . . . . . . . . . . . . . 25

PMC register (address: value read from

address 34h + 2h) . . . . . . . . . . . . . . . . . . . . . 25

PMCSR register (address: value read from

address 34h + 4h) . . . . . . . . . . . . . . . . . . . . . 26

PMCSR_BSE register (address: value read

from address 34h + 6h) . . . . . . . . . . . . . . . . . 28

Data register (address: value read from

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

8.2.2.1

8.2.2.2

8.2.2.3

8.2.3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

8.2.3.1

8.2.3.2

8.2.3.3

8.2.3.4

8.2.3.5

8.2.3.6

7

Functional description . . . . . . . . . . . . . . . . . . 11

OHCI Host Controller . . . . . . . . . . . . . . . . . . . 11

EHCI Host Controller . . . . . . . . . . . . . . . . . . . 11

Dynamic port-routing logic . . . . . . . . . . . . . . . 11

Hi-Speed USB analog transceivers . . . . . . . . 11

LED indicators for downstream ports . . . . . . . 11

Power management . . . . . . . . . . . . . . . . . . . . 12

Legacy support. . . . . . . . . . . . . . . . . . . . . . . . 12

Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . 12

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

address 34h + 7h) . . . . . . . . . . . . . . . . . . . . . 29

9

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 30

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Hardware connections . . . . . . . . . . . . . . . . . . 30

Information loading from EEPROM . . . . . . . . 31

8

8.1

8.1.1

8.1.2

8.2

8.2.1

8.2.1.1

8.2.1.2

8.2.1.3

8.2.1.4

8.2.1.5

8.2.1.6

8.2.1.7

8.2.1.8

8.2.1.9

PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PCI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 12

PCI conﬁguration space . . . . . . . . . . . . . . . . . 12

PCI initiator and target . . . . . . . . . . . . . . . . . . 13

PCI conﬁguration registers . . . . . . . . . . . . . . . 13

PCI conﬁguration header registers . . . . . . . . . 14

Vendor ID register (address: 00h). . . . . . . . . . 14

Device ID register (address: 02h). . . . . . . . . . 14

Command register (address: 04h) . . . . . . . . . 15

Status register (address: 06h) . . . . . . . . . . . . 16

Revision ID register (address: 08h) . . . . . . . . 18

Class Code register (address: 09h) . . . . . . . . 18

CacheLine Size register (address: 0Ch). . . . . 19

Latency Timer register (address: 0Dh) . . . . . . 19

Header Type register (address: 0Eh) . . . . . . . 19

9.1

9.2

9.3

10

10.1

10.2

Power management. . . . . . . . . . . . . . . . . . . . . 31

PCI bus power states . . . . . . . . . . . . . . . . . . . 31

USB bus states . . . . . . . . . . . . . . . . . . . . . . . 32

11

11.1

USB Host Controller registers . . . . . . . . . . . . 32

OHCI USB Host Controller operational

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

HcRevision register (address: content of the

base address register + 00h) . . . . . . . . . . . . . 35

HcControl register (address: content of the

base address register + 04h) . . . . . . . . . . . . . 36

HcCommandStatus register (address: content

of the base address register + 08h) . . . . . . . . 38

HcInterruptStatus register (address: content

of the base address register + 0Ch). . . . . . . . 40

HcInterruptEnable register (address: content

of the base address register + 10h) . . . . . . . . 41

HcInterruptDisable register (address: content

of the base address register + 14h) . . . . . . . . 43

HcHCCA register (address: content of the

11.1.1

11.1.2

11.1.3

11.1.4

11.1.5

11.1.6

11.1.7

11.1.8

11.1.9

8.2.1.10 BIST register (address: 0Fh) . . . . . . . . . . . . . 20

8.2.1.11 Base Address registers. . . . . . . . . . . . . . . . . . 20

8.2.1.12 CardBus CIS Pointer register (address: 28h) . 20

8.2.1.13 Subsystem Vendor ID register (address: 2Ch) 20

8.2.1.14 Subsystem ID register (address: 2Eh) . . . . . . 21

8.2.1.15 Expansion ROM Base Address register

(address: 30h). . . . . . . . . . . . . . . . . . . . . . . . . 21

8.2.1.16 Capabilities Pointer register (address: 34h) . . 21

8.2.1.17 Interrupt Line register (address: 3Ch). . . . . . . 21

8.2.1.18 Interrupt Pin register (address: 3Dh) . . . . . . . 22

8.2.1.19 MIN_GNT and MAX_LAT registers (address:

3Eh and 3Fh) . . . . . . . . . . . . . . . . . . . . . . . . . 22

base address register + 18h) . . . . . . . . . . . . . 44

HcPeriodCurrentED register (address: content

of the base address register + 1Ch). . . . . . . . 45

HcControlHeadED register (address: content

of the base address register + 20h) . . . . . . . . 46

8.2.1.20 TRDY Timeout register (R/W: 40h). . . . . . . . . 22

8.2.1.21 Retry Timeout register (R/W: 41h) . . . . . . . . . 22

continued >>

ISP1561_2

Product data sheet

Rev. 02 — 5 March 2007

102 of 103

ISP1561

NXP Semiconductors

HS USB PCI Host Controller

11.1.10 HcControlCurrentED register (address: content

of the base address register + 24h) . . . . . . . . 47

11.1.11 HcBulkHeadED register (address: content of

the base address register + 28h) . . . . . . . . . . 47

11.1.12 HcBulkCurrentED register (address: content

of the base address register + 2Ch) . . . . . . . . 48

11.1.13 HcDoneHead register (address: content of

the base address register + 30h) . . . . . . . . . . 49

11.1.14 HcFmInterval register (address: content of

the base address register + 34h) . . . . . . . . . . 50

11.1.15 HcFmRemaining register (address: content of

the base address register + 38h) . . . . . . . . . . 51

11.1.16 HcFmNumber register (address: content of

the base address register + 3Ch) . . . . . . . . . . 51

11.1.17 HcPeriodicStart register (address: content of

the base address register + 40h) . . . . . . . . . . 52

11.1.18 HcLSThreshold register (address: content of

the base address register + 44h) . . . . . . . . . . 53

11.1.19 HcRhDescriptorA register (address: content of

the base address register + 48h) . . . . . . . . . . 54

11.1.20 HcRhDescriptorB register (address: content of

the base address register + 4Ch) . . . . . . . . . . 55

11.1.21 HcRhStatus register (address: content of the

base address register + 50h) . . . . . . . . . . . . . 56

11.1.22 HcRhPortStatus[1:4] register (address: content

of the base address register + 54h) . . . . . . . . 58

11.4.4

11.4.5

11.4.6

11.4.7

11.4.8

11.4.9

FRINDEX register (address: content of the

base address register + 18h) . . . . . . . . . . . . . 75

CTRLDSSEGMENT register (address: content

of the base address register + 1Ch). . . . . . . . 76

PERIODICLISTBASE register (address:

content of the base address register + 20h). . 76

ASYNCLISTADDR register (address: content

of the base address register + 24h) . . . . . . . . 77

CONFIGFLAG register (address: content of

the base address register + 4Ch). . . . . . . . . . 78

PORTSC registers 1, 2, 3, 4 (address: content

of the base address register + 50h + (4 times

Port Number - 1)) where Port Number is 1, 2,

3,...N_Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 79

12

Current consumption . . . . . . . . . . . . . . . . . . . 83

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 85

Recommended operating conditions . . . . . . 85

Static characteristics . . . . . . . . . . . . . . . . . . . 86

Dynamic characteristics. . . . . . . . . . . . . . . . . 88

Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 92

13

14

15

16

16.1

17

18

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Introduction to soldering. . . . . . . . . . . . . . . . . 93

Wave and reﬂow soldering . . . . . . . . . . . . . . . 93

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 93

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 94

18.1

18.2

18.3

18.4

11.2

11.2.1

USB legacy support registers. . . . . . . . . . . . . 61

HceControl register (address: content of the

base address register + 100h) . . . . . . . . . . . . 62

HceInput register (address: content of the

base address register + 104h) . . . . . . . . . . . . 63

HceOutput register (address: content of the

base address register + 108h) . . . . . . . . . . . . 64

HceStatus register (address: content of the

base address register + 10Ch) . . . . . . . . . . . . 65

EHCI controller capability registers. . . . . . . . . 66

CAPLENGTH/HCIVERSION register

19

20

21

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 95

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Revision history . . . . . . . . . . . . . . . . . . . . . . . 97

11.2.2

11.2.3

11.2.4

22

Legal information . . . . . . . . . . . . . . . . . . . . . . 98

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 98

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 98

22.1

22.2

22.3

22.4

11.3

11.3.1

23

24

25

26

Contact information . . . . . . . . . . . . . . . . . . . . 98

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

(address: content of the base address

register + 00h) . . . . . . . . . . . . . . . . . . . . . . . . 66

HCSPARAMS register (address: content of

the base address register + 04h) . . . . . . . . . . 67

HCCPARAMS register (address: content of

the base address register + 08h) . . . . . . . . . . 68

Operational registers of enhanced USB Host

Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

USBCMD register (address: content of the

base address register + 0Ch) . . . . . . . . . . . . . 69

USBSTS register (address: content of the

base address register + 10h) . . . . . . . . . . . . . 72

USBINTR register (address: content of the

base address register + 14h) . . . . . . . . . . . . . 74

11.3.2

11.3.3

11.4

11.4.1

11.4.2

11.4.3

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 5 March 2007

Document identifier: ISP1561_2


型号：	ISP1561BM,551
厂家：	NXP
描述：	IC UNIVERSAL SERIAL BUS CONTROLLER, PQFP128, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-420-1, LQFP-128, Bus Controller 时钟 PC 外围集成电路
文件：	总104页 (文件大小：482K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1561BM,551 [NXP]

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