ISP1564HL,551_技术文档

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ISP1564

Hi-Speed USB PCI host controller

Rev. 02 — 13 November 2008

Product data sheet

1. General description

The ISP1564 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal

Serial Bus (USB) host controller. It integrates one Original USB Open Host Controller

Interface (OHCI) core, one Hi-Speed USB Enhanced Host Controller Interface (EHCI)

core, and two transceivers that are compliant with Hi-Speed USB and Original USB. The

functional parts of the ISP1564 are fully compliant with Universal Serial Bus Speciﬁcation

Rev. 2.0, Open Host Controller Interface Speciﬁcation for USB Rev. 1.0a, Enhanced Host

Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0, PCI Local Bus

Speciﬁcation Rev. 2.2, and PCI Bus Power Management Interface Speciﬁcation Rev. 1.1.

The ISP1564 is pin-to-pin and function compatible with the NXP ISP1562, subject to the

structure of the software.

Integrated high performance USB transceivers allow the ISP1564 to handle all Hi-Speed

USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s). The ISP1564 provides two downstream ports, allowing simultaneous

connection of USB devices at different speeds.

The ISP1564 is fully compatible with various operating system drivers, such as Microsoft

Windows standard OHCI and EHCI drivers that are present in Windows XP,

Windows 2000 and Red Hat Linux.

The ISP1564 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source

3.3 V.

The ISP1564 is ideally suited for use in Hi-Speed USB mobile applications and embedded

solutions.

2. Features

I Complies with Universal Serial Bus Speciﬁcation Rev. 2.0

I Complies with PCI Local Bus Speciﬁcation Rev. 2.2

I Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and

low-speed (1.5 Mbit/s)

I One Original USB OHCI core is compliant with Open Host Controller Interface

Speciﬁcation for USB Rev. 1.0a

I One Hi-Speed USB EHCI core is compliant with Enhanced Host Controller Interface

Speciﬁcation for Universal Serial Bus Rev. 1.0

ISP1564

NXP Semiconductors

HS USB PCI host controller

I Supports PCI 32-bit, 33 MHz interface compliant with PCI Local Bus Speciﬁcation

Rev. 2.2, with support for D3_coldstandby and wake-up modes; all I/O pins are 3.3 V

standard

I Compliant with PCI Bus Power Management Interface Speciﬁcation Rev. 1.1 for all

hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3_hotand D3_cold

I CLKRUN support for mobile applications, such as internal notebook design

I Conﬁgurable subsystem ID and subsystem vendor ID through external EEPROM

I External EEPROM can be programmed using the external PCI interface; refer to

Appendix I of PCI Local Bus Speciﬁcation Rev. 2.2

I Digital and analog power separation for better ElectroMagnetic Interference (EMI) and

ElectroStatic Discharge (ESD) protection

I Supports hot Plug and Play and remote wake-up of peripherals

I Supports individual power switching and individual overcurrent protection for

downstream ports

I Supports partial dynamic port-routing capability for downstream ports that allows

sharing of the same physical downstream ports between the Original USB host

controller and the Hi-Speed USB host controller

I Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions

I Supports dual power supply: PCI V_aux(3V3)and V_CC

I Operates at +3.3 V power supply input

I Low power consumption

I Full industrial operating temperature range from −40 °C to +85 °C

I Available in LQFP100 and TFBGA100 packages

3. Applications

I Digital consumer appliances:

N Portable consumer

N Home entertainment

I Notebook

I PCI add-on card

I PC motherboard

4. Ordering information

Table 1.

Ordering information

Type number

Package

Name

Description

Pitch

Version

ISP1564HL

ISP1564ET

LQFP100

plastic low proﬁle quad ﬂat package; 100 leads;

body 14 × 14 × 1.4 mm

0.5 mm

SOT407-1

TFBGA100

plastic thin ﬁne-pitch ball grid array package; 100 balls; 0.8 mm

SOT926-1

body 9 × 9 × 0.7 mm

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

2 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

6. Pinning information

6.1 Pinning

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

GNDA

XTAL2

2

AUX(1V8)

XTAL1

3

V

AUX(1V8)

GNDA

CC(AUX)

4

INTA#

5

RST#

V

CC(IO)

6

SYS_TUNE

CLK

AD[0]

AD[1]

7

8

GNT#

AD[2]

9

REQ#

AD[3]

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

AD[31]

AD[4]

V

AD[5]

CC(IO)

AD[30]

AD[29]

AD[28]

AD[27]

GND

ISP1564HL

AD[6]

AD[7]

GNDA

C/BE[0]#

AD[8]

V

CC(REG)

GNDA

REG(1V8)

GND

REG(1V8)

AD[9]

AD[26]

AD[25]

AD[24]

C/BE[3]#

IDSEL

AD[10]

V

CC(IO)

AD[11]

AD[12]

52 AD[13]

51

V

AD[14]

CC(IO)

004aaa791

Fig 2. Pin conﬁguration LQFP100 (top view)

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

4 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

ball A1

index area

ISP1564ET

1

2

3

4

5

6

7

8

9

10

A

B

C

D

E

F

G

H

J

K

004aaa815

Transparent top view

Fig 3. Pin conﬁguration TFBGA100 (top view)

6.2 Pin description

Table 2.

Pin description

Symbol^[1]

Type^[2]Description

LQFP100 TFBGA100

GNDA

1

2

B1

C2

-

analog ground

AUX(1V8)

1.8 V auxiliary output voltage; only for voltage conditioning; cannot be

used to supply power to external components; see Section 7.8

V_CC(AUX)

INTA#

3

4

C1

D1

-

auxiliary supply voltage; see Section 7.8

PCI interrupt

O

PCI pad; 3.3 V signaling; open-drain

RST#

5

C3

I

PCI reset; used to bring PCI-speciﬁc registers, sequencers and signals

to a consistent state

3.3 V input pad; CMOS

SYS_TUNE

CLK

6

7

C6

D2

I

used for system tuning; for connection details, see Section 11.4 and

Table 118

PCI system clock; see Table 128

PCI pad; 3.3 V signaling

GNT#

REQ#

8

9

D3

D4

I

PCI grant; indicates to the agent that access to the bus is granted

PCI pad; 3.3 V signaling

O

PCI request; indicates to the arbitrator that the agent wants to use the

bus

PCI pad; 3.3 V signaling

AD[31]

10

E1

I/O

bit 31 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

V_CC(IO)

AD[30]

11

12

E2

E3

-

I/O pads supply voltage; see Section 7.8

bit 30 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

I/O

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

5 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 2.

Pin description …continued

Symbol^[1]

Type^[2]Description

LQFP100 TFBGA100

AD[29]

AD[28]

AD[27]

13

14

15

E4

E5

F3

I/O

bit 29 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 28 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 27 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

V_CC(REG)

GNDA

16

17

18

F1

G1

G2

-

regulator supply voltage; see Section 7.8

analog ground

REG(1V8)

1.8 V regulator output voltage; only for voltage conditioning; cannot be

used to supply power to external components; see Section 7.8

GND

19

20

F4

F2

-

ground

AD[26]

I/O

bit 26 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

AD[25]

AD[24]

C/BE[3]#

IDSEL

21

22

23

24

G3

H1

H2

J1

I/O

I

bit 25 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 24 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

byte 3 of multiplexed PCI bus command and byte enable

PCI pad; 3.3 V signaling

PCI initialization device select; used as a chip select during conﬁguration

read and write transactions

PCI pad; 3.3 V signaling

V_CC(IO)

AD[23]

25

26

J2

-

I/O pads supply voltage; see Section 7.8

bit 23 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

K1

I/O

AD[22]

AD[21]

AD[20]

AD[19]

AD[18]

27

28

29

30

31

K2

H3

J3

I/O

bit 22 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 21 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 20 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

K3

G4

bit 19 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 18 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

GND

32

33

H4

J4

-

ground

AD[17]

I/O

bit 17 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

AD[16]

34

K4

I/O

bit 16 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

6 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 2.

Pin description …continued

Symbol^[1]

Type^[2]Description

LQFP100 TFBGA100

C/BE[2]#

FRAME#

35

F5

I/O

byte 2 of multiplexed PCI bus command and byte enable

PCI pad; 3.3 V signaling

36

G5

PCI cycle frame; driven by the master to indicate the beginning and

duration of an access

PCI pad; 3.3 V signaling

IRDY#

37

38

39

H5

J5

I/O

PCI initiator ready; indicates the ability of the initiating agent to complete

the current data phase of a transaction

PCI pad; 3.3 V signaling

TRDY#

PCI target ready; indicates the ability of the target agent to complete the

current data phase of a transaction

PCI pad; 3.3 V signaling

DEVSEL#

H6

PCI device select; indicates if any device is selected on the bus

PCI pad; 3.3 V signaling

V_CC(IO)

STOP#

40

41

K5

G6

-

I/O pads supply voltage; see Section 7.8

I/O

PCI stop; indicates that the current target is requesting the master to

stop the current transaction

PCI pad; 3.3 V signaling

CLKRUN#

42

K6

I/O

PCI CLKRUN signal; pull down to ground through a 10 kΩ resistor

PCI pad; 3.3 V signaling; open-drain

REG(1V8)

PERR#

43

44

J6

J7

-

1.8 V regulator output voltage; only for voltage conditioning; cannot be

used to supply power to external components; see Section 7.8

I/O

PCI parity error; used to report data parity errors during all PCI

transactions, except a special cycle

PCI pad; 3.3 V signaling

SERR#

45

J8

O

PCI system error; used to report address parity errors and data parity

errors on the Special Cycle command, or any other system error in

which the result will be catastrophic

PCI pad; 3.3 V signaling; open-drain

analog ground

GNDA

PAR

46

47

K7

K8

-

I/O

PCI parity

PCI pad; 3.3 V signaling

C/BE[1]#

48

K9

I/O

byte 1 of multiplexed PCI bus command and byte enable

PCI pad; 3.3 V signaling

GND

49

50

H7

-

ground

AD[15]

K10

I/O

bit 15 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

AD[14]

AD[13]

AD[12]

51

52

53

J10

H10

H9

I/O

bit 14 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 13 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 12 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

7 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 2.

Pin description …continued

Symbol^[1]

Type^[2]Description

LQFP100 TFBGA100

AD[11]

54

H8

I/O

bit 11 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

V_CC(IO)

AD[10]

55

56

J9

-

I/O pads supply voltage; see Section 7.8

G7

I/O

bit 10 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

AD[9]

57

G8

I/O

bit 9 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

REG(1V8)

AD[8]

58

59

G9

-

1.8 V regulator output voltage; only for voltage conditioning; cannot be

used to supply power to external components; see Section 7.8

F10

I/O

bit 8 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

C/BE[0]#

60

F6

I/O

byte 0 of multiplexed PCI bus command and byte enable

PCI pad; 3.3 V signaling

GNDA

AD[7]

61

62

G10

F9

-

analog ground

I/O

bit 7 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

AD[6]

63

F8

I/O

bit 6 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

GND

64

65

F7

E7

-

ground

AD[5]

I/O

bit 5 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

AD[4]

AD[3]

AD[2]

AD[1]

AD[0]

66

67

68

69

70

E8

I/O

bit 4 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

E10

D10

D9

bit 3 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 2 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

bit 1 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

D8

bit 0 of multiplexed PCI address and data

PCI pad; 3.3 V signaling

V_CC(IO)

71

72

73

E9

-

I/O pads supply voltage; see Section 7.8

analog ground

GNDA

C10

B9

AUX(1V8)

1.8 V auxiliary output voltage; only for voltage conditioning; cannot be

used to supply power to external components; see Section 7.8

XTAL1

XTAL2

GND

74

75

76

77

78

B10

A10

C8

AI

crystal oscillator input; this can also be a 12 MHz clock input at 1.8 V

crystal oscillator output (12 MHz); leave open when clock is used

ground

AO

-

I

V_CC(IO)AUX

OC1_N

A9

I/O pads auxiliary supply voltage; see Section 7.8

C9

overcurrent sense input for the USB downstream port 1 (digital); when

not in use, connect this pin to 3.3 V

3.3 V input pad; CMOS

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

8 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 2.

Pin description …continued

Symbol^[1]

Type^[2]Description

LQFP100 TFBGA100

PWE1_N

79

D7

O

power enable for the USB downstream port 1

3.3 V output pad; 3 ns slew rate control; CMOS; open-drain

GND_RREF

RREF

80

81

82

83

A8

B8

C7

A7

-

ground for external resistor on pin RREF

analog connection for the external resistor (11 kΩ ± 1 %)

analog ground

AI/O

-

GNDA

DM1

AI/O

D−; analog connection for the USB downstream port 1; pull down to

ground through a 15 kΩ resistor, even when the port is not used

GNDA

DP1

84

85

B7

A6

-

analog ground

AI/O

D+; analog connection for the USB downstream port 1; pull down to

ground through a 15 kΩ resistor, even when the port is not used

V_CCA(AUX)

OC2_N

86

87

B6

E6

-

I

auxiliary analog supply voltage; see Section 7.8

overcurrent sense input for the USB downstream port 2 (digital); when

not in use, connect this pin to 3.3 V

3.3 V input pad; CMOS

PWE2_N

88

D6

O

power enable for the USB downstream port 2

3.3 V output pad; 3 ns slew rate control; CMOS; open-drain

analog ground

GNDA

DM2

89

90

C5

A5

-

AI/O

D−; analog connection for the USB downstream port 2; pull down to

ground through a 15 kΩ resistor, even when the port is not used

GNDA

DP2

91

92

B5

A4

-

analog ground

AI/O

D+; analog connection for the USB downstream port 2; pull down to

ground through a 15 kΩ resistor, even when the port is not used

V_CCA(AUX)

GND

93

94

95

96

B4

B2

D5

B3

-

auxiliary analog supply voltage; see Section 7.8

ground

-

GND

-

ground

SCL

I/O

I²C-bus clock; pull up to 3.3 V through a 10 kΩ resistor^[3]

I²C-bus pad; clock signal

SDA

97

A3

I/O

I²C-bus data; pull up to 3.3 V through a 10 kΩ resistor^[3]

I²C-bus pad; data signal

V_CC(IO)AUX

PME#

98

99

A2

A1

-

I/O pads auxiliary supply voltage; see Section 7.8

O

PCI Power Management Event; used by a device to request a change in

the device or system power state

PCI pad; 3.3 V signaling; open-drain

V_CC(IO)AUX

100

C4

-

I/O pads auxiliary supply voltage; see Section 7.8

[1] Symbol names ending with # represent active LOW signals for PCI pins, for example: NAME#. Symbol names ending with underscore N

represent active LOW signals for USB pins, for example: NAME_N.

[2] I = input; O = output; I/O = input/output; AI/O = analog input/output; AI = analog input; AO = analog output.

[3] Connect to ground if I²C-bus is not used.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

9 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

7. Functional description

7.1 OHCI host controller

An OHCI host controller per port transfers data to devices at the Original USB deﬁned bit

rate of 12 Mbit/s or 1.5 Mbit/s.

7.2 EHCI host controller

The EHCI host controller transfers data to a Hi-Speed USB compliant device at the

Hi-Speed USB deﬁned bit rate of 480 Mbit/s. When the EHCI host controller has the

ownership of a port, OHCI host controllers are not allowed to modify the port register. All

additional port bit deﬁnitions required for the enhanced host controller are not visible to

the OHCI host controller.

7.3 Dynamic port-routing logic

The port-routing feature allows sharing of the same physical downstream ports between

the Original USB host controller and the Hi-Speed USB host controller. This requirement

of Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0

provides ports that are multiplexed with the ports of the OHCI.

The EHCI is responsible for the port-routing switching mechanism. Two register bits are

used for ownership switching. During power-on and system reset, the default ownership of

all downstream ports is the OHCI. The enhanced Host Controller Driver (HCD) controls

the ownership during normal functionality.

7.4 Hi-Speed USB analog transceivers

The Hi-Speed USB analog transceivers directly interface to the USB cables through

integrated termination resistors. These transceivers can transmit and receive serial data

at all data rates: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed

(1.5 Mbit/s).

7.5 Power management

The ISP1564 provides an advanced power management capability interface that is

compliant with PCI Bus Power Management Interface Speciﬁcation Rev. 1.1. Power is

controlled and managed by the interaction between drivers and PCI registers.

For a detailed description on power management, see Section 10.

7.6 Phase-Locked Loop (PLL)

A 12 MHz-to-30 MHz and 48 MHz clock multiplier PLL is integrated on-chip. This allows

the use of a low-cost 12 MHz crystal, which also minimizes EMI.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

10 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

7.7 Power-On Reset (POR)

Figure 4 shows a possible curve of V_I(VAUX3V3)and V_I(VREG3V3)with dips at t2 to t3 and

t4 to t5. At t0, POR will start with 1. At t1, the detector passes through the trip level.

Another delay will be added before POR drops to 0 to ensure that the length of the

generated detector pulse, POR, is large enough to reset asynchronous ﬂip-ﬂops. If the dip

is too short (t4 to t5 < 11 µs), POR will not react and will stay LOW.

V

I(VAUX3V3), I(VREG3V3)

V

POR(trip)

t4

t0

t1

t3

t5

t2

POR

004aab194

V_POR(trip)is typically 0.9 V.

Fig 4. Power-on reset

7.8 Power supply

Figure 5 shows the ISP1564 power supply connection.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

11 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

V

CC(REG)

16

PCI 3.3 V

100 nF

V

CC(IO)

11, 25,

40, 55, 71

PCI 3.3 V

100 nF

CC(AUX)

(1)

PCI V

3

aux(3V3)

100 nF

ISP1564

CC(IO)AUX

(1)

77, 98, 100

PCI V

aux(3V3)

100 nF

V

CCA(AUX)

(1)

86, 93

aux(3V3)

19, 32, 49,

GND

(3)

64, 76,

94, 95

AUX(1V8)

2, 73

(2)(4)

100 nF

4.7 µF

GND_RREF

80

REG(1V8)

18, 43, 58

5

(2)( )

100 nF

4.7 µF

1, 17, 46,

61, 72, 82,

84, 89, 91

004aaa792

GNDA

Remark: The 100 nF capacitor is needed on each individual pin, and is not shared among the

listed pins.

Remark: The ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

(1) If V_aux(3V3)is not present on PCI, the pin must be connected to PCI 3.3 V.

(2) This electrolytic or tantalum capacitor must be of LOW ESR type (0.2 Ω to 2 Ω).

(3) The use of ferrite bead is optional. Can be directly tied to ground.

(4) This electrolytic or tantalum capacitor is needed only on pin 2.

(5) This electrolytic or tantalum capacitor is needed only on pin 18.

Fig 5. Power supply connection

8. PCI

8.1 PCI interface

The PCI interface has two functions. Function #0 is for the OHCI host controller and

function #2 is for the EHCI host controller. These functions support both master and target

accesses, and share the same PCI interrupt signal INTA#. These functions provide

memory-mapped, addressable operational registers as required in Open Host Controller

Interface Speciﬁcation for USB Rev. 1.0a and Enhanced Host Controller Interface

Speciﬁcation for Universal Serial Bus Rev. 1.0.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

12 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Each function has its own conﬁguration space. The PCI enumerator must allocate the

memory address space for each of these functions. Power management is implemented

in each PCI function and all power states are provided. This allows the system to achieve

low power consumption by switching off the functions that are not required.

8.1.1 PCI conﬁguration space

PCI Local Bus Speciﬁcation Rev. 2.2 requires that each of the two PCI functions of the

ISP1564 provides its own PCI conﬁguration registers, which can vary in size. In addition to

the basic PCI conﬁguration header registers, these functions implement capability

registers to support power management.

The registers of each of these functions are accessed by the respective driver. Section 8.2

provides a detailed description of various PCI conﬁguration registers.

8.1.2 PCI initiator and target

A PCI initiator initiates PCI transactions to the PCI bus. A PCI target responds to PCI

transactions as a slave. In the ISP1564, the open host controller and the enhanced host

controller function as both initiators or targets of PCI transactions issued by the host CPU.

All USB host controllers have their own operational registers that can be accessed by the

system driver software. Drivers use these registers to conﬁgure the host controller

hardware system, issue commands to it, and monitor the status of the current hardware

operation. The host controller plays the role of a PCI target. All operational registers of the

host controllers are the PCI transaction targets of the CPU.

Normal USB transfers require the host controller to access system memory ﬁelds, which

are allocated by USB HCDs and PCI drivers. The host controller hardware interacts with

the HCD by accessing these buffers. The host controller works as an initiator in this case

and becomes a PCI master.

8.2 PCI conﬁguration registers

OHCI USB host controllers and the EHCI USB host controller contain two sets of

software-accessible hardware registers: PCI conﬁguration registers and memory-mapped

host controller registers.

A set of conﬁguration registers is implemented for each of the two PCI functions of the

ISP1564, see Table 3.

Remark: In addition to the normal PCI header, from offset index 00h to 3Fh,

implementation-speciﬁc registers are deﬁned to support power management and

function-speciﬁc features.

The HCD does not usually interact with the PCI conﬁguration space. The conﬁguration

space is used only by the PCI enumerator to identify the USB host controller and assign

appropriate system resources by reading the Vendor ID (VID) and the Device ID (DID).

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Table 3.

Address

PCI conﬁguration space registers of OHCI and EHCI

Bits 31 to 24 Bits 23 to 16 Bits 15 to 8

Bits 7 to 0

Reset value^[1]

Func0 OHCI

Func2 EHCI

PCI conﬁguration header registers

00h

04h

08h

0Ch

Device ID[15:0]

Status[15:0]

Vendor ID[15:0]

Command[15:0]

1561 1131h

1562 1131h

0210 0000h

0C03 2011h

0080 0000h

0210 0000h

Class Code[23:0]

Revision ID[7:0] 0C03 1011h

reserved

Header

Latency

Timer[7:0]

CacheLine

Size[7:0]

0080 0000h

Type[7:0]

10h

14h

18h

1Ch

20h

24h

28h

2Ch

30h

34h

Base Address 0[31:0]

0000 0000h

reserved

0000 0000h

Subsystem ID[15:0]

Subsystem Vendor ID[15:0]

1561 1131h

0000 0000h

0000 00DCh

1562 1131h

0000 0000h

0000 00DCh

reserved

Capabilities

Pointer[7:0]

38h

3Ch

0000 0000h

Max_Lat[7:0]

Min_Gnt[7:0]

Interrupt Pin[7:0]

Interrupt

Line[7:0]

2A01 0100h

1002 0100h

40h

reserved

Retry

Timeout

TRDY Timeout 0000 0000h

0000 0000h

0007 2020h

Enhanced host controller-speciﬁc PCI registers

60h PORTWAKECAP[15:0]

Power management registers

FLADJ[7:0]

SBRN[7:0]

-

DCh

PMC[15:0]

Next_Item_Ptr

[7:0]

Cap_ID[7:0]

D282 0001h

FE82 E401h

E0h

Data[7:0]

PMCSR_BSE

[7:0]

PMCSR[15:0]

0000 XX00h^[2]

VPD speciﬁc registers

E4h

VPD_Addr[15:0]

VPD_Next_Item VPD_Cap_ID

_Ptr[7:0] [7:0]

-

0000 0003h

0000 0000h

E8h

VPD_Data[31:0]

[1] Reset values that are highlighted (for example, 0) indicate read and write accesses; and reset values that are not highlighted (for

example, 0) indicate read-only.

[2] See Section 8.2.3.4.

8.2.1 PCI conﬁguration header registers

The enhanced host controller implements normal PCI header register values, except the

values for the memory-mapping base address register, serial bus number and device ID.

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8.2.1.1 Vendor ID register

This read-only register identiﬁes the manufacturer of the device. PCI Special Interest

Group (PCI-SIG) assigns valid vendor identiﬁers to ensure the uniqueness of the

identiﬁer. The bit description is shown in Table 4.

Table 4.

VID - Vendor ID register (address 00h) bit description

Legend: * reset value

Bit Symbol

15 to 0 VID[15:0]

Access Value

1131h*

Description

R

Vendor ID: This read-only register value is assigned to NXP Semiconductors by

PCI-SIG as 1131h.

8.2.1.2 Device ID register

This is a 2-byte read-only register that identiﬁes a particular device. The identiﬁer is

allocated by NXP Semiconductors. Table 5 shows the bit description of the register.

Table 5.

DID - Device ID register (address 02h) bit description

Legend: * reset value

Bit

Symbol

Access

Value

Description

15 to 0

DID[15:0]

R

156Xh*^[1]Device ID: This register value is deﬁned by NXP Semiconductors to identify

the USB host controller IC product.

[1] X is 1h for OHCI; X is 2h for EHCI.

8.2.1.3 Command register

This is a 2-byte register that provides coarse control over the ability of a device to

generate and respond to PCI cycles. The bit allocation of the Command register is given

in Table 6. When logic 0 is written to this register, the device is logically disconnected from

the PCI bus for all accesses, except conﬁguration accesses. All devices are required to

support this base level of functionality. Individual bits in the Command register may or may

not support this base level of functionality.

Table 6.

Bit

Command register (address 04h) bit allocation

15

14

13

12

11

10

9

FBBE

0

8

SERRE

0

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

6

0

R/W

4

0

R/W

3

0

R/W

2

R/W

1

R/W

0

7

5

Symbol

Reset

Access

SCTRL

PER

0

VGAPS

MWIE

0

SC

0

BM

0

MS

0

IOS

0

R

R/W

R

R/W

R

R/W

[1] The reserved bits must always be written with the reset value.

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HS USB PCI host controller

Table 7.

Bit

Command register (address 04h) bit description

Symbol

reserved

FBBE

Description

15 to 10

9

-

Fast Back-to-Back Enable: This bit controls whether a master can do fast back-to-back

transactions to various devices. The initialization software must set this bit if all targets are fast

back-to-back capable.

0 — Fast back-to-back transactions are only allowed to the same agent (value after RST#).

1 — The master is allowed to generate fast back-to-back transactions to different agents.

8

SERRE

SERR# Enable: This bit is an enable bit for the SERR# driver. All devices that have an SERR# pin

must implement this bit. Address parity errors are reported only if this bit and the PER bit are

logic 1.

0 — Disable the SERR# driver.

1 — Enable the SERR# driver.

7

6

SCTRL

PER

Stepping Control: This bit controls whether a device does address and data stepping. Devices

that never do stepping must clear this bit. Devices that always do stepping must set this bit.

Devices that can do either, must make this bit read or write, and initialize it to logic 1 after RST#.

Parity Error Response: This bit controls the response of a device to parity errors. When the bit is

set, the device must take its normal action when a parity error is detected. When the bit is logic 0,

the device sets DPE (bit 15 in the Status register) when an error is detected, but does not assert

PERR# and continues normal operation. The state of this bit after RST# is logic 0. Devices that

check parity must implement this bit. Devices are required to generate parity, even if parity

checking is disabled.

5

4

VGAPS

MWIE

VGA Palette Snoop: This bit controls how VGA compatible and graphics devices handle accesses

to VGA palette registers.

0 — The device must treat palette write accesses like all other accesses.

1 — Palette snooping is enabled, that is, the device does not respond to palette register writes and

snoops data.

VGA compatible devices must implement this bit.

Memory Write and Invalidate Enable: This is an enable bit for using the Memory Write and

Invalidate command.

0 — Memory writes must be used instead. State after RST# is logic 0.

1 — Masters may generate the command.

This bit must be implemented by master devices that can generate the Memory Write and

Invalidate command.

3

2

1

0

SC

BM

MS

IOS

Special Cycles: Controls the action of a device on special cycle operations.

0 — Causes the device to ignore all special cycle operations. State after RST# is logic 0.

1 — Allows the device to monitor special cycle operations.

Bus Master: Controls the ability of a device to act as a master on the PCI bus.

0 — Disables the device from generating PCI accesses. State after RST# is logic 0.

1 — Allows the device to behave as a bus master.

Memory Space: Controls the response of a device to memory space accesses.

0 — Disables the device response. State after RST# is logic 0.

1 — Allows the device to respond to memory space accesses.

IO Space: Controls the response of a device to I/O space accesses.

0 — Disables the device response. State after RST# is logic 0.

1 — Allows the device to respond to I/O space accesses.

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8.2.1.4 Status register

The Status register is a 2-byte read-only register used to record status information on PCI

bus-related events. For bit allocation, see Table 8.

Table 8.

Bit

Status register (address 06h) bit allocation

15

14

13

12

RTA

0

11

STA

0

10

9

8

Symbol

Reset

Access

Bit

DPE

SSE

RMA

DEVSELT[1:0]

MDPE

0

R

2

1

R

1

0

R

0

R

7

FBBC

0

6

5

66MC

0

4

3

Symbol

Reset

Access

reserved

CL

1

reserved

0

R

Table 9.

Bit

Status register (address 06h) bit description

Symbol

Description

15

DPE

Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if

the parity error handling is disabled.

14

13

12

11

SSE

RMA

RTA

STA

Signaled System Error: This bit must be set whenever the device asserts SERR#. Devices that

never assert SERR# do not need to implement this bit.

Received Master Abort: This bit must be set by a master device whenever its transaction, except for

special cycle, is terminated with master abort. All master devices must implement this bit.

Received Target Abort: This bit must be set by a master device whenever its transaction is

terminated with target abort. All master devices must implement this bit.

Signaled Target Abort: This bit must be set by a target device whenever it terminates a transaction

with target abort. Devices that never signal target abort do not need to implement this bit.

10 to 9 DEVSELT DEVSEL Timing: These bits encode the timing of DEVSEL#. There are three allowable timing to

[1:0]

assert DEVSEL#:

00b — Fast

01b — Medium

10b — Slow

11b — Reserved

These bits are read-only and must indicate the slowest time that a device asserts DEVSEL# for any

bus command, except Conﬁguration Read and Conﬁguration Write.

8

MDPE

Master Data Parity Error: This bit is implemented by bus masters. It is set when the following three

conditions are met:

• The bus agent asserted PERR# itself, on a read; or observed PERR# asserted, on a write.

• The agent setting the bit acted as the bus master for the operation in which error occurred.

• PER (bit 6 in the Command register) is set.

7

6

FBBC

Fast Back-to-Back Capable: This read-only bit indicates whether the target is capable of accepting

fast back-to-back transactions when the transactions are not to the same agent. This bit can be set to

logic 1, if the device can accept these transactions; and must be set to logic 0 otherwise.

reserved

-

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Table 9.

Status register (address 06h) bit description …continued

Bit

Symbol

Description

5

66MC

66 MHz Capable: This read-only bit indicates whether this device is capable of running at 66 MHz.

0 — 33 MHz

1 — 66 MHz

4

CL

Capabilities List: This read-only bit indicates whether this device implements the pointer for a new

capabilities linked list at offset 34h.

0 — No new capabilities linked list is available.

1 — The value read at offset 34h is a pointer in conﬁguration space to a linked list of new capabilities.

3 to 0

reserved

-

8.2.1.5 Revision ID register

This 1-byte read-only register indicates a device-speciﬁc revision identiﬁer. The value is

chosen by the vendor. This ﬁeld is a vendor-deﬁned extension of the device ID. The

Revision ID register bit description is given in Table 10.

Table 10. REVID - Revision ID register (address 08h) bit description

Legend: * reset value

Bit

Symbol

Access

Value

Description

7 to 0

REVID[7:0]

R

11h*

Revision ID: This byte speciﬁes the design revision number of functions.

8.2.1.6 Class Code register

Class Code is a 24-bit read-only register used to identify the generic function of the

device, and in some cases, a speciﬁc register-level programming interface. Table 11

shows the bit allocation of the register.

The Class Code register is divided into three byte-size ﬁelds. The upper byte is a base

class code that broadly classiﬁes the type of function the device performs. The middle

byte is a sub-class code that identiﬁes more speciﬁcally the function of the device. The

lower byte identiﬁes a speciﬁc register-level programming interface, if any, so that

device-independent software can interact with the device.

Table 11. Class Code register (address 09h) bit allocation

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

BCC[7:0]

0Ch

R

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

SCC[7:0]

03h

R

7

6

5

4

3

2

1

0

Symbol

Reset

Access

RLPI[7:0]

X0h^[1]

R

[1] X is 1h for OHCI; X is 2h for EHCI.

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Table 12. Class Code register (address 09h) bit description

Bit

Symbol

Description

23 to 16 BCC[7:0] Base Class Code: 0Ch is the base class code assigned to this byte. It implies a serial bus controller.

15 to 8

7 to 0

SCC[7:0] Sub-Class Code: 03h is the sub-class code assigned to this byte. It implies the USB host controller.

RLPI[7:0] Register-Level Programming Interface: 10h is the programming interface code assigned to OHCI,

which is USB 1.1 speciﬁcation compliant. 20h is the programming interface code assigned to EHCI,

which is USB 2.0 speciﬁcation compliant.

8.2.1.7 CacheLine Size register

The CacheLine Size register is a read and write single-byte register that speciﬁes the

system CacheLine size in units of DWORDs. This register must be implemented by

master devices that can generate the Memory Write and Invalidate command. The value

in this register is also used by master devices to determine whether to use the Read,

Read Line or Read Multiple command to access the memory.

Slave devices that want to allow memory bursting using CacheLine-wrap addressing

mode must implement this register to know when a burst sequence wraps to the

beginning of the CacheLine.

This ﬁeld must be initialized to logic 0 on activation of RST#. Table 13 shows the bit

description of the CacheLine Size register.

Table 13. CLS - CacheLine Size register (address 0Ch) bit description

Legend: * reset value

Bit

Symbol

Access

Value

Description

7 to 0

CLS[7:0]

R/W

00h*

CacheLine Size: This byte identiﬁes the system CacheLine size.

8.2.1.8 Latency Timer register

This register speciﬁes, in units of PCI bus clocks, the value of the latency timer for the PCI

bus master. Table 14 shows the bit description of the Latency Timer register.

Table 14. LT - Latency Timer register (address 0Dh) bit description

Legend: * reset value

Bit

Symbol

Access

Value

Description

7 to 0

LT[7:0]

R/W

00h*

Latency Timer: This byte identiﬁes the latency timer.

Remark: It is recommended that you set the value of the Latency Timer register to 20h.

8.2.1.9 Header Type register

The Header Type register identiﬁes the layout of the second part of the predeﬁned header,

beginning at byte 10h in conﬁguration space. It also identiﬁes whether the device contains

multiple functions. For bit allocation, see Table 15.

Table 15. Header Type register (address 0Eh) bit allocation

Bit

7

MFD

1

6

5

4

3

2

1

0

Symbol

Reset

Access

HT[6:0]

0

R

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Table 16. Header Type register (address 0Eh) bit description

Bit

Symbol Description

MFD Multi-Function Device: This bit identiﬁes a multifunction device.

7

0 — The device has a single function.

1 — The device has multiple functions.

6 to 0 HT[6:0]

Header Type: These bits identify the layout of the part of the predeﬁned header, beginning at byte 10h

in conﬁguration space.

8.2.1.10 Base Address register 0

Power-up software must build a consistent address map before booting the machine to an

operating system. This means it must determine how much memory is in the system, and

how much address space the I/O controllers in the system require. After determining this

information, power-up software can map the I/O controllers into reasonable locations and

proceed with system boot. To do this mapping in a device-independent manner, base

registers for this mapping are placed in the predeﬁned header portion of conﬁguration

space.

Bit 0 in all Base Address registers is read-only and used to determine whether the register

maps into memory or I/O space. Base Address registers that map to memory space must

return logic 0 in bit 0. Base Address registers that map to I/O space must return logic 1 in

bit 0.

The bit description of the BAR0 register is given in Table 17.

Table 17. BAR0 - Base Address register 0 (address 10h) bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

31 to 0

BAR0[31:0] R/W

0000 0000h* Base Address to Memory-Mapped Host Controller Register Space:

The memory size required by OHCI and EHCI are 4 kB and 256 bytes,

respectively. Therefore, BAR0[31:12] is assigned to the OHCI port, and

BAR0[31:8] is assigned to the EHCI port.

8.2.1.11 Subsystem Vendor ID register

The Subsystem Vendor ID register is used to uniquely identify the expansion board or

subsystem where the PCI device resides. This register allows expansion board vendors to

distinguish their boards, even though the boards may have the same vendor ID and device

ID.

Subsystem vendor IDs are assigned by PCI-SIG to maintain uniqueness. The bit

description of the Subsystem Vendor ID register is given in Table 18.

Table 18. SVID - Subsystem Vendor ID register (address 2Ch) bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

15 to 0 SVID[15:0]

R

1131h* Subsystem Vendor ID: 1131h is the subsystem vendor ID assigned to NXP

Semiconductors.

8.2.1.12 Subsystem ID register

Subsystem ID values are vendor speciﬁc. The bit description of the Subsystem ID register

is given in Table 19.

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Table 19. SID - Subsystem ID register (address 2Eh) bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

15 to 0

SID[15:0]

R

156Xh*^[1]Subsystem ID: For the ISP1564, NXP Semiconductors has deﬁned OHCI

functions as 1561h, and the EHCI function as 1562h.

[1] X is 1h for OHCI; X is 2h for EHCI.

8.2.1.13 Capabilities Pointer register

This register is used to point to a linked list of new capabilities implemented by the device.

This register is only valid if CL (bit 4 in the Status register) is set. If implemented, bit 1 and

bit 0 are reserved and must be set to 00b. Software must mask these bits off before using

this register as a pointer in conﬁguration space to the ﬁrst entry of a linked list of new

capabilities. The bit description of the register is given in Table 20.

Table 20. CP - Capabilities Pointer register (address 34h) bit description

Legend: * reset value

Bit

Symbol

Access Value

DCh*

Description

7 to 0

CP[7:0]

R

Capabilities Pointer: EHCI efﬁciently manages power using this register. This

Power Management register is allocated at offset DCh. Only one host controller

is needed to manage power in the ISP1564.

8.2.1.14 Interrupt Line register

This is a 1-byte register used to communicate interrupt line routing information. This

register must be implemented by any device or device function that uses an interrupt pin.

The interrupt allocation is done by the BIOS. The POST software needs to write the

routing information to this register because it initializes and conﬁgures the system.

The value in this register speciﬁes which input of the system interrupt controller(s) the

interrupt pin of the device is connected. This value is used by device drivers and operating

systems to determine priority and vector information. Values in this register are system

architecture speciﬁc. The bit description of the register is given in Table 21.

Table 21. IL - Interrupt Line register (address 3Ch) bit description

Legend: * reset value

Bit

Symbol Access Value

IL[7:0] R/W 00h*

Description

7 to 0

Interrupt Line: Indicates which IRQ is used to report interrupt from the ISP1564.

8.2.1.15 Interrupt Pin register

This 1-byte register is use to specify which interrupt pin the device or device function uses.

A value of 1h corresponds to INTA#, 2h corresponds to INTB#, 3h corresponds to INTC#,

and 4h corresponds to INTD#. Devices or functions that do not use the interrupt pin must

set this register to logic 0. The bit description is given in Table 22.

Table 22. IP - Interrupt Pin register (address 3Dh) bit description

Legend: * reset value

Bit

Symbol

Access Value

01h*

Description

7 to 0

IP[7:0]

R

Interrupt Pin: INTA# is the default interrupt pin used by the ISP1564.

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8.2.1.16 Min_Gnt and Max_Lat registers

The Minimum Grant (Min_Gnt) and Maximum Latency (Max_Lat) registers are used to

specify the desired settings of the device for latency timer values. For both registers, the

value speciﬁes a period of time in units of 250 ns. Logic 0 indicates that the device has no

major requirements for setting latency timers.

The Min_Gnt register bit description is given in Table 23.

Table 23. Min_Gnt - Minimum Grant register (address 3Eh) bit description

Legend: * reset value

Bit

Symbol

Access Value

0Xh*^[1]

Description

7 to 0

MIN_GNT[7:0]

R

Min_Gnt: It is used to specify how long a burst period the device needs,

assuming a clock rate of 33 MHz.

[1] X is 1h for OHCI; X is 2h for EHCI.

The Max_Lat register bit description is given in Table 24.

Table 24. Max_Lat - Maximum Latency register (address 3Fh) bit description

Legend: * reset value

Bit

Symbol

Access Value

Description

7 to 0

MAX_LAT[7:0]

R

XXh*^[1]Max_Lat: It is used to specify how often the device needs to gain access to

the PCI bus.

[1] XX is 2Ah for OHCI; XX is 10h for EHCI.

8.2.1.17 TRDY Timeout register

This is a read and write register at address 40h. The default and recommended value is

00h, TRDY time-out disabled. This value can, however, be modiﬁed. It is an

implementation-speciﬁc register, and not a standard PCI conﬁguration register.

The TRDY timer is 13 bits: the lower 5 bits are ﬁxed as logic 0, and the upper 8 bits are

determined by the TRDY Timeout register value. The time-out is calculated by multiplying

the 13-bit timer with the PCI CLK cycle time.

This register determines the maximum TRDY delay, without asserting the UE

(Unrecoverable Error) bit. If TRDY is longer than the delay determined by this register

value, then the UE bit will be set.

8.2.1.18 Retry Timeout register

The default value of this read and write register is 00h, and is located at address 41h. This

value can, however, be modiﬁed. Programming this register as 00h means that retry

time-out is disabled. This is an implementation-speciﬁc register, and not a standard PCI

conﬁguration register.

The time-out is determined by multiplying the register value with the PCI CLK cycle time.

This register determines the maximum number of PCI retires before the UE bit is set. If the

number of retries is longer than the delay determined by this register value, then the UE

bit will be set.

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8.2.2 Enhanced host controller-speciﬁc PCI registers

In addition to PCI conﬁguration header registers, EHCI needs some additional PCI

conﬁguration space registers to indicate the serial bus release number, downstream port

wake-up event capability, and adjust the USB bus frame length for Start-Of-Frame (SOF).

The EHCI-speciﬁc PCI registers are given in Table 25.

Table 25. EHCI-speciﬁc PCI registers

Offset

60h

Register

Serial Bus Release Number (SBRN)

Frame Length Adjustment (FLADJ)

Port Wake Capability (PORTWAKECAP)

61h

62h to 63h

8.2.2.1 SBRN register

The Serial Bus Release Number (SBRN) register is a 1-byte register, and the bit

description is given in Table 26. This register contains the release number of the USB

speciﬁcation with which this USB host controller module is compliant.

Table 26. SBRN - Serial Bus Release Number register (address 60h) bit description

Legend: * reset value

Bit Symbol

7 to 0 SBRN[7:0]

Access Value Description

R

20h*

Serial Bus Speciﬁcation Release Number: This register value is to identify

Universal Serial Bus Speciﬁcation Rev. 2.0. All other combinations are reserved.

8.2.2.2 FLADJ register

This feature is used to adjust any offset from the clock source that generates the clock that

drives the SOF counter. When a new value is written to these six bits, the length of the

frame is adjusted. The bit allocation of the Frame Length Adjustment (FLADJ) register is

given in Table 27.

Table 27. FLADJ - Frame Length Adjustment register (address 61h) bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

reserved^[1]

FLADJ[5:0]

0

1

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 28. FLADJ - Frame Length Adjustment register (address 61h) bit description

Bit

Symbol

Description

7 to 6

5 to 0

reserved

FLADJ[5:0]

-

Frame Length Timing Value: Each decimal value change to this register corresponds to 16

high-speed bit times. The SOF cycle time, number of SOF counter clock periods to generate a

SOF microframe length, is equal to 59488 + value in this ﬁeld. The default value is decimal 32

(20h), which gives an SOF cycle time of 60000. See Table 29.

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Table 29. FLADJ value vs. SOF cycle time

FLADJ value

0 (00h)

1 (01h)

2 (02h)

:

SOF cycle time (480 MHz)

59488

59504

59520

:

31 (1Fh)

32 (20h)

:

59984

60000

:

62 (3Eh)

63 (3Fh)

60480

60496

8.2.2.3 PORTWAKECAP register

Port Wake Capability (PORTWAKECAP) is a 2-byte register used to establish a policy

about which ports are for wake events; see Table 30. Bit positions 15 to 1 in the mask

correspond to a physical port implemented on the current EHCI controller. Logic 1 in a bit

position indicates that a device connected below the port can be enabled as a wake-up

device and the port may be enabled for disconnect or connect, or overcurrent events as

wake-up events. This is an information only mask register. The bits in this register do not

affect the actual operation of the EHCI host controller. The system-speciﬁc policy can be

established by BIOS initializing this register to a system-speciﬁc value. The system

software uses the information in this register when enabling devices and ports for remote

wake-up.

Table 30. PORTWAKECAP - Port Wake Capability register (address 62h) bit description

Legend: * reset value

Bit Symbol

Access Value

0007h*

Description

15 to 0 PORTWAKECAP[15:0] R/W

Port Wake-Up Capability Mask: EHCI does not implement this

feature.

8.2.3 Power management registers

Table 31. Power management registers

Offset

Register

Value read from address 34h + 0h

Value read from address 34h + 1h

Value read from address 34h + 2h

Value read from address 34h + 4h

Value read from address 34h + 6h

Capability Identiﬁer (Cap_ID)

Next Item Pointer (Next_Item_Ptr)

Power Management Capabilities (PMC)

Power Management Control/Status (PMCSR)

Power Management Control/Status PCI-to-PCI Bridge

Support Extensions (PMCSR_BSE)

Value read from address 34h + 7h

Data

8.2.3.1 Cap_ID register

The Capability Identiﬁer (Cap_ID) register when read by the system software as 01h

indicates that the data structure currently being pointed to is the PCI power management

data structure. Each function of a PCI device may have only one item in its capability list

with Cap_ID set to 01h. The bit description of the register is given in Table 32.

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Table 32. Cap_ID - Capability Identiﬁer register bit description

Address: Value read from address 34h + 0h

Legend: * reset value

Bit

Symbol

Access Value

01h*

Description

7 to 0

CAP_ID[7:0]

R

ID: This ﬁeld when 01h identiﬁes the linked list item as being PCI power

management registers.

8.2.3.2 Next_Item_Ptr register

The Next Item Pointer (Next_Item_Ptr) register describes the location of the next item in

the function’s capability list. The value given is an offset into the function’s PCI

conﬁguration space. If the function does not implement any other capabilities deﬁned by

the PCI-SIG for inclusion in the capabilities list, or if power management is the last item in

the list, then this register must be set to 00h. See Table 33.

Table 33. Next_Item_Ptr - Next Item Pointer register bit description

Address: Value read from address 34h + 1h

Legend: * reset value

Bit

Symbol

Access Value

-^[1]*

Description

7 to 0

NEXT_ITEM_

PTR[7:0]

R

Next Item Pointer: This ﬁeld provides an offset into the function’s PCI

conﬁguration space, pointing to the location of the next item in the

function’s capability list.

[1] Reset value for OHCI is 00h and for EHCI is E4h.

8.2.3.3 PMC register

The Power Management Capabilities (PMC) register is a 2-byte register, and the bit

allocation is given in Table 34. This register provides information on the capabilities of the

function related to power management.

Table 34. PMC - Power Management Capabilities register bit allocation

Address: Value read from address 34h + 2h

Bit

15

14

13

12

11

10

D2_S

X^[1]

R

9

8

Symbol

Reset

Access

Bit

PME_S[4:0]

D1_S

AUX_C

1

R

7

1

R

6

X^[1]

1

X^[1]

R

1

0

R

0

R

5

4

3

2

1

Symbol

Reset

Access

AUX_C[1:0]

DSI

0

reserved

PMI

0

VER[2:0]

1

0

1

0

R

[1] X is 0 for OHCI; X is 1 for EHCI.

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Table 35. PMC - Power Management Capabilities register bit description

Address: Value read from address 34h + 2h

Bit

Symbol Description

15 to 11 PME_S

[4:0]

PME Support: These bits indicate the power states in which the function may assert PME#. Logic 0

for any bit indicates that the function is not capable of asserting the PME# signal while in that power

state.

PME_S[0] — PME# can be asserted from D0

PME_S[1] — PME# can be asserted from D1

PME_S[2] — PME# can be asserted from D2

PME_S[3] — PME# can be asserted from D3_hot

PME_S[4] — PME# can be asserted from D3_cold

10

D2_S

D1_S

D2 Support: If this bit is logic 1, this function supports the D2 power management state. Functions

that do not support D2 must always return logic 0 for this bit.

9

D1 Support: If this bit is logic 1, this function supports the D1 power management state. Functions

that do not support D1 must always return logic 0 for this bit.

8 to 6

AUX_C

[2:0]

Auxiliary Current: This three-bit ﬁeld reports the V_aux(3V3)auxiliary current requirements for the PCI

function.

If the Data register is implemented by this function:

• A read from this ﬁeld needs to return a value of 000b.

• The Data register takes precedence over this ﬁeld for V_aux(3V3)current requirement reporting.

If the PME# generation from D3_coldis not supported by the function (PMC[15] = 0), this ﬁeld must

return a value of 000b when read.

For functions that support PME# from D3_coldand do not implement the Data register, bit assignments

corresponding to the maximum current required for V_aux(3V3)are:

111b — 375 mA

110b — 320 mA

101b — 270 mA

100b — 220 mA

011b — 160 mA

010b — 100 mA

001b — 55 mA

000b — 0 (self powered)

5

DSI

Device Speciﬁc Initialization: This bit indicates whether special initialization of this function is

required, beyond the standard PCI conﬁguration header, before the generic class device driver can

use it.

This bit is not used by some operating systems. For example, Microsoft Windows and Windows NT

do not use this bit to determine whether to use D3. Instead, it is determined using the capabilities of

the driver.

Logic 1 indicates that the function requires a device-speciﬁc initialization sequence, following

transition to D0 un-initialized state.

4

3

reserved

PMI

-

PME Clock:

0 — Indicates that no PCI clock is required for the function to generate PME#.

1 — Indicates that the function relies on the presence of the PCI clock for the PME# operation.

Functions that do not support the PME# generation in any state must return logic 0 for this ﬁeld.

2 to 0

VER[2:0] Version: A value of 010b indicates that this function complies with PCI Bus Power Management

Interface Speciﬁcation Rev. 1.1.

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8.2.3.4 PMCSR register

The Power Management Control/Status (PMCSR) register is a 2-byte register used to

manage the power management state of the PCI function, as well as to allow and monitor

Power Management Events (PMEs). The bit allocation of the register is given in Table 36.

Table 36. PMCSR - Power Management Control/Status register bit allocation

Address: Value read from address 34h + 4h

Bit

15

PMES

X^[1]

14

13

12

11

10

9

8

PMEE

X^[1]

Symbol

Reset

Access

Bit

DS[1:0]

D_S[3:0]

0

R

6

0

R

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

R/W

7

R/W

0

Symbol

Reset

Access

reserved^[2]

PS[1:0]

0

R/W

[1] Sticky bit, if the function supports PME# from D3_cold, then X is indeterminate at the time of initial operating system boot; X is 0 if the

function does not support PME# from D3_cold

.

[2] The reserved bits must always be written with the reset value.

Table 37. PMCSR - Power Management Control/Status register bit description

Address: Value read from address 34h + 4h

Bit

Symbol

Description

15

PMES

PME Status: This bit is set when the function normally asserts the PME# signal independent of

the state of the PMEE bit. Writing logic 1 to this bit clears it and causes the function to stop

asserting PME#, if enabled. Writing logic 0 has no effect. This bit defaults to logic 0, if the function

does not support the PME# generation from D3_cold. If the function supports the PME# generation

from D3_cold, then this bit is sticky and must be explicitly cleared by the operating system each time

the operating system is initially loaded.

14 to 13

12 to 9

DS[1:0]

Data Scale: This two-bit read-only ﬁeld indicates the scaling factor when interpreting the value of

the Data register. The value and meaning of this ﬁeld vary, depending on which data value is

selected by the D_S ﬁeld. This ﬁeld is a required component of the Data register (offset 7) and

must be implemented, if the Data register is implemented. If the Data register is not implemented,

this ﬁeld must return 00b when PMCSR is read.

D_S

[3:0]

Data Select: This four-bit ﬁeld selects the data that is reported through the Data register and the

D_S ﬁeld. This ﬁeld is a required component of the Data register (offset 7) and must be

implemented, if the Data register is implemented. If the Data register is not implemented, this ﬁeld

must return 00b when PMCSR is read.

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Table 37. PMCSR - Power Management Control/Status register bit description …continued

Address: Value read from address 34h + 4h

Bit

Symbol

Description

8

PMEE

PME Enabled: Logic 1 allows the function to assert PME#. When it is logic 0, PME# assertion is

disabled. This bit defaults to logic 0, if the function does not support the PME# generation from

D3_cold. If the function supports PME# from D3_cold, then this bit is sticky and must explicitly be

cleared by the operating system each time the operating system is initially loaded.

7 to 2

1 to 0

reserved

PS[1:0]

-

Power State: This two-bit ﬁeld is used to determine the current power state of the EHCI function

and to set the function into a new power state. The deﬁnition of the ﬁeld values is given as:

00b — D0

01b — D1

10b — D2

11b — D3_hot

If the software attempts to write an unsupported, optional state to this ﬁeld, the write operation

must complete normally on the bus; however, data is discarded and no status change occurs.

8.2.3.5 PMCSR_BSE register

The PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI

bridge-speciﬁc functionality and is required for all PCI-to-PCI bridges. The bit allocation of

this register is given in Table 38.

Table 38. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit allocation

Address: Value read from address 34h + 6h

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

BPCC_EN

B2_B3#

reserved

0

R

Table 39. PMCSR_BSE - PMCSR PCI-to-PCI Bridge Support Extensions register bit description

Address: Value read from address 34h + 6h

Bit

Symbol

Description

7

BPCC_EN Bus Power or Clock Control Enable:

1 — Indicates that the bus power or clock control mechanism as deﬁned in Table 40 is enabled.

0 — Indicates that the bus power or control policies as deﬁned in Table 40 are disabled.

When the bus power or clock control mechanism is disabled, the bridge’s PMCSR Power State (PS)

ﬁeld cannot be used by the system software to control the power or clock of the bridge’s secondary

bus.

6

B2_B3#

B2 or B3 support for D3_hot: The state of this bit determines the action that is to occur as a direct

result of programming the function to D3_hot

.

1 — Indicates that when the bridge function is programmed to D3_hot, its secondary bus’s PCI clock will

be stopped (B2).

0 — Indicates that when the bridge function is programmed to D3_hot, its secondary bus will have its

power removed (B3).

This bit is only meaningful if bit 7 (BPCC_EN) is logic 1.

-

5 to 0 reserved

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Table 40. PCI bus power and clock control

Originating device’s Secondary bus Resultant actions by bridge (either direct or indirect)

bridge PM state

PM state

D0

B0

none

D1

B1

none

D2

B2

clock stopped on secondary bus

D3_hot

B2, B3

clock stopped and PCI V_CCremoved from secondary

bus (B3 only); for deﬁnition of B2_B3#, see Table 39

D3_cold

B3

none

8.2.3.6 Data register

The Data register is an optional, 1-byte register that provides a mechanism for the

function to report state dependent operating data, such as power consumed or heat

dissipated. Table 41 shows the bit description of the register.

Table 41. Data register bit description

Address: Value read from address 34h + 7h

Legend: * reset value

Bit

Symbol

Access

Value

Description

7 to 0

DATA[7:0]

R

00h*

DATA: This register is used to report the state dependent data requested

by the D_S ﬁeld of the PMCSR register. The value of this register is scaled

by the value reported by the DS ﬁeld of the PMCSR register.

8.2.4 VPD register

Table 42. VPD speciﬁc registers

Offset

Register

Value read from address 34h + 8h

Value read from address 34h + 9h

Vital Product Data Capability Identiﬁer (VPD_Cap_ID)

Vital Product Data Next Item Pointer (VPD_Next_Item_Ptr)

Value read from address 34h + Ah Vital Product Data Address (VPD_Addr)

Value read from address 34h + Ch Vital Product Data Data (VPD_Data)

8.2.4.1 VPD_Cap_ID register

The Capability Identiﬁer (Cap_ID) register when read by the system software as 03h

indicates that the data structure currently being pointed to is the VPD_Data structure. The

bit description of the register is given in Table 43.

Table 43. VPD_Cap_ID - Vital Product Data Capability Identiﬁer register bit description

Address: Value read from address 34h + 8h

Legend: * reset value

Bit

Symbol

Access Value Description

03h* VPD Capability ID: Capability structure ID; for details, refer to Appendix I of

PCI Local Bus Speciﬁcation Rev. 2.2

7 to 0 VPD_CAP_ID[7:0]

R

8.2.4.2 VPD_Next_Item_Ptr register

The Next Item Pointer (Next_Item_Ptr) register describes the location of the next item in

the function’s capability list. The value given is an offset into the function’s PCI

conﬁguration space. If the function does not implement any other capabilities deﬁned by

the PCI-SIG for inclusion in the capabilities list, or if the power management is the last

item in the list, then this register must be set to 00h. See Table 44.

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Table 44. VPD_Next_Item_Ptr - Vital Product Data Next Item Pointer register bit description

Address: Value read from address 34h + 9h

Legend: * reset value

Bit

Symbol

Access Value Description

7 to 0

VPD_NEXT_ITEM R

_PTR[7:0]

00h*

VPD Next Item Pointer: Pointer to the next capability structure, or 00h if

this is the last structure in the capability list; for details, refer to Appendix I

of PCI Local Bus Speciﬁcation Rev. 2.2

8.2.4.3 VPD_Addr register

The DWORD-aligned byte address of the VPD to be accessed. This is a R/W register, and

the initial value at power-up is indeterminate. The bit description of the register is given in

Table 45.

Table 45. VPD_Addr - Vital Product Data Address register bit allocation

Address: Value read from address 34h + 9Ah

Bit

7

F

6

5

4

3

2

1

0

Symbol

Reset

Access

VPD_ADDR[6:0]

0

R/W

Table 46. VPD_Addr - Vital Product Data Address register bit description

Address: Value read from address 34h + 9h

Bit

Symbol

Description^[1]

7

F

Flag: A ﬂag used to indicate when the transfer of data between the VPD Data register and the

storage component is completed.

6 to 0

VPD_ADDR[6:0] VPD Address: DWORD-aligned byte address of the VPD to be accessed.

[1] For details on these bits, refer to Appendix I, PCI Local Bus Speciﬁcation Rev. 2.2.

8.2.4.4 VPD_Data register

VPD data can be read or written through this register. The bit description of the register is

given in Table 47.

Table 47. VPD_Data - Vital Product Data Data bit description

Address: Value read from address 34h + Ch

Legend: * reset value

Bit

Symbol

Access Value Description

31 to 0 VPD_DATA[7:0] R/W

00h*

VPD Data: VPD data can be read through this register; for details, refer to

Appendix I of PCI Local Bus Speciﬁcation Rev. 2.2

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9. I²C-bus interface

A simple I²C-bus interface is provided in the ISP1564 to read customized vendor ID,

product ID and some other conﬁguration bits from an external EEPROM.

The I²C-bus interface is for bidirectional communication between ICs using two serial bus

wires: SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must

be connected to the positive supply voltage through pull-up resistors when in use;

otherwise, they must be connected to ground.

9.1 Protocol

The I²C-bus protocol deﬁnes the following conditions:

• Bus free: both SDA and SCL are HIGH

• START: a HIGH-to-LOW transition on SDA, while SCL is HIGH

• STOP: a LOW-to-HIGH transition on SDA, while SCL is HIGH

• Data valid: after a START condition, data on SDA is stable during the HIGH period of

SCL; data on SDA may only change while SCL is LOW

Each device on the I²C-bus has a unique slave address, which the master uses to select a

device for access.

The master starts a data transfer using a START condition and ends it by generating a

STOP condition. Transfers can only be initiated when the bus is free. The receiver must

acknowledge each byte by using a LOW level on SDA during the ninth clock pulse on

SCL.

For detailed information, refer to The I²C-bus Speciﬁcation Version 2.1.

9.2 Hardware connections

The ISP1564 can be connected to an external EEPROM through the I²C-bus interface.

The hardware connections are shown in Figure 6.

V

aux(3V3)

R

P

R

P

SCL

SDA

SCL

SDA

A0

A1

A2

2

I C-bus

ISP1564

USB HOST

24C01

EEPROM

or

equivalent

004aaa793

Fig 6. EEPROM connection diagram

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The slave address that the ISP1564 uses to access the EEPROM is 101 0000b. Page

mode addressing is not supported. Therefore, pins A0, A1 and A2 of the EEPROM must

be connected to ground (logic 0).

9.3 Information loading from EEPROM

Figure 7 shows the content of the EEPROM memory. If the EEPROM is not present, the

default values of device ID, vendor ID, subsystem VID and subsystem DID assigned to

NXP Semiconductors by PCI-SIG will be loaded. For default values, see Table 3.

address

0

1

2

3

4

5

6

7

subsystem vendor ID (L)

subsystem vendor ID (H)

subsystem device ID (L) - OHCI

subsystem device ID (H) - OHCI

subsystem device ID (L) - EHCI

subsystem device ID (H) - EHCI

reserved - FFh

15h - loads subsystem vendor ID, device ID

signature

1Ah - loads default values defined by NXP Semiconductors

004aaa930

L = LOW; H = HIGH.

Fig 7. Information loading from EEPROM

9.4 EEPROM programming

To simplify the manufacturing of products based on the ISP1564, which requires changing

of subsystem DID and VID, information can be written in-circuit to the EEPROM through

the PCI bus. Reading and writing of the EEPROM is achieved by the mechanism

described in Appendix I of PCI Local Bus Speciﬁcation Rev. 2.2.

Remark: The VPD data structure described in Appendix I of PCI Local Bus Speciﬁcation

Rev. 2.2 is not adopted and only the read write mechanism is adopted in the ISP1564.

10. Power management

10.1 PCI bus power states

The PCI bus can be characterized by one of the four power management states: B0, B1,

B2 and B3.

B0 state (PCI clock = 33 MHz, PCI bus power = on) — This corresponds to the bus

being fully operational.

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B1 state (PCI clock = intermittent clock operation mode, PCI bus power = on) —

When a PCI bus is in B1, PCI V_CCis still applied to all devices on the bus. No bus

transactions, however, are allowed to take place on the bus. The B1 state indicates a

perpetual idle state on the PCI bus.

B2 state (PCI clock = stop, PCI bus power = on) — PCI V_CCis still applied on the bus,

but the clock is stopped and held in the LOW state.

B3 state (PCI clock = stop, PCI bus power = off) — PCI V_CCis removed from all

devices on the PCI bus segment.

10.2 USB bus states

Reset state — When the USB bus is in the reset state, the USB system is stopped.

Operational state — When the USB bus is in the active state, the USB system is

operating normally.

Suspend state — When the USB bus is in the suspend state, the USB system is

stopped.

Resume state — When the USB bus is in the resume state, the USB system is operating

normally.

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11. USB host controller registers

Each host controller contains a set of on-chip operational registers that are mapped to

un-cached memory of the system addressable space. This memory space must begin on

a DWORD (32-bit) boundary. The size of the allocated space is deﬁned by the initial value

in the Base Address register 0. HCDs must interact with these registers to implement USB

functionality.

After the PCI enumeration driver ﬁnishes the PCI device conﬁguration, the new base

address of these memory-mapped operational registers is deﬁned in BAR0. The HCD can

access these registers by using the address of base address value + offset.

Table 48 contains a list of host controller registers.

For the OHCI host controller, there are only operational registers for the USB operation.

For the enhanced host controller, there are two types of registers: one set of read-only

capability registers, and one set of read and write operational registers.

Table 48. USB host controller registers

Address OHCI register

Reset value

func0 OHCI^[1]

EHCI register

Reset value

func2 EHCI^[1]

00h

04h

08h

0Ch

10h

14h

18h

1Ch

20h

24h

28h

2Ch

30h

34h

38h

3Ch

40h

44h

48h

4Ch

50h

54h

58h

5Ch

60h

HcRevision

0000 0010h

0000 0000h

0000 2EDFh

0000 0000h

0000 0628h

FF00 0902h

0006 0000h

0000 0000h

-

CAPLENGTH/HCIVERSION^[2]

HCSPARAMS

HCCPARAMS

HCSP-PORTROUTE1[31:0]

HCSP-PORTROUTE2[59:32]

reserved

0100 0020h

HcControl

0000 1292h

HcCommandStatus

HcInterruptStatus

HcInterruptEnable

HcInterruptDisable

HcHCCA

0000 0012h

0000 1010h

0000 0000h

-

reserved

-

HcPeriodCurrentED

HcControlHeadED

HcControlCurrentED

HcBulkHeadED

HcBulkCurrentED

HcDoneHead

reserved

-

USBCMD

0008 0000h

USBSTS

0000 1000h

USBINTR

0000 0000h

FRINDEX

0000 0000h

reserved

-

HcFmInterval

PERIODICLISTBASE

ASYNCLISTADDR

reserved

0000 0000h

HcFmRemaining

HcFmNumber

0000 0000h

-

HcPeriodicStart

HcLSThreshold

HcRhDescriptorA

HcRhDescriptorB

HcRhStatus

reserved

-

reserved

-

reserved

-

reserved

-

reserved

-

HcRhPortStatus[1]

HcRhPortStatus[2]

reserved

-

reserved

-

reserved

-

reserved

-

CONFIGFLAG

0000 0000h

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Table 48. USB host controller registers …continued

Address OHCI register

Reset value

func0 OHCI^[1]

EHCI register

Reset value

func2 EHCI^[1]

64h

68h

6Ch

70h

reserved

-

PORTSC1

PORTSC2

System Tuning

reserved

0000 0000h

-

[1] Reset values that are highlighted, for example, 0, are the ISP1564 implementation-speciﬁc reset values; and reset values that are not

highlighted, for example, 0, are compliant with the OHCI and EHCI speciﬁcations.

[2] HCIVERSION is 0100h when subsystem ID and subsystem vendor ID are conﬁgured through the external EEPROM, or when SCL is

pulled down. Otherwise, it is 0095h.

11.1 OHCI USB host controller operational registers

OHCI HCDs must communicate with these registers to implement USB data transfers.

Based on their functions, these registers are classiﬁed into four partitions:

• Control and status

• Memory pointer

• Frame counter

• Root hub

11.1.1 HcRevision register

Table 49. HcRevision - Host Controller Revision register bit allocation

Address: Content of the base address register + 00h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

REV[7:0]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

0

1

0

R

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 50. HcRevision - Host Controller Revision register bit description

Address: Content of the base address register + 00h

Bit

Symbol

Description

31 to 8

7 to 0

reserved

-

REV[7:0] Revision: This read-only ﬁeld contains the BCD representation of the version of the HCI

speciﬁcation that is implemented by this host controller. For example, a value of 11h corresponds to

version 1.1. All of the host controller implementations that are compliant with this speciﬁcation must

have a value of 10h.

11.1.2 HcControl register

This register deﬁnes the operating modes for the host controller. All the ﬁelds in this

register, except HCFS and RWC, are modiﬁed only by the HCD. The bit allocation is given

in Table 51.

Table 51. HcControl - Host Controller Control register bit allocation

Address: Content of the base address register + 04h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

10

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

12

R/W

11

13

Symbol

Reset

Access

Bit

reserved^[1]

RWE

0

RWC

0

IR

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

R/W

1

R/W

0

Symbol

Reset

Access

HCFS[1:0]

BLE

0

CLE

0

IE

PLE

0

CBSR[1:0]

0

R/W

[1] The reserved bits must always be written with the reset value.

ISP1564_2

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ISP1564

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HS USB PCI host controller

Table 52. HcControl - Host Controller Control register bit description

Address: Content of the base address register + 04h

Bit

Symbol

Description

31 to 11 reserved

-

10

9

RWE

RWC

Remote Wake-up Enable: This bit is used by the HCD to enable or disable the remote wake-up

feature on detecting upstream resume signaling. When this bit and RD (bit 3) in the

HcInterruptStatus register are set, a remote wake-up is signaled to the host system. Setting this bit

has no impact on the generation of hardware interrupt.

Remote Wake-up Connected: This bit indicates whether the host controller supports remote

wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of

the system ﬁrmware to set this bit during POST. The host controller clears the bit on a hardware

reset but does not alter it on a software reset. Remote wake-up signaling of the host system is

host-bus-speciﬁc and is not described in this speciﬁcation.

8

IR

Interrupt Routing: This bit determines the routing of interrupts generated by events registered in

HcInterruptStatus. If clear, all interrupts are routed to the normal host bus interrupt mechanism. If

set, interrupts are routed to the system management interrupt. The HCD clears this bit on a

hardware reset, but it does not alter this bit on a software reset. The HCD uses this bit as a tag to

indicate the ownership of the host controller.

7 to 6

HCFS

[1:0]

Host Controller Functional State for USB:

00b — USBRESET

01b — USBRESUME

10b — USBOPERATIONAL

11b — USBSUSPEND

A transition to USBOPERATIONAL from another state causes SOF generation to begin 1 ms later.

The HCD may determine whether the host controller has begun sending SOFs by reading SF (bit 2)

in HcInterruptStatus.

This ﬁeld may be changed by the host controller only when in the USBSUSPEND state. The host

controller may move from the USBSUSPEND state to the USBRESUME state after detecting the

resume signaling from a downstream port.

The host controller enters USBSUSPEND after a software reset; it enters USBRESET after a

hardware reset. The latter also resets the root hub and asserts subsequent reset signaling to

downstream ports.

5

BLE

Bulk List Enable: This bit is set to enable the processing of the bulk list in the next frame. If cleared

by the HCD, processing of the bulk list does not occur after the next SOF. The host controller checks

this bit whenever it wants to process the list. When disabled, the HCD may modify the list. If

HcBulkCurrentED is pointing to an Endpoint Descriptor (ED) to be removed, the HCD must advance

the pointer by updating HcBulkCurrentED before re-enabling processing of the list.

ISP1564_2

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ISP1564

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HS USB PCI host controller

Table 52. HcControl - Host Controller Control register bit description …continued

Address: Content of the base address register + 04h

Bit

Symbol

Description

4

CLE

Control List Enable: This bit is set to enable the processing of the control list in the next frame. If

cleared by the HCD, processing of the control list does not occur after the next SOF. The host

controller must check this bit whenever it wants to process the list. When disabled, the HCD may

modify the list. If HcControlCurrentED is pointing to an ED to be removed, the HCD must advance

the pointer by updating HcControlCurrentED before re-enabling processing of the list.

3

IE

Isochronous Enable: This bit is used by the HCD to enable or disable processing of isochronous

EDs. While processing the periodic list in a frame, the host controller checks the status of this bit

when it ﬁnds an isochronous ED (F = 1). If set (enabled), the host controller continues processing

EDs. If cleared (disabled), the host controller halts processing of the periodic list, which now

contains only isochronous EDs, and begins processing bulk or control lists. Setting this bit is

guaranteed to take effect in the next frame and not the current frame.

2

PLE

Periodic List Enable: This bit is set to enable the processing of the periodic list in the next frame. If

cleared by the HCD, processing of the periodic list does not occur after the next SOF. The host

controller must check this bit before it starts processing the list.

1 to 0

CBSR

[1:0]

Control Bulk Service Ratio: This speciﬁes the service ratio of control EDs over bulk EDs. Before

processing any of the nonperiodic lists, the host controller must compare the ratio speciﬁed with its

internal count on how many nonempty control EDs are processed, in determining whether to

continue serving another control ED or switching to bulk EDs. The internal count must be retained

when crossing the frame boundary. After a reset, the HCD is responsible to restore this value.

00b — 1 : 1

01b — 2 : 1

10b — 3 : 1

11b — 4 : 1

11.1.3 HcCommandStatus register

The HcCommandStatus register is used by the host controller to receive commands

issued by the HCD. It also reﬂects the current status of the host controller. To the HCD, it

appears as a ‘write to set’ register. The host controller must ensure that bits written as

logic 1 become set in the register while bits written as logic 0 remain unchanged in the

register. The HCD may issue multiple distinct commands to the host controller without

concern for corrupting previously issued commands. The HCD has normal read access to

all bits.

The SOC[1:0] ﬁeld (bits 17 and 16 in the HcCommandStatus register) indicates the

number of frames with which the host controller has detected the scheduling overrun

error. This occurs when the periodic list does not complete before EOF. When a

scheduling overrun error is detected, the host controller increments the counter and sets

SO (bit 0 in the HcInterruptStatus register).

Table 53 shows the bit allocation of the HcCommandStatus register.

Table 53. HcCommandStatus - Host Controller Command Status register bit allocation

Address: Content of the base address register + 08h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved^[1]

SOC[1:0]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

12

R/W

11

R/W

10

13

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved^[1]

OCR

0

BLF

0

CLF

0

HCR

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 54. HcCommandStatus - Host Controller Command Status register bit description

Address: Content of the base address register + 08h

Bit

Symbol Description

31 to 18 reserved

-

17 to 16 SOC[1:0] Scheduling Overrun Count: The bit is incremented on each scheduling overrun error. It is initialized

to 00b and wraps around at 11b. It must be incremented when a scheduling overrun is detected, even

if SO (bit 0 in HcInterruptStatus) is already set. This is used by the HCD to monitor any persistent

scheduling problems.

15 to 4 reserved

-

3

OCR

Ownership Change Request: This bit is set by an OS HCD to request a change of control of the host

controller. When set, the host controller must set OC (bit 30 in HcInterruptStatus). After the

changeover, this bit is cleared and remains so until the next request from the OS HCD.

2

BLF

Bulk List Filled: This bit is used to indicate whether there are any Transfer Descriptors (TDs) on the

bulk list. It is set by the HCD whenever it adds a TD to an ED in the bulk list. When the host controller

begins to process the head of the bulk list, it checks Bulk-Filled (BF). If BLF is logic 0, the host

controller does not need to process the bulk list. If BLF is logic 1, the host controller must start

processing the bulk list and set BF to logic 0. If the host controller ﬁnds a TD on the list, then the host

controller must set BLF to logic 1, causing the bulk list processing to continue. If no TD is found on the

bulk list, and if the HCD does not set BLF, then BLF is still logic 0 when the host controller completes

processing the bulk list and the bulk list processing stops.

1

CLF

Control List Filled: This bit is used to indicate whether there are any TDs on the control list. It is set

by the HCD whenever it adds a TD to an ED in the control list.

When the host controller begins to process the head of the control list, it checks CLF. If CLF is logic 0,

the host controller does not need to process the control list. If Control-Filled (CF) is logic 1, the host

controller needs to start processing the control list and set CLF to logic 0. If the host controller ﬁnds a

TD on the list, then the host controller must set CLF to logic 1, causing the control list processing to

continue. If no TD is found on the control list, and if the HCD does not set CLF, then CLF is still logic 0

when the host controller completes processing the control list and the control list processing stops.

0

HCR

Host Controller Reset: This bit is set by the HCD to initiate a software reset of the host controller.

Regardless of the functional state of the host controller, it moves to the USBSUSPEND state in which

most of the operational registers are reset, except those stated otherwise; for example, IR (bit 8) in the

HcControl register, and no host bus accesses are allowed. This bit is cleared by the host controller on

completing the reset operation. The reset operation must be completed within 10 µs. This bit, when

set, must not cause a reset to the root hub and no subsequent reset signaling must be asserted to its

downstream ports.

ISP1564_2

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ISP1564

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HS USB PCI host controller

11.1.4 HcInterruptStatus register

This is a 4-byte register that provides the status of the events that cause hardware

interrupts. The bit allocation of the register is given in Table 55. When an event occurs, the

host controller sets the corresponding bit in this register. When a bit becomes set, a

hardware interrupt is generated, if the interrupt is enabled in the HcInterruptEnable

register (see Table 57) and the MIE (Master Interrupt Enable) bit is set. The HCD may

clear speciﬁc bits in this register by writing logic 1 to the bit positions to be cleared. The

HCD may not set any of these bits. The host controller does not clear the bit.

Table 55. HcInterruptStatus - Host Controller Interrupt Status register bit allocation

Address: Content of the base address register + 0Ch

Bit

31

30

OC

0

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

18

R/W

17

R/W

16

19

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

7

reserved^[1]

0

Symbol

Reset

Access

RHSC

0

FNO

0

UE

0

RD

0

SF

0

WDH

0

SO

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 56. HcInterruptStatus - Host Controller Interrupt Status register bit description

Address: Content of the base address register + 0Ch

Bit

31

30

Symbol

reserved

OC

Description

-

Ownership Change: This bit is set by the host controller when HCD sets OCR (bit 3) in the

HcCommandStatus register. This event, when unmasked, will always immediately generate a

System Management Interrupt (SMI). This bit is forced to logic 0 when the SMI# pin is not

implemented.

29 to 7 reserved

-

6

RHSC

Root Hub Status Change: This bit is set when the content of HcRhStatus or the content of any of

HcRhPortStatus[NumberofDownstreamPort] has changed.

ISP1564_2

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ISP1564

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HS USB PCI host controller

Table 56. HcInterruptStatus - Host Controller Interrupt Status register bit description …continued

Address: Content of the base address register + 0Ch

Bit

Symbol

Description

5

FNO

Frame Number Overﬂow: This bit is set when the Most Signiﬁcant Bit (MSB) of HcFmNumber

(bit 15) changes value, or after HccaFrameNumber is updated.

4

3

UE

RD

Unrecoverable Error: This bit is set when the host controller detects a system error not related to

USB. The host controller must not proceed with any processing or signaling before the system error

is corrected. The HCD clears this bit after the host controller is reset.

Resume Detected: This bit is set when the host controller detects that a device on the USB is

asserting resume signaling. This bit is set by the transition from no resume signaling to resume

signaling. This bit is not set when the HCD sets the USBRESUME state.

2

1

SF

Start-of-Frame: At the start of each frame, this bit is set by the host controller and an SOF token is

generated at the same time.

WDH

Write-back Done Head: This bit is immediately set after the host controller has written HcDoneHead

to HccaDoneHead. Further, updates of HccaDoneHead occur only after this bit is cleared. The HCD

must only clear this bit after it has saved the content of HccaDoneHead.

0

SO

Scheduling Overrun: This bit is set when USB schedules for current frame overruns and after the

update of HccaFrameNumber. A scheduling overrun increments the SOC[1:0] ﬁeld (bits 17 to 16 of

HcCommandStatus).

11.1.5 HcInterruptEnable register

Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt

bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control

which events generate a hardware interrupt. A hardware interrupt is requested on the host

bus if the following conditions occur:

• A bit is set in the HcInterruptStatus register.

• The corresponding bit in the HcInterruptEnable register is set.

• The MIE (Master Interrupt Enable) bit is set.

Writing logic 1 to a bit in this register sets the corresponding bit, whereas writing logic 0 to

a bit in this register leaves the corresponding bit unchanged. On a read, the current value

of this register is returned. The bit allocation is given in Table 57.

Table 57. HcInterruptEnable - Host Controller Interrupt Enable register bit allocation

Address: Content of the base address register + 10h

Bit

31

MIE

0

30

OC

0

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

18

R/W

17

R/W

16

19

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1564_2

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ISP1564

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HS USB PCI host controller

Bit

7

reserved^[1]

0

6

RHSC

0

5

4

UE

0

3

RD

0

2

SF

0

1

WDH

0

SO

0

Symbol

Reset

Access

FNO

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 58. HcInterruptEnable - Host Controller Interrupt Enable register bit description

Address: Content of the base address register + 10h

Bit

Symbol

Description

31

MIE

Master Interrupt Enable:

0 — Ignore

1 — Enables interrupt generation by events speciﬁed in other bits of this register.

30

OC

Ownership Change:

0 — Ignore

1 — Enables interrupt generation because of ownership change.

29 to 7

6

reserved

RHSC

-

Root Hub Status Change:

0 — Ignore

1 — Enables interrupt generation because of root hub status change.

5

4

3

2

1

0

FNO

UE

Frame Number Overﬂow:

0 — Ignore

1 — Enables interrupt generation because of frame number overﬂow.

Unrecoverable Error:

0 — Ignore

1 — Enables interrupt generation because of unrecoverable error.

RD

Resume Detect:

0 — Ignore

1 — Enables interrupt generation because of resume detect.

SF

Start-of-Frame:

0 — Ignore

1 — Enables interrupt generation because of Start-of-Frame.

HcDoneHead Write-back:

WDH

SO

0 — Ignore

1 — Enables interrupt generation because of HcDoneHead write-back.

Scheduling Overrun:

0 — Ignore

1 — Enables interrupt generation because of scheduling overrun.

11.1.6 HcInterruptDisable register

Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt

bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the

HcInterruptEnable register. Therefore, writing logic 1 to a bit in this register clears the

corresponding bit in the HcInterruptEnable register, whereas writing logic 0 to a bit in this

register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a

read, the current value of the HcInterruptEnable register is returned.

ISP1564_2

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HS USB PCI host controller

The register contains 4 bytes, and the bit allocation is given in Table 59.

Table 59. HcInterruptDisable - Host Controller Interrupt Disable register bit allocation

Address: Content of the base address register + 14h

Bit

31

MIE

0

30

OC

0

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

18

R/W

17

R/W

16

19

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

7

reserved^[1]

0

Symbol

Reset

Access

RHSC

0

FNO

0

UE

0

RD

0

SF

0

WDH

0

SO

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 60. HcInterruptDisable - Host Controller Interrupt Disable register bit description

Address: Content of the base address register + 14h

Bit

Symbol

Description

31

MIE

Master Interrupt Enable:

0 — Ignore

1 — Disables interrupt generation because of events speciﬁed in other bits of this register.

This ﬁeld is set after a hardware or software reset. Interrupts are disabled.

30

OC

Ownership Change:

0 — Ignore

1 — Disables interrupt generation because of ownership change.

29 to 7 reserved

-

6

5

4

RHSC

FNO

UE

Root Hub Status Change:

0 — Ignore

1 — Disables interrupt generation because of root hub status change.

Frame Number Overﬂow:

0 — Ignore

1 — Disables interrupt generation because of frame number overﬂow.

Unrecoverable Error:

0 — Ignore

1 — Disables interrupt generation because of unrecoverable error.

ISP1564_2

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ISP1564

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HS USB PCI host controller

Table 60. HcInterruptDisable - Host Controller Interrupt Disable register bit description …continued

Address: Content of the base address register + 14h

Bit

Symbol

Description

3

RD

Resume Detect:

0 — Ignore

1 — Disables interrupt generation because of resume detect.

2

1

0

SF

Start-of-Frame:

0 — Ignore

1 — Disables interrupt generation because of Start-of-Frame.

HcDoneHead Write-back:

WDH

SO

0 — Ignore

1 — Disables interrupt generation because of HcDoneHead write-back.

Scheduling Overrun:

0 — Ignore

1 — Disables interrupt generation because of scheduling overrun.

11.1.7 HcHCCA register

The HcHCCA register contains the physical address of Host Controller Communication

Area (HCCA). The bit allocation is given in Table 61. The HCD determines alignment

restrictions by writing all 1s to HcHCCA and reading the content of HcHCCA. The

alignment is evaluated by examining the number of zeroes in lower order bits. The

minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0

when read. This area is used to hold control structures and the interrupt table that are

accessed by both the host controller and the HCD.

Table 61. HcHCCA - Host Controller Communication Area register bit allocation

Address: Content of the base address register + 18h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

HCCA[23:16]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

HCCA[15:8]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

HCCA[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved^[1]

0

R/W

[1] The reserved bits must always be written with the reset value.

ISP1564_2

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ISP1564

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HS USB PCI host controller

Table 62. HcHCCA - Host Controller Communication Area register bit description

Address: Content of the base address register + 18h

Bit

31 to 8 HCCA[23:0] Host Controller Communication Area Base Address: This is the base address of the HCCA.

7 to 0 reserved

Symbol

Description

-

11.1.8 HcPeriodCurrentED register

The HcPeriodCurrentED register contains the physical address of the current isochronous

or interrupt ED. Table 63 shows the bit allocation of the register.

Table 63. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit allocation

Address: Content of the base address register + 1Ch

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

PCED[27:20]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

PCED[19:12]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

PCED[11:4]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

PCED[3:0]

reserved

0

R

Table 64. HcPeriodCurrentED - Host Controller Period Current Endpoint Descriptor register bit description

Address: Content of the base address register + 1Ch

Bit

Symbol

Description

31 to 4 PCED[27:0] Period Current ED: This is used by the host controller to point to the head of one of the periodic

lists that must be processed in the current frame. The content of this register is updated by the

host controller after a periodic ED is processed. The HCD may read the content in determining

which ED is being processed at the time of reading.

3 to 0

reserved

-

11.1.9 HcControlHeadED register

The HcControlHeadED register contains the physical address of the ﬁrst ED of the control

list. The bit allocation is given in Table 65.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

45 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 65. HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit allocation

Address: Content of the base address register + 20h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

CHED[27:20]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

CHED[19:12]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

CHED[11:4]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

CHED[3:0]

reserved

0

R

Table 66. HcControlHeadED - Host Controller Control Head Endpoint Descriptor register bit description

Address: Content of the base address register + 20h

Bit

Symbol

Description

31 to 4 CHED[27:0] Control Head ED: The host controller traverses the control list, starting with the HcControlHeadED

pointer. The content is loaded from HCCA during the initialization of the host controller.

3 to 0

reserved

-

11.1.10 HcControlCurrentED register

The HcControlCurrentED register contains the physical address of the current ED of the

control list. The bit allocation is given in Table 67.

Table 67. HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit allocation

Address: Content of the base address register + 24h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

CCED[27:20]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

CCED[19:12]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

CCED[11:4]

0

R

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

46 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

CCED[3:0]

reserved

0

R

Table 68. HcControlCurrentED - Host Controller Control Current Endpoint Descriptor register bit description

Address: Content of the base address register + 24h

Bit

Symbol

Description

31 to 4

CCED[27:0] Control Current ED: This pointer is advanced to the next ED after serving the present. The host

controller must continue processing the list from where it left in the last frame. When it reaches

the end of the control list, the host controller checks CLF (bit 1 of HcCommandStatus). If set, it

copies the content of HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it

does nothing. The HCD is allowed to modify this register only when CLE (bit 4 in the HcControl

register) is cleared. When set, the HCD only reads the instantaneous value of this register.

Initially, this is set to logic 0 to indicate the end of the control list.

3 to 0

reserved

-

11.1.11 HcBulkHeadED register

This register (see Table 69) contains the physical address of the ﬁrst ED of the bulk list.

Table 69. HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit allocation

Address: Content of the base address register + 28h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

BHED[27:20]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

BHED[19:12]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

BHED[11:4]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

BHED[3:0]

reserved^[1]

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 70. HcBulkHeadED - Host Controller Bulk Head Endpoint Descriptor register bit description

Address: Content of the base address register + 28h

Bit

Symbol

Description

31 to 4 BHED[27:0] Bulk Head ED: The host controller traverses the bulk list starting with the HcBulkHeadED pointer.

The content is loaded from HCCA during the initialization of the host controller.

3 to 0

reserved

-

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

47 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

11.1.12 HcBulkCurrentED register

This register contains the physical address of the current endpoint of the bulk list. The

endpoints are ordered according to their insertion to the list because the bulk list must be

served in a round-robin fashion.

The bit allocation is given in Table 71.

Table 71. HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit allocation

Address: Content of the base address register + 2Ch

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

BCED[27:20]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

BCED[19:12]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

BCED[11:4]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

BCED[3:0]

reserved^[1]

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 72. HcBulkCurrentED - Host Controller Bulk Current Endpoint Descriptor register bit description

Address: Content of the base address register + 2Ch

Bit

Symbol

Description

31 to 4 BCED[27:0] Bulk Current ED: This is advanced to the next ED after the host controller has served the current

ED. The host controller continues processing the list from where it left off in the last frame. When it

reaches the end of the bulk list, the host controller checks CLF (bit 1 of HcCommandStatus). If the

CLF bit is not set, nothing is done. If the CLF bit is set, it copies the content of HcBulkHeadED to

HcBulkCurrentED and clears the CLF bit. The HCD can modify this register only when BLE (bit 5 in

the HcControl register) is cleared. When HcControl is set, the HCD reads the instantaneous value

of this register. This is initially set to logic 0 to indicate the end of the bulk list.

3 to 0

reserved

-

11.1.13 HcDoneHead register

The HcDoneHead register contains the physical address of the last completed TD that

was added to the done queue. In a normal operation, the HCD need not read this register

because its content is periodically written to the HCCA. Table 73 contains the bit allocation

of the register.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

48 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 73. HcDoneHead - Host Controller Done Head register bit allocation

Address: Content of the base address register + 30h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

DH[27:20]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

DH[19:12]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

DH[11:4]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

DH[3:0]

reserved^[1]

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 74. HcDoneHead - Host Controller Done Head register bit description

Address: Content of the base address register + 30h

Bit

Symbol

Description

31 to 4

DH[27:0] Done Head: When a TD is completed, the host controller writes the content of HcDoneHead to the

NextTD ﬁeld of the TD. The host controller then overwrites the content of HcDoneHead with the

address of this TD. This is set to logic 0 whenever the host controller writes the content of this

register to HCCA.

3 to 0

reserved

-

11.1.14 HcFmInterval register

This register contains a 14-bit value that indicates the bit time interval in a frame, that is,

between two consecutive SOFs, and a 15-bit value indicating the full-speed maximum

packet size that the host controller may transmit or receive, without causing a scheduling

overrun. The HCD may carry out minor adjustment on FI (Frame Interval) by writing a new

value over the present at each SOF. This provides the possibility for the host controller to

synchronize with an external clocking resource and to adjust any unknown local clock

offset. The bit allocation of the register is given in Table 75.

Table 75. HcFmInterval - Host Controller Frame Interval register bit allocation

Address: Content of the base address register + 34h

Bit

31

FIT

0

30

29

28

27

26

25

24

Symbol

Reset

Access

FSMPS[14:8]

0

R/W

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

49 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

FSMPS[7:0]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

FI[13:8]

0

R/W

7

0

R/W

6

1

R/W

5

0

R/W

4

1

R/W

3

1

R/W

2

1

R/W

1

0

R/W

0

Symbol

Reset

Access

FI[7:0]

1

0

1

R/W

[1] The reserved bits must always be written with the reset value.

Table 76. HcFmInterval - Host Controller Frame Interval register bit description

Address: Content of the base address register + 34h

Bit

Symbol

Description

31

FIT

Frame Interval Toggle: The HCD toggles this bit whenever it loads a new value to Frame

Interval.

30 to 16 FSMPS[14:0] FS Largest Data Packet: This ﬁeld speciﬁes the value that is loaded into the largest data

packet counter at the beginning of each frame. The counter value represents the largest amount

of data in bits that can be sent or received by the host controller in a single transaction at any

given time, without causing a scheduling overrun. The ﬁeld value is calculated by the HCD.

15 to 14 reserved

13 to 0 FI[13:0]

-

Frame Interval: This speciﬁes the interval between two consecutive SOFs in bit times. The

nominal value is set to 11,999. The HCD must store the current value of this ﬁeld before

resetting the host controller to reset this ﬁeld to its nominal value. The HCD can then restore the

stored value on completing the reset sequence.

11.1.15 HcFmRemaining register

This register is a 14-bit down counter showing the bit time remaining in the current frame.

Table 77 contains the bit allocation of this register.

Table 77. HcFmRemaining - Host Controller Frame Remaining register bit allocation

Address: Content of the base address register + 38h

Bit

31

FRT

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

50 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

reserved^[1]

FR[13:8]

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

7

Symbol

Reset

Access

FR[7:0]

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 78. HcFmRemaining - Host Controller Frame Remaining register bit description

Address: Content of the base address register + 38h

Bit

Symbol

Description

31

FRT

Frame Remaining Toggle: This bit is loaded from FIT (bit 31 of HcFmInterval) whenever

FR[13:0] reaches 0. This bit is used by the HCD for the synchronization between FI[13:0]

(bits 13 to 0 of HcFmInterval) and FR[13:0].

30 to 14

13 to 0

reserved

FR[13:0]

-

Frame Remaining: This counter is decremented at each bit time. When it reaches 0, it is reset by

loading the FI[13:0] value speciﬁed in HcFmInterval at the next bit time boundary. When entering

the USBOPERATIONAL state, the host controller reloads the content with FI[13:0] of

HcFmInterval and uses the updated value from the next SOF.

11.1.16 HcFmNumber register

This register is a 16-bit counter, and the bit allocation is given in Table 79.

It provides a timing reference among events happening in the host controller and the HCD.

The HCD may use the 16-bit value speciﬁed in this register and generate a 32-bit frame

number, without requiring frequent access to the register.

Table 79. HcFmNumber - Host Controller Frame Number register bit allocation

Address: Content of the base address register + 3Ch

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

reserved^[1]

FN[13:8]

0

R/W

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

51 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

Access

FN[7:0]

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 80. HcFmNumber - Host Controller Frame Number register bit description

Address: Content of the base address register + 3Ch

Bit

31 to 14 reserved

13 to 0 FN[13:0]

Symbol

Description

-

Frame Number: Incremented when HcFmRemaining is reloaded. It must be rolled over to 0h after

FFFFh. Automatically incremented when entering the USBOPERATIONAL state. The content is

written to HCCA after the host controller has incremented Frame Number at each frame boundary

and sent an SOF but before the host controller reads the ﬁrst ED in that frame. After writing to

HCCA, the host controller sets SF (bit 2 in HcInterruptStatus).

11.1.17 HcPeriodicStart register

This register has a 14-bit programmable value that determines when is the earliest time

for the host controller to start processing the periodic list. For bit allocation, see Table 81.

Table 81. HcPeriodicStart - Host Controller Periodic Start register bit allocation

Address: Content of the base address register + 40h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

P_S[13:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

P_S[7:0]

0

R/W

[1] The reserved bits must always be written with the reset value.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

52 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 82. HcPeriodicStart - Host Controller Periodic Start register bit description

Address: Content of the base address register + 40h

Bit

31 to 14 reserved

13 to 0 P_S[13:0]

Symbol

Description

-

Periodic Start: After a hardware reset, this ﬁeld is cleared. It is then set by the HCD during the

host controller initialization. The value is roughly calculated as 10 % of HcFmInterval. A typical

value is 3E67h. When HcFmRemaining reaches the value speciﬁed, processing of the periodic

lists have priority over control or bulk processing. The host controller, therefore, starts processing

the interrupt list after completing the current control or bulk transaction that is in progress.

11.1.18 HcLSThreshold register

This register contains an 11-bit value used by the host controller to determine whether to

commit to the transfer of a maximum of 8-byte low-speed packet before EOF. Neither the

host controller nor the HCD can change this value. For bit allocation, see Table 83.

Table 83. HcLSThreshold - Host Controller Low-Speed Threshold register bit allocation

Address: Content of the base address register + 44h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

LST[11:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

1

R/W

2

1

R/W

1

0

R/W

0

Symbol

Reset

Access

LST[7:0]

0

1

0

1

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 84. HcLSThreshold - Host Controller Low-Speed Threshold register bit description

Address: Content of the base address register + 44h

Bit

Symbol

reserved

LST[11:0]

Description

31 to 12

11 to 0

-

LS Threshold: This ﬁeld contains a value that is compared to the FR[13:0] ﬁeld, before initiating

a low-speed transaction. The transaction is started only if FR ≥ this ﬁeld. The value is calculated

by the HCD, considering the transmission and set-up overhead.

11.1.19 HcRhDescriptorA register

This register is the ﬁrst of two registers describing the characteristics of the root hub.

Reset values are implementation-speciﬁc.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

53 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 85 contains the bit allocation of the HcRhDescriptorA register.

Table 85. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit allocation

Address: Content of the base address register + 48h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

POTPGT[7:0]

1

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

12

0

R/W

11

0

R/W

10

DT

0

R/W

9

0

R/W

8

R/W

15

R/W

13

14

Symbol

Reset

Access

Bit

reserved^[1]

NOCP

0

OCPM

1

NPS

0

PSM

1

0

R/W

7

0

R/W

6

0

R/W

5

R/W

4

R/W

3

R

R/W

1

R/W

0

2

Symbol

Reset

Access

NDP[7:0]

0

1

0

R

[1] The reserved bits must always be written with the reset value.

Table 86. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description

Address: Content of the base address register + 48h

Bit

Symbol

Description

31 to 24

POTPGT

[7:0]

Power On To Power Good Time: This byte speciﬁes the duration the HCD must wait before

accessing a powered-on port of the root hub. It is implementation-speciﬁc. The unit of time is

2 ms. The duration is calculated as POTPGT × 2 ms.

23 to 13

12

reserved

NOCP

-

No Overcurrent Protection: This bit describes how the overcurrent status for root hub ports are

reported. When this bit is cleared, the OCPM bit speciﬁes global or per-port reporting.

0 — Overcurrent status is collectively reported for all downstream ports.

1 — No overcurrent protection supported.

11

10

OCPM

Overcurrent Protection Mode: This bit describes how the overcurrent status for root hub ports

are reported. At reset, this ﬁelds reﬂects the same mode as Power Switching Mode. This ﬁeld is

valid only if the NOCP bit is cleared.

0 — Overcurrent status is collectively reported for all downstream ports.

1 — Overcurrent status is reported on a per-port basis.

DT

Device Type: This bit speciﬁes that the root hub is not a compound device. The root hub is not

permitted to be a compound device. This ﬁeld must always read logic 0.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

54 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 86. HcRhDescriptorA - Host Controller Root Hub Descriptor A register bit description …continued

Address: Content of the base address register + 48h

Bit

Symbol

Description

9

NPS

No Power Switching: This bit is used to specify whether power switching is supported or ports

are always powered. It is implementation-speciﬁc. When this bit is cleared, the PSM bit speciﬁes

global or per-port switching.

0 — Ports are power switched.

1 — Ports are always powered on when the host controller is powered on.

8

PSM

Power Switching Mode: This bit is used to specify how the power switching of root hub ports is

controlled. It is implementation-speciﬁc. This ﬁeld is only valid if the NPS ﬁeld is cleared.

0 — All ports are powered at the same time.

1 — Each port is individually powered. This mode allows port power to be controlled by either the

global switch or per-port switching. If the PPCM (Port Power Control Mask) bit is set, the port

responds only to port power commands (Set/Clear Port Power). If the port mask is cleared, then

the port is controlled only by the global power switch (Set/Clear Global Power).

7 to 0

NDP[7:0]

Number Downstream Ports: These bits specify the number of downstream ports supported by

the root hub. It is implementation-speciﬁc. The minimum number of ports is 1. The maximum

number of ports supported by OHCI is 15.

11.1.20 HcRhDescriptorB register

The HcRhDescriptorB register is the second of two registers describing the characteristics

of the root hub. The bit allocation is given in Table 87. These ﬁelds are written during

initialization to correspond to the system implementation. Reset values are

implementation-speciﬁc.

Table 87. HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit allocation

Address: Content of the base address register + 4Ch

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

PPCM[15:0]

0

R

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

18

R/W

17

R/W

16

19

Symbol

Reset

Access

Bit

PPCM[7:0]

0

1

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

DR[15:8]

DR[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

0

R/W

ISP1564_2

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ISP1564

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HS USB PCI host controller

Table 88. HcRhDescriptorB - Host Controller Root Hub Descriptor B register bit description

Address: Content of the base address register + 4Ch

Bit

Symbol

Description

31 to 16 PPCM[15:0] Port Power Control Mask: Each bit indicates whether a port is affected by a global power control

command when Power Switching Mode is set. When set, only the power state of the port is

affected by per-port power control (Set/Clear Port Power). When cleared, the port is controlled by

the global power switch (Set/Clear Global Power). If the device is conﬁgured to global switching

mode (Power Switching Mode = 0), this ﬁeld is not valid.

Bit 0 — Reserved

Bit 1 — Ganged-power mask on port 1

Bit 2 — Ganged-power mask on port 2

15 to 0

DR[15:0]

Device Removable: Each bit is dedicated to a port of the root hub. When cleared, the attached

device is removable. When set, the attached device is not removable.

Bit 0 — Reserved

Bit 1 — Device attached to port 1

Bit 2 — Device attached to port 2

11.1.21 HcRhStatus register

This register is divided into two parts. The lower word of a DWORD represents the Hub

Status ﬁeld, and the upper word represents the Hub Status Change ﬁeld. Reserved bits

must always be written as logic 0. Table 89 shows the bit allocation of the register.

Table 89. HcRhStatus - Host Controller Root Hub Status register bit allocation

Address: Content of the base address register + 50h

Bit

31

CRWE

0

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

17

0

R/W

16

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

Symbol

Reset

Access

Bit

reserved^[1]

CCIC

0

LPSC

0

R/W

15

0

R/W

14

R/W

13

R/W

12

R/W

10

R/W

9

R/W

8

11

Symbol

Reset

Access

Bit

DRWE

0

reserved^[1]

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

7

Symbol

Reset

Access

reserved^[1]

OCI

0

LPS

0

R/W

R

RW

[1] The reserved bits must always be written with the reset value.

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 90. HcRhStatus - Host Controller Root Hub Status register bit description

Address: Content of the base address register + 50h

Bit

Symbol

Description

31

CRWE

On write Clear Remote Wake-up Enable:

0 — No effect

1 — Clears DRWE (Device Remote Wake-up Enable)

30 to 18 reserved

-

17

CCIC

Overcurrent Indicator Change: This bit is set by hardware when a change has occurred to the OCI

bit of this register.

0 — No effect

1 — The HCD clears this bit.

16

LPSC

On read Local Power Status Change: The root hub does not support the local power status feature.

Therefore, this bit is always logic 0.

On write Set Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to

this bit to turn on power to all ports (clear Port Power Status). In per-port power mode, it sets Port

Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no

effect.

15

DRWE

On read Device Remote Wake-up Enable: This bit enables bit Connect Status Change (CSC) as a

resume event, causing a state transition from USBSUSPEND to USBRESUME and setting the

Resume Detected interrupt.

0 — CSC is not a remote wake-up event.

1 — CSC is a remote wake-up event.

On write Set Remote Wake-up Enable: Writing logic 1 sets DRWE (Device Remote Wake-up

Enable). Writing logic 0 has no effect.

14 to 2 reserved

-

1

OCI

Overcurrent Indicator: This bit reports overcurrent conditions when global reporting is implemented.

When set, an overcurrent condition exists. When cleared, all power operations are normal. If the

per-port overcurrent protection is implemented, this bit is always logic 0.

0

LPS

On read Local Power Status: The root hub does not support the local power status feature.

Therefore, this bit is always read as logic 0.

On write Clear Global Power: In global power mode (Power Switching Mode = 0), logic 1 is written to

this bit to turn off power to all ports (clear Port Power Status). In per-port power mode, it clears Port

Power Status only on ports whose Port Power Control Mask bit is not set. Writing logic 0 has no

effect.

11.1.22 HcRhPortStatus[2:1] register

The HcRhPortStatus[2:1] register is used to control and report port events on a per-port

basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that

are implemented in hardware. The lower word reﬂects the port status. The upper word

reﬂects status change bits. Some status bits are implemented with special write behavior.

If a transaction, token through handshake, is in progress when a write to change port

status occurs, the resulting port status change is postponed until the transaction

completes. Always write logic 0 to the reserved bits. The bit allocation of the register is

given in Table 91.

ISP1564_2

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57 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 91. HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit allocation

Address: Content of the base address register + 54h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

22

0

R/W

19

0

R/W

18

0

R/W

17

0

R/W

16

R/W

23

R/W

21

R/W

20

Symbol

Reset

Access

Bit

reserved^[1]

PRSC

0

OCIC

0

PSSC

0

PESC

0

CSC

0

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

Symbol

Reset

Access

Bit

reserved^[1]

LSDA

0

PPS

0

R/W

7

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

R/W

1

R/W

0

6

reserved^[1]

0

Symbol

Reset

Access

PRS

0

POCI

0

PSS

0

PES

0

CCS

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 92. HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description

Address: Content of the base address register + 54h

Bit

Symbol

Description

31 to 21 reserved

-

20

19

PRSC

OCIC

Port Reset Status Change: This bit is set at the end of the 10 ms port reset signal. The HCD can

write logic 1 to clear this bit. Writing logic 0 has no effect.

0 — Port reset is not complete.

1 — Port reset is complete.

Port Overcurrent Indicator Change: This bit is valid only if overcurrent conditions are reported on

a per-port basis. This bit is set when the root hub changes the POCI (Port Overcurrent Indicator) bit.

The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect.

0 — No change in POCI.

1 — POCI has changed.

18

17

PSSC

PESC

Port Suspend Status Change: This bit is set when the resume sequence is completed. This

sequence includes the 20 ms resume pulse, LS EOP and 3 ms re-synchronization delay. The HCD

can write logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also cleared when Reset

Status Change is set.

0 — Resume is not completed.

1 — Resume is completed.

Port Enable Status Change: This bit is set when hardware events cause the PES (Port Enable

Status) bit to be cleared. Changes from the HCD writes do not set this bit. The HCD can write

logic 1 to clear this bit. Writing logic 0 has no effect.

0 — No change in PES.

1 — Change in PES.

ISP1564_2

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HS USB PCI host controller

Table 92. HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description …continued

Address: Content of the base address register + 54h

Bit

Symbol

Description

16

CSC

Connect Status Change: This bit is set whenever a connect or disconnect event occurs. The HCD

can write logic 1 to clear this bit. Writing logic 0 has no effect. If CCS (Current Connect Status) is

cleared when a Set Port Reset, Set Port Enable or Set Port Suspend write occurs, this bit is set to

force the driver to re-evaluate the connection status because these writes must not occur if the port

is disconnected.

0 — No change in CCS.

1 — Change in CCS.

Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a root hub reset to inform

the system that the device is attached.

15 to 10 reserved

-

9

LSDA

On read Low-Speed Device Attached: This bit indicates the speed of the device attached to this

port. When set, a low-speed device is attached to this port. When cleared, a full-speed device is

attached to this port. This ﬁeld is valid only when CCS is set.

0 — Port is not suspended.

1 — Port is suspended.

On write Clear Port Power: The HCD can clear the PPS (Port Power Status) bit by writing logic 1 to

this bit. Writing logic 0 has no effect.

8

PPS

On read Port Power Status: This bit reﬂects the port power status, regardless of the type of power

switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD can set

this bit by writing Set Port Power or Set Global Power. The HCD can clear this bit by writing Clear

Port Power or Clear Global Power. Power Switching Mode and PortPowerControlMask[NDP]

determine which power control switches are enabled. In Global Switching mode (Power Switching

Mode = 0), only Set/Clear Global Power controls this bit. In the per-port power switching (Power

Switching Mode = 1), if the PortPowerControlMask[NDP] bit for the port is set, only Set/Clear Port

Power commands are enabled. If the mask is not set, only Set/Clear Global Power commands are

enabled.

When port power is disabled, bits CCS (Current Connect Status), PES (Port Enable Status), PSS

(Port Suspend Status) and PRS (Port Reset Status) must be reset.

0 — Port power is off.

1 — Port power is on.

On write Set Port Power: The HCD can write logic 1 to set the PPS (Port Power Status) bit. Writing

logic 0 has no effect.

Remark: This bit always reads logic 1 if power switching is not supported.

7 to 5

4

reserved

PRS

-

On read Port Reset Status: When this bit is set by a write to Set Port Reset, port reset signaling is

asserted. When reset is completed and PRSC is set, this bit is cleared.

0 — Port reset signal is inactive.

1 — Port reset signal is active.

On write Set Port Reset: The HCD can set the port reset signaling by writing logic 1 to this bit.

Writing logic 0 has no effect. If CCS is cleared, this write does not set PRS (Port Reset Status) but

instead sets CCS. This informs the driver that it attempted to reset a disconnected port.

ISP1564_2

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ISP1564

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HS USB PCI host controller

Table 92. HcRhPortStatus[2:1] - Host Controller Root Hub Port Status[2:1] register bit description …continued

Address: Content of the base address register + 54h

Bit

Symbol

Description

3

POCI

On read Port Overcurrent Indicator: This bit is valid only when the root hub is conﬁgured to show

overcurrent conditions are reported on a per-port basis. If the per-port overcurrent reporting is not

supported, this bit is set to logic 0. If cleared, all power operations are normal for this port. If set, an

overcurrent condition exists on this port.

0 — No overcurrent condition.

1 — Overcurrent condition detected.

On write Clear Suspend Status: The HCD can write logic 1 to initiate a resume. Writing logic 0 has

no effect. A resume is initiated only if PSS (Port Suspend Status) is set.

2

PSS

On read Port Suspend Status: This bit indicates whether the port is suspended or is in the resume

sequence. It is set by a Set Suspend State write and cleared when PSSC (Port Suspend Status

Change) is set at the end of the resume interval. This bit is not set if CCS (Current Connect Status)

is cleared. This bit is also cleared when PRSC is set at the end of the port reset or when the host

controller is placed in the USBRESUME state. If an upstream resume is in progress, it will

propagate to the host controller.

0 — Port is not suspended.

1 — Port is suspended.

On write Set Port Suspend: The HCD can set the PSS (Port Suspend Status) bit by writing logic 1

to this bit. Writing logic 0 has no effect. If CCS is cleared, this write does not set PSS; instead it sets

CSS. This informs the driver that it attempted to suspend a disconnected port.

1

PES

On read Port Enable Status: This bit indicates whether the port is enabled or disabled. The root

hub may clear this bit when an overcurrent condition, disconnect event, switched-off power or

operational bus error is detected. This change also causes Port Enabled Status Change to be set.

The HCD can set this bit by writing Set Port Enable and clear it by writing Clear Port Enable. This bit

cannot be set when CCS (Current Connect Status) is cleared. This bit is also set on completing a

port reset when Reset Status Change is set or on completing a port suspend when Suspend Status

Change is set.

0 — Port is disabled.

1 — Port is enabled.

On write Set Port Enable: The HCD can set PES (Port Enable Status) by writing logic 1. Writing

logic 0 has no effect. If CCS is cleared, this write does not set PES, but instead sets CSC (Connect

Status Change). This informs the driver that it attempted to enable a disconnected port.

0

CCS

On read Current Connect Status: This bit reﬂects the current state of the downstream port.

0 — No device is connected.

1 — Device is connected.

On write Clear Port Enable: The HCD can write logic 1 to this bit to clear the PES (Port Enable

Status) bit. Writing logic 0 has no effect. The CCS bit is not affected by any write.

Remark: This bit always reads logic 1 when the attached device is nonremovable

(DeviceRemovable[NDP]).

11.2 EHCI controller capability registers

Other than the OHCI host controller, there are some registers in EHCI that deﬁne the

capability of EHCI. The address range of these registers is located before operational

registers.

11.2.1 CAPLENGTH/HCIVERSION register

The bit allocation of this 4-byte register is given in Table 93.

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 93. CAPLENGTH/HCIVERSION - Capability Length/Host Controller Interface Version Number register bit

allocation

Address: Content of the base address register + 00h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

HCIVERSION[15:8]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

1

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

HCIVERSION[7:0]

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

reserved

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

1

0

R

0

Symbol

Reset

Access

CAPLENGTH[7:0]

0

1

0

R

Table 94. CAPLENGTH/HCIVERSION - Capability Length/Host Controller Interface Version Number register bit

description

Address: Content of the base address register + 00h

Bit

Symbol

Description

31 to 16

HCIVERSION

[15:0]

Host Controller Interface Version Number: This ﬁeld contains a BCD encoded version

number of the interface to which the host controller interface conforms.

15 to 8

7 to 0

reserved

-

CAPLENGTH

[7:0]

Capability Register Length: This is used as an offset. It is added to the register base to ﬁnd

the beginning of the operational register space.

11.2.2 HCSPARAMS register

The Host Controller Structural Parameters (HCSPARAMS) register is a set of ﬁelds that

are structural parameters. The bit allocation is given in Table 95.

Table 95. HCSPARAMS - Host Controller Structural Parameters register bit allocation

Address: Content of the base address register + 04h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

0

R

ISP1564_2

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HS USB PCI host controller

Bit

15

14

13

12

11

10

N_PCC[3:0]

9

8

Symbol

Reset

Access

Bit

N_CC[3:0]

reserved

0

R

0

R

6

0

R

5

1

R

0

R

3

0

R

2

1

R

1

0

R

0

7

4

Symbol

Reset

Access

PRR

1

PPC

1

N_PORTS[3:0]

0

1

0

R

Table 96. HCSPARAMS - Host Controller Structural Parameters register bit description

Address: Content of the base address register + 04h

Bit

Symbol

Description

31 to 16 reserved

-

15 to 12 N_CC

[3:0]

Number of Companion Controller: This ﬁeld indicates the number of companion controllers

associated with this Hi-Speed USB host controller. A value of zero in this ﬁeld indicates there are no

companion host controllers. Port-ownership hand-off is not supported. Only high-speed devices are

supported on the host controller root ports. A value larger than zero in this ﬁeld indicates there are

companion Original USB host controller(s). Port-ownership hand-offs are supported.

11 to 8

N_PCC

[3:0]

Number of Ports per Companion Controller: This ﬁeld indicates the number of ports supported

per companion host controller. It is used to indicate the port routing conﬁguration to the system

software. For example, if N_PORTS has a value of 6 and N_CC has a value of 2, then N_PCC can

have a value of 3. The convention is that the ﬁrst N_PCC ports are assumed to be routed to

companion controller 1, the next N_PCC ports to companion controller 2, and so on. In the previous

example, N_PCC could have been 4, in which case the ﬁrst four are routed to companion

controller 1 and the last two are routed to companion controller 2.

The number in this ﬁeld must be consistent with N_PORTS and N_CC.

7

PRR

Port Routing Rules: This ﬁeld indicates the method used to map ports to companion controllers.

0 — The ﬁrst N_PCC ports are routed to the lowest numbered function companion host controller,

the next N_PCC ports are routed to the next lowest function companion controller, and so on.

1 — The port routing is explicitly enumerated by the ﬁrst N_PORTS elements of the

HCSP-PORTROUTE array.

6 to 5

4

reserved

PPC

-

Port Power Control: This ﬁeld indicates whether the host controller implementation includes port

power control. Logic 1 indicates the port has port power switches. Logic 0 indicates the port does

not have port power switches. The value of this ﬁeld affects the functionality of the Port Power ﬁeld

in each port status and control register.

3 to 0

N_PORTS Number of Ports: This ﬁeld speciﬁes the number of physical downstream ports implemented on

[3:0]

this host controller. The value in this ﬁeld determines how many port registers are addressable in

the operational register space. Logic 0 in this ﬁeld is undeﬁned.

11.2.3 HCCPARAMS register

The Host Controller Capability Parameters (HCCPARAMS) register is a 4-byte register,

and the bit allocation is given in Table 97.

ISP1564_2

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ISP1564

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HS USB PCI host controller

Table 97. HCCPARAMS - Host Controller Capability Parameters register bit allocation

Address: Content of the base address register + 08h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

0

R

0

R

0

R

0

R

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

2

0

R

0

R

1

0

Symbol

Reset

Access

IST[3:0]

reserved

PFLF

1

64AC

0

1

0

R

Table 98. HCCPARAMS - Host Controller Capability Parameters register bit description

Address: Content of the base address register + 08h

Bit

Symbol

reserved

IST[3:0]

Description

31 to 8

7 to 4

-

Isochronous Scheduling Threshold: Default = implementation dependent. This ﬁeld indicates,

relative to the current position of the executing host controller, where software can reliably update

the isochronous schedule. When IST[3] is logic 0, the value of the least signiﬁcant three bits

indicates the number of microframes a host controller can hold a set of isochronous data structures,

one or more, before ﬂushing the state. When IST[3] is logic 1, the host software assumes the host

controller may cache an isochronous data structure for an entire frame.

3 to 2

1

reserved

PFLF

-

Programmable Frame List Flag: Default = implementation dependent. If this bit is cleared, the

system software must use a frame list length of 1024 elements with the host controller. The

USBCMD register FLS[1:0] (bits 3 and 2) is read-only and must be cleared. If PFLF is set, the

system software can specify and use a smaller frame list, and conﬁgure the host through the FLS

bit. The frame list must always be aligned on a 4 kB page boundary to ensure that the frame list is

always physically contiguous.

0

64AC

64-bit Addressing Capability: This ﬁeld contains the addressing range capability.

0 — Data structures using 32-bit address memory pointers.

1 — Data structures using 64-bit address memory pointers.

11.2.4 HCSP-PORTROUTE register

The HCSP-PORTROUTE (Companion Port Route Description) register is an optional

read-only ﬁeld that is valid only if PRR (bit 7 in the HCSPARAMS register) is logic 1. Its

address is content of the base address register + 0Ch.

This ﬁeld is a 15-element nibble array, each 4 bits is one array element. Each array

location corresponds one-to-one with a physical port provided by the host controller. For

example, PORTROUTE[0] corresponds to the ﬁrst PORTSC port, PORTROUTE[1] to the

ISP1564_2

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HS USB PCI host controller

second PORTSC port, and so on. The value of each element indicates to which of the

companion host controllers this port is routed. Only the ﬁrst N_PORTS elements have

valid information. A value of zero indicates that the port is routed to the lowest numbered

function companion host controller. A value of one indicates that the port is routed to the

next lowest numbered function companion host controller, and so on.

11.3 Operational registers of enhanced USB host controller

11.3.1 USBCMD register

The USB Command (USBCMD) register indicates the command to be executed by the

serial host controller. Writing to this register causes a command to be executed. Table 99

shows the bit allocation.

Table 99. USBCMD - USB Command register bit allocation

Address: Content of the base address register + 20h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

ITC[7:0]

0

1

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

5

R/W

4

Symbol

LHCR

IAAD

ASE

PSE

FLS[1:0]

HC

RS

RESET

Reset

0

Access

R/W

[1] The reserved bits must always be written with the reset value.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

64 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 100. USBCMD - USB Command register bit description

Address: Content of the base address register + 20h

Bit

Symbol

Description

31 to 24 reserved

23 to 16 ITC[7:0]

-

Interrupt Threshold Control: Default = 08h. This ﬁeld is used by the system software to select the

maximum rate at which the host controller will issue interrupts. If software writes an invalid value to

this register, the results are undeﬁned. Valid values are:

00h — reserved

01h — 1 microframe

02h — 2 microframes

04h — 4 microframes

08h — 8 microframes (equals 1 ms)

10h — 16 microframes (equals 2 ms)

20h — 32 microframes (equals 4 ms)

40h — 64 microframes (equals 8 ms)

Software modiﬁcations to this ﬁeld while HCH (bit 12) in the USBSTS register is zero results in

undeﬁned behavior.

15 to 8

7

reserved

LHCR

-

Light Host Controller Reset: This control bit is not required. It allows the driver software to reset

the EHCI controller, without affecting the state of the ports or the relationship to the companion host

controllers. If not implemented, a read of this ﬁeld will always return zero. If implemented, on read:

0 — Indicates that the light host controller reset has completed and it is ready for the host software

to re-initialize the host controller.

1 — Indicates that the light host controller reset has not yet completed.

6

IAAD

Interrupt on Asynchronous Advance Doorbell: This bit is used as a doorbell by software to notify

the host controller to issue an interrupt the next time it advances the asynchronous schedule.

Software must write logic 1 to this bit to ring the doorbell. When the host controller has evicted all

appropriate cached schedule states, it sets IAA (bit 5 in the USBSTS register). If IAAE (bit 5 in the

USBINTR register) is logic 1, then the host controller will assert an interrupt at the next interrupt

threshold. The host controller sets this bit to logic 0 after it sets IAA. Software must not set this bit

when the asynchronous schedule is inactive because this results in an undeﬁned value.

ISP1564_2

Product data sheet

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65 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 100. USBCMD - USB Command register bit description …continued

Address: Content of the base address register + 20h

Bit

Symbol

Description

5

ASE

Asynchronous Schedule Enable: Default = 0. This bit controls whether the host controller skips

processing the asynchronous schedule.

0 — Do not process the asynchronous schedule.

1 — Use the ASYNCLISTADDR register to access the asynchronous schedule.

4

PSE

Periodic Schedule Enable: Default = 0. This bit controls whether the host controller skips

processing the periodic schedule.

0 — Do not process the periodic schedule.

1 — Use the PERIODICLISTBASE register to access the periodic schedule.

3 to 2

FLS[1:0]

Frame List Size: Default = 00b. This ﬁeld is read and write only if PFLF (bit 1) in the HCCPARAMS

register is set to logic 1. This ﬁeld speciﬁes the size of the frame list. The size the frame list controls

which bits in the Frame Index register must be used for the frame list current index.

00b — 1024 elements (4096 bytes)

01b — 512 elements (2048 bytes)

10b — 256 elements (1024 bytes) for small environments

11b — reserved

1

HCRESET Host Controller Reset: This control bit is used by the software to reset the host controller. The

effects of this on Root Hub registers are similar to a chip hardware reset. Setting this bit causes the

host controller to reset its internal pipelines, timers, counters, state machines, and so on, to their

initial values. Any transaction currently in progress on USB is immediately terminated. A USB reset

is not driven on downstream ports. This reset does not affect the PCI Conﬁguration registers. All

operational registers, including port registers and port state machines, are set to their initial values.

Port ownership reverts to the companion host controller(s). The software must re-initialize the host

controller to return it to an operational state. This bit is cleared by the host controller when the reset

process is complete. Software cannot terminate the reset process early by writing logic 0 to this

register. Software must check that bit HCH is logic 0 before setting this bit. Attempting to reset an

actively running host controller results in undeﬁned behavior.

0

RS

Run/Stop: 1 = Run. 0 = Stop. When set, the host controller executes the schedule. The host

controller continues execution as long as this bit is set. When this bit is cleared, the host controller

completes the current and active transactions in the USB pipeline, and then halts. Bit HCH indicates

when the host controller has ﬁnished the transaction and has entered the stopped state. Software

must check that the HCH bit is logic 1, before setting this bit.

11.3.2 USBSTS register

The USB Status (USBSTS) register indicates pending interrupts and various states of the

host controller. The status resulting from a transaction on the serial bus is not indicated in

this register. Software clears the register bits by writing ones to them. The bit allocation is

given in Table 101.

Table 101. USBSTS - USB Status register bit allocation

Address: Content of the base address register + 24h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

66 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

15

ASS

0

R/W

13

0

R/W

9

0

R/W

8

R/W

12

R/W

11

R/W

10

14

Symbol

Reset

Access

Bit

PSSTAT

RECL

0

HCH

1

reserved^[1]

0

R

6

0

R/W

1

0

R/W

0

R

R/W

3

R/W

2

7

5

4

Symbol

reserved^[1]

IAA

HSE

FLR

PCD

USB

USBINT

ERRINT

Reset

0

Access

R/W

R

R/W

[1] The reserved bits must always be written with the reset value.

Table 102. USBSTS - USB Status register bit description

Address: Content of the base address register + 24h

Bit

Symbol

Description

31 to 16 reserved

-

15

14

ASS

Asynchronous Schedule Status: Default = 0. The bit reports the current real status of the

asynchronous schedule. If this bit is logic 0, the status of the asynchronous schedule is disabled. If

this bit is logic 1, the status of the asynchronous schedule is enabled. The host controller is not

required to immediately disable or enable the asynchronous schedule when software changes ASE

(bit 5 in the USBCMD register). When this bit and the ASE bit have the same value, the

asynchronous schedule is either enabled (1) or disabled (0).

PSSTAT

Periodic Schedule Status: Default = 0. This bit reports the current status of the periodic schedule.

If this bit is logic 0, the status of the periodic schedule is disabled. If this bit is logic 1, the status of

the periodic schedule is enabled. The host controller is not required to immediately disable or

enable the periodic schedule when software changes PSE (bit 4) in the USBCMD register. When

this bit and the PSE bit have the same value, the periodic schedule is either enabled (1) or disabled

(0).

13

12

RECL

HCH

Reclamation: Default = 0. This is a read-only status bit that is used to detect an empty

asynchronous schedule.

HC Halted: Default = 1. This bit is logic 0 when RS (bit 0) in the USBCMD register is logic 1. The

host controller sets this bit to logic 1 after it has stopped executing because the RS bit is set to

logic 0, either by software or by the host controller hardware. For example, on an internal error.

11 to 6

5

reserved

IAA

-

Interrupt on Asynchronous Advance: Default = 0. The system software can force the host

controller to issue an interrupt the next time the host controller advances the asynchronous

schedule by writing logic 1 to IAAD (bit 6) in the USBCMD register. This status bit indicates the

assertion of that interrupt source.

4

HSE

Host System Error: The host controller sets this bit when a serious error occurs during a host

system access, involving the host controller module. In a PCI system, conditions that set this bit

include PCI parity error, PCI master abort and PCI target abort. When this error occurs, the host

controller clears RS (bit 0 in the USBCMD register) to prevent further execution of the scheduled

TDs.

ISP1564_2

Product data sheet

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67 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 102. USBSTS - USB Status register bit description …continued

Address: Content of the base address register + 24h

Bit

Symbol

Description

3

FLR

Frame List Rollover: The host controller sets this bit to logic 1 when the frame list index rolls over

from its maximum value to zero. The exact value at which the rollover occurs depends on the frame

list size. For example, if the frame list size, as programmed in FLS (bits 3 to 2) of the USBCMD

register, is 1024, the Frame Index register rolls over every time bit 13 of the FRINDEX register

toggles. Similarly, if the size is 512, the host controller sets this bit to logic 1 every time bit 12 of the

FRINDEX register toggles.

2

PCD

Port Change Detect: The host controller sets this bit to logic 1 when any port, where PO (bit 13 of

PORTSC) is cleared, changes to logic 1, or FPR (bit 6 of PORTSC) changes to logic 1 as a result of

a J-K transition detected on a suspended port. This bit is allowed to be maintained in the auxiliary

power well. Alternatively, it is also acceptable that, on a D3-to-D0 transition of the EHCI host

controller device, this bit is loaded with the logical OR of all the PORTSC change bits, including

force port resume, overcurrent change, enable or disable change, and connect status change.

1

0

USBERR USB Error Interrupt: The host controller sets this bit when an error condition occurs because of

INT

completing a USB transaction. For example, error counter underﬂow. If the Transfer Descriptor (TD)

on which the error interrupt occurred also had its IOC bit set, both this bit and the USBINT bit are

set. For details, refer to Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus

Rev. 1.0.

USBINT

USB Interrupt: The host controller sets this bit on completing a USB transaction, which results in

the retirement of a TD that had its IOC bit set. The host controller also sets this bit when a short

packet is detected, that is, the actual number of bytes received was less than the expected number

of bytes. For details, refer to Enhanced Host Controller Interface Speciﬁcation for Universal Serial

Bus Rev. 1.0.

11.3.3 USBINTR register

The USB Interrupt Enable (USBINTR) register enables and disables reporting of the

corresponding interrupt to the software. When a bit is set and the corresponding interrupt

is active, an interrupt is generated to the host. Interrupt sources that are disabled in this

register still appear in USBSTS to allow the software to poll for events. The USBSTS

register bit allocation is given in Table 103.

Table 103. USBINTR - USB Interrupt Enable register bit allocation

Address: Content of the base address register + 28h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1564_2

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Rev. 02 — 13 November 2008

68 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

7

6

5

4

3

2

1

0

Symbol

reserved^[1]

IAAE

HSEE

FLRE

PCIE

USBERR

INTE

USBINTE

Reset

0

Access

R/W

[1] The reserved bits must always be written with the reset value.

Table 104. USBINTR - USB Interrupt Enable register bit description

Address: Content of the base address register + 28h

Bit

Symbol

reserved

IAAE

Description

31 to 6

5

-

Interrupt on Asynchronous Advance Enable: When this bit and IAA (bit 5 in the USBSTS

register) are set, the host controller issues an interrupt at the next interrupt threshold. The interrupt

is acknowledged by software clearing bit IAA.

4

3

2

1

HSEE

FLRE

PCIE

USB

Host System Error Enable: When this bit and HSE (bit 4 in the USBSTS register) are set, the host

controller issues an interrupt. The interrupt is acknowledged by software clearing bit HSE.

Frame List Rollover Enable: When this bit and FLR (bit 3 in the USBSTS register) are set, the host

controller issues an interrupt. The interrupt is acknowledged by software clearing bit FLR.

Port Change Interrupt Enable: When this bit and PCD (bit 2 in the USBSTS register) are set, the

host controller issues an interrupt. The interrupt is acknowledged by software clearing bit PCD.

USB Error Interrupt Enable: When this bit and USBERRINT (bit 1 in the USBSTS register) are set,

ERRINTE the host controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged

by software clearing bit USBERRINT.

0

USBINTE USB Interrupt Enable: When this bit and USBINT (bit 0 in the USBSTS register) are set, the host

controller issues an interrupt at the next interrupt threshold. The interrupt is acknowledged by

software clearing bit USBINT.

11.3.4 FRINDEX register

The Frame Index (FRINDEX) register is used by the host controller to index into the

periodic frame list. The register updates every 125 µs, once each microframe. Bits N to 3

are used to select a particular entry in the periodic frame list during periodic schedule

execution. The number of bits used for the index depends on the size of the frame list as

set by the system software in FLS[1:0] (bits 3 to 2) of the USBCMD register. This register

must be written as a DWORD. Byte writes produce undeﬁned results. This register cannot

be written unless the host controller is in the halted state, as indicated by HCH (bit 12 in

the USBSTS register). A write to this register while RS (bit 0 in the USBCMD register) is

set produces undeﬁned results. Writes to this register also affect the SOF value.

The bit allocation is given in Table 105.

Table 105. FRINDEX - Frame Index register bit allocation

Address: Content of the base address register + 2Ch

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

69 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

11

R/W

10

12

Symbol

Reset

Access

Bit

reserved^[1]

FRINDEX[13:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

FRINDEX[7:0]

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 106. FRINDEX - Frame Index register bit description

Address: Content of the base address register + 2Ch

Bit

Symbol

Description

31 to 14

13 to 0

reserved

-

FRINDEX [13:0] Frame Index: Bits in this register are used for the frame number in the SOF packet and as

the index into the frame list. The value in this register increments at the end of each time

frame. For example, microframe. The bits used for the frame number in the SOF token are

taken from bits 13 to 3 of this register. Bits N to 3 are used for the frame list current index.

This means that each location of the frame list is accessed eight times, frames or

microframes, before moving to the next index.

Table 107 illustrates N based on the value of FLS[1:0] (bits 3 to 2 in the USBCMD register).

Table 107. N based value of FLS[1:0]

FLS[1:0]

00b

Number elements

N

1024

512

12

11

10

-

01b

10b

256

11b

reserved

11.3.5 PERIODICLISTBASE register

The Periodic Frame List Base Address (PERIODICLISTBASE) register contains the

beginning address of the periodic frame list in the system memory. If the host controller is

in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of the HCCPARAMS register), the

most signiﬁcant 32 bits of every control data structure address comes from the

CTRLDSSEGMENT register. For details on the CTRLDSSEGMENT register, refer to

Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0. The

system software loads this register before starting the schedule execution by the host

controller. The memory structure referenced by this physical memory pointer is assumed

as 4 kB aligned. The contents of this register are combined with the FRINDEX register to

enable the host controller to step through the periodic frame list in sequence.

The bit allocation is given in Table 108.

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 108. PERIODICLISTBASE - Periodic Frame List Base Address register bit allocation

Address: Content of the base address register + 34h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

BA[19:12]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

BA[11:4]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

BA[3:0]

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved^[1]

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 109. PERIODICLISTBASE - Periodic Frame List Base Address register bit description

Address: Content of the base address register + 34h

Bit

Symbol

BA[19:0]

reserved

Description

31 to 12

11 to 0

Base Address: These bits correspond to memory address signals 31 to 12, respectively.

-

11.3.6 ASYNCLISTADDR register

This 32-bit register contains the address of the next asynchronous queue head to be

executed. If the host controller is in 64-bit mode, as indicated by logic 1 in 64AC (bit 0 of

the HCCPARAMS register), the most signiﬁcant 32 bits of every control data structure

address comes from the CTRLDSSEGMENT register. For details on the

CTRLDSSEGMENT register, refer to Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0. Bits 4 to 0 of this register always return zeros when read.

The memory structure referenced by the physical memory pointer is assumed as 32 bytes

(cache aligned). For bit allocation, see Table 110.

Table 110. ASYNCLISTADDR - Current Asynchronous List Address register bit allocation

Address: Content of the base address register + 38h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

LPL[26:19]

0

R/W

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

71 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

LPL[18:11]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

11

R/W

10

12

Symbol

Reset

Access

Bit

LPL[10:3]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

1

0

R/W

0

R/W

2

reserved^[1]

0

Symbol

Reset

Access

LPL[2:0]

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 111. ASYNCLISTADDR - Current Asynchronous List Address register bit description

Address: Content of the base address register + 38h

Bit

Symbol

Description

31 to 5

LPL[26:0] Link Pointer List: These bits correspond to memory address signals 31 to 12, respectively. This

ﬁeld may only reference a Queue Head (QH).

4 to 0

reserved

-

11.3.7 CONFIGFLAG register

The bit allocation of the Conﬁgure Flag (CONFIGFLAG) register is given in Table 112.

Table 112. CONFIGFLAG - Conﬁgure Flag register bit allocation

Address: Content of the base address register + 60h

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

4

reserved^[1]

0

Symbol

Reset

Access

CF

0

R/W

[1] The reserved bits must always be written with the reset value.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

72 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 113. CONFIGFLAG - Conﬁgure Flag register bit description

Address: Content of the base address register + 60h

Bit

Symbol

reserved

CF

Description

31 to 1

0

-

Conﬁgure Flag: The host software sets this bit as the last action in its process of conﬁguring

the host controller. This bit controls the default port-routing control logic.

0 — Port routing control logic default-routes each port to an implementation dependent classic

host controller.

1 — Port routing control logic default-routes all ports to this host controller.

11.3.8 PORTSC registers 1, 2

The Port Status and Control (PORTSC) register is in the auxiliary power well. It is only

reset by hardware when the auxiliary power is initially applied or in response to a host

controller reset. The initial conditions of a port are:

• No device connected

• Port disabled

If the port has power control, software cannot change the state of the port until it sets port

power bits. Software must not attempt to change the state of the port until power is stable

on the port; maximum delay is 20 ms from the transition. For bit allocation, see Table 114.

Table 114. PORTSC 1, 2 - Port Status and Control 1, 2 register bit allocation

Address: Content of the base address register + 64h + (4 × Port Number − 1) where Port Number is 1, 2

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

0

R/W

0

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

23

22

20

Symbol

reserved

WKOC_E

WKDS

CNNT_E

WKCNNT_

E

PTC[3:0]

Reset

Access

Bit

0

R/W

13

0

R/W

12

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

PO

1

PP

0

LS[1:0]

reserved^[1]

PR

0

R/W

7

0

R/W

6

0

R/W

3

0

R/W

2

0

R/W

1

R/W

5

R/W

4

R

0

Symbol

Reset

Access

SUSP

0

FPR

0

OCC

0

OCA

0

PEDC

0

PED

0

ECSC

0

ECCS

0

R/W

R

R/W

R

[1] The reserved bits must always be written with the reset value.

ISP1564_2

Product data sheet

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 115. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description

Address: Content of the base address register + 64h + (4 × Port Number − 1) where Port Number is 1, 2

Bit

Symbol

reserved

WKOC_E

Description

31 to 23

22

-

Wake on Overcurrent Enable: Default = 0. Setting this bit enables the port to be sensitive to

overcurrent conditions as wake-up events.^[1]

21

WKDS

CNNT_E

Wake on Disconnect Enable: Default = 0. Setting this bit enables the port to be sensitive to

device disconnects as wake-up events.^[1]

20

WKCNNT_E Wake on Connect Enable: Default = 0. Setting this bit enables the port to be sensitive to device

connects as wake-up events.^[1]

19 to 16

PTC[3:0]

Port Test Control: Default = 0000b. When this ﬁeld is logic 0, the port is not operating in test

mode. A nonzero value indicates that it is operating in test mode and test mode is indicated by

the value. The encoding of test mode bits are:

0000b — Test mode disabled

0001b — Test J_STATE

0010b — Test K_STATE

0011b — Test SE0_NAK

0100b — Test packet

0101b — Test FORCE_ENABLE

0110b to 1111b — reserved

-

15 to 14

13

reserved

PO

Port Owner: Default = 1. This bit unconditionally goes to logic 0 when CF (bit 0) in the

CONFIGFLAG register makes logic 0 to logic 1 transition. This bit unconditionally goes to logic 1

when the CF bit is logic 0. The system software uses this ﬁeld to release ownership of the port to

a selected host controller, if the attached device is not a high-speed device. Software writes

logic 1 to this bit, if the attached device is not a high-speed device. Logic 1 in this bit means that

a companion host controller owns and controls the port.

12

PP

Port Power: The function of this bit depends on the value of PPC (bit 4) in the HCSPARAMS

register.

If PPC = 0 and PP = 1 — The host controller does not have port power control switches. Always

powered.

If PPC = 1 and PP = 1 or 0 — The host controller has port power control switches. This bit

represents the current setting of the switch: logic 0 = off, logic 1 = on. When PP is logic 0, the

port is nonfunctional and will not report any status.

When an overcurrent condition is detected on a powered port and PPC is logic 1, the PP bit in

each affected port may be changed by the host controller from logic 1 to logic 0, removing power

from the port.

11 to 10

LS[1:0]

Line Status: This ﬁeld reﬂects the current logical levels of the DP (bit 11) and DM (bit 10) signal

lines. These bits are used to detect low-speed USB devices before the port reset and enable

sequence. This ﬁeld is valid only when the Port Enable bit is logic 0, and the Current Connect

Status bit is set to logic 1.

00b — SE0: Not a low-speed device, perform EHCI reset

01b — K-state: Low-speed device, release ownership of the port

10b — J-state: Not a low-speed device, perform EHCI reset

11b — Undeﬁned: Not a low-speed device, perform EHCI reset

If the PP bit is logic 0, this ﬁeld is undeﬁned.

-

9

reserved

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 115. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description …continued

Address: Content of the base address register + 64h + (4 × Port Number − 1) where Port Number is 1, 2

Bit

Symbol

Description

8

PR

Port Reset: Logic 1 means the port is in reset. Logic 0 means the port is not in reset.

Default = 0. When software sets this bit from logic 0, the bus reset sequence as deﬁned in

Universal Serial Bus Speciﬁcation Rev. 2.0 is started. Software clears this bit to terminate the

bus reset sequence. Software must hold this bit at logic 1 until the reset sequence, as speciﬁed

in Universal Serial Bus Speciﬁcation Rev. 2.0, is completed.

Remark: When software sets this bit, it must also clear the Port Enable bit.

Remark: When software clears this bit, there may be a delay before the bit status changes to

logic 0 because it will not read logic 0 until the reset is completed. If the port is in high-speed

mode after reset is completed, the host controller will automatically enable this port; it can set

the Port Enable bit. A host controller must terminate the reset and stabilize the state of the port

within 2 ms of software changing this bit from logic 1 to logic 0. For example, if the port detects

that the attached device is high-speed during a reset, then the host controller must enable the

port within 2 ms of software clearing this bit.

HCH (bit 12) in the USBSTS register must be logic 0 before software attempts to use this bit.

The host controller may hold Port Reset asserted when the HCH bit is set.^[1]

7

SUSP

Suspend: Default = 0. Logic 1 means the port is in the suspend state. Logic 0 means the port is

not suspended. The PED (Port Enabled) bit and this bit deﬁne the port states as follows:

PED = 0 and SUSP = X — Port is disabled.

PED = 1 and SUSP = 0 — Port is enabled.

PED = 1 and SUSP = 1 — Port is suspended.

When in the suspend state, downstream propagation of data is blocked on this port, except for

the port reset. If a transaction was in progress when this bit was set, blocking occurs at the end

of the current transaction. In the suspend state, the port is sensitive to resume detection. The bit

status does not change until the port is suspended and there may be a delay in suspending a

port, if there is a transaction currently in progress on USB. Attempts to clear this bit are ignored

by the host controller. The host controller will unconditionally set this bit to logic 0 when:

• Software changes the FPR (Force Port Resume) bit to logic 0.

• Software changes the PR (Port Reset) bit to logic 1.

If the host software sets this bit when the Port Enabled bit is logic 0, the results are undeﬁned.^[1]

6

FPR

Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no

resume (K-state) detected or driven on the port. Default = 0. Software sets this bit to drive the

resume signaling. The host controller sets this bit if a J-to-K transition is detected, while the port

is in the suspend state. When this bit changes to logic 1 because a J-to-K transition is detected,

PCD (bit 2) in the USBSTS register is also set to logic 1. If software sets this bit to logic 1, the

host controller must not set the PCD bit. When the EHCI controller owns the port, the resume

sequence follows the sequence speciﬁed in Universal Serial Bus Speciﬁcation Rev. 2.0. The

resume signaling (full-speed ‘K’) is driven on the port as long as this bit remains set. Software

must time the resume and clear this bit after the correct amount of time has elapsed. Clearing

this bit causes the port to return to high-speed mode, forcing the bus below the port into a

high-speed idle. This bit will remain at logic 1, until the port has switched to the high-speed idle.

The host controller must complete this transition within 2 ms of software clearing this bit.^[1]

5

4

OCC

OCA

Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a change in

overcurrent active. Software clears this bit by setting it to logic 1.

Overcurrent Active: Default = 0. If set to logic 1, this port has an overcurrent condition. If set to

logic 0, this port does not have an overcurrent condition. This bit will automatically change from

logic 1 to logic 0 when the overcurrent condition is removed.

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 115. PORTSC 1, 2 - Port Status and Control 1, 2 register bit description …continued

Address: Content of the base address register + 64h + (4 × Port Number − 1) where Port Number is 1, 2

Bit

Symbol

Description

3

PEDC

Port Enable/Disable Change: Logic 1 means the port enabled or disabled status has changed.

Logic 0 means no change. Default = 0. For the root hub, this bit is set only when a port is

disabled because of the appropriate conditions existing at the EOF2 point. For deﬁnition of port

error, refer to Chapter 11 of Universal Serial Bus Speciﬁcation Rev. 2.0. Software clears this bit

by setting it.^[1]

2

PED

Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. Default = 0. Ports can

only be enabled by the host controller as a part of the reset and enable sequence. Software

cannot enable a port by writing logic 1 to this ﬁeld. The host controller will only set this bit when

the reset sequence determines that the attached device is a high-speed device. Ports can be

disabled by either a fault condition or by host software. The bit status does not change until the

port state has changed. There may be a delay in disabling or enabling a port because of other

host controller and bus events. When the port is disabled, downstream propagation of data is

blocked on this port, except for reset.^[1]

1

0

ECSC

ECCS

Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change.

Default = 0. This bit indicates a change has occurred in the ECCS of the port. The host

controller sets this bit for all changes to the port device connect status, even if the system

software has not cleared an existing connect status change. For example, the insertion status

changes two times before the system software has cleared the changed condition, hub

hardware will be setting an already-set bit, that is, the bit will remain set. Software clears this bit

by writing logic 1 to it.^[1]

Current Connect Status: Logic 1 indicates a device is present on the port. Logic 0 indicates no

device is present. Default = 0. This value reﬂects the current state of the port and may not

directly correspond to the event that caused the ECSC bit to be set.^[1]

[1] These ﬁelds read logic 0, if the PP bit is logic 0.

11.4 Miscellaneous registers

The ISP1564 employs mechanisms to improve throughput in USB transfers. In certain

system in which PCI throughput is low, however, these mechanisms may fail. The system

tuning register provide a mean to disable these mechanisms using software. For bit

allocation of the register, see Table 116.

Table 116. System Tuning register bit allocation

Address: Content of the base address register + 6Ch

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Bit

7

6

5

4

3

2

1

0

WMD

0

Symbol

Reset

Access

reserved^[1]

RBD

0

R/W

[1] The reserved bits must always be written with the reset value.

Table 117. System Tuning register bit description

Address: Content of the base address register + 6Ch

Bit

Symbol

Description

31 to 2

1

-

reserved

RBD

Ring Buffering Disable: Default = SYS_TUNE pin. To enable the ring buffering, clear the RBD bit

to logic 0. To disable the ring buffering, set the RBD bit to logic 1.

The ISP1564 employs the ring buffering mechanism to improve throughput in USB IN transfers.

This mechanism allows the start of an IN packet transfer immediately after a previous IN packet is

received.

In some systems, with congested PCI bus, data overrun conditions may occur when the ring

buffering is enabled. Software can set this bit to disable the ring buffering. See Table 118.

Remark: If the SYS_TUNE pin is connected to V_CC, the RBD bit will always be logic 1.

0

WMD

Watermark Disable: Default = SYS_TUNE pin. To enable the watermark feature, clear the WMD

bit to logic 0; to disable the watermark feature, set WMD to logic 1.

The ISP1564 employs a watermark mechanism to improve throughput in USB OUT transfers.

This mechanism starts USB transfer over the USB bus when data fetched from the host system

reaches the watermark level (191 bytes, 255 bytes, 383 bytes, 511 bytes, 639 bytes and 767 bytes)

just before the full packet size. For example, the ISP1564 will start transferring an OUT packet of

size 1024 bytes over the USB bus when 767 bytes has been fetched from the host system.

In some systems, with congested PCI bus, data underrun conditions may occur when the

watermark is enabled. Software can set this bit to disable the watermark feature. See Table 119.

Remark: If the SYS_TUNE pin is connected to V_CC, the WMD bit will always be logic 1.

Table 118. Ring buffering disable

SYS_TUNE pin

LOW

RBD bit

Ring buffering

enable

0

1

X

LOW

disable

HIGH

disable

Table 119. Watermark disable

SYS_TUNE pin

LOW

WMD bit

Watermark

enable

0

1

X

LOW

disable

HIGH

disable

ISP1564_2

Product data sheet

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ISP1564

NXP Semiconductors

HS USB PCI host controller

12. Limiting values

Table 120. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC(IO)

Parameter

Conditions

Min

−0.5

Max

+4.6

Unit

V

IO supply voltage

regulator supply voltage

V_CC(REG)

V_CC(IO)AUX

V

auxiliary input/output supply

voltage

V

V_CC(AUX)

V_CCA(AUX)

I_lu

auxiliary supply voltage

auxiliary analog supply voltage

latch-up current

−0.5

-

+4.6

100

+2

V

V_I< 0 V or V_I> V_CC(IO)

mA

kV

°C

[1]

V_esd

electrostatic discharge voltage

storage temperature

all pins (I_LI< 1 µA)

−2

T_stg

−40

+125

[1] Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model JESD22-A114C).

13. Recommended operating conditions

Table 121. Recommended operating conditions

Symbol

Parameter

Conditions

Min

3.0

0

Typ

3.3

-

Max

3.6

Unit

V_CC(IO)

IO supply voltage

V

°C

V_CC(REG)regulator supply voltage

3.6

V_CC(IO)AUXauxiliary input/output supply voltage

3.6

V_CC(AUX)

auxiliary supply voltage

3.6

V_CCA(AUX)auxiliary analog supply voltage

3.6

V_I

input voltage

V_CC(IO)

1.95

+85

V_i(XTAL1)

T_amb

input voltage on pin XTAL1

ambient temperature

0

-

−40

-

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ISP1564

NXP Semiconductors

HS USB PCI host controller

14. Static characteristics

Table 122. Static characteristics: I²C-bus interface (SDA and SCL)

V_CC(IO)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

V_IH

Parameter

Conditions

Min

Typ

Max

Unit

V

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

0.7 × V_CC(IO)

-

V_IL

-

0.3 × V_CC(IO)

V

V_hys

0.15

-

V

V_OL

LOW-level output voltage

suspend supply current

I_OL= 3 mA

-

0.4

-

V

I_CC(susp)

1

µA

Table 123. Static characteristics: digital pins (PWE1_N, OC1_N, PWE2_N and OC2_N)

V_CC(IO)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

V_IH

Parameter

Conditions

Min

2.0

-

Typ

Max

Unit

V

HIGH-level input voltage

LOW-level input voltage

hysteresis voltage

-

V_IL

0.8

-

V

V_hys

V_OL

0.4

-

V

LOW-level output voltage I_OL= 3 mA

HIGH-level output voltage

0.4

-

V

V_OH

2.4

V

Table 124. Static characteristics: PCI interface block

V_CC(IO)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

V_IH

Parameter

Conditions

Min

Typ

Max

Unit

V

HIGH-level input voltage

LOW-level input voltage

input pull-up voltage

input leakage current

HIGH-level output voltage

LOW-level output voltage

input capacitance

0.5 × V_CC(IO)

-

V_IL

-

0.3 × V_CC(IO)

V

V_IPU

I_LI

2.1

−10

2.7

-

V

0 V < V_I< V_CC(IO)

I_O= 500 µA

+10

-

µA

V

V_OH

V_OL

I_O= 1500 µA

0.3

10

12

8

V

C_in

-

pF

C_clk

clock capacitance

5

C_IDSEL

IDSEL pin capacitance

-

Table 125. Static characteristics: USB interface block (pins DM1 to DM2 and DP1 to DP2)

V_CCA(AUX)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CCA(AUX)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input levels for high-speed

V_HSSQ

V_HSDSC

ISP1564_2

high-speed squelch detection

threshold voltage (differential

signal amplitude)

100

-

150

mV

high-speed disconnect detection

threshold voltage (differential

signal amplitude)

525

-

625

mV

Product data sheet

Rev. 02 — 13 November 2008

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 125. Static characteristics: USB interface block (pins DM1 to DM2 and DP1 to DP2) …continued

V_CCA(AUX)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CCA(AUX)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_HSDI

high-speed differential input

sensitivity

|V_DP− V_DM

|

300

-

mV

V_HSCM

high-speed data signaling

common mode voltage range

(guideline for receiver)

−50

-

+500

mV

Output levels for high-speed

V_HSOI

high-speed idle level voltage

−10

-

+10

440

mV

V_HSOH

high-speed data signaling

HIGH-level voltage

360

V_HSOL

high-speed data signaling

LOW-level voltage

−10

-

+10

mV

V_CHIRPJ

V_CHIRPK

Chirp J level (differential voltage)

700^[1]

−900^[1]

-

1100

mV

Chirp K level (differential

voltage)

−500

Input levels for full-speed and low-speed

V_IH

HIGH-level input voltage

drive

2.0

2.7

-

V

V_IHZ

HIGH-level input voltage

3.6

(ﬂoating) for low-/full-speed

V_IL

V_DI

LOW-level input voltage

-

0.8

-

V

differential input sensitivity

voltage

|V_DP− V_DM

|

0.2

V_CM

differential common mode

voltage range

0.8

-

2.5

V

Output levels for full-speed and low-speed

V_OH

HIGH-level output voltage

LOW-level output voltage

SE1 output voltage

2.8

0

-

3.6

0.3

-

V

V_OL

V_OSE1

V_CRS

0.8

1.3

output signal crossover voltage

2.0

Leakage current

I_LZ

off-state leakage current

−1

-

+1

5

µA

Capacitance

C_in

input capacitance

pin to GND

-

pF

[1] High-speed termination resistor disabled, pull-up resistor connected. Only during reset, when both the hub and the device are capable

of high-speed operation.

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HS USB PCI host controller

Table 126. Current consumption

V_CC(IO)AUX= 3.0 V to 3.6 V; V_CC(AUX)= 3.0 V to 3.6 V; V_CCA(AUX)= 3.0 V to 3.6 V; V_CC(IO)= 3.0 V to 3.6 V;

_CC(REG)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)AUX= 3.3 V; V_CC(AUX)= 3.3 V; V_CCA(AUX)= 3.3 V; V_CC(IO)= 3.3 V; V_CC(REG)= 3.3 V;

_amb= +25 °C; unless otherwise speciﬁed.

V

T

Cumulative current

Conditions

Typ

27

54

75

19

43

63

8

Unit

mA

Total current on pins V_CC(IO)AUX

plus V_CC(AUX)plus V_CCA(AUX)plus

no device connected to the ISP1564^[1]

one high-speed device connected to the ISP1564

two high-speed devices connected to the ISP1564

V_CC(IO)plus V_CC(REG)

Auxiliary current on pins V_CC(IO)AUXno device connected to the ISP1564^[1]

plus V_CC(AUX)plus V_CCA(AUX)

one high-speed device connected to the ISP1564

two high-speed devices connected to the ISP1564

no device connected to the ISP1564^[1]

On pins V_CC(IO)plus V_CC(REG)

one high-speed device connected to the ISP1564

two high-speed devices connected to the ISP1564

11

12

[1] When one or two full-speed or low-speed power devices are connected, the current consumption is comparable to the current

consumption when no high-speed devices are connected. There is a difference of approximately 1 mA.

Table 127. Current consumption: S1 and S3

V_CC(IO)AUX= 3.0 V to 3.6 V; V_CC(AUX)= 3.0 V to 3.6 V; V_CCA(AUX)= 3.0 V to 3.6 V; V_CC(IO)= 3.0 V to 3.6 V;

V

_CC(REG)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)AUX= 3.3 V; V_CC(AUX)= 3.3 V; V_CCA(AUX)= 3.3 V; V_CC(IO)= 3.3 V; V_CC(REG)= 3.3 V;

_amb= +25 °C; unless otherwise speciﬁed.

T

Current consumption

Typ

2.10

160

Unit

mA

µA

S1^[1]

S3^[2]

[1] S1 represents the system state that will determine the B1 and D1 states. For details, refer to PCI Bus Power Management Interface

Speciﬁcation Rev. 1.1.

[2] S3 represents the system state that will determine the B3 and D3 states. For details, refer to PCI Bus Power Management Interface

Speciﬁcation Rev. 1.1.

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

15. Dynamic characteristics

Table 128. Dynamic characteristics: system clock timing

V_CC(IO)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

PCI clock

f_clk(PCI)

Parameter

Conditions

Min

Typ

Max

Unit

PCI clock frequency

31

-

33

MHz

Crystal speciﬁcation

[1]

f_clk

R_S

C_L

clock frequency

-

12

-

MHz

Ω

series resistance

load capacitance

100

-

18

-

pF

t_{jit(i)(XTAL1)RMS}RMS input jitter on pin XTAL1

∆f/f frequency stability

External clock speciﬁcation

200

50

ps

on pin XTAL1

-

ppm

f_i(XTAL1)

input frequency on pin XTAL1

-

12

-

MHz

ps

t_{jit(i)(XTAL1)RMS}RMS input jitter on pin XTAL1

200

50

∆f_i(XTAL1)

input frequency tolerance on

pin XTAL1

-

ppm

δ_i(XTAL1)

input duty cycle on pin XTAL1

45

50

55

%

[1] Suggested values for external capacitors are 22 pF to 27 pF.

Table 129. Dynamic characteristics: I²C-bus interface (SDA and SCL)

V_CC(IO)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t_f(o)

output fall time

V_IHto V_IL; 10 pF < C_b< 400 pF^[1]

-

0

250

ns

[1] The capacitive load for each bus line (C_b) is speciﬁed in pF. To meet the speciﬁcation for V_OLand the maximum rise time (300 ns), use

an external pull-up resistor with R_UP(max)= 850 / C_bkΩ and R_UP(min)= (V_CC(IO)− 0.4) / 3 kΩ.

Table 130. Dynamic characteristics: PCI interface block

V_CC(IO)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SR

slew rate

standard load^[1]

1

-

4

V/ns

[1] Standard load is 10 pF together with a pull-up and pull-down resistor of 10 kΩ.

Table 131. Dynamic characteristics: high-speed source electrical characteristics

V_CCA(AUX)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CCA(AUX)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Driver characteristics

Conditions

Min

Typ

Max

Unit

t_HSR

t_HSF

rise time (10 % to 90 %)

fall time (10 % to 90 %)

500

-

ps

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 131. Dynamic characteristics: high-speed source electrical characteristics …continued

V_CCA(AUX)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CCA(AUX)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Z_HSDRVdriver output impedance (which also includes the R_S

serves as high-speed termination) resistor

Clock timing

Conditions

Min

Typ

Max

Unit

40.5

45

49.5

Ω

t_HSDRAThigh-speed data rate

t_HSFRAMmicroframe interval

479.76

124.9375

1

-

480.24

Mbit/s

µs

125.0625

t_HSRFI

consecutive microframe interval

difference

four

high-speed

bit times

ns

Table 132. Dynamic characteristics: full-speed source electrical characteristics

V_CCA(AUX)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CCA(AUX)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Driver characteristics

Conditions

Min

Typ

Max

Unit

t_FR

rise time

C_L= 50 pF; 10 % to 90 %

4

-

20

ns

%

of |V_OH− V_OL

C_L= 50 pF; 90 % to 10 %

of |V_OH− V_OL

|

t_FF

fall time

4

20

|

t_FRFM

differential rise and fall time matching

90

111.1

Data timing; see Figure 8

t_FDEOP

source jitter for differential transition to

SE0 transition

full-speed timing

low-speed timing

−2

-

+5

ns

t_FEOPT

t_FEOPR

t_LDEOP

source SE0 interval of EOP

receiver SE0 interval of EOP

160

82

-

175

-

ns

upstream facing port source jitter for

differential transition to SE0 transition

−40

+100

t_LEOPT

t_LEOPR

t_FST

source SE0 interval of EOP

receiver SE0 interval of EOP

1.25

670

-

1.5

-

µs

ns

width of SE0 interval during differential

transition

14

Table 133. Dynamic characteristics: low-speed source electrical characteristics

V_CCA(AUX)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CCA(AUX)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Driver characteristics

t_LR

transition time: rise time

75

90

-

300

125

ns

%

t_LF

transition time: fall time

t_LRFM

rise and fall time matching

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

T

PERIOD

+3.3 V

crossover point

extended

crossover point

differential

data lines

0 V

differential data to

SE0/EOP skew

source EOP width: t

, t

FEOPT LEOPT

N × T

+ t

FDEOP

+ t

LDEOP

PERIOD

receiver EOP width: t

, t

FEOPR LEOPR

004aaa929

T_PERIODis the bit duration corresponding to the USB data rate.

Fig 8. USB source differential data-to-EOP transition skew and EOP width

15.1 Timing

Table 134. PCI clock and I/O timing

V_CC(IO)= 3.0 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Typical values are at V_CC(IO)= 3.3 V; T_amb= +25 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

PCI clock timing; see Figure 9

T_cyc

t_high

t_low

CLK cycle time

CLK HIGH time

CLK LOW time

30

11

1

-

32

-

ns

-

ns

SR_CLKCLK slew rate

4

-

V/ns

mV/ns

SR_RST#RST# slew rate

PCI input timing; see Figure 10

50

t_su

input set-up time to CLK - bused signals

7

-

ns

[1]

t_su(ptp)

t_h

input set-up time to CLK - point-to-point

input hold time from CLK

10

0

PCI output timing; see Figure 11

t_val

CLK to signal valid delay time - bused signals

2

-

11

12

-

ns

t_val(ptp)

t_dZH

t_dHZ

CLK to signal valid delay time - point-to-point

ﬂoat to active HIGH delay time

active HIGH to ﬂoat delay time

28

PCI reset timing

t_rst

reset active time after power stable

reset active time after CLK stable

1

-

ms

t_rst-clk

100

µs

[1] REQ# and GNT# are point-to-point signals. GNT# has a set up of 10 ns; REQ# has a set up of 12 ns. All others are bus signals.

ISP1564_2

Product data sheet

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ISP1564

NXP Semiconductors

HS USB PCI host controller

T

cyc

t

low

high

0.6V

0.5V

CC(IO)

minimum value

0.4V

0.3V

0.2V

CC(IO)

0.4V

CC(IO)

004aaa923

Fig 9. PCI clock

0.6V

CC(IO)

0.4V

CLK

CC(IO)

0.2V

CC(IO)

t

; t

su su(ptp)

t

h

0.6V

0.4V

0.2V

CC(IO)

input

delay

inputs valid

004aaa924

Fig 10. PCI input timing

0.6V

0.4V

0.2V

CC(IO)

CLK

CC(IO)

t

; t

val val(ptp)

0.615V

0.285V

(falling edge)

(rising edge)

CC(IO)

output

delay

CC(IO)

output

t

dZH

t

004aaa925

dHZ

Fig 11. PCI output timing

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

16. Package outline

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm

SOT407-1

y

X

A

51

75

50

26

(1)

76

Z

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

detail X

100

1

25

Z

D

v

M

A

B

e

w M

b

p

D

B

H

v

M

5

D

0

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

θ

1

2

3

p

E

p

D

E

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 14.1 14.1

0.17 0.09 13.9 13.9

16.25 16.25

15.75 15.75

0.75

0.45

1.15 1.15

0.85 0.85

mm

1.6

0.25

0.5

1

0.2 0.08 0.08

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-02-01

03-02-20

SOT407-1

136E20

MS-026

Fig 12. Package outline SOT407-1 (LQFP100)

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

86 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm

SOT926-1

D

B

A

ball A1

index area

A

2

E

A

1

detail X

e

1

C

M

v

C

A

B

b

e

1/2 e

y

M

w

C

1

K

J

H

G

F

e

2

E

D

C

B

A

1/2 e

ball A1

index area

1

2

3

4

5

6

7

8

9

10

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

1

e

2

v

w

y

1

max

0.4

0.3

0.8

0.65

0.5

0.4

9.1

8.9

9.1

8.9

mm

1.2

0.8

7.2

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

05-12-09

05-12-22

SOT926-1

- - -

Fig 13. Package outline SOT926-1 (TFBGA100)

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

87 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

ISP1564_2

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ISP1564

NXP Semiconductors

HS USB PCI host controller

17.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 14) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 135 and 136

Table 135. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 136. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 14.

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

89 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 14. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

18. Abbreviations

Table 137. Abbreviations

Acronym

CMOS

DID

Description

Complementary Metal-Oxide Semiconductor

Device ID

DWORD

ED

Double Word

Endpoint Descriptor

EEPROM

EHCI

EMI

Electrically Erasable Programmable Read-Only Memory

Enhanced Host Controller Interface

ElectroMagnetic Interference

End-Of-Frame

EOF

EOP

ESD

End-Of-Packet

ElectroStatic Discharge

Effective Series Resistance

Host Controller

ESR

HC

HCCA

HCD

HCI

Host Controller Communication Area

Host Controller Driver

Host Controller Interface

High-Speed

HS

LS

Low-Speed

MSB

OHCI

Most Signiﬁcant Bit

Open Host Controller Interface

ISP1564_2

Product data sheet

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ISP1564

NXP Semiconductors

HS USB PCI host controller

Table 137. Abbreviations …continued

Acronym

Description

PCI

Peripheral Component Interconnect

PCI-Special Interest Group

Phase-Locked Loop

Power Management Capabilities

Power Management Event

Power-On Reset

PCI-SIG

PLL

PMC

PME

POR

POST

QH

Power-On System Test

Queue Head

SMI

System Management Interrupt

Start-Of-Frame

SOF

STB

TD

Set-Top Box

Transfer Descriptor

Universal Serial Bus

Vendor ID

USB

VID

19. References

[1] Universal Serial Bus Speciﬁcation — Rev. 2.0

[2] Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus —

Rev. 1.0

[3] Open Host Controller Interface Speciﬁcation for USB — Rev. 1.0a

[4] PCI Local Bus Speciﬁcation — Rev. 2.2

[5] PCI Bus Power Management Interface Speciﬁcation — Rev. 1.1

[6] The I²C-bus Speciﬁcation — Version 2.1

20. Revision history

Table 138. Revision history

Document ID

ISP1564_2

Release date

Data sheet status

Change notice

Supersedes

20081113

Product data sheet

-

ISP1564_1

Modiﬁcations:

• Table 2 “Pin description”: updated description of pin SYS_TUNE.

• Updated Figure 4 “Power-on reset”.

• Section 8.2.1.8 “Latency Timer register”: added a remark.

• Table 48 “USB host controller registers”: added Table note 2.

• Table 110 “ASYNCLISTADDR - Current Asynchronous List Address register bit allocation” and Table

111 “ASYNCLISTADDR - Current Asynchronous List Address register bit description”: changed

LPL[19:0] to LPL[26:0].

• Table 128 “Dynamic characteristics: system clock timing”: removed t_{W(RESET_N)}

.

ISP1564_1

20061204

Product data sheet

-

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

91 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

21. Legal information

21.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

21.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

21.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

I²C-bus — logo is a trademark of NXP B.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

ISP1564_2

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Rev. 02 — 13 November 2008

92 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

23. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .2

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3. PCI conﬁguration space registers of

OHCI and EHCI . . . . . . . . . . . . . . . . . . . . . . . .14

Table 4. VID - Vendor ID register (address 00h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 5. DID - Device ID register (address 02h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 6. Command register (address 04h)

(address 61h) bit allocation . . . . . . . . . . . . . . . 23

Table 28. FLADJ - Frame Length Adjustment register

(address 61h) bit description . . . . . . . . . . . . . . 23

Table 29. FLADJ value vs. SOF cycle time . . . . . . . . . . . 24

Table 30. PORTWAKECAP - Port Wake Capability

register (address 62h) bit description . . . . . . . 24

Table 31. Power management registers . . . . . . . . . . . . . 24

Table 32. Cap_ID - Capability Identiﬁer register bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 33. Next_Item_Ptr - Next Item Pointer register

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 34. PMC - Power Management Capabilities

register bit allocation . . . . . . . . . . . . . . . . . . . . 25

Table 35. PMC - Power Management Capabilities

register bit description . . . . . . . . . . . . . . . . . . . 26

Table 36. PMCSR - Power Management Control/

Status register bit allocation . . . . . . . . . . . . . . 27

Table 37. PMCSR - Power Management Control/

Status register bit description . . . . . . . . . . . . . 27

Table 38. PMCSR_BSE - PMCSR PCI-to-PCI Bridge

Support Extensions register bit allocation . . . . 28

Table 39. PMCSR_BSE - PMCSR PCI-to-PCI Bridge

Support Extensions register bit description . . . 28

Table 40. PCI bus power and clock control . . . . . . . . . . . 29

Table 41. Data register bit description . . . . . . . . . . . . . . 29

Table 42. VPD speciﬁc registers . . . . . . . . . . . . . . . . . . . 29

Table 43. VPD_Cap_ID - Vital Product Data

Capability Identiﬁer register bit description . . . 29

Table 44. VPD_Next_Item_Ptr - Vital Product Data

Next Item Pointer register bit description . . . . 30

Table 45. VPD_Addr - Vital Product Data Address

register bit allocation . . . . . . . . . . . . . . . . . . . . 30

Table 46. VPD_Addr - Vital Product Data Address

register bit description . . . . . . . . . . . . . . . . . . . 30

Table 47. VPD_Data - Vital Product Data Data bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 48. USB host controller registers . . . . . . . . . . . . . 34

Table 49. HcRevision - Host Controller Revision

register bit allocation . . . . . . . . . . . . . . . . . . . . 35

Table 50. HcRevision - Host Controller Revision

register bit description . . . . . . . . . . . . . . . . . . . 36

Table 51. HcControl - Host Controller Control

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 7. Command register (address 04h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 8. Status register (address 06h) bit allocation . . .17

Table 9. Status register (address 06h) bit description . .17

Table 10. REVID - Revision ID register (address 08h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 11. Class Code register (address 09h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 12. Class Code register (address 09h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 13. CLS - CacheLine Size register (address 0Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 14. LT - Latency Timer register (address 0Dh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 15. Header Type register (address 0Eh)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 16. Header Type register (address 0Eh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 17. BAR0 - Base Address register 0 (address 10h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 18. SVID - Subsystem Vendor ID register

(address 2Ch) bit description . . . . . . . . . . . . . .20

Table 19. SID - Subsystem ID register (address 2Eh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 20. CP - Capabilities Pointer register (address 34h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 21. IL - Interrupt Line register (address 3Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 22. IP - Interrupt Pin register (address 3Dh)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .21

Table 23. Min_Gnt - Minimum Grant register

(address 3Eh) bit description . . . . . . . . . . . . . .22

Table 24. Max_Lat - Maximum Latency register

(address 3Fh) bit description . . . . . . . . . . . . . .22

Table 25. EHCI-speciﬁc PCI registers . . . . . . . . . . . . . . .23

Table 26. SBRN - Serial Bus Release Number register

(address 60h) bit description . . . . . . . . . . . . . .23

Table 27. FLADJ - Frame Length Adjustment register

register bit allocation . . . . . . . . . . . . . . . . . . . . 36

Table 52. HcControl - Host Controller Control

register bit description . . . . . . . . . . . . . . . . . . . 37

Table 53. HcCommandStatus - Host Controller

Command Status register bit allocation . . . . . 38

Table 54. HcCommandStatus - Host Controller

continued >>

ISP1564_2

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Rev. 02 — 13 November 2008

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NXP Semiconductors

HS USB PCI host controller

Command Status register bit description . . . . .39

Table 75. HcFmInterval - Host Controller Frame

Table 55. HcInterruptStatus - Host Controller

Interrupt Status register bit allocation . . . . . . .40

Table 56. HcInterruptStatus - Host Controller

Interrupt Status register bit description . . . . . .40

Table 57. HcInterruptEnable - Host Controller

Interrupt Enable register bit allocation . . . . . . .41

Table 58. HcInterruptEnable - Host Controller

Interrupt Enable register bit description . . . . . .42

Table 59. HcInterruptDisable - Host Controller

Interrupt Disable register bit allocation . . . . . .43

Table 60. HcInterruptDisable - Host Controller

Interrupt Disable register bit description . . . . .43

Table 61. HcHCCA - Host Controller Communication

Area register bit allocation . . . . . . . . . . . . . . . .44

Table 62. HcHCCA - Host Controller Communication

Area register bit description . . . . . . . . . . . . . . .45

Table 63. HcPeriodCurrentED - Host Controller

Period Current Endpoint Descriptor

Interval register bit allocation . . . . . . . . . . . . . 49

Table 76. HcFmInterval - Host Controller Frame

Interval register bit description . . . . . . . . . . . . 50

Table 77. HcFmRemaining - Host Controller Frame

Remaining register bit allocation . . . . . . . . . . . 50

Table 78. HcFmRemaining - Host Controller Frame

Remaining register bit description . . . . . . . . . . 51

Table 79. HcFmNumber - Host Controller Frame

Number register bit allocation . . . . . . . . . . . . . 51

Table 80. HcFmNumber - Host Controller Frame

Number register bit description . . . . . . . . . . . . 52

Table 81. HcPeriodicStart - Host Controller Periodic

Start register bit allocation . . . . . . . . . . . . . . . 52

Table 82. HcPeriodicStart - Host Controller Periodic

Start register bit description . . . . . . . . . . . . . . 53

Table 83. HcLSThreshold - Host Controller

Low-Speed Threshold register bit allocation . . 53

Table 84. HcLSThreshold - Host Controller

register bit allocation . . . . . . . . . . . . . . . . . . . .45

Table 64. HcPeriodCurrentED - Host Controller

Period Current Endpoint Descriptor

register bit description . . . . . . . . . . . . . . . . . . .45

Table 65. HcControlHeadED - Host Controller Control

Head Endpoint Descriptor register

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 66. HcControlHeadED - Host Controller Control

Head Endpoint Descriptor register

bit description . . . . . . . . . . . . . . . . . . . . . . . . .46

Table 67. HcControlCurrentED - Host Controller

Control Current Endpoint Descriptor

register bit allocation . . . . . . . . . . . . . . . . . . . .46

Table 68. HcControlCurrentED - Host Controller

Control Current Endpoint Descriptor

register bit description . . . . . . . . . . . . . . . . . . .47

Table 69. HcBulkHeadED - Host Controller Bulk

Head Endpoint Descriptor register

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 70. HcBulkHeadED - Host Controller Bulk

Head Endpoint Descriptor register

bit description . . . . . . . . . . . . . . . . . . . . . . . . .47

Table 71. HcBulkCurrentED - Host Controller Bulk

Current Endpoint Descriptor register

Low-Speed Threshold register bit description . 53

Table 85. HcRhDescriptorA - Host Controller Root

Hub Descriptor A register bit allocation . . . . . . 54

Table 86. HcRhDescriptorA - Host Controller Root

Hub Descriptor A register bit description . . . . . 54

Table 87. HcRhDescriptorB - Host Controller Root

Hub Descriptor B register bit allocation . . . . . . 55

Table 88. HcRhDescriptorB - Host Controller Root

Hub Descriptor B register bit description . . . . . 56

Table 89. HcRhStatus - Host Controller Root Hub

Status register bit allocation . . . . . . . . . . . . . . 56

Table 90. HcRhStatus - Host Controller Root Hub

Status register bit description . . . . . . . . . . . . . 57

Table 91. HcRhPortStatus[2:1] - Host Controller Root

Hub Port Status[2:1] register bit allocation . . . 58

Table 92. HcRhPortStatus[2:1] - Host Controller Root

Hub Port Status[2:1] register bit description . . 58

Table 93. CAPLENGTH/HCIVERSION - Capability

Length/Host Controller Interface Version

Number register bit allocation . . . . . . . . . . . . . 61

Table 94. CAPLENGTH/HCIVERSION - Capability

Length/Host Controller Interface Version

Number register bit description . . . . . . . . . . . . 61

Table 95. HCSPARAMS - Host Controller Structural

Parameters register bit allocation . . . . . . . . . . 61

Table 96. HCSPARAMS - Host Controller Structural

Parameters register bit description . . . . . . . . . 62

Table 97. HCCPARAMS - Host Controller Capability

Parameters register bit allocation . . . . . . . . . . 63

Table 98. HCCPARAMS - Host Controller Capability

Parameters register bit description . . . . . . . . . 63

Table 99. USBCMD - USB Command register

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 72. HcBulkCurrentED - Host Controller Bulk

Current Endpoint Descriptor register

bit description . . . . . . . . . . . . . . . . . . . . . . . . .48

Table 73. HcDoneHead - Host Controller Done Head

register bit allocation . . . . . . . . . . . . . . . . . . . .49

Table 74. HcDoneHead - Host Controller Done Head

register bit description . . . . . . . . . . . . . . . . . . .49

continued >>

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

94 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 137.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table 138.Revision history . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 100.USBCMD - USB Command register bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 101.USBSTS - USB Status register bit allocation . .66

Table 102.USBSTS - USB Status register bit description 67

Table 103.USBINTR - USB Interrupt Enable register

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 104.USBINTR - USB Interrupt Enable register

bit description . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 105.FRINDEX - Frame Index register

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 106.FRINDEX - Frame Index register

bit description . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 107.N based value of FLS[1:0] . . . . . . . . . . . . . . . .70

Table 108.PERIODICLISTBASE - Periodic Frame List

Base Address register bit allocation . . . . . . . .71

Table 109.PERIODICLISTBASE - Periodic Frame List

Base Address register bit description . . . . . . .71

Table 110.ASYNCLISTADDR - Current Asynchronous

List Address register bit allocation . . . . . . . . . .71

Table 111.ASYNCLISTADDR - Current Asynchronous

List Address register bit description . . . . . . . . .72

Table 112.CONFIGFLAG - Conﬁgure Flag register

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 113.CONFIGFLAG - Conﬁgure Flag register

bit description . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 114.PORTSC 1, 2 - Port Status and Control 1, 2

register bit allocation . . . . . . . . . . . . . . . . . . . .73

Table 115.PORTSC 1, 2 - Port Status and Control 1, 2

register bit description . . . . . . . . . . . . . . . . . . .74

Table 116.System Tuning register bit allocation . . . . . . . .76

Table 117.System Tuning register bit description . . . . . . .77

Table 118.Ring buffering disable . . . . . . . . . . . . . . . . . . .77

Table 119.Watermark disable . . . . . . . . . . . . . . . . . . . . . .77

Table 120.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 121.Recommended operating conditions . . . . . . . .78

Table 122.Static characteristics: I²C-bus interface

(SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .79

Table 123.Static characteristics: digital pins

(PWE1_N, OC1_N, PWE2_N and OC2_N) . . .79

Table 124.Static characteristics: PCI interface block . . . .79

Table 125.Static characteristics: USB interface block

(pins DM1 to DM2 and DP1 to DP2) . . . . . . . .79

Table 126.Current consumption . . . . . . . . . . . . . . . . . . . .81

Table 127.Current consumption: S1 and S3 . . . . . . . . . . .81

Table 128.Dynamic characteristics: system clock timing .82

Table 129.Dynamic characteristics: I²C-bus interface

(SDA and SCL) . . . . . . . . . . . . . . . . . . . . . . . .82

Table 130.Dynamic characteristics: PCI interface block . .82

Table 131.Dynamic characteristics: high-speed source

electrical characteristics . . . . . . . . . . . . . . . . .82

Table 132.Dynamic characteristics: full-speed source

electrical characteristics . . . . . . . . . . . . . . . . .83

Table 133.Dynamic characteristics: low-speed source

electrical characteristics . . . . . . . . . . . . . . . . .83

Table 134.PCI clock and I/O timing . . . . . . . . . . . . . . . . .84

Table 135.SnPb eutectic process (from J-STD-020C) . . .89

Table 136.Lead-free process (from J-STD-020C) . . . . . .89

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

95 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

24. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Fig 2. Pin conﬁguration LQFP100 (top view) . . . . . . . . . .4

Fig 3. Pin conﬁguration TFBGA100 (top view). . . . . . . . .5

Fig 4. Power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . .11

Fig 5. Power supply connection . . . . . . . . . . . . . . . . . . .12

Fig 6. EEPROM connection diagram. . . . . . . . . . . . . . .31

Fig 7. Information loading from EEPROM . . . . . . . . . . .32

Fig 8. USB source differential data-to-EOP transition

skew and EOP width . . . . . . . . . . . . . . . . . . . . . .84

Fig 9. PCI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Fig 10. PCI input timing . . . . . . . . . . . . . . . . . . . . . . . . . .85

Fig 11. PCI output timing . . . . . . . . . . . . . . . . . . . . . . . . .85

Fig 12. Package outline SOT407-1 (LQFP100) . . . . . . . .86

Fig 13. Package outline SOT926-1 (TFBGA100). . . . . . .87

Fig 14. Temperature proﬁles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

96 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

25. Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.2.3

Power management registers. . . . . . . . . . . . . 24

Cap_ID register . . . . . . . . . . . . . . . . . . . . . . . 24

Next_Item_Ptr register . . . . . . . . . . . . . . . . . . 25

PMC register . . . . . . . . . . . . . . . . . . . . . . . . . 25

PMCSR register . . . . . . . . . . . . . . . . . . . . . . . 27

PMCSR_BSE register . . . . . . . . . . . . . . . . . . 28

Data register. . . . . . . . . . . . . . . . . . . . . . . . . . 29

VPD register. . . . . . . . . . . . . . . . . . . . . . . . . . 29

VPD_Cap_ID register. . . . . . . . . . . . . . . . . . . 29

VPD_Next_Item_Ptr register . . . . . . . . . . . . . 29

VPD_Addr register . . . . . . . . . . . . . . . . . . . . . 30

VPD_Data register . . . . . . . . . . . . . . . . . . . . . 30

I²C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 31

Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Hardware connections . . . . . . . . . . . . . . . . . . 31

Information loading from EEPROM . . . . . . . . 32

EEPROM programming . . . . . . . . . . . . . . . . . 32

8.2.3.1

8.2.3.2

8.2.3.3

8.2.3.4

8.2.3.5

8.2.3.6

8.2.4

8.2.4.1

8.2.4.2

8.2.4.3

8.2.4.4

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

Functional description . . . . . . . . . . . . . . . . . . 10

OHCI host controller . . . . . . . . . . . . . . . . . . . . 10

EHCI host controller . . . . . . . . . . . . . . . . . . . . 10

Dynamic port-routing logic . . . . . . . . . . . . . . . 10

Hi-Speed USB analog transceivers . . . . . . . . 10

Power management . . . . . . . . . . . . . . . . . . . . 10

Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . 10

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 11

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 11

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

9

9.1

9.2

9.3

9.4

10

10.1

10.2

Power management. . . . . . . . . . . . . . . . . . . . . 32

PCI bus power states . . . . . . . . . . . . . . . . . . . 32

USB bus states . . . . . . . . . . . . . . . . . . . . . . . 33

8

8.1

8.1.1

8.1.2

8.2

8.2.1

8.2.1.1

8.2.1.2

8.2.1.3

8.2.1.4

8.2.1.5

8.2.1.6

8.2.1.7

8.2.1.8

8.2.1.9

PCI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PCI interface. . . . . . . . . . . . . . . . . . . . . . . . . . 12

PCI conﬁguration space . . . . . . . . . . . . . . . . . 13

PCI initiator and target . . . . . . . . . . . . . . . . . . 13

PCI conﬁguration registers . . . . . . . . . . . . . . . 13

PCI conﬁguration header registers . . . . . . . . . 14

Vendor ID register. . . . . . . . . . . . . . . . . . . . . . 15

Device ID register . . . . . . . . . . . . . . . . . . . . . . 15

Command register . . . . . . . . . . . . . . . . . . . . . 15

Status register. . . . . . . . . . . . . . . . . . . . . . . . . 17

Revision ID register . . . . . . . . . . . . . . . . . . . . 18

Class Code register . . . . . . . . . . . . . . . . . . . . 18

CacheLine Size register . . . . . . . . . . . . . . . . . 19

Latency Timer register . . . . . . . . . . . . . . . . . . 19

Header Type register . . . . . . . . . . . . . . . . . . . 19

11

11.1

USB host controller registers. . . . . . . . . . . . . 34

OHCI USB host controller operational

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

HcRevision register . . . . . . . . . . . . . . . . . . . . 35

HcControl register . . . . . . . . . . . . . . . . . . . . . 36

HcCommandStatus register. . . . . . . . . . . . . . 38

HcInterruptStatus register . . . . . . . . . . . . . . . 40

HcInterruptEnable register . . . . . . . . . . . . . . . 41

HcInterruptDisable register . . . . . . . . . . . . . . 42

HcHCCA register . . . . . . . . . . . . . . . . . . . . . . 44

HcPeriodCurrentED register. . . . . . . . . . . . . . 45

HcControlHeadED register. . . . . . . . . . . . . . . 45

11.1.1

11.1.2

11.1.3

11.1.4

11.1.5

11.1.6

11.1.7

11.1.8

11.1.9

11.1.10 HcControlCurrentED register . . . . . . . . . . . . . 46

11.1.11 HcBulkHeadED register . . . . . . . . . . . . . . . . . 47

11.1.12 HcBulkCurrentED register . . . . . . . . . . . . . . . 48

11.1.13 HcDoneHead register. . . . . . . . . . . . . . . . . . . 48

11.1.14 HcFmInterval register. . . . . . . . . . . . . . . . . . . 49

11.1.15 HcFmRemaining register . . . . . . . . . . . . . . . . 50

11.1.16 HcFmNumber register . . . . . . . . . . . . . . . . . . 51

11.1.17 HcPeriodicStart register . . . . . . . . . . . . . . . . . 52

11.1.18 HcLSThreshold register . . . . . . . . . . . . . . . . . 53

11.1.19 HcRhDescriptorA register . . . . . . . . . . . . . . . 53

11.1.20 HcRhDescriptorB register . . . . . . . . . . . . . . . 55

11.1.21 HcRhStatus register. . . . . . . . . . . . . . . . . . . . 56

11.1.22 HcRhPortStatus[2:1] register . . . . . . . . . . . . . 57

8.2.1.10 Base Address register 0 . . . . . . . . . . . . . . . . . 20

8.2.1.11 Subsystem Vendor ID register . . . . . . . . . . . . 20

8.2.1.12 Subsystem ID register . . . . . . . . . . . . . . . . . . 20

8.2.1.13 Capabilities Pointer register . . . . . . . . . . . . . . 21

8.2.1.14 Interrupt Line register . . . . . . . . . . . . . . . . . . . 21

8.2.1.15 Interrupt Pin register. . . . . . . . . . . . . . . . . . . . 21

8.2.1.16 Min_Gnt and Max_Lat registers . . . . . . . . . . . 22

8.2.1.17 TRDY Timeout register . . . . . . . . . . . . . . . . . . 22

8.2.1.18 Retry Timeout register . . . . . . . . . . . . . . . . . . 22

8.2.2

Enhanced host controller-speciﬁc

PCI registers. . . . . . . . . . . . . . . . . . . . . . . . . . 23

SBRN register. . . . . . . . . . . . . . . . . . . . . . . . . 23

FLADJ register . . . . . . . . . . . . . . . . . . . . . . . . 23

PORTWAKECAP register. . . . . . . . . . . . . . . . 24

8.2.2.1

8.2.2.2

8.2.2.3

11.2

EHCI controller capability registers . . . . . . . . 60

CAPLENGTH/HCIVERSION register. . . . . . . 60

11.2.1

continued >>

ISP1564_2

Product data sheet

Rev. 02 — 13 November 2008

97 of 98

ISP1564

NXP Semiconductors

HS USB PCI host controller

11.2.2

11.2.3

11.2.4

11.3

HCSPARAMS register . . . . . . . . . . . . . . . . . . 61

HCCPARAMS register . . . . . . . . . . . . . . . . . . 62

HCSP-PORTROUTE register . . . . . . . . . . . . . 63

Operational registers of enhanced USB host

controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

USBCMD register . . . . . . . . . . . . . . . . . . . . . . 64

USBSTS register . . . . . . . . . . . . . . . . . . . . . . 66

USBINTR register. . . . . . . . . . . . . . . . . . . . . . 68

FRINDEX register. . . . . . . . . . . . . . . . . . . . . . 69

PERIODICLISTBASE register . . . . . . . . . . . . 70

ASYNCLISTADDR register. . . . . . . . . . . . . . . 71

CONFIGFLAG register . . . . . . . . . . . . . . . . . . 72

PORTSC registers 1, 2. . . . . . . . . . . . . . . . . . 73

Miscellaneous registers . . . . . . . . . . . . . . . . . 76

11.3.1

11.3.2

11.3.3

11.3.4

11.3.5

11.3.6

11.3.7

11.3.8

11.4

12

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 78

Recommended operating conditions. . . . . . . 78

Static characteristics. . . . . . . . . . . . . . . . . . . . 79

Dynamic characteristics . . . . . . . . . . . . . . . . . 82

Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 86

13

14

15

15.1

16

17

Soldering of SMD packages . . . . . . . . . . . . . . 88

Introduction to soldering . . . . . . . . . . . . . . . . . 88

Wave and reﬂow soldering . . . . . . . . . . . . . . . 88

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 88

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 89

17.1

17.2

17.3

17.4

18

19

20

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 90

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 91

21

Legal information. . . . . . . . . . . . . . . . . . . . . . . 92

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 92

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 92

21.1

21.2

21.3

21.4

22

23

24

25

Contact information. . . . . . . . . . . . . . . . . . . . . 92

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 November 2008

Document identifier: ISP1564_2


型号：	ISP1564HL,551
厂家：	NXP
描述：	IC PCI BUS CONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MS-026, SOT407-1, LQFP-100, Bus Controller 时钟 PC 外围集成电路
文件：	总99页 (文件大小：493K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1564HL,551 [NXP]

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