ISP1581BD,557_技术文档

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ISP1581

Hi-Speed Universal Serial Bus peripheral controller

Rev. 06 — 23 December 2004

Product data

1. General description

The ISP1581 is a cost-optimized and feature-optimized Hi-Speed Universal Serial

Bus (USB) peripheral controller, which fully complies with the Universal Serial Bus

Speciﬁcation Rev. 2.0. It provides high-speed USB communication capacity to

systems based on a microcontroller or microprocessor. The ISP1581 communicates

with the system’s microcontroller/processor through a high-speed general-purpose

parallel interface.

The ISP1581 supports automatic detection of Hi-Speed USB system operation. The

Original USB fall-back mode allows the device to remain operational under full-speed

conditions. It is designed as a generic USB peripheral controller so that it can ﬁt into

all existing device classes, such as: Imaging Class, Mass Storage Devices,

Communication Devices, Printing Devices and Human interface devices.

The internal generic DMA block allows easy integration into data streaming

applications. In addition, the various conﬁgurations of the DMA block are tailored for

mass storage applications.

The modular approach to implementing a USB peripheral controller allows the

designer to select the optimum system microcontroller from the wide variety available.

The ability to re-use existing architecture and ﬁrmware investments shortens the

development time, eliminates risk and reduces costs. The result is fast and efﬁcient

development of the most cost-effective USB peripheral solution.

The ISP1581 is ideally suited for many types of peripherals, such as: printers;

scanners; magneto-optical (MO), compact disc (CD), digital video disc (DVD) and

Zip^®/Jaz^®drives; digital still cameras; USB-to-Ethernet links; cable and DSL

modems. The low power consumption during ‘suspend’ mode allows easy design of

equipment that is compliant to the ACPI™, OnNow™ and USB power management

requirements.

The ISP1581 also incorporates features such as SoftConnect™, a reduced

frequency crystal oscillator and integrated termination resistors. These features allow

signiﬁcant cost savings in system design and easy implementation of advanced USB

functionality into PC peripherals.

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

2. Features

■ Direct interface to ATA/ATAPI peripherals; applicable only in the split bus mode

■ Complies fully with Universal Serial Bus Speciﬁcation Rev. 2.0

■ Complies with most Device Class speciﬁcations

■ High performance USB peripheral controller with integrated Serial Interface

Engine (SIE), PIE, FIFO memory, data transceiver and 3.3 V voltage regulators

■ Supports automatic Hi-Speed USB mode detection and Original USB fall-back

mode

■ High-speed DMA interface (12.8 Mword/s)

■ Fully autonomous and multi-conﬁguration DMA operation

■ 7 IN endpoints, 7 OUT endpoints and a ﬁxed control IN/OUT endpoint

■ Integrated physical 8 kbyte of multi-conﬁguration FIFO memory

■ Endpoints with double buffering to increase throughput and ease real-time data

transfer

■ Bus independent interface with most microcontroller/microprocessors

(12.5 Mbyte/s)

■ 12 MHz crystal oscillator with integrated PLL for low EMI

■ Integrated 5 V-to-3 V built-in voltage regulator

■ Software controlled connection to the USB bus (SoftConnect™)

■ Complies with the ACPI™, OnNow™ and USB power management requirements

■ Internal power-on and low-voltage reset circuit, also supporting a software reset

■ Operation over the extended USB bus voltage range (4.0 to 5.5 V) with 5 V

tolerant I/O pads

■ Operating temperature range −40 to +85 °C

■ Available in LQFP64 package.

3. Applications

■ Personal Digital Assistant (PDA)

■ Mass storage device, for example: Zip^®, Jaz^®, MO, CD, DVD drive

■ Digital Video Camera

■ Digital Still Camera

■ 3G mobile phone

■ MP3 player

■ Communication device, for example: router, modem

■ Printer

■ Scanner.

4. Ordering information

Table 1:

Ordering information

Type number

Package

Name

Description

Version

ISP1581BD

LQFP64

plastic low proﬁle quad ﬂat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

9397 750 13462

Product data

Rev. 06 — 23 December 2004

2 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

6. Pinning information

6.1 Pinning

idth

DGND

1

2

3

4

5

6

7

8

9

48 DATA6

V

DATA5

47

CC(5.0)

AGND

46 DATA4

45 DATA3

V

CCA(3.3)

D−

D+

DATA2

44

43

V

CC(3.3)

RPU

42 DGND

DATA1

RREF

MODE1

41

ISP1581BD

40 DATA0

39 AD7

RESET 10

EOT 11

38 AD6

DREQ 12

DACK 13

DIOR 14

DIOW 15

INTRQ 16

37

V

CC(3.3)

36 DGND

AD5

35

34 AD4

33 AD3

MBL248

Fig 2. Pin conﬁguration LQFP64.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

4 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

6.2 Pin description

Table 2:

Symbol^[1]

DGND

Pin description for LQFP64

1

Type^[2]Description

-

digital ground

[3]

V_CC(5.0)

2

supply voltage (3.3 or 5.0 V)

for 5.0 V operation, this is the only pin used. Refer to

Section 10

AGND

3

4

-

analog ground

[3]

V_CCA(3.3)

regulated supply voltage (3.3 V ± 0.3 V) from internal

regulator; supplies internal analog circuits; used to connect

decoupling capacitor and 1.5 kΩ pull-up resistor on D+ line

Remark: Cannot be used to supply external devices. Refer

to Section 10

D−

5

6

7

A

USB D− connection (analog)

USB D+ connection (analog)

D+

RPU

connection for external pull-up resistor for USB D+ line;

must be connected to V_CCA(3.3)via a 1.5 kΩ resistor

RREF

8

9

A

I

connection for external bias resistor; must be connected to

ground via a 12.0 kΩ (± 1%) resistor

MODE1

selects function of pin ALE/A0 (in Split Bus mode only):

0 — ALE function (address latch enable)

1 — A0 function (address/data indicator).

Remark: Connect to V_CC(5.0)in the Generic Processor

mode.

input pad; TTL; 5 V tolerant; internal pull-down resistor.

RESET

EOT

10

11

I

reset input; a LOW level produces an asynchronous reset;

connect to V_CCfor power-on reset (internal POR circuit)

TTL with hysteresis; 5 V tolerant; internal pull-up resistor.

End Of Transfer input (programmable polarity, see

Table 37); used in DMA slave mode only; when not in use,

connect this pin to V_CC(I/O)through a 10 kΩ resistor

input pad; TTL; 5 V tolerant; 5 ns slew rate control.

DREQ

DACK

12

13

I/O

DMA request (programmable polarity); direction depends

on the bit MASTER in the DMA Hardware register (DMA

master: input, DMA slave: output); see Table 35 and

Table 36; when not in use, connect this pin to ground

through a 10 kΩ resistor;

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DMA acknowledge (programmable polarity); direction

depends on bit MASTER in the DMA Hardware register

(DMA slave: input, DMA master: output); see Table 35 and

Table 36; when not in use, connect this pin to V_CC(I/O)

through a 10 kΩ resistor

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

5 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 2:

Pin description for LQFP64 …continued

Symbol^[1]

Type^[2]Description

DIOR

14

I/O

DMA read strobe (programmable polarity); direction

depends on bit MASTER in the DMA Hardware register

(DMA slave: input, DMA master: output); see Table 35 and

Table 36; when not in use, connect this pin to V_CC(I/O)

through a 10 kΩ resistor

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DIOW

15

I/O

DMA write strobe (programmable polarity); direction

depends on bit MASTER in the DMA Hardware register

(DMA slave: input, DMA master: output); see Table 35 and

Table 36; when not in use, connect this pin to V_CC(I/O)

through a 10 kΩ resistor

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

INTRQ

CS1^[5]

CS0^[5]

16

17

18

19

I

interrupt request input from ATA/ATAPI peripheral

input pad; TTL with hysteresis; 5 V tolerant; internal

pull-down resistor.

O

I/O

chip select output for ATA/ATAPI device; see Table 33 and

Table 34

CMOS output; 5 ns slew rate control

chip select output for ATA/ATAPI device; see Table 33 and

Table 34

CMOS output; 5 ns slew rate control

BUS_CONF/

DA0^[5]

during power-up: input to select the bus conﬁguration;

see Table 33 and Table 34

0 — Split Bus mode; multiplexed 8-bit address/data bus on

AD[7:0], separate DMA data bus on DATA[15:0]^[4]

1 — Generic Processor mode; separate 8-bit address on

AD[7:0], 16-bit processor data bus on DATA[15:0]. DMA is

multiplexed on the processor bus as DATA[15:0].

normal operation: address output to select the task ﬁle

register of an ATA/ATAPI device.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant

MODE0

DA1^[5]

20

I/O

during power-up: input to select the read/write strobe

functionality in generic processor mode; see Table 33 and

Table 34

0 — Motorola style: pin 26 is R/W and pin 27 is DS

1 — 8051 style: pin 26 is RD and pin 27 is WR

normal operation: address output to select the task ﬁle

register of an ATA/ATAPI device

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant

DA2^[5]

21

O

address output to select the task ﬁle register of an

ATA/ATAPI device; see Table 33 and Table 34

CMOS output; 5 ns slew rate control

9397 750 13462

Product data

Rev. 06 — 23 December 2004

6 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 2:

Pin description for LQFP64 …continued

Symbol^[1]

Type^[2]Description

READY/

IORDY

22

I/O

Generic processor mode: ready signal (READY; output)

A LOW level signals that ISP1581 is processing a previous

command or data and is not ready for the next command or

data transfer; a HIGH level signals that ISP1581 is ready

for the next microprocessor read or write.

Split Bus mode: DMA ready signal (IORDY; input); used

for accessing ATA/ATAPI peripherals (PIO and UDMA

modes only).

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DGND

23

24

-

digital ground

[3]

V_CC(3.3)

supply voltage (3.3 V ± 0.3 V); supplies internal digital

circuits or it is the tapped out voltage from the internal

regulator; this regulated voltage cannot be used to drive

external devices; see Section 10

CS

25

26

I

chip select input; TTL; 5 V tolerant.

(R/W)/RD

input; function is determined by input MODE0 at power-up:

MODE0 = 0 — pin functions as R/W (Motorola style)

MODE0 = 1 — pin functions as RD (8051 style).

input pad; TTL with hysteresis; 5 V tolerant.

DS/WR

27

I

input; function is determined by input MODE0 at power-up:

MODE0 = 0 — pin functions as DS (Motorola style)

MODE0 = 1 — pin functions as WR (8051 style).

input pad; TTL with hysteresis; 5 V tolerant.

INT

28

29

O

I

interrupt output; programmable polarity (active HIGH or

LOW) and signaling (edge or level triggered)

CMOS output; 5 ns slew rate control.

ALE/A0

input; function determined by input MODE1 during

power-up:

MODE1 = 0 — pin functions as ALE (address latch

enable); a falling edge latches the address on the

multiplexed address/data bus (AD[7:0])

MODE1 = 1 — pin functions as A0 (address/data selection

on AD[7:0]); a logic 1 detected on the rising edge of the

WR pulse qualiﬁes AD[7:0] as a register address; a logic 0

detected on the rising edge of the WR pulse qualiﬁes

AD[7:0] as a register data; used in Split Bus mode only.

Remark: Connect to DGND in the Generic Processor

mode.

input pad; TTL; 5 V tolerant.

AD0

30

I/O

bit 0 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

7 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 2:

Pin description for LQFP64 …continued

Symbol^[1]

Type^[2]Description

AD1

31

I/O

bit 1 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

AD2

32

33

34

35

bit 2 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

AD3

bit 3 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

AD4

bit 4 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

AD5

bit 5 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DGND

36

37

-

digital ground

[3]

V_CC(3.3)

supply voltage (3.3 V ± 0.3 V); supplies internal digital

circuits or it is the tapped out voltage from the internal

regulator; this regulated voltage cannot be used to drive

external devices; see Section 10

AD6

38

39

40

41

I/O

bit 6 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

AD7

bit 7 of multiplexed address/data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DATA0

DATA1

DGND

bit 0 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

bit 1 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

42

43

-

digital ground

[3]

V_CC(3.3)

supply voltage (3.3 V ± 0.3 V); supplies internal digital

circuits or it is the tapped out voltage from the internal

regulator; this regulated voltage cannot be used to drive

external devices; see Section 10

DATA2

DATA3

44

45

I/O

bit 2 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

bit 3 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

8 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 2:

Pin description for LQFP64 …continued

Symbol^[1]

Type^[2]Description

DATA4

46

I/O

-

bit 4 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DATA5

47

48

49

50

51

52

53

54

55

56

57

58

bit 5 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DATA6

bit 6 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DATA7

bit 7 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DATA8

bit 8 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DATA9

bit 9 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

bit 10 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

bit 11 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

bit 12 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

bit 13 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

bit 14 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

bit 15 of bidirectional data.

bidirectional pad; push pull output; 5 ns slew rate control;

TTL; 5 V tolerant.

[3]

V_CC(3.3)

supply voltage (3.3 V ± 0.3 V); supplies internal digital

circuits or it is the tapped out voltage from the internal

regulator; this regulated voltage cannot be used to drive

external devices; see Section 10

XTAL2

XTAL1

59

60

O

I

crystal oscillator output (12 MHz); connect a fundamental

parallel-resonant crystal; leave this pin open when using an

external clock source on pin XTAL1

crystal oscillator input (12 MHz); connect a fundamental

parallel-resonant crystal or an external clock source

(leaving pin XTAL2 unconnected)

9397 750 13462

Product data

Rev. 06 — 23 December 2004

9 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 2:

Pin description for LQFP64 …continued

Symbol^[1]

61

Type^[2]Description

DGND

-

I

digital ground

WAKEUP

62

wake-up input (edge triggered); a LOW-to-HIGH transition

generates a remote wake-up from ‘suspend’ state.

input pad; TTL with hysteresis; with internal pull-down

resistor; 5 V tolerant; internal pull-down resistor.

TEST

63

64

O

-

test output; this pin is used for test purposes only

[3]

V_CC(3.3)

supply voltage (3.3 V ± 0.3 V); supplies internal digital

circuits or it is the tapped out voltage from the internal

regulator; this regulated voltage cannot be used to drive

external devices; see Section 10

[1] Symbol names with an overscore (for example, NAME) represent active LOW signals.

[2] All outputs and I/O pins can source 4 mA of current.

[3] Add a decoupling capacitor (0.1 µF) to all the supply pins. For better EMI results, add a 0.01 µF

capacitor in parallel to the 0.1 µF.

[4] The DMA bus is in three-state until a DMA command (see Section 9.4.1) is executed.

[5] The control signals are not three-state.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

10 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

7. Functional description

The ISP1581 is a high-speed USB device controller. It implements the Hi-Speed USB

and Original USB physical layer, the packet protocol layer and maintains up to 16

USB endpoints concurrently (control IN and control OUT, 7 IN and 7 OUT

conﬁgurable) along with Endpoint EP0SETUP, which is used to access the setup

buffer. USB Chapter 9 protocol handling is executed by means of external ﬁrmware.

The ISP1581 has a fast general-purpose interface for communication with most types

of microcontrollers/processors. This Microcontroller Interface is conﬁgured by pins

BUS_CONF, MODE1 and MODE0 to accommodate most interface types. Two bus

conﬁgurations are available, selected via input BUS_CONF during power-up:

• Generic Processor mode (BUS_CONF = 1):

– AD[7:0]: 8-bit address bus (selects target register)

– DATA[15:0]: 16-bit data bus (shared by processor and DMA)

– Control signals: R/W and DS or RD and WR (selected via pin MODE0), CS

– DMA interface (generic slave mode only): uses lines DATA[15:0] as data bus,

DIOR and DIOW as dedicated read and write strobes.

• Split Bus mode (BUS_CONF = 0):

– AD[7:0]: 8-bit local microprocessor bus (multiplexed address/data)

– DATA[15:0]: 16-bit DMA data bus

– Control signals: CS, ALE or A0 (selected via pin MODE1), R/W and DS or RD

and WR (selected via pin MODE0)

– DMA interface (master or slave mode): uses DIOR and DIOW as dedicated read

and write strobes.

For high-bandwidth data transfer, the integrated DMA handler can be invoked to

transfer data to/from external memory or devices. The DMA Interface can be

conﬁgured by writing to the proper DMA registers (see Section 9.4).

The ISP1581 supports Hi-Speed USB and Original USB signaling. Detection of the

USB signaling speed is done automatically.

ISP1581 has 8 kbytes of internal FIFO memory, which is shared among the enabled

USB endpoints.

There are 7 IN endpoints, 7 OUT endpoints and 2 control endpoints that are a ﬁxed

64 bytes long. Any of the 7 IN and 7 OUT endpoints can be separately enabled or

disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these

endpoints can be individually conﬁgured depending on the requirements of the

application. Optional double buffering increases the data throughput of these data

endpoints.

The ISP1581 requires a single supply of 3.3 V or 5.0 V, depending on the I/O voltage.

It has 5.0 V tolerant I/O pads and has an internal 3.3 V regulator for powering the

analog transceiver.

The ISP1581 operates on a 12 MHz crystal oscillator. An integrated 40× PLL clock

multiplier generates the internal sampling clock of 480 MHz.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

11 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

7.1 Hi-Speed USB transceiver

The analog transceiver interfaces directly to the USB cable via integrated termination

resistors. The high-speed transceiver requires an external resistor (12.0 kΩ ± 1%)

between pin RREF and ground to ensure an accurate current mirror that is used to

generate the Hi-Speed USB current drive. A full-speed transceiver is integrated as

well. This makes the ISP1581 compliant with Hi-Speed USB and Original USB,

supporting both the high-speed and full-speed physical layer. After automatic speed

detection, the Philips Serial Interface Engine sets the transceiver to use either

high-speed or full-speed signaling.

7.2 Philips Serial Interface Engine (SIE)

The Philips SIE implements the full USB protocol layer. It is completely hardwired for

speed and needs no ﬁrmware intervention. The functions of this block include:

synchronization pattern recognition, parallel/serial conversion, bit (de-)stufﬁng, CRC

checking/generation, Packet IDentiﬁer (PID) veriﬁcation/generation, address

recognition, handshake evaluation/generation.

7.3 Philips HS (High-Speed) Transceiver

7.3.1 Philips Parallel Interface Engine

In the HS Transceiver, the Philips PIE interface uses a 16 bit Parallel bi-directional

data interface. The functions of the HS (High-speed) module also include

Bit-stufﬁng/De-stufﬁng and NRZI Encoding/Decoding logic.

7.3.2 Peripheral circuit

To maintain a constant current driver for HS (High-Speed) transmit circuits and to bias

other analog circuits, an internal band-gap reference circuit and RREF resistor are

used to form the reference current. This circuit requires an external precision resistor

(12.0 kΩ ± 1%) connected to analog ground.

7.3.3 HS detection

ISP1581 handles more than one electrical state (FS/HS) under the USB

speciﬁcation. When the USB cable is connected from the device to the host

controller, at ﬁrst the device ISP1581 defaults to the Full-speed (FS) state until it sees

a bus reset from the host controller.

During the bus reset, the device initiates a HS chirp to detect whether the

host-controller supports Hi-Speed USB or Original USB. Chirping must be done with

the pull-up resistor connected and the internal termination resistors disabled. If the

HS handshake shows that there is a HS host connected, then ISP1581 switches to

the HS state.

In HS state, the ISP1581 observes the bus for periodic activity. If the bus remains

inactive for 3 ms, the device switches to the FS state to check for an

SE0 (Single-ended zero) condition on the USB bus. If an SE0 condition is detected

for the designated time window (100 µs to 875 µs, see Section 7.1.7.6 of the USB

speciﬁcation Rev. 2.0), the ISP1581 switches to the HS chirp state again to do a HS

detection handshake. Otherwise, the ISP1581 remains in the FS state adhering to the

bus-suspend speciﬁcation.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

12 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

7.4 Voltage regulators

Two 5 V-to-3.3 V voltage regulators are integrated on-chip to separately supply the

analog transceiver and the internal logic. The output of these voltage regulators are

termed as V_CCA(3.3)and V_CC(3.3)to distinguish them as being used for the analog

block and the digital block, respectively. The pin V_CCA(3.3)is also used to supply an

external 1.5 kΩ pull-up resistor on the D+ line.

Remark: Pins V_CCA(3.3)and V_CC(3.3)cannot be used to supply external devices.

7.5 Memory Management Unit (MMU) and integrated RAM

The MMU and the integrated RAM provide the conversion between the USB speed

(full-speed: 12 Mbit/s, high-speed: 480 Mbit/s) and the Microcontroller Handler or the

DMA Handler. The data from the USB Bus is stored in the integrated RAM, which is

cleared only when the microcontroller has read/written all data from/to the

corresponding endpoint buffer or when the DMA Handler has read/written all data

from/to the endpoint buffer. The endpoint buffer can also be cleared forcibly by setting

the CLBUF bit in the control function register. A total of 8 kbytes RAM is available for

buffering.

7.6 SoftConnect

The connection to the USB is established by pulling the D+ line (for full-speed

devices) HIGH through a 1.5 kΩ pull-up resistor. In the ISP1581 an external 1.5 kΩ

pull-up resistor must be connected between pins RPU and V_CCA(3.3). The RPU pin

connects the pull-up resistor to the D+ line, when bit SOFTCT in the Mode register is

set (see Table 7). After a hardware reset the pull-up resistor is disconnected by

default (SOFTCT = 0). Bit SOFTCT remains unchanged by a USB bus reset.

7.7 Microcontroller/Processor Interface and

Microcontroller/Processor Handler

The Microcontroller Interface allows direct interfacing to most microcontrollers. The

interface is conﬁgured at power-up via inputs BUS_CONF, MODE1 and MODE0.

When BUS_CONF is set to logic 1, the Microcontroller Interface switches to the

Generic Processor mode in which AD[7:0] is the 8-bit address bus and DATA[15:0]

is the separate 16-bit data bus. If BUS_CONF is made logic 0, the interface is in the

Split Bus mode, where AD[7:0] is the local microprocessor bus (multiplexed

address/data) and DATA[15:0] is solely used as the DMA bus.

If pin MODE0 is set to logic 1, pins RD and WR are the read and write strobes (8051

style). If pin MODE0 is logic 0, pins R/W and DS pins represent the direction and data

strobe (Motorola style).

When pin MODE1 is made logic 0, ALE is used to latch the multiplexed address on

pins AD[7:0]. If pin MODE1 is set to logic 1, A0 is used to indicate address or data.

Pin MODE1 is only used in Split Bus mode: in Generic Processor mode it must be

tied to V_CC(5.0)(logic 1).

The Microcontroller Handler allows the external microcontroller to access the register

set in the Philips SIE as well as the DMA Handler. The initialization of the DMA

conﬁguration is done via the Microcontroller Handler.

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7.8 DMA Interface and DMA Handler

The DMA block can be subdivided into two blocks: the DMA Handler and the DMA

Interface.

The ﬁrmware writes to the DMA Command register to start a DMA transfer (see

Table 28). The command opcode determines whether a generic DMA, PIO, MDMA or

UDMA transfer will start. The Handler interfaces to the same FIFO (internal RAM) as

used by the USB core. Upon receiving the DMA Command, the DMA Handler directs

the data from the internal RAM to the external DMA device or from the external DMA

device to the internal RAM.

The DMA Interface conﬁgures the timings and the DMA handshake. Data can be

transferred either using DIOR and DIOW strobes or by the DACK and DREQ

handshakes. The different DMA conﬁgurations are set up by writing to the DMA

Conﬁguration register (see Table 33 and Table 34).

For an IDE-based storage interface, the applicable DMA modes are PIO (Parallel

I/O), MDMA (Multi word DMA; ATA), and UDMA (Ultra DMA; ATA).

For a generic DMA interface, the DMA modes that can be used are Generic DMA

(Slave) and MDMA (Master).

7.9 Power-on reset

The ISP1581 requires a minimum pulse width of 500 µs.

The RESET pin can be either connected to V_CC(3.3)using the internal POR circuit or

externally controlled by the microcontroller, ASIC, and so on. When V_CC(3.3)is directly

connected to the RESET pin, the internal pulse width t_PORPwill be typically 200 ns.

The power-on reset function can be explained by viewing the dips at t2–t3 and t4–t5

on the V_CC(3.3)curve (Figure 3).

t0 — The internal POR starts with a HIGH level.

t1 — The detector will see the passing of the trip level and a delay element will add

another t_PORPbefore it drops to LOW.

t2-t3 — The internal POR pulse will be generated whenever V_CC(3.3)drops below V_trip

for more than 11 µs.

t4-t5 — The dip is too short (< 11 µs) and the internal POR pulse will not react and

will remain LOW.

V

CC(3.3)

V

trip

t4

t0

t1

t

t3

t5

t2

(1)

PORP

t

PORP

004aaa682

(1) PORP = power-on reset pulse.

Fig 3. POR timing.

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Figure 4 shows the availability of the clock with respect to the external POR.

POR

EXTERNAL CLOCK

004aaa365

A

Stable external clock is to be available at A.

Fig 4. Clock with respect to the external POR.

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8. Modes of operation

The ISP1581 has two bus conﬁguration modes, selected via pin BUS_CONF/DA0 at

power-up:

• Split Bus mode (BUS_CONF = 0): 8-bit multiplexed address/data bus and

separate 8-bit/16-bit DMA bus

• Generic Processor mode (BUS_CONF = 1); separate 8-bit address and 16-bit

data bus

Details of the bus conﬁgurations for each mode are given in Table 3. Typical interface

circuits for each mode are given in Section 15.

Table 3:

Bus conﬁguration modes

BUS_CONF PIO width

DMA width

Description

DMAWD = 0 DMAWD = 1

0

1

AD[7:0]

D[7:0]

D[15:0]

Split Bus mode: multiplexed address/data on pins AD[7:0];

separate 8/16-bit DMA bus on pins DATA[15:0]

A[7:0]

D[7:0]

D[15:0]

Generic Processor mode: separate 8-bit address on pins

D[15:0]

AD[7:0]; 16-bit data (PIO and DMA) on pins DATA[15:0]

9. Register descriptions

Table 4:

Name

Register overview

Destination

Address

(Hex)

Description

Size

(bytes)

Initialization registers

Address

device

00

USB device address + enable

1

Mode

0C

power-down options, global interrupt

enable, SoftConnect

Interrupt Conﬁguration

device

10

interrupt sources, trigger mode, output

polarity

1

Interrupt Enable

DMA Conﬁguration

DMA Hardware

Data ﬂow registers

Endpoint Index

Control Function

Data Port

device

14

38

3C

interrupt source enabling

4

2

1

DMA controller

see sub-section “DMA registers”

endpoints

endpoint

2C

28

20

1C

04

08

endpoint selection, data ﬂow direction

endpoint buffer management

data access to endpoint FIFO

packet size counter

1

2

Buffer Length

Endpoint MaxPacketSize

Endpoint Type

maximum packet size

selects endpoint type: control,

isochronous, bulk or interrupt

Short Packet

endpoint

24

short packet received on OUT endpoint

2

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Table 4:

Name

Register overview…continued

Destination

Address

(Hex)

Description

Size

(bytes)

DMA registers

DMA Command

DMA controller

30

controls all DMA transfers

1

4

1

DMA Transfer Counter

DMA Conﬁguration

34

sets byte count for DMA Transfer

38 (byte 0)

sets GDMA conﬁguration (counter enable,

burst length, data strobing, bus width)

39 (byte 1)

sets ATA conﬁguration (IORDY enable,

mode selection: ATA/UDMA/MDMA/PIO)

1

2

DMA Hardware

1F0 Task File

DMA controller

3C

40

endian type, master/slave selection, signal

polarity for DACK, DREQ, DIOW, DIOR

ATAPI peripheral

single address word register: byte 0 (lower

byte) is accessed ﬁrst

1F1Task File

1F2 Task File

1F3 Task File

1F4 Task File

1F5 Task File

1F6 Task File

1F7 Task File

ATAPI peripheral

48

49

4A

4B

4C

4D

44

IDE device access

1

IDE device access (write only; reading

returns FFH)

3F6 Task File

ATAPI peripheral

DMA controller

4E

IDE device access

1

3F7 Task File

4F

IDE device access

DMA Interrupt Reason

50 (byte 0)

51 (byte 1)

54 (byte 0)

55 (byte 1)

58

shows reason (source) for DMA interrupt

DMA Interrupt Enable

DMA controller

enables DMA interrupt sources

DMA Endpoint

DMA Strobe Timing

General registers

Interrupt

DMA controller

selects endpoint FIFO, data ﬂow direction

strobe duration in UDMA/MDMA mode

60

device

18

70

74

shows interrupt sources

4

3

2

Chip ID

product ID code and hardware version

Frame Number

last successfully received Start Of Frame:

lower byte (byte 0) is accessed ﬁrst

Scratch

device

PHY

78

84

allows save/restore of ﬁrmware status

during ‘suspend’

2

1

Test Mode

direct setting of D+, D− states, internal

transceiver test (PHY)

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9.1 Register access

Register access depends on the bus width used:

• 8-bit bus: multi-byte registers are accessed lower byte (LSByte) ﬁrst.

• 16-bit bus: for single-byte registers the upper byte (MSByte) must be ignored.

Endpoint speciﬁc registers are indexed via the Endpoint Index register. The target

endpoint must be selected ﬁrst, before accessing the following registers:

• Buffer Length

• Control Function

• Data Port

• Endpoint MaxPacketSize

• Endpoint Type

• Short Packet.

Remark: All reserved bits are not implemented. The bus and bus reset values are not

deﬁned. Therefore, writing to these reserved bits will have no effect.

9.2 Initialization registers

9.2.1 Address register (address: 00H)

This register is used to set the USB assigned address and enable the USB device.

Table 5 shows the Address register bit allocation.

The DEVEN and DEVADDR bits will be cleared whenever a bus reset, a power-on

reset or a soft reset occurs.

In response to the standard USB request SET_ADDRESS, the ﬁrmware must write

the (enabled) device address to the Address register, followed by sending an empty

packet to the host. The new device address is activated when the host acknowledges

the empty packet.

Table 5:

Bit

Address register: bit allocation

7

6

5

4

3

DEVADDR[6:0]

00H

2

1

0

Symbol

Reset

DEVEN

0

Bus reset

Access

00H

R/W

Table 6:

Bit

Endpoint Conﬁguration register: bit description

Symbol

Description

7

DEVEN

A logic 1 enables the device.

6 to 0

DEVADDR[6:0]

This ﬁeld speciﬁes the USB device address.

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9.2.2 Mode register (address: 0CH)

This register consists of 1 byte (bit allocation: see Table 7). In 16-bit bus mode the

upper byte is ignored.

The Mode register controls the resume, suspend and wake-up behavior, interrupt

activity, soft reset, clock signals and SoftConnect operation.

Table 7:

Bit

Mode register: bit allocation

7

6

5

4

3

2

1

0

SOFTCT

0

Symbol

Reset

CLKAON SNDRSU

GOSUSP

SFRESET GLINTENA WKUPCS

reserved

0

-

Bus reset

Access

unchanged

R/W

unchanged

R/W

Table 8:

Mode register: bit description

Bit

Symbol

Description

7

CLKAON

Clock Always On: A logic 1 indicates that the internal clocks

are always running even during ‘suspend’ state. A logic 0

switches off the internal oscillator and PLL, when they are not

needed. During ‘suspend’ state, this bit must be set to logic 0 to

meet the suspend current requirements. The clock is stopped

after a delay of approximately 2 ms, following the setting of bit

GOSUSP.

6

SNDRSU

Send Resume: Writing a logic 1 followed by a logic 0 will

generate an upstream ‘resume’ signal of 10 ms duration, after a

5 ms delay.

5

4

GOSUSP

SFRESET

Go Suspend: Writing a logic 1 followed by a logic 0 will activate

‘suspend’ mode.

Soft Reset: Writing a logic 1 followed by a logic 0 will enable a

software-initiated reset to ISP1581. A soft reset is similar to a

hardware-initiated reset (via the RESET pin).

3

GLINTENA

WKUPCS

Global Interrupt Enable: A logic 1 enables all interrupts.

Individual interrupts can be masked OFF by clearing the

corresponding bits in the Interrupt Enable register. Bus reset

value: unchanged.

2

Wake-up on Chip Select: A logic 1 enables remote wake-up

via a LOW level on input CS.

1

0

-

reserved; must write logic 0

SOFTCT

SoftConnect: A logic 1 enables the connection of the 1.5 kΩ

pull-up resistor on pin RPU to the D+ line. Bus reset value:

unchanged.

9.2.3 Interrupt Conﬁguration register (address: 10H)

This 1-byte register determines the behavior and polarity of the INT output. The bit

allocation is shown in Table 9. When the USB SIE receives or generates a ACK, NAK

or STALL, it will generate interrupts depending on three Debug mode bit ﬁelds:

• CDBGMOD[1:0]: interrupts for the Control endpoint 0

• DDBGMODIN[1:0]: interrupts for the DATA IN endpoints 1 to 7

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• DDBGMODOUT[1:0]: interrupts for the DATA OUT endpoints 1 to 7.

The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow

the user to individually conﬁgure when the ISP1581 will send an interrupt to the

external microprocessor. Table 11 lists the available combinations.

Bit INTPOL controls the signal polarity of the INT output (active HIGH or LOW, rising

or falling edge). For level-triggering bit INTLVL must be made logic 0. By setting

INTLVL to logic 1 an interrupt will generate a pulse of 60 ns (edge-triggering).

Table 9:

Bit

Interrupt Conﬁguration register: bit allocation

7

6

5

4

3

2

1

INTLVL

0

INTPOL

0

Symbol

Reset

CDBGMOD[1:0]

DDBGMODIN[1:0]

DDBGMODOUT[1:0]

03H

R/W

03H

R/W

03H

R/W

Bus reset

Access

unchanged unchanged

R/W R/W

Table 10: Interrupt Conﬁguration register: bit description

Bit

Symbol

Description

7 to 6

5 to 4

3 to 2

1

CDBGMOD[1:0]

DDBGMODIN[1:0]

Control 0 Debug Mode: values see Table 11

Data Debug Mode IN: values see Table 11

DDBGMODOUT[1:0] Data Debug Mode OUT: values see Table 11

INTLVL

Interrupt Level: selects the signaling mode on output

INT (0 = level, 1 = pulsed). In pulsed mode an interrupt

produces a 60 ns pulse. Bus reset value: unchanged.

0

INTPOL

Interrupt Polarity: selects signal polarity on output INT

(0 = active LOW, 1 = active HIGH). Bus reset value:

unchanged.

Table 11: Debug mode settings

Value

CDBGMOD

DDBGMODIN

DDBGMODOUT

00H

Interrupt on all ACK and

NAK

Interrupt on all ACK

and NAK

Interrupt on all ACK, NYET

and NAK

01H

1XH

Interrupt on all ACK.

Interrupt on ACK

Interrupt on ACK and NYET

Interrupt on all ACK and

ﬁrst NAK^[1]

Interrupt on all ACK

and ﬁrst NAK^[1]

Interrupt on all ACK, NYET

and ﬁrst NAK^[1]

[1] First NAK: the ﬁrst NAK on an IN or OUT token after a previous ACK response.

9.2.4 Interrupt Enable register (address: 14H)

This register enables/disables individual interrupt sources. The interrupt for each

endpoint can be individually controlled via the associated IEPnRX or IEPnTX bits (‘n’

representing the endpoint number). All interrupts can be globally disabled via bit

GLINTENA in the Mode Register (see Table 7).

An interrupt is generated when the USB SIE receives or generates an ACK or NAK

on the USB bus. The interrupt generation depends on the Debug mode settings of bit

ﬁelds CDBGMOD, DDBGMODIN and DDBGMODOUT.

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All data IN transactions use the Transmit buffers (TX), which are handled by the

DDBGMODIN bits. All data OUT transactions go via the Receive buffers (RX), which

are handled by the DDBGMODOUT bits. Transactions on Control endpoint 0 (IN,

OUT and SETUP) are handled by the CDBGMOD bits.

Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume,

bus reset, Setup and High-Speed Status) can also be controlled individually. A bus

reset disables all enabled interrupts except bit IEBRST (bus reset), which remains

unchanged.

The Interrupt Enable Register consists of 4 bytes. The bit allocation is given in

Table 12.

Table 12: Interrupt Enable register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

reserved

IEP7TX

IEP7RX

-

0

Bus Reset

Access

Bit

-

0

R/W

17

0

R/W

16

R/W

23

22

21

20

19

18

Symbol

Reset

IEP6TX

IEP6RX

IEP5TX

IEP5RX

IEP4TX

IEP4RX

IEP3TX

0

IEP3RX

0

Bus Reset

Access

Bit

0

R/W

9

R/W

8

15

14

13

12

11

10

Symbol

Reset

IEP2TX

IEP2RX

IEP1TX

IEP1RX

IEP0TX

IEP0RX

reserved IEP0SETUP

0

-

0

Bus Reset

Access

Bit

0

R/W

6

0

-

R/W

1

0

R/W

7

5

4

3

2

0

Symbol

Reset

reserved

IEDMA

0

IEHS_STA

IERESM

IESUSP

IEPSOF

IESOF

0

IEBRST

0

-

0

Bus Reset

Access

0

unchanged

R/W

Table 13: Interrupt Enable register: bit description

Bit

Symbol

Description

reserved; must write logic 0

31 to 26

25 to 12

-

IEP7TX to

IEP1RX

A logic 1 enables interrupt from the indicated endpoint.

11

10

9

IEP0TX

IEP0RX

-

A logic 1 enables interrupt from the Control IN endpoint 0.

A logic 1 enables interrupt from the Control OUT endpoint 0.

reserved

8

IEP0SETUP

A logic 1 enables the interrupt for the Setup data received on

endpoint 0.

7

-

reserved

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Table 13: Interrupt Enable register: bit description…continued

Bit

6

Symbol

IEDMA

Description

A logic 1 enables interrupt upon DMA status change detection.

5

IEHS_STA

A logic 1 enables interrupt upon detection of a High Speed

Status change.

4

3

2

1

0

IERESM

IESUSP

IEPSOF

IESOF

A logic 1 enables interrupt upon detection of a ‘resume’ state.

A logic 1 enables interrupt upon detection of a ‘suspend’ state.

A logic 1 enables interrupt upon detection of a Pseudo SOF.

A logic 1 enables interrupt upon detection of an SOF.

IEBRST

A logic 1 enables interrupt upon detection of a bus reset.

9.2.5 DMA Conﬁguration register (address: 38H)

See Section 9.4.3.

9.2.6 DMA Hardware register (address: 3CH)

See Section 9.4.4.

9.3 Data ﬂow registers

9.3.1 Endpoint Index register (address: 2CH)

The Endpoint Index register selects a target endpoint for register access by the

microcontroller. The register consists of 1 byte and the bit allocation is shown in

Table 14. The following registers are indexed:

• Endpoint MaxPacketSize

• Endpoint Type

• Buffer Length

• Data Port

• Short Packet

• Control Function.

For example, to access the OUT data buffer of endpoint 1 via the Data Port register,

the Endpoint Index register has to be written ﬁrst with 02H.

Table 14: Endpoint Index register: bit allocation

Bit

7

6

5

4

3

2

1

0

DIR

0

Symbol

Reset

reserved

EP0SETUP

0

ENDPIDX[3:0]

00H

-

Bus reset

Access

unchanged

R/W

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Table 15: Endpoint Index register: bit description

Bit

7 to 6

5

Symbol

Description

-

reserved

EP0SETUP

Selects the SETUP buffer for Endpoint 0:

0 — EP0 data buffer

1 — SETUP buffer.

Must be logic 0 for access to other endpoints than Endpoint 0.

4 to 1

0

ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access

of Buffer Length, Control Function, Data Port, Endpoint Type,

MaxPacketSize and Short Packet.

DIR

Direction bit: Sets the target endpoint as IN or OUT endpoint:

0 — target endpoint refers to OUT (RX) FIFO

1 — target endpoint refers to IN (TX) FIFO.

Table 16: Addressing of Endpoint 0 buffers

Buffer name

SETUP

EP0SETUP

ENDPIDX

00H

DIR

0

1

0

Data OUT

Data IN

00H

0

00H

1

9.3.2 Control Function register (address: 28H)

The Control Function register is used to perform the buffer management on the

endpoints. It consists of 1 byte and the bit conﬁguration is given in Table 17.The

register bits can stall, clear or validate any enabled data endpoint. Before accessing

this register, the Endpoint Index register must be written ﬁrst to specify the target

endpoint.

Table 17: Control Function register: bit allocation

Bit

7

6

5

4

CLBUF

0

3

VENDP

0

2

1

0

STALL

0

Symbol

Reset

reserved

STATUS^[1]

-

0

Bus reset

Access

0

R/W

[1] Only applicable for control IN/OUT.

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Table 18: Control Function register: bit description

Bit

7 to 5

4

Symbol

-

Description

reserved.

CLBUF

Clear Buffer: A logic 1 clears the RX buffer of the indexed

endpoint; the TX buffer is not affected. The RX buffer is cleared

automatically once the endpoint is read completely. This bit is

set only when it is necessary to forcefully clear the buffer.

3

VENDP

Validate Endpoint: A logic 1 validates the data in the TX FIFO

of an IN endpoint for sending on the next IN token. In general,

the endpoint is validated automatically when its FIFO byte count

has reached the endpoint MaxPacketSize. This bit is set only

when it is necessary to validate the endpoint with the FIFO byte

count which is below the Endpoint MaxPacketSize.

2

1

-

reserved

STATUS

Status Acknowledge: This bit controls the generation of ACK

or NAK during the status stage of a SETUP transfer. It is

automatically cleared upon completion of the status stage and

upon receiving a SETUP token:

0 — sends NAK

1 — sends empty packet following IN token (host-to-device) or

ACK following OUT token (device-to-host).

0

STALL

Stall Endpoint: A logic 1 stalls the indexed endpoint. This bit is

not applicable for isochronous transfers.

Note: ‘Stalling’ a data endpoint will confuse the Data Toggle bit

about the stalled endpoint because the internal logic picks up

from where it is stalled. Therefore, the Data Toggle bit must be

reset by disabling and re-enabling the corresponding endpoint

(by setting the bit ‘ENABLE’ to 0 or 1 in the endpoint type

register) to reset the PID.

9.3.3 Data Port register (address: 20H)

This 2-byte register provides direct access for a microcontroller to the FIFO of the

indexed endpoint. In case of an 8-bit bus the upper byte is not used. The bit allocation

is shown in Table 19.

Device to host (IN endpoint): After each write action an internal counter is

auto-incremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next

location in the TX FIFO. When all bytes have been written (FIFO byte count =

endpoint MaxPacketSize), the buffer is validated automatically. The data packet will

then be sent on the next IN token. When it is necessary to validate the endpoint

whose byte count is less than the MaxPacketSize, it can be done via the control

function register (bit VENDP).

Host to device (OUT endpoint): After each read action an internal counter is

auto-decremented (by 2 for a 16-bit access, by 1 for an 8-bit access) to the next

location in the RX FIFO. When all bytes have been read, the buffer contents are

cleared automatically. A new data packet can then be received on the next OUT

token. The buffer contents can also be cleared via the Control Function register (bit

CLBUF), when it is necessary to forcefully clear the contents.

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Remark: The buffer can be validated or cleared automatically by using the Buffer

Length register (see Table 21).

Table 19: Data Port register: bit allocation

Bit

15

14

13

12

11

10

9

1

8

0

Symbol

Reset

DATAPORT[15:8]

00H

R/W

Bus reset

Access

Bit

7

6

5

4

3

2

Symbol

Reset

DATAPORT[7:0]

00H

R/W

Bus reset

Access

Table 20: Data Port register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

DATAPORT[15:8]

DATAPORT[7:0]

data (upper byte); not used in 8-bit bus mode

data (lower byte)

9.3.4 Buffer Length register (address: 1CH)

This 2-byte register determines the current packet size (DATACOUNT) of the indexed

endpoint FIFO. The bit allocation is given in Table 21.

The Buffer Length register is automatically loaded with the FIFO size, when the

Endpoint MaxPacketSize register is written (see Table 22). A smaller value can be

written when required. After a bus reset the Buffer Length register is made zero.

IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the

Buffer Length register is not signiﬁcant. This register is useful only when transferring

data that is not a multiple of MaxPacketSize. The following two examples

demonstrate the signiﬁcance of the Buffer Length register.

Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register need not be ﬁlled. This is

because the transfer size is a multiple of MaxPacketSize, and the MaxPacketSize

packets will be automatically validated because the last packet is also of

MaxPacketSize.

Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register should be ﬁlled with 62 bytes just

before the MCU writes the last packet of 62 bytes. This ensures that the last packet,

which is a short packet of 62 bytes, is automatically validated.

This is only applicable to the PIO mode access.

OUT endpoint: The DATACOUNT value is automatically initialized to the number of

data bytes sent by the host on each ACK.

Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized

packet is output as the lower byte (LSByte).

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Table 21: Buffer Length register: bit allocation

Bit

15

14

13

12

11

10

9

1

8

0

Symbol

Reset

DATACOUNT[15:8]

00H

R/W

Bus reset

Access

Bit

7

6

5

4

3

2

Symbol

Reset

DATACOUNT[7:0]

00H

R/W

Bus reset

Access

9.3.5 Endpoint MaxPacketSize register (address: 04H)

This register determines the maximum packet size for all endpoints except Control 0.

The register contains 2 bytes and the bit allocation is given in Table 22.

Each time the register is written, the Buffer Length registers of all endpoints are

re-initialized to the FFOSZ ﬁeld value. The NTRANS bits control the number of

transactions allowed in a single micro-frame (for high-speed Isochronous and

interrupt endpoints only).

Table 22: Endpoint MaxPacketSize register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved

NTRANS[1:0]

FFOSZ[10:8]

-

00H

R/W

00H

R/W

1

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

4

3

2

0

Symbol

Reset

FFOSZ[7:0]

00H

Bus reset

Access

00H

R/W

Table 23: Endpoint MaxPacketSize register: bit description

Bit

Symbol

Description

15 to 13

12 to 11

reserved

NTRANS[1:0] Number of Transactions (HS mode only):

0 — 1 packet per microframe

1 — 2 packets per microframe

2 — 3 packets per microframe

3 — reserved.

These bits are applicable for Isochronous/interrupt transactions

only.

10 to 0

FFOSZ[10:0] FIFO Size: Sets the FIFO size in bytes for the indexed endpoint.

Applies to both HS and FS operation.

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9.3.6 Endpoint Type register (address: 08H)

This register sets the Endpoint type of the indexed endpoint: isochronous, bulk or

interrupt. It also serves to enable the endpoint and conﬁgure it for double buffering.

Automatic generation of an empty packet for a zero length TX buffer can be disabled

via bit NOEMPKT. The register contains 2 bytes and the bit allocation is shown in

Table 24.

Table 24: Endpoint Type register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved

R/W

-

Bus reset

Access

Bit

7

6

5

4

3

2

1

0

ENDPTYP[1:0]

00H

Symbol

Reset

reserved

NOEMPKT

ENABLE

DBLBUF

-

0

Bus reset

Access

00H

R/W

Table 25: Endpoint Type register: bit description

Bit

Symbol

Description

15 to 5 reserved

reserved.

4

3

NOEMPKT

ENABLE

No Empty Packet: A logic 0 causes an empty packet to be

appended to the next IN token of the USB data, if the Buffer

Length register or the Endpoint MaxPacketSize register is zero.

A logic 1 disables this function. This bit is applicable only in

DMA mode.

Endpoint Enable: A logic 1 enables the FIFO of the indexed

endpoint. The memory size is allocated as speciﬁed in the

Endpoint MaxPacketSize register. A logic 0 disables the FIFO.

Note: ‘Stalling’ a data endpoint will confuse the Data Toggle bit

on the stalled endpoint because the internal logic picks up from

where it has stalled. Therefore, the Data Toggle bit must be

reset by disabling and re-enabling the corresponding endpoint

(by setting the bit ‘ENABLE’ to 0 or 1 in the endpoint type

register) to reset the PID.

2

DBLBUF

Double Buffering: A logic 1 enables double buffering for the

indexed endpoint. A logic 0 disables double buffering.

1 to 0

ENDPTYP[1:0]

Endpoint Type: These bits select the endpoint type as follows:

01H — isochronous

02H — bulk

03H — interrupt.

9.3.7 Short Packet register (address: 24H)

This register is reserved.

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9.4 DMA registers

Two types of Generic DMA transfer and three types of IDE-speciﬁed transfer can be

done by writing the proper opcode in the DMA Command Register. The control bits

are given in Table 26 (Generic DMA transfers) and Table 27 (IDE-speciﬁed transfers).

GDMA read/write (opcode = 00H/01H) — Generic DMA Slave mode; Depending on

the MODE[1:0] bit set in the DMA conﬁguration register, either the DACK signal or the

DIOR/DIOW signals are used to strobe the data. These signals are driven by the

external DMA Controller.

GDMA slave mode can operate in either counter mode or EOT only mode.

In counter mode, the DIS_XFER_CNT bit in the DMA conﬁguration register must be

set to logic 0. The DMA transfer counter register must be programmed before any

DMA command is issued. The DMA transfer counter is set by writing from the LSByte

to the MSByte (address: 34H to 37H). The DMA transfer count is updated internally

only after the MSByte has been written. Once the DMA transfer is started, the transfer

counter starts decrementing and upon reaching ‘0’, the DMA_XFER_OK bit is set

and an interrupt is generated by the ISP1581. If the DMA master wants to terminate

the DMA transfer, it can issue an EOT signal to the ISP1581. This EOT signal

overrides the transfer counter and can terminate the DMA transfer at any time.

In the EOT only mode, DIS_XFER_CNT has to be set to logic 1. Although the DMA

transfer counter can still be programmed, it will not have any effect on the DMA

transfer. DMA transfer will start once the DMA command is issued. Any of the

following three ways will terminate this DMA transfer:

• Detecting an external EOT

• Detecting an internal EOT (short packet on an OUT token)

• Resetting the DMA.

There are basically 3 interrupts programmable to differentiate the method of DMA

termination; namely, the INT_EOT, EXT_EOT and the DMA_XFER_OK bits in the

DMA Interrupt Reason register. Refer to Table 53 for details.

MDMA (Master) read/write (opcode = 06H/07H) — Generic DMA Master mode;

Depending on the MODE[1:0] bit set in the DMA conﬁguration register, either the

DACK signal or the DIOR/DIOW signals are used to strobe the data. these signals

are driven by the ISP1581.

In the Master mode, BURST[2:0],DIS_XFER_CNT in the DMA conﬁguration register

and the external EOT signal are not applicable. DMA transfer counter is always

enabled and the DMA_XFER_OK bit is set to ‘1’ once the counter reaches ‘0’.

PIO read/write (opcode = 04H/05H) — PIO mode for IDE transfers; the speciﬁcation

of this mode can be obtained from the ATA Speciﬁcation Rev. 4. DIOR and DIOW are

used as data strobes, IORDY can be used by the device to extend the PIO cycle.

MDMA read/write (opcode = 06H/07H) — Multi word DMA mode for IDE transfers;

the speciﬁcation of this mode can be obtained from the ATA Speciﬁcation Rev. 4.

DIOR and DIOW are used as data strobes, while DREQ and DACK serve as

handshake signals.

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UDMA read/write (opcode = 02H/03H) — Ultra DMA mode for IDE transfers; the

speciﬁcation of this mode can be obtained from the ATA Speciﬁcation Rev. 4. Pins

DA0 to DA2, CS0 and CS1 are used to select a device register for access. Control

signals are mapped as follows: DREQ (= DMARQ), DACK (= DMACK), DIOW

(= STOP), DIOR (= HDMARDY or HSTROBE), IORDY (= DSTROBE or DDMARDY).

Table 26: Control bits for Generic DMA transfers

Control bits

Description

GDMA read/write (opcode = 00H/01H)

DMA Conﬁguration register (see Table 33 and Table 34)

BURST[2:0]

determines the number of DMA cycles, during which pin

DREQ is kept asserted

MODE[1:0]

WIDTH0

determines the active read/write data strobe signals

selects the DMA bus width: 8 or 16 bits

disables the use of the DMA Transfer Counter

set to logic 0 (non-ATA transfer)

DIS_XFER_CNT

ATA_MODE

DMA Hardware register (see Table 35 and Table 36)

EOT_POL

selects the polarity of the EOT signal

ENDIAN[1:0]

determines whether the data is to be byte swapped or

normal. Applicable only in 16 bit mode.

ACK_POL, DREQ_POL,

WRITE_POL, READ_POL

select the polarity of the DMA handshake signals

MASTER

set to logic 0 (slave)

MDMA (Master) read/write (opcode = 06H/07H)

DMA Conﬁguration register (see Table 33 and Table 34)

DMA_MODE[1:0]

determines the MDMA timings for the DIOR and DIOW

strobes (value 03H is used for UDMA only)

determines the active data strobe(s).

selects the DMA bus width: 8 or 16 bits

disables the use of the DMA Transfer Counter

set to logic 1 (ATA transfer)

MODE[1:0]

WIDTH

DIS_XFER_CNT

ATA_MODE

DMA Hardware register (see Table 35 and Table 36)

EOT_POL

input EOT is not used

ENDIAN[1:0]

determines whether the data is to be byte swapped or

normal. Applicable only in 16 bit mode.

ACK_POL, DREQ_POL,

WRITE_POL, READ_POL

select the polarity of the DMA handshake signals

MASTER

set to logic 1 (master)

Table 27: Control bits for IDE-speciﬁed DMA transfers

Control bits Description

PIO read/write (opcode = 04H/05H)

DMA Conﬁguration register (see Table 33 and Table 34)

PIO_MODE[2:0]

ATA_MODE

selects the PIO mode; timings are ATA(PI) compatible

set to logic 1 (ATA transfer)

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Table 27: Control bits for IDE-speciﬁed DMA transfers…continued

Control bits Description

DMA Hardware register (see Table 35 and Table 36)

MASTER set to logic 0

MDMA read/write (opcode = 06H/07H)

DMA Conﬁguration register (see Table 33 and Table 34)

DMA_MODE[1:0]

ATA_MODE

selects the MDMA mode; timings are ATA(PI) compatible

set to logic 1 (ATA transfer)

DMA Hardware register (see Table 35 and Table 36)

MASTER set to logic 0

UDMA read/write (opcode = 02H/03H)

DMA Conﬁguration register (see Table 33 and Table 34)

DMA_MODE[1:0]

IGNORE_IORDY

ATA_MODE

selects the UDMA mode; timings are ATA(PI) compatible

used to ignore the IORDY pin during transfer

set to logic 1 (ATA transfer)

DMA Hardware register (see Table 35 and Table 36)

MASTER set to logic 0

Remark: The DMA bus defaults to three-state, until a DMA command is executed. All

the other control signals are not three-stated.

9.4.1 DMA Command register (address: 30H)

The DMA Command register is a 1-byte register that initiates all DMA transfer activity

on the DMA Controller. The register is write-only: reading it will return FFH.

Remark: The DMA bus will be in three-state until a DMA command is executed.

Table 28: DMA Command register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

DMA_CMD[7:0]

FFH

W

Bus reset

Access

Table 29: DMA Command register: bit description

Bit

Symbol

Description

7:0

DMA_CMD[7:0] DMA command code, see Table 30.

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Table 30: DMA commands

Code (Hex) Name

Description

00

GDMA Read

Generic DMA IN token transfer (slave mode only):

Data is transferred from the external DMA bus to the

internal buffer. Strobe: DIOW by external DMA

Controller.

01

GDMA Write

Generic DMA OUT token transfer (slave mode

only): Data is transferred from the internal buffer to the

external DMA bus. Strobe: DIOR by external DMA

Controller.

02

03

04

UDMA Read

UDMA Write

PIO Read^[1]

UDMA Read command: Data is transferred from the

external DMA to the internal DMA bus.

UDMA Write command: Data is transferred in UDMA

mode from the internal buffer to the external DMA bus.

PIO Read command for ATAPI device: Data is

transferred in PIO mode from the external DMA bus to

the internal buffer. Data transfer starts when IORDY is

asserted. Inputs DREQ and DACK are ignored.

05

PIO Write^[1]

PIO Write command for ATAPI device: Data is

transferred in PIO mode from the internal buffer to the

external DMA bus. Data transfer starts when IORDY is

asserted. Inputs DREQ and DACK are ignored.

06

07

0A

MDMA Read

MDMA Write

Read 1F0

Multiword DMA Read: Data is transferred from the

external DMA bus to the internal buffer.

Multiword DMA Write: Data is transferred from the

internal buffer to the external DMA bus.

Read at address 01F0H: Initiates a PIO Read cycle

from Task File 1F0. Before issuing this command the

task ﬁle byte count should be programmed at address

1F4H (LSB) and 1F5H (MSB).

0B

0C

Poll BSY

Poll BSY status bit for ATAPI device: Starts repeated

PIO Read commands to poll the BSY status bit of the

ATAPI device. When BSY = 0, polling is terminated and

an interrupt is generated.

Read Task Files

Read Task Files: Reads all task ﬁle registers except

1F0H and 1F7H. When reading has been completed,

an interrupt is generated.

0D

0E

-

reserved

Validate Buffer

Validate Buffer (for debugging only): Request from

the microcontroller to validate the endpoint buffer

following an ATA to USB data transfer.

0F

10

Clear Buffer

Restart

Clear Buffer: Request from the microcontroller to clear

the endpoint buffer after a USB to ATA data transfer.

Restart: Request from the microcontroller to move the

buffer pointers to the beginning of the endpoint FIFO.

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Table 30: DMA commands…continued

Code (Hex) Name Description

11

Reset DMA

Reset DMA: Initializes the DMA core to its power-on

reset state.

Remark: When the DMA core is reset during the Reset

DMA command, the DREQ, DACK, DIOW and DIOR

handshake pins will be temporarily asserted. This can

cause some confusion to the external DMA Controller.

To prevent this from happening, start the external DMA

Controller only after the DMA reset is done.

12

MDMA stop

-

MDMA stop: This command immediately stops the

MDMA data transfer. This is applicable for commands

06H and 07H only.

13 to FF

reserved

[1] PIO Read or Write that started using DMA Command Register only performs 16-bit transfer.

9.4.2 DMA Transfer Counter register (address: 34H)

This 4-byte register is used to set up the total byte count of a DMA transfer (DMACR).

It indicates the remaining number of bytes left for transfer. The bit allocation is given

in Table 31.

The transfer counter is used in DMA modes: PIO (commands: 04H, 05H), UDMA

(commands: 02H, 03H), MDMA (commands: 06H, 07H) and GDMA (commands:

00H, 01H).

A new value is written into the register starting with the lower byte (DMACR1) or the

lower word (MSByte: DMACR2, LSByte: DMACR1). Internally, the transfer counter is

initialized only after the last byte (DMACR4) has been written.

In the GDMA Slave mode only, the transfer counter can be disabled via bit

DIS_XFER_CNT in the DMA Conﬁguration Register (see Table 33). In this case,

input signal EOT can be used to terminate the DMA transfer when data is transferred

from the external device to the host via IN tokens. The last packet in the FIFO is

validated when pin EOT is asserted.

Table 31: DMA Transfer Counter register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

DMACR4 = DMACR[31:24]

00H

R/W

Bus reset

Access

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

DMACR3 = DMACR[23:16]

00H

R/W

Bus reset

Access

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Bit

15

14

13

12

11

10

9

8

Symbol

Reset

DMACR2 = DMACR[15:8]

00H

R/W

Bus reset

Access

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

DMACR1 = DMACR[7:0]

00H

R/W

Bus reset

Access

Table 32: DMA Transfer Counter register: bit description

Bit

Symbol

Description

31 to 24

DMACR4,

DMA transfer counter byte 4 (MSB)

DMACR[31:24]

23 to 16

15 to 8

7 to 0

DMACR3,

DMACR[23:16]

DMA transfer counter byte 3

DMA transfer counter byte 2

DMA transfer counter byte 1 (LSB)

DMACR2,

DMACR[15:8]

DMACR1,

DMACR[7:0]

9.4.3 DMA Conﬁguration register (address: 38H)

This register deﬁnes the DMA conﬁguration for the Generic DMA (GDMA) and the

Ultra-DMA (UDMA) modes. The DMA Conﬁguration register consists of 2 bytes. The

bit allocation is given in Table 33.

Table 33: DMA Conﬁguration register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

IGNORE_

IORDY

ATA_

MODE

DMA_MODE[1:0]

PIO_MODE[2:0]

Reset

-

0

00H

R/W

00H

Bus Reset

Access

Bit

0

R/W

7

R/W

6

R/W

5

4

3

2

1

0

Symbol

DIS_

XFER_

CNT

BURST[2:0]

MODE[1:0]

reserved

WIDTH

Reset

0

00H

R/W

00H

R/W

-

1

Bus Reset

Access

R/W

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Table 34: DMA Conﬁguration register: bit description

Bit^[1]

Symbol

Description

15

14

13

-

reserved

IGNORE_IORDY

ATA_MODE

A logic 1 ignores the IORDY input signal (UDMA mode only).

A logic 1 conﬁgures the DMA core for ATA or MDMA mode.

Used when issuing DMA commands 02H to 07H, 0AH and

0CH; also used when directly accessing task ﬁle registers.

A logic 0 conﬁgures the DMA core for non-ATA mode. Used

when issuing DMA commands 00H and 01H.

12 to 11 DMA_MODE[1:0]

These bits affect the timing for UDMA and MDMA mode:

00H — UDMA/MDMA mode 0: ATA(PI) compatible timings

01H — UDMA/MDMA mode 1: ATA(PI) compatible timings

02H — UDMA/MDMA mode 2: ATA(PI) compatible timings

03H — MDMA mode 3: enables the DMA Strobe Timing

register (see Table 37 and Table 38) for non-standard strobe

durations; only used in MDMA mode.

10 to 8 PIO_MODE[2:0]^[4]These bits affect the PIO timing (see Table 77):

00H to 04H — PIO mode 0 to 4: ATA(PI) compatible timings

05H to 07H — reserved.

7

DIS_XFER_CNT

BURST[2:0]

A logic 1 disables the DMA Transfer Counter (see Table 31).

The transfer counter can only be disabled in GDMA slave

mode; in master mode the counter is always enabled.

6 to 4

These bits select the DMA burst length and the DREQ timing

(GDMA Slave mode only):

00H — DREQ is asserted until the last byte/word is

transferred or until the FIFO becomes full or empty

01H — DREQ is asserted and negated for each byte/word

transferred^[2][3]

02H — DREQ is asserted and negated for every

2 bytes/words transferred^[2][3]

03H — DREQ is asserted and negated for every

4 bytes/words transferred^[2][3]

04H — DREQ is asserted and negated for every

8 bytes/words transferred^[2][3]

05H — DREQ is asserted and negated for every

12 bytes/words transferred^[2][3]

06H — DREQ is asserted and negated for every

16 bytes/words transferred^[2][3]

07H — DREQ is asserted and negated for every

32 bytes/words transferred^[2][3]

.

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Table 34: DMA Conﬁguration register: bit description…continued

Bit^[1]

Symbol

Description

3 to 2

MODE[1:0]

These bits only affect the GDMA (slave) and MDMA (master)

handshake signals:

00H — DIOR (master) or DIOW (slave): strobes data from the

DMA bus into the ISP1581; DIOW (master) or DIOR (slave):

puts data from the ISP1581 on the DMA bus

01H — DIOR (master) or DACK (slave) strobes the data from

the DMA bus into the ISP1581; DACK (master) or DIOR

(slave) puts the data from the ISP1581 on the DMA bus

02H — DACK (master and slave) strobes the data from the

DMA bus into the ISP1581 and also puts the data from the

ISP1581 on the DMA bus (This mode is applicable only to

16-bit DMA; this mode cannot be used for 8-bit DMA.)

03H — reserved.

1

0

-

reserved

WIDTH

This bit selects the DMA bus width for GDMA (slave) and

MDMA (master):

0 — 8-bit data bus

1 — 16-bit data bus.

[1] The DREQ pin will be driven only after you perform a write access to the DMA Conﬁguration register.

That is, after you have conﬁgured the DMA Conﬁguration register.

[2] DREQ is asserted only if space (writing) or data (reading) is available in the FIFO.

[3] This process is stopped when the transfer FIFO becomes empty.

[4] PIO Read or Write that started using DMA Command Register only performs 16-bit transfer.

9.4.4 DMA Hardware register (address: 3CH)

The DMA Hardware register consists of 1 byte. The bit allocation is shown in

Table 35.

This register determines the polarity of the bus control signals (EOT, DACK, DREQ,

DIOR, DIOW) and the DMA mode (master or slave). It also controls whether the

upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes

GDMA (slave) and MDMA (master) only.

Table 35: DMA Hardware register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

ENDIAN[1:0]

EOT_

POL

MASTER

ACK_

POL

DREQ_

POL

WRITE_

POL

READ_

POL

Reset

00H

R/W

0

1

0

Bus reset

Access

R/W

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Table 36: DMA Hardware register: bit description

Bit

Symbol

Description

7 to 6

ENDIAN[1:0] These bits determine whether the data bus is swapped between

internal RAM and the DMA bus: This only applies for modes

GDMA (slave) and MDMA (master):

00H — normal data representation

16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0]

01H — swapped data representation

16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8]

02H, 03H — reserved.

Note: while operating with 8 bit data bus, ENDIAN bits should be

always set to 00H.

5

EOT_POL

Selects the polarity of the End Of Transfer input (used in GDMA

slave mode only):

0 — EOT is active LOW

1 — EOT is active HIGH.

4

3

2

1

0

MASTER

Selects the DMA master/slave mode:

0 — GDMA slave mode.

1 — MDMA master mode.

ACK_POL

DREQ_POL

Selects the DMA acknowledgement polarity:

0 — DACK is active LOW

1 — DACK is active HIGH.

Selects the DMA request polarity:

0 — DREQ is active LOW

1 — DREQ is active HIGH.

WRITE_POL Selects the DIOW strobe polarity:

0 — DIOW is active LOW

1 — DIOW is active HIGH.

READ_POL

Selects the DIOR strobe polarity:

0 — DIOR is active LOW

1 — DIOR is active HIGH.

9.4.5 DMA Strobe Timing register (address: 60H)

This 1-byte register controls the strobe timings for the MDMA mode, when the

DMA_MODE bits in the DMA Conﬁguration register have been set to 03H. The bit

allocation is given in Table 37.

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Table 37: DMA Strobe Timing register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

reserved

DMA_STROBE_CNT[4:0]

-

1FH

R/W

Bus reset

Access

R/W

Table 38: DMA Strobe Timing register: bit description

Bit

Symbol

Description

7 to 5

4 to 0

-

reserved.

DMA_

STROBE_

CNT[4:0]

These bits select the strobe duration for DMA_MODE = 03H

(see Table 33). The strobe duration is (N+1) cycles^[1], with N

representing the value of DMA_STROBE_CNT (see Figure 5).

[1] The cycle duration indicates the internal clock cycle (33.3 ns/cycle).

x

(N + 1) cycles

004aaa125

Fig 5. Programmable strobe timing.

9.4.6 Task File registers (addresses: 40H to 4FH)

These registers allow direct access to the internal registers of an ATAPI peripheral

using PIO mode. The supported Task File registers and their functions are shown in

Table 39. The correct peripheral register is automatically addressed via pins CS1,

CS0, DA2, DA1 and DA0 (see Table 40).

Table 39: Task File register functions

Address (Hex)

ATA function

ATAPI function

data (16-bits)

error/feature

1F0

1F1

1F2

1F3

1F4

1F5

1F6

1F7

3F6

3F7

data (16-bits)

error/feature

sector count

interrupt reason

reserved

sector number/LBA[7:0]

cylinder low/LBA[15:8]

cylinder high/LBA[23:16]

drive/head/LBA[27:24]

command

cylinder low

cylinder high

drive select

status/command

alternate status/command

reserved

alternate status/command

drive address

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Table 40: ATAPI peripheral register addressing

Task ﬁle

CS1

H

CS0

L

DA2

L

DA1

L

DA0

L

1F0

1F1

1F2

1F3

1F4

1F5

1F6

1F7

3F6

3F7

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

In 8-bit bus mode, the 16-bit Task File register 1F0 requires 2 consecutive write/read

accesses before the proper PIO write/read is generated on the IDE interface. The ﬁrst

byte is always the lower byte (LSByte). Other task ﬁle registers can be accessed

directly.

Writing to Task File registers can be done in any order except for Task File register

1F7, which must be written last.

Table 41: Task File register 1F0 (address: 40H): bit allocation

CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = L.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

data (ATA or ATAPI)

00H

R/W

Bus reset

Access

Table 42: Task File register 1F1 (address: 48H): bit allocation

CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = H.

Bit

7

6

5

4

3

2

1

Symbol

Reset

error/feature (ATA or ATAPI)

00H

R/W

Bus reset

Access

Table 43: Task File register 1F2 (address: 49H): bit allocation

CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = L.

Bit

7

6

5

4

3

2

1

Symbol

Reset

sector count (ATA) or interrupt reason (ATAPI)

00H

R/W

Bus reset

Access

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Product data

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38 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 44: Task File register 1F3 (address: 4AH): bit allocation

CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = H.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

sector number/LBA[7:0] (ATA), reserved (ATAPI)

00H

R/W

Bus reset

Access

Table 45: Task File register 1F4 (address: 4BH): bit allocation

CS1 = H, CS0 = L, DA2 = H, DA1 = L, DA0 = L.

Bit

7

6

5

4

3

2

1

Symbol

Reset

cylinder low/LBA[15:8] (ATA) or cylinder low (ATAPI)

00H

R/W

Bus reset

Access

Table 46: Task File register 1F5 (address: 4CH): bit allocation

CS1 = H, CS0 = L, DA2 = H, DA1 = L, DA0 = H.

Bit

7

6

5

4

3

2

1

Symbol

Reset

cylinder high/LBA[23:16] (ATA) or cylinder high (ATAPI)

00H

R/W

Bus reset

Access

Table 47: Task File register 1F6 (address: 4DH): bit allocation

CS1 = H, CS0 = L, DA2 = H, DA1 = H, DA0 = L.

Bit

7

6

5

4

3

2

1

Symbol

Reset

drive/head/LBA[27:24] (ATA) or drive (ATAPI)

00H

R/W

Bus reset

Access

Table 48: Task File register 1F7 (address: 44H): bit allocation

CS1 = H, CS0 = L, DA2 = H, DA1 = H, DA0 = H.

Bit

7

6

5

4

3

2

1

Symbol

Reset

command (ATA) or status^[1]/command (ATAPI)

00H

W

Bus reset

Access

[1] Task File register 1F7 is a write-only register; a read will return FFH.

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 49: Task File register 3F6 (address: 4EH): bit allocation

CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = L.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

alternate status/command (ATA or ATAPI)

00H

R/W

Bus reset

Access

Table 50: Task File register 3F7 (address: 4FH): bit allocation

CS1 = L, CS0 = H, DA2 = H, DA1 = H, DA0 = H.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

drive address (ATA) or reserved (ATAPI)

00H

R/W

Bus reset

Access

9.4.7 DMA Interrupt Reason register (address: 50H)

This 2-byte register shows the source(s) of a DMA interrupt. Each bit is refreshed

after a DMA command has been executed. An interrupt source is cleared by writing a

logic 1 to the corresponding bit. The bit allocation is given in Table 51.

Table 51: DMA Interrupt Reason register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

ODD_IND

EXT_EOT

INT_EOT

INTRQ_

DMA_

PENDING XFER_OK

Reset

-

0

Bus reset

Access

Bit

0

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

0

Symbol

1F0_WF_E 1F0_WF_F 1F0_RF_E READ_1F0

BSY_

DONE

TF_RD_

DONE

CMD_

INTRQ_OK

reserved

Reset

0

-

Bus reset

Access

R/W

Table 52: DMA Interrupt Reason Register: bit description

Bit

Symbol

Description

15 to 13 -

reserved

12

ODD_IND

A logic 1 indicates that the last packet with odd bytes has

been transferred from the OUT token buffer to the DMA. This

is applicable only for the OUT token data in the DMA slave

mode. It has no meaning for the IN token data. Refer to the

document Using the Odd Bit Indicator for DMA.

11

10

EXT_EOT

INT_EOT

A logic 1 indicates that an external EOT is detected. This is

applicable only in GDMA slave mode.

A logic 1 indicates that an internal EOT is detected. see

Table 53.

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 52: DMA Interrupt Reason Register: bit description…continued

Bit

Symbol

Description

9

INTRQ_PENDING A logic 1 indicates that a pending interrupt was detected on

pin INTRQ.

8

DMA_XFER_OK

A logic 1 indicates that the DMA transfer has been completed

(DMA Transfer Counter has become zero). This bit is only

used in GDMA (slave) mode and MDMA (master) mode.

7

6

5

4

3

2

1

1F0_WF_E

A logic 1 indicates that the 1F0 write FIFO is empty and the

microcontroller can start writing data.

1F0_WF_F

A logic 1 indicates that the 1F0 write FIFO is full and the

microcontroller must stop writing data.

1F0_RF_E

A logic 1 indicates that 1F0 read FIFO is empty and the

microcontroller must stop reading data.

READ_1F0

A logic 1 indicates that 1F0 FIFO contains unread data and

the microcontroller can start reading data.

BSY_DONE

TF_RD_DONE

CMD_INTRQ_OK

A logic 1 indicates that the BSY status bit has become zero

and polling has been stopped.

A logic 1 indicates that the Read Task Files command has

been completed.

A logic 1 indicates that all bytes from the FIFO have been

transferred (DMA Transfer Count zero) and an interrupt on pin

INTRQ was detected.

0

-

reserved

Table 53: Internal EOT-Functional relation with DMA_XFER_OK bit

INT_EOT DMA_XFER_OK Description

1

0

1

During the DMA transfer, there is a premature termination

with short packet^[1].

DMA transfer is completed with short packet and the DMA

transfer counter has reached ‘0’.

DMA transfer is completed without any short packet and the

DMA transfer counter has reached ‘0’.

[1] The short packet does not include zero-length packets.

9.4.8 DMA Interrupt Enable register (address: 54H)

This 2-byte register controls the interrupt generation of the source bits in the DMA

Interrupt Reason register (see Table 51). The bit allocation is given in Table 54. The

bit descriptions are given in Table 52. A logic 1 enables interrupt generation. The

values after a (bus) reset are logic 0 (disabled).

Table 54: DMA Interrupt Enable register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

IE_ODD IE_EXT_EOT IE_INT_EOT

_IND

IE_INTRQ_

PENDING

IE_DMA_

XFER_OK

Reset

-

0

Bus reset

Access

R/W

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Product data

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41 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Bit

7

6

5

4

3

2

1

0

Symbol

IE_1F0_

WF_E

IE_1F0_

WF_F

IE_1F0_

RF_E

IE_

READ_1F0

IE_BSY_

DONE

IE_TF_

RD_DONE INTRQ_OK

IE_CMD_

reserved

Reset

0

-

Bus reset

Access

R/W

9.4.9 DMA Endpoint register (address: 58H)

This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA

transfers. The bit allocation is given in Table 55.

Table 55: DMA Endpoint register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Power Reset

Bus Reset

Access

reserved

EPIDX[2:0]

DMADIR

-

0

R/W

Table 56: DMA Endpoint register: bit description

Bit

Symbol

-

Description

7 to 4

3 to 1

0

reserved

EPIDX[2:0]

DMADIR

selects the indicated endpoint for DMA access

0 — selects the RX/OUT FIFO for DMA read transfers

1 — selects the TX/IN FIFO for DMA write transfers.

The DMA Endpoint register must not reference the endpoint that is indexed by the

Endpoint Index register (02CH) at any time. Doing so would result in data corruption.

Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint.

However, if the DMA Endpoint register is pointed to an active endpoint, the ﬁrmware

must not reference the same endpoint on the Endpoint Index register.

9.5 General registers

9.5.1 Interrupt register (address: 18H)

The Interrupt register consists of 4 bytes. The bit allocation is given in Table 57.

When a bit is set in the Interrupt register, this indicates that the hardware condition for

an interrupt has occurred. When the Interrupt register content is non-zero, the INT

output will be asserted. Upon detecting the interrupt, the external microprocessor

must read the Interrupt register to determine the source of the interrupt.

Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition,

various bus states can generate an interrupt: Resume, Suspend, Pseudo-SOF, SOF

and Bus Reset. The DMA Controller only has one interrupt bit: the source for a DMA

interrupt is shown in the DMA Interrupt Reason register (see Table 51).

Each interrupt bit can be individually cleared by writing a logic 1. The DMA interrupt

bit can be cleared by writing a logic 1 to the related interrupt source bit in the DMA

Interrupt Reason register and writing a logic 1 to the DMA bit of the interrupt register.

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Product data

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Hi-Speed USB peripheral controller

Philips Semiconductors

Table 57: Interrupt register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

reserved

EP7TX

EP7RX

-

0

Bus reset

Access

Bit

-

R/W

22

-

R/W

19

-

R/W

18

0

R/W

21

R/W

23

20

17

16

Symbol

Reset

EP6TX

EP6RX

0

EP5TX

EP5RX

EP4TX

0

EP4RX

0

EP3TX

EP3RX

0

Bus reset

Access

Bit

0

R/W

14

R/W

11

R/W

10

R/W

15

13

12

9

8

Symbol

Reset

EP2TX

EP2RX

0

EP1TX

EP1RX

EP0TX

0

EP0RX

0

reserved

EP0SETUP

0

-

0

Bus reset

Access

Bit

0

R/W

6

R/W

3

R/W

2

R/W

1

7

5

4

0

Symbol

Reset

reserved

DMA

0

HS_STAT

RESUME

SUSP

0

PSOF

0

SOF

0

BRESET

0

-

0

Bus reset

Access

0

unchanged

R/W

Table 58: Interrupt register: bit description

Bit

31 to 26

25

Symbol

reserved

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

Description

reserved; must write logic 0

A logic 1 indicates the Endpoint 7 TX buffer as interrupt source.

A logic 1 indicates the Endpoint 7 RX buffer as interrupt source.

A logic 1 indicates the Endpoint 6 TX buffer as interrupt source.

A logic 1 indicates the Endpoint 6 RX buffer as interrupt source.

A logic 1 indicates the Endpoint 5 TX buffer as interrupt source.

A logic 1 indicates the Endpoint 5 RX buffer as interrupt source.

A logic 1 indicates the Endpoint 4 TX buffer as interrupt source.

A logic 1 indicates the Endpoint 4 RX buffer as interrupt source.

A logic 1 indicates the Endpoint 3 TX buffer as interrupt source.

A logic 1 indicates the Endpoint 3 RX buffer as interrupt source.

A logic 1 indicates the Endpoint 2 TX buffer as interrupt source.

A logic 1 indicates the Endpoint 2 RX buffer as interrupt source.

A logic 1 indicates the Endpoint 1 TX buffer as interrupt source.

A logic 1 indicates the Endpoint 1 RX buffer as interrupt source.

24

23

22

21

20

19

18

17

16

15

14

13

12

11

A logic 1 indicates the Endpoint 0 data TX buffer as interrupt

source.

10

EP0RX

A logic 1 indicates the Endpoint 0 data RX buffer as interrupt

source.

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Product data

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 58: Interrupt register: bit description…continued

Bit

9

Symbol

Description

reserved

EP0SETUP

reserved.

8

A logic 1 indicates that a SETUP token was received on

Endpoint 0.

7

6

reserved

DMA

reserved.

DMA status: A logic 1 indicates a change in the DMA Status

register.

5

HS_STAT

High Speed Status:.A logic 1 indicates a change from FS to

HS mode (HS connection). This bit is not set, when the system

goes into a FS suspend.

4

3

2

RESUME

SUSP

Resume status: A logic 1 indicates that a status change from

‘suspend’ to ‘resume’ (active) was detected.

Suspend status: A logic 1 indicates that a status change from

active to ‘suspend’ was detected on the bus.

PSOF

Pseudo SOF interrupt: A logic 1 indicates that a Pseudo SOF

or µSOF was received. Pseudo SOF is an internally generated

clock signal (FS: 1 ms period, HS: 125 µs period) synchronized

to the USB bus SOF/µSOF.

1

0

SOF

SOF interrupt: A logic 1 indicates that a SOF/µSOF was

received.

BRESET

Bus Reset: A logic 1 indicates that a USB bus reset was

detected.

9.5.2 Chip ID register (address: 70H)

This read-only register contains the chip identiﬁcation and the hardware version

numbers. The ﬁrmware should check this information to determine the functions and

features supported. The register contains 3 bytes and the bit allocation is shown in

Table 59.

Table 59: Chip ID register: bit allocation

Bit

23

15

7

22

14

6

21

13

5

20

19

18

10

2

17

16

Symbol

Reset

CHIPID[23:16]

15H

R

Bus reset

Access

Bit

12

11

9

8

Symbol

Reset

CHIPID[15:8]

81H

R

Bus reset

Access

Bit

4

3

1

0

Symbol

Reset

VERSION[7:0]

51H

R

Bus reset

Access

9397 750 13462

Product data

Rev. 06 — 23 December 2004

44 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 60: Chip ID Register: bit description

Bit

Symbol

Description

23 to 16

15 to 8

7 to 0

CHIPID[23:16] Chip ID: lower byte (15H)

CHIPID[15:8] Chip ID: upper byte (81H)

VERSION

Version number (51H): The version number will be upgraded as

and when there are new revisions with improved performance

and functionality.

9.5.3 Frame Number register (address: 74H)

This read-only register contains the frame number of the last successfully received

Start Of Frame (SOF). The register contains 2 bytes and the bit allocation is given in

Table 61. In case of 8-bit access the register content is returned lower byte ﬁrst.

Table 61: Frame Number register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Power Reset

Bus Reset

Access

reserved

MICROSOF[2:0]

SOFR[10:8]

-

00H

R

00H

R

7

R

6

Bit

5

4

3

2

1

0

Symbol

Power Reset

Bus Reset

Access

SOFR[7:0]

00H

R

Table 62: Frame Number register: bit description

Bit

Symbol

MICROSOF[2:0] microframe number

SOFR[10:0] frame number

Description

13 to 11

10 to 0

9.5.4 Scratch register (address: 78H)

This 16-bit register can be used by the ﬁrmware to save and restore information, for

example, the device status before it enters ‘suspend’ state. The bit allocation is given

in Table 63.

Table 63: Scratch Register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

SFIRH[7:0]

00H

Bus reset

Access

Bit

00H

R/W

7

6

5

4

3

2

1

0

Symbol

Reset

SFIRL[7:0]

00H

Bus reset

Access

00H

R/W

9397 750 13462

Product data

Rev. 06 — 23 December 2004

45 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 64: Scratch Information register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

SFIRH[7:0]

SFIRL[7:0]

scratch ﬁrmware information register (high byte)

scratch ﬁrmware information register (low byte)

9.5.5 Test Mode register (address: 84H)

This 1-byte register allows the ﬁrmware to set the (D+, D−) lines to predetermined

states for testing purposes. The bit allocation is given in Table 65.

Remark: Only one bit can be set at a time.

Table 65: Test Mode register: bit allocation

Bit

7

6

5

4

3

PRBS

0

2

1

JSTATE

0

Symbol

Reset

FORCEHS

reserved

FORCEFS

KSTATE

SE0_NAK

0

-

0

Bus reset

Access

0

R/W

Table 66: Test Mode Register: bit description

Bit

Symbol

Description

7^[1]

FORCEHS

A logic 1 forces the hardware to high-speed mode only and

disables the chirp detection logic.

6 to 5

4^[1]

-

reserved.

FORCEFS

A logic 1 forces the physical layer to full-speed mode only and

disables the chirp detection logic.

3^[2]

PRBS

A logic 1 sets the (D+, D−) lines to toggle in a pre-determined

random pattern.

2^[2]

1^[2]

0^[2]

KSTATE

JSTATE

Writing a logic 1 sets the (D+, D−) lines to the K state.

Writing a logic 1 sets the (D+, D−) lines to the J state.

SE0_NAK

Writing a logic 1 sets the (D+, D−) lines to a HS quiescent state.

The device only responds to a valid HS IN token with a NAK.

[1] Either FORCEHS or FORCEFS should be set to logic 1 at a time.

[2] Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit must be set to logic 1 at a

time.

10. Power supply

The ISP1581 can be powered from 3.3 V or 5.0 V.

If the ISP1581 is powered from V_CC= 5.0 V, an integrated voltage regulator provides

a 3.3 V supply voltage for the internal logic and the USB transceiver. For connection

details, see Figure 6.

The ISP1581 can also be operated from V_CC= 3.3 V. In this case, the internal

regulator is disabled and all the supply pins are connected to V_CC. For connection

details see Figure 7.

9397 750 13462

Product data

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46 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

ISP1581

V

CC(5.0)

2

4

5.0 V

V

0.01 µF

0.1 µF

CCA(3.3)

CC(3.3)

V

0.01 µF

0.1 µF

24

0.1 µF

10 µF

37

0.01 µF

0.1 µF

V

CC(3.3)

43

58

0.01 µF

0.1 µF

CC(3.3)

0.01 µF

0.1 µF

64

0.01 µF

0.1 µF

10 µF

0.01 µF

004aaa014

Fig 6. ISP1581 with 5.0 V supply.

ISP1581

V

CC(5.0)

2

4

3.3 V

10 µF

V

0.1 µF

0.01 µF

0.1 µF

CCA(3.3)

0.01 µF

24

CC(3.3)

V

0.01 µF

0.1 µF

CC(3.3)

37

V

0.01 µF

0.1 µF

43

58

V

0.01 µF

0.1 µF

CC(3.3)

V

0.01 µF

CC(3.3)

64

004aaa015

10 µF

0.01 µF

0.1 µF

Fig 7. ISP1581 with 3.3 V supply.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

47 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

11. Limiting values

Table 67: Absolute maximum ratings

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC

V_I

Parameter

Conditions

Min

−0.5

-

Max

Unit

V

supply voltage

+6.0

input voltage

V_CC+ 0.5

100

V

I_lu

latch-up current

electrostatic discharge voltage

V_I< 0 or V_I> V_CC

I_LI< 1 µA

mA

V_esd

pins D+, D-, GND and V_CC(5.0)

other pins

-

±4000

±2000

+150

770

V

-

V

T_stg

P_tot

storage temperature

total power dissipation

−60

°C

mW

-

12. Recommended operating conditions

Table 68: Recommended operating conditions

Symbol

Parameter

Conditions

Min

4.0

3.0

0

Max

5.5

3.6

5.5

3.6

Unit

V

V_CC

supply voltage

with voltage converter

without voltage converter

V

V_I

input voltage range

V

V_I(AI/O)

input voltage on analog I/O pins

0

V

(D+, D−)

V_O(od)

T_amb

open-drain output pull-up voltage

ambient temperature

0

V_CC

V

−40

+85

°C

13. Static characteristics

Table 69: Static characteristics; supply pins

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

V_CCA(3.3)

I_CC

Parameter

Conditions

Min

3.0^[1]

Typ

Max

Unit

V

regulated supply voltage

operating supply current

suspend supply current

with voltage converter

3.3

3.6

-

130

450

-

mA

µA

I_CC(susp)

no pull-up on pin D+

[1] In ‘suspend’ mode the minimum voltage is 2.7 V.

9397 750 13462

Product data

Rev. 06 — 23 December 2004

48 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 70: Static characteristics: digital pins

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_IL

Parameter

Conditions

Min

Typ

Max

Unit

LOW-level input voltage

HIGH-level input voltage

-

0.8

-

V

V_IH

2.0

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

I_OL= rated drive

I_OH= rated drive

-

0.4

-

V

V_OH

2.6

Leakage current

I_LIinput leakage current

−5^[1]

-

+5^[1]

µA

[1] This value is applicable to transistor input only. The value will be different if internal pull-up or pull-down resistors are used.

Table 71: Static characteristics: analog I/O pins (D+, D−)^[1]

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Original USB transceiver (full-speed)

Input levels (differential receiver)

V_DI

differential input sensitivity

|V_I(D+)− V_I(D−)

|

0.2

0.8

-

V

V_CM

differential common mode

voltage

includes V_DIrange

2.5

Input levels (single-ended receiver)

V_IL

LOW-level input voltage

HIGH-level input voltage

hysteresis voltage

-

0.8

-

V

V_IH

2.0

0.4

V_hys

0.7

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

pull-up on D+;

R_L= 1.5 kΩ to +3.6V

0

-

0.4

3.6

V

V_OH

pull-down on D+, D-;

2.8

R_L= 15 kΩ to GND

Hi-Speed USB transceiver

Input levels (differential receiver)

V_HSSQ

high-speed squelch detection

threshold (differential)

squelch detected

-

100

mV

no squelch detected

150

625

-

V_HSDSC

high-speed disconnect detection disconnect detected

threshold (differential)

-

disconnect not detected

525

-

V_HSDI

high-speed differential input

sensitivity

|V_I(D+)- V_I(D-)

|

300

V_HSCM

high-speed data signaling

−50

-

+500

mV

common mode voltage range

Output levels

V_HSOI

high-speed idle level output

voltage (differential)

−10

-

+10

mV

V_HSOL

high-speed LOW-level output

voltage (differential)

9397 750 13462

Product data

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 71: Static characteristics: analog I/O pins (D+, D−)^[1]…continued

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_HSOH

high-speed HIGH-level output

voltage (differential)

360

-

440

mV

[1]

V_CHIRPJ

V_CHIRPK

chirp-J output voltage

(differential)

700

-

1100

mV

chirp-K output voltage

(differential)

−900

−500

Leakage current

I_LZ

three-state leakage current

-

±10

µA

Capacitance

C_IN

transceiver capacitance

pin to GND

10

pF

Resistance

[2]

Z_DRV2

driver output impedance for

Hi-Speed USB and Original USB

steady-state drive

40.5

10

45

-

49.5

-

Ω

Z_INP

input impedance

MΩ

Termination

V_TERM

termination voltage for pull-up

resistor on pin RPU

3.0^[3]

-

3.6

V

[1] HS termination resistor is disabled, and pull-up resistor is connected. Occurs only during reset when both hub and device are

high-speed capable.

[2] Includes internal matching resistors on both D+ and D−. This tolerance range complies with USB speciﬁcation 2.0.

[3] In the ‘suspend’ mode, the minimum voltage is 2.7 V.

14. Dynamic characteristics

Table 72: Dynamic characteristics

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; unless otherwise speciﬁed.

Symbol

Reset

Parameter

Conditions

Min

500

-

Typ

-

Max

Unit

t_W(RESET)

pulse width on input RESET

crystal oscillator running

-

µs

Crystal oscillator

f_XTALcrystal frequency

12

MHz

Table 73: Dynamic characteristics: analog I/O pins (D+, D−)^[1]

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; C_L= 50 pF; R_PU= 1.5 kΩ on D+ to V_TERM.; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min.

Typ

Max

Unit

Driver characteristics

Full-speed mode

t_FR

rise time

C_L= 50 pF;

10 to 90% of |V_OH− V_OL

4

-

20

ns

%

|

t_FF

fall time

C_L= 50 pF;

90 to 10% of |V_OH− V_OL

4

20

|

[2]

FRFM

differential rise/fall time

90

111.11

matching (t_FR/t_FF

)

9397 750 13462

Product data

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 73: Dynamic characteristics: analog I/O pins (D+, D−)^[1]…continued

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C; C_L= 50 pF; R_PU= 1.5 kΩ on D+ to V_TERM.; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min.

Typ

Max

Unit

[2][3]

V_CRS

output signal crossover voltage

1.3

-

2.0

V

High-speed mode

t_HSRhigh-speed differential rise

with captive cable

500

-

ps

time

t_HSF

high-speed differential

fall time

Data source timing

Full-speed mode

[3]

t_FEOPT

t_FDEOP

source EOP width

see Figure 8

160

-

175

ns

source differential data-to-EOP see Figure 8

transition skew

−2

+5

Receiver timing

Full-speed mode

[3]

t_JR1

receiver data jitter tolerance to see Figure 9

next transition

−18.5

−9

-

+18.5

+9

ns

t_JR2

receiver data jitter tolerance for see Figure 9

paired transitions

t_FEOPR

t_FST

receiver SE0 width

accepted as EOP;

see Figure 8

width of SE0 during differential rejected as EOP;

transition see Figure 10

82

-

14

[1] Test circuit: see Figure 40.

[2] Excluding the ﬁrst transition from Idle state.

[3] Characterized only, not tested. Limits guaranteed by design.

T

PERIOD

+3.3 V

crossover point

extended

crossover point

differential

data lines

0 V

differential data to

SE0/EOP skew

N × T + t

source EOP width: t

EOPT

receiver EOP width: t

EOPR

mgr776

PERIOD

DEOP

T_PERIODis the bit duration corresponding with the USB data rate.

Full-speed timing symbols have a subscript preﬁx ‘F’, low-speed timings a preﬁx ‘L’.

Fig 8. Source differential data-to-EOP transition skew and EOP width.

9397 750 13462

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

T

PERIOD

+3.3 V

differential

data lines

0 V

mgr871

t

JR2

JR

JR1

consecutive

transitions

N × T

+ t

PERIOD

JR1

paired

transitions

N × T

+ t

PERIOD

JR2

T_PERIODis the bit duration corresponding with the USB data rate.

Fig 9. Receiver differential data jitter.

t

FST

+3.3 V

V

IH(min)

differential

data lines

0 V

mgr872

Fig 10. Receiver SE0 width tolerance.

9397 750 13462

Product data

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

14.1 Register access timing

14.1.1 Generic Processor mode (BUS_CONF = 1)

T

cy(RW)

t

WHSH

t

RHSH

CS

t

WHAX

t

RHAX

[

]

AD 7:0

t

RLDV

RHDZ

[

]

(read) DATA 15:0

t

AVRL

RLRH

RD

t

WHDZ

t

AVWL

[

]

(write) DATA 15:0

t

I1VI2L

DVWH

t

WR

(I2)

WLWH

004aaa130

Fig 11. ISP1581 register access timing: separate address and data buses (MODE0 = 1).

T

cy(RW)

t

WHSH

t

RHSH

CS

t

WHAX

t

RHAX

[

]

AD 7:0

t

RLDV

RHDZ

[

]

(read) DATA 15:0

t

WHDZ

t

AVWL

I1VI2L

[

]

(write) DATA 15:0

t

DVWH

t

DS

(I2)

WLWH

t

I2HI1X

read

write

R/W

(I1)

004aaa131

Fig 12. ISP1581 register access timing: separate address and data buses (MODE0 = 0).

9397 750 13462

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ISP1581

Hi-Speed USB peripheral controller

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RD/WR

CS

READY

t

004aaa152

RDY1

t

RDY2

Fig 13. ISP1581 READY signal timing.

Table 74: ISP1581 register access timing parameters: separate address and data buses

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol

Reading

t_RLRH

Parameter

Min

Max

Unit

RD LOW pulse width

>t_RLDV

-

ns

t_AVRL

address set-up time before RD LOW

address hold time after RD HIGH

RD LOW to data valid delay

0

-

t_RHAX

-

t_RLDV

26

15

-

t_RHDZ

RD HIGH to data outputs three-state delay

RD HIGH to CS HIGH delay

0

t_RHSH

Writing

t_WLWH

t_AVWL

WR LOW pulse width

15

0

-

ns

address set-up time before WR LOW

address hold time after WR HIGH

data set-up time before WR HIGH

data hold time after WR HIGH

WR HIGH to CS HIGH delay

t_WHAX

t_DVWH

t_WHDZ

t_WHSH

General

T_cy(RW)

t_I1VI2L

t_I2HI1X

t_RDY1

0

11

5

0

read/write cycle time

80

0

-

ns

R/W set-up time before DS LOW

R/W hold time after DS HIGH

-

READY LOW to CS LOW delay

READY HIGH to RD/WR HIGH of the last access

3

91

t_RDY2

-

9397 750 13462

Product data

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

14.1.2 Split Bus mode (BUS_CONF = 0)

Split Bus mode (BUS_CONF = 0, MODE1 = 0, MODE0 = 0/1)

T

cy(RW)

t

WHSH

CS

]

[

data

(read) AD 7:0

address

t

WHDZ

[

]

(write) AD 7:0

address

t

DVWH

t

LLWL

LLI2L

t

WLWH

DS

(I2)

t

I2HI1X

R/W

(I1)

t

AVLL

I1VLL

ALE

MGT498

Fig 14. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 0, MODE0 = 0).

T

cy(RW)

t

WHSH

CS

t

RLDV

RHDZ

[

]

data

(read) AD 7:0

address

t

LLRL

RLRH

RHSH

RD

t

WHDZ

[

]

(write) AD 7:0

data

address

t

DVWH

t

LLWL

t

LLI2L

WLWH

WR

(I2)

t

AVLL

ALE

004aaa132

Fig 15. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 0, MODE0 = 1).

9397 750 13462

Product data

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ISP1581

Hi-Speed USB peripheral controller

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t

WHSH

LLSH

SLWL

CS

ALE

WR

RD

004aaa277

t

SLRL

t

RHSH

Fig 16. Set-up and hold time.

Table 75: ISP1581 register access timing parameters: multiplexed address/data bus (MODE1 = 0)

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol

Reading

t_RLRH

Parameter

Min

Max

Unit

RD LOW pulse width

>t_RLDV

-

ns

t_RLDV

RD LOW to data valid delay

-

25

15

-

t_RHDZ

RD HIGH to data outputs three-state delay

RD HIGH to CS HIGH delay

0

t_RHSH

t_LLRL

ALE LOW set-up time before RD LOW

-

Writing

t_WLWH

t_DVWH

t_LLWL

WR/DS LOW pulse width

15

5

-

ns

data set-up time before WR HIGH

ALE LOW to WR/DS LOW delay

data hold time after WR/DS HIGH

WR/DS HIGH to CS HIGH delay

0

t_WHDZ

t_WHSH

General

T_cy(RW)

t_AVLL

5

0

read/write cycle time

80

5

-

ns

address set-up time before ALE LOW

R/W set-up time before ALE LOW

ALE LOW to DS LOW delay

R/W hold time after DS HIGH

ALE LOW to CS HIGH

t_I1VLL

5

t_LLI2L

5

t_I2HI1X

t_LLSH

5

0

t_SLWL

CS LOW to WR LOW

0

t_SLRL

CS LOW to RD LOW

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Product data

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Split Bus mode (BUS_CONF = 0, MODE1 = 1, MODE 0 = 0/1)

t

A0WL

A0

T

cy(RW)

t

WHSH

CS

]

t

RHDZ

RLDV

t

[

data

(read) AD 7:0

address

t

RLRH

RHSH

RD

t

AVWH

t

WHRH

WR

t

WHDZ

[

]

(write) AD 7:0

data

address

t

DVWH

t

WLWH

WR

(I2)

t

WHWH

RD

(I1)

004aaa011

Fig 17. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 0, MODE0 = 1).

9397 750 13462

Product data

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

t

A0WL

A0

T

cy(RW)

t

WHSH

CS

]

t

RHDZ

RLDV

t

[

data

(read) AD 7:0

address

t

RLRH

RHSH

R/W

DS

t

WHRH

t

AVWH

t

WHDZ

[

]

(write) AD 7:0

data

address

t

DVWH

t

WLWH

DS

(I2)

t

I2HI1X

t

WHWH

R/W

(I1)

004aaa133

Fig 18. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 1, MODE0 = 0).

9397 750 13462

Product data

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58 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

t

A0WL

A0

T

cy(RW)

t

WHSH

CS

]

t

RHDZ

RLDV

t

[

data

(read) AD 7:0

address

t

RLRH

RHSH

RD

t

AVWH

t

WHRH

WR

t

WHDZ

[

]

(write) AD 7:0

data

address

t

DVWH

t

WLWH

WR

(I2)

t

WHWH

RD

(I1)

004aaa011

Fig 19. ISP1581 register access timing: multiplexed address/data bus (BUS_CONF = 0, MODE1 = 1, MODE0 = 1).

Table 76: ISP1581 register access timing parameters: multiplexed address/data bus (MODE1 = 1)

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol

Reading

t_RLDV

Parameter

Min

Max

Unit

RD LOW to data valid delay

RD HIGH to data outputs three-state delay

RD HIGH to CS HIGH delay

RD LOW pulse width

-

26

15

-

ns

t_RHDZ

0

t_RHSH

0

t_RLRH

>t_RLDV

40

-

t_WHRH

Writing

t_A0WL

WR/DS HIGH to RD HIGH delay

-

A0 set-up time before WR/DS LOW

address set-up time before WR/DS HIGH

data set-up time before WR/DS HIGH

data hold time after WR/DS HIGH

WR/DS HIGH to CS HIGH delay

0

-

ns

t_AVWH

5

t_DVWH

5

t_WHDZ

5

t_WHSH

t_WLWH

t_WHWH

General

T_cy(RW)

t_I2HI1X

0

WR/DS LOW pulse width

15

40

WR/DS HIGH (address) to WR/DS HIGH (data) delay

read/write cycle time

80

5

-

ns

R/W hold time after DS HIGH

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Product data

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ISP1581

Hi-Speed USB peripheral controller

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14.2 DMA timing

14.2.1 PIO mode

T

cy1

(1)

device

address

valid

t

su1

h1

(4)

DIOR, DIOW

t

w2

w1

(2)

[

]

(write) DATA 7:0

t

h2

su2

t

[

]

(read) DATA 7:0

t

h3(min)

su3

t

d2

HIGH

(3a)

IORDY

t

su4

(3b)

(3c)

IORDY

t

su5

MGT499

t

w3

(1) The device address consists of signals CS1, CS0, DA2, DA1 and DA0.

(2) The data bus width depends on the PIO access command used. Task File register access uses 8 bits (DATA[7:0]), except

for Task File register 1F0 which uses 16 bits (DATA[15:0]). DMA commands 04H and 05H also use a 16-bit data bus.

(3) The device can negate IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the

current cycle after t_su4following the assertion of DIOR or DIOW. The following three cases are distinguished:

a). Device keeps IORDY released (high-impedance): no wait state is generated.

b). Device negates IORDY during t_su4, but re-asserts IORDY before t_su4expires: no wait state is generated.

c). Device negates IORDY during t_su4and keeps IORDY negated for at least 5 ns after t_su4expires: a wait state is

generated. The cycle is completed as soon as IORDY is re-asserted. For extended read cycles (DIOR asserted), the read

data on lines DATAn must be valid at t_d1before IORDY is asserted.

(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.

Fig 20. PIO mode timing.

Table 77: PIO mode timing parameters

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol Parameter

T_cy1(min)read/write cycle time (minimum)

t_su1(min)

Mode 0

600

Mode 1

383

Mode 2

240

Mode 3

180

Mode 4

120

Unit

ns

[1]

address to DIOR/DIOW on set-up time

(minimum)

70

50

30

25

ns

[1]

t_w1(min)

t_w2(min)

t_su2(min)

DIOR/DIOW pulse width (minimum)

DIOR/DIOW recovery time (minimum)

165

-

125

-

100

-

80

70

30

70

25

20

ns

data set-up time before DIOW off

(minimum)

60

45

30

t_h2(min)

data hold time after DIOW off (minimum)

30

20

15

10

ns

9397 750 13462

Product data

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60 of 79

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Table 77: PIO mode timing parameters…continued

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol Parameter

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Unit

t_su3(min)

data set-up time before DIOR on

(minimum)

50

35

20

ns

t_h3(min.)

t_d2(max)

data hold time after DIOR off (minimum)

5

ns

[2]

data to three-state delay after DIOR off

(minimum)

30

t_h1(min)

t_su4(min)

t_su5(min)

t_w3(max)

address hold time after DIOR/DIOW off

(minimum)

20

15

10

ns

[3]

IORDY after DIOR/DIOW on set-up time

(minimum)

35

read data to IORDY HIGH set-up time

(minimum)

0

IORDY LOW pulse width (maximum)

1250

[1] T_cy1is the total cycle time, consisting of the command active time t_w1and is the command recovery (= inactive) time t_w2: T_cy1= t_w1+ t_w2

The minimum timing requirements for T_cy1, t_w1and t_w2must all be met. Since T_cy1(min)is greater than the sum of t_w1(min)and t_w2(min), a

host implementation must lengthen t_w1and/or t_w2to ensure that T_cy1is equal to or greater than the value reported in the IDENTIFY

DEVICE data. A device implementation shall support any legal host implementation.

.

[2] t_d2speciﬁes the time after DIOR is negated, when the data bus is no longer driven by the device (three-state).

[3] If IORDY is LOW at t_su4, the host waits until IORDY is made HIGH before the PIO cycle is completed. In that case, t_su5must be met for

reading (t_su3does not apply). When IORDY is HIGH at t_su4, t_su3must be met for reading (t_su5does not apply).

14.2.2 GDMA slave mode

(2)

DREQ

t

su1

t

h1

T

w1

cy1

(1)

DACK

t

d1

su3

DIOR/DIOW

t

w2

t

a1

t

d2

h2

[

]

(read) DATA 15:0

t

h3

su2

[

(write) DATA 15:0

MGT500

DREQ is continuously asserted until the last transfer is done or the FIFO is full.

Data strobes: DIOR (read), DIOW (write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 21. GDMA slave mode timing (BURST = 00H, MODE = 00H).

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ISP1581

Hi-Speed USB peripheral controller

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(2)

DREQ

t

T

cy1

t

su1

w1

h1

(1)

DACK

t

w2

t

d2

d1

HIGH

DIOR/DIOW

t

h2

[

]

(read) DATA 15:0

t

su2

h3

[

(write) DATA 15:0

MGT501

DREQ is continuously asserted until the last transfer is done or the FIFO is full.

Data strobe: DACK (read/write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 22. GDMA slave mode timing (BURST = 00H, MODE = 02H).

(2)

DREQ

t

su1

t

h1

T

d1

w1

cy1

t

su3

(1)

DACK

t

a1

d2

DIOR/DIOW

t

h2

[

]

(read) DATA 15:0

t

h3

su2

[

(write) DATA 15:0

MGT502

DREQ is asserted for every transfer.

Data strobes: DIOR (read), DIOW (write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 23. GDMA slave mode timing (BURST = 01H, MODE = 00H).

9397 750 13462

Product data

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ISP1581

Hi-Speed USB peripheral controller

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(2)

DREQ

t

d1

t

h1

T

su1

w1

cy1

(1)

DACK

t

w2

t

d2

HIGH

DIOR/DIOW

t

h2

[

]

(read) DATA 15:0

t

su2

h3

[

(write) DATA 15:0

MGT503

DREQ is asserted for every transfer.

Data strobe: DACK (read/write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 24. GDMA slave mode timing (BURST = 01H, MODE = 02H).

t

(2)

(1)

su1

DREQ

DACK

t

h1

t

w1

w2

t

su3

t

T

d1

cy1

d2

DIOR/DIOW

t

h2

[

]

(read) DATA 15:0

t

h3

su2

[

]

(write) DATA 15:0

MGT504

DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2.

Data strobes: DIOR (read), DIOW (write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 25. GDMA slave mode timing (BURST > 01H, MODE = 00H).

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Product data

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ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

(2)

DREQ

t

h1

su1

w1

w2

(1)

DACK

t

T

t

d1

cy1

d2

HIGH

DIOR/DIOW

t

h2

[

]

(read) DATA 15:0

t

su2

h3

[

(write) DATA 15:0

MGT505

DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2.

Data strobe: DACK (read/write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 26. GDMA slave mode timing (BURST > 01H, MODE = 02H).

(1)

DIOR/DIOW

36 ns (min)

(1)

EOT

DREQ

t

h1

004aaa012

(1) Programmable polarity: shown as active LOW.

Note: EOT should be valid for 36 ns (minimum) when DIOR/DIOW is active.

Fig 27. EOT timing in Split Bus mode.

RD/WR

36 ns (min)

(1)

EOT

DREQ

t

h1

004aaa013

(1) Programmable polarity: shown as active LOW.

Note: EOT should be valid for 36 ns (minimum) when RD/WR is active.

Fig 28. EOT timing in Generic Processor mode.

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Table 78: GDMA slave mode timing parameters

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol

T_cy1

t_su1

t_d1

Parameter

Min

78

10

33.33

0

Max

Unit

ns

read/write cycle time

-

DREQ set-up time before ﬁrst DACK on

DREQ on delay after last strobe off

DREQ hold time after last strobe on

DIOR/DIOW pulse width

-

t_h1

53

t_w1

39

36

-

600

t_w2

DIOR/DIOW recovery time

-

t_d2

read data valid delay after strobe on

read data hold time after strobe off

write data hold time after strobe off

write data set-up time before strobe off

20

5

-

t_h2

-

t_h3

1

t_su2

t_su3

10

0

-

DACK setup time before DIOR/DIOW

assertion

-

t_a1

DACK de-assertion after DIOR/DIOW

de-assertion

0

30

ns

14.2.3 MDMA mode

(2)

DREQ

DACK

T

cy1

(1)

t

su1

w1

w2

h1

d2

DIOR/DIOW

t

d3

t

d1

[

]

(write) DATA 15:0

t

h3

t

su2

h2

[

(read) DATA 15:0

MGT506

t

su2

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 29. MDMA master mode timing.

Table 79: MDMA mode timing parameters

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol

T_cy1(min)

t_w1(min)

Parameter

Mode 0 Mode 1 Mode 2 Unit

read/write cycle time (minimum)^[1]

DIOR/DIOW pulse width (minimum)^[1]

480

215

150

80

120

70

ns

t_d1(max)

data valid delay after DIOR on

(maximum)

60

50

t_h3(min)

data hold time after DIOR off (minimum)

5

ns

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Table 79: MDMA mode timing parameters…continued

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol

Parameter

Mode 0 Mode 1 Mode 2 Unit

t_su2(min)

data set-up time before DIOR/DIOW off 100

(minimum)

30

20

ns

t_h2(min)

data hold time after DIOW off (minimum) 20

15

0

10

0

ns

t_su1(min)

DACK set-up time before DIOR/DIOW on

(minimum)

0

t_h1(min)

t_w2(min)

DACK hold time after DIOR/DIOW off

(minimum)

DIOR recovery time (minimum)^[1]

DIOW recovery time (minimum)^[1]

20

5

ns

50

40

25

35

25

ns

215

t_d2(max)

DIOR on to DREQ off delay (maximum) 120

DIOW on to DREQ off delay (maximum) 40

t_d3(max)

DACK off to data lines three-state delay 20

(maximum)

[1] T_cy1is the total cycle time, consisting of the command active time t_w1and is the command recovery

(= inactive) time t_w2: T_cy1= t_w1+ t_w2. The minimum timing requirements for T_cy1, t_w1and t_w2must all

be met. Since T_cy1(min)is greater than the sum of t_w1(min)and t_w2(min), a host implementation must

lengthen t_w1and/or t_w2to ensure that T_cy1is equal to or greater than the value reported in the

IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.

14.2.4 UDMA mode

T

cy1

t

su1

(1)

DIOR

(sender)

t

h1

[

]

DATA 15:0

(sender)

t

su2

t

h2

su2

h2

(1)

IORDY

(receiver)

[

]

DATA 15:0

MGT507

(1) DATA[15:0] and strobe signals at the receiver require some time to stabilize due to the settling time and propagation delay

of the cable.

Fig 30. UDMA timing: sustained synchronous burst.

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DREQ (drive)

t

d1

(1)

DACK (host)

t

su3

d6

d13

DIOW (host)

t

d13

DIOR (host)

t

d11

t

IORDY (drive)

t

h1

d5

d4

su1

[

]

DATA 15:0 (drive)

t

su3

[

]

[

]

DA 2:0 and CS 1:0

MGT508

(1) Programmable polarity: shown as active LOW.

Fig 31. UDMA timing: drive initiating a burst for a read command.

DREQ (drive)

t

d1

(1)

DACK (host)

t

d6

su3

DIOW (host)

IORDY (drive)

DIOR (host)

t

d2

d11

t

d1

su3

t

h1

su1

[

]

DATA 15:0 (host)

t

su3

[

]

[

]

DA 2:0 and CS 1:0

MGT509

(1) Programmable polarity: shown as active LOW.

Fig 32. UDMA timing: drive initiating a burst for a write command.

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t

d7

DREQ (drive)

(1)

DACK (host)

LOW

t

d7

DIOW (host)

IORDY

t

d8

t

d9

DIOR

[

]

DATA 15:0

MGT510

(1) Programmable polarity: shown as active LOW.

Fig 33. UDMA timing: receiver pausing a burst.

DREQ (drive)

t

d3

(1)

DACK (host)

t

d2

h3

DIOW (host)

t

h3

d2

DIOR (host)

t

d2

t

d12

d10

IORDY (drive)

t

h1

t

su1

d4

[

]

CRC

t

DATA 15:0 (drive)

t

d5

h3

[

]

[

]

DA 2:0 and CS 1:0

MGT511

(1) Programmable polarity: shown as active LOW.

Fig 34. UDMA timing: drive terminating a burst during a read command.

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DREQ (drive)

t

h3

(1)

DACK (host)

t

d2

d3

DIOW (host)

t

d10

d7

IORDY (drive)

t

d9

h3

DIOR (host)

t

h1

su1

CRC

[

]

DATA 15:0 (host)

t

h3

[

]

[

]

DA 2:0 and CS 1:0

MGT512

(1) Programmable polarity: shown as active LOW.

Fig 35. UDMA timing: drive terminating a burst during a write command.

t

d2

DREQ (drive)

t

d3

t

(1)

d5

DACK (host)

t

h3

d4

t

d7

DIOW (host)

DIOR (host)

t

d3

d2

t

d9

d10

IORDY (drive)

t

h1

su1

CRC

[

]

DATA 15:0 (drive)

t

h3

[

]

[

]

DA 2:0 and CS 1:0

MGT513

(1) Programmable polarity: shown as active LOW.

Fig 36. UDMA timing: host terminating a burst during a read command.

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t

d2

DREQ (drive)

t

d3

d2

(1)

DACK (host)

t

h3

DIOW (host)

t

d2

d10

IORDY (drive)

t

d12

t

h3

DIOR (host)

t

su1

CRC

h1

[

]

DATA 15:0 (host)

t

h3

[

]

[

]

DA 2:0 and CS 1:0

MGT514

(1) Programmable polarity: shown as active LOW.

Fig 37. UDMA timing: host terminating a burst during a write command.

Table 80: UDMA mode timing parameters

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol

Parameter

Mode 0

Mode 1

Mode 2

Min Max

Unit

Min

Max

Min

Max

T_cy1

read/write cycle time (from strobe edge

to strobe edge)

114

-

75

-

55

-

ns

t_su2

t_h2

t_su1

t_h1

t_d1

t_d2

t_d3

t_d4

t_d5

data set-up time at receiver

data hold time at receiver

15

5

-

10

5

-

7

5

-

ns

-

data set-up time at sender

70

6

-

48

6

-

34

6

-

data hold time at sender

unlimited interlock time^[1]

limited interlock time^[1]

limited interlock time with minimum^[1]

data line drivers switch-off delay

data line drivers switch-on delay (host)

data line drivers switch-on delay (drive)

-

0

-

0

-

0

-

0

150

0

150

0

150

20

-

10

-

20

-

10

-

20

-

10

-

20

0

20

0

20

0

-

t_su3

control signal set-up time before DACK

on

20

-

20

-

20

-

t_h3

t_d6

t_d7

t_d8

control signal hold time after DACK off

DACK on to control signal transition delay

ready to paused delay

20

160

-

20

125

-

20

100

-

ns

70

-

70

-

70

-

strobe to ready delay to ensure a

synchronous pause

50

30

20

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Table 80: UDMA mode timing parameters…continued

V_CC= 4.0 to 5.5 V; V_GND= 0 V; T_amb= −40 to +85 °C.

Symbol

Parameter

Mode 0

Min

Mode 1

Min

Mode 2

Min

Unit

Max

75

20

-

Max

60

20

-

Max

50

20

-

t_d9

ready to ﬁnal strobe edge delay

DACK off to IORDY high-Z delay

DACK on to IORDY HIGH delay

-

ns

t_d10

t_d11

t_d12

0

ﬁnal strobe edge to DREQ off or DIOW

on delay

50

-

50

-

50

-

t_d13

ﬁrst strobe delay after control signal on

0

230

0

200

0

170

ns

[1] Interlock time is the time allowed between an action by one agent and the following action by the other agent. An agent can be a sender

or a receiver. Interlocking actions require a response signal from the other agent before processing can continue.

15. Application information

ISP1581

address

8

AD7 to AD0

data 16

DATA15 to DATA0

CPU

read strobe

write strobe

chip select

(R/W)/RD

DS/WR

CS

MGT515

Fig 38. Typical interface connections for Generic Processor mode.

[

]

DATA 15:0

DREQ

DACK

DIOW

DIOR

DMA

ISP1581

AD7 to

AD0

ALE/A0

address

INT

(R/W)/RD DS/WR

address/data

read

write

latch

enable

interrupt

strobe

8

ALE

P0.7/AD7

to

P0.0/AD0

INTn

RD

WR

8051

MICROCONTROLLER

MGT516

Fig 39. Typical interface connections for Split Bus mode (slave mode).

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16. Test information

The dynamic characteristics of the analog I/O ports (D+, D−) as listed in Table 73,

were determined using the circuit shown in Figure 40.

test point

D.U.T

C

L

50 pF

15 kΩ

MGT495

In full-speed mode an internal 1.5 kΩ pull-up resistor is connected to pin D+.

Fig 40. Load impedance for D+ and D− pins (full-speed mode).

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17. Package outline

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

y

X

A

48

33

Z

49

32

E

e

H

A

E

2

E

A

(A )

3

A

1

w M

p

θ

b

L

p

pin 1 index

L

64

17

detail X

1

16

Z

v

M

A

D

e

w M

b

p

D

B

H

v

M

B

D

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

L

v

w

y

Z

E

θ

1

2

3

p

D

E

p

D

max.

7^o

0^o

0.20 1.45

0.05 1.35

0.27 0.18 10.1 10.1

0.17 0.12 9.9 9.9

12.15 12.15

11.85 11.85

0.75

0.45

1.45 1.45

1.05 1.05

1.6

mm

0.25

0.5

1

0.2 0.12 0.1

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-25

SOT314-2

136E10

MS-026

Fig 41. LQFP64 package outline.

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18. Soldering

18.1 Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology. A more in-depth account

of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit

Packages (document order number 9398 652 90011).

There is no soldering method that is ideal for all surface mount IC packages. Wave

soldering can still be used for certain surface mount ICs, but it is not suitable for ﬁne

pitch SMDs. In these situations reﬂow soldering is recommended. In these situations

reﬂow soldering is recommended.

18.2 Reﬂow soldering

Reﬂow soldering requires solder paste (a suspension of ﬁne solder particles, ﬂux and

binding agent) to be applied to the printed-circuit board by screen printing, stencilling

or pressure-syringe dispensing before package placement. Driven by legislation and

environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reﬂowing; for example, convection or convection/infrared

heating in a conveyor type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending on heating method.

Typical reﬂow peak temperatures range from 215 to 270 °C depending on solder

paste material. The top-surface temperature of the packages should preferably be

kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free process)

– for all BGA, HTSSON..T and SSOP..T packages

– for packages with a thickness ≥ 2.5 mm

– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm³so called

thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with

a thickness < 2.5 mm and a volume < 350 mm³so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all

times.

18.3 Wave soldering

Conventional single wave soldering is not recommended for surface mount devices

(SMDs) or printed-circuit boards with a high component density, as solder bridging

and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was speciﬁcally

developed.

If wave soldering is used the following conditions must be observed for optimal

results:

• Use a double-wave soldering method comprising a turbulent wave with high

upward pressure followed by a smooth laminar wave.

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• For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be

parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the

transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• For packages with leads on four sides, the footprint must be placed at a 45° angle

to the transport direction of the printed-circuit board. The footprint must

incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be ﬁxed with a droplet of

adhesive. The adhesive can be applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or

265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated ﬂux will eliminate the need for removal of corrosive residues in

most applications.

18.4 Manual soldering

Fix the component by ﬁrst soldering two diagonally-opposite end leads. Use a low

voltage (24 V or less) soldering iron applied to the ﬂat part of the lead. Contact time

must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within

2 to 5 seconds between 270 and 320 °C.

18.5 Package related soldering information

Table 81: Suitability of surface mount IC packages for wave and reﬂow soldering

methods

Package^[1]

Soldering method

Wave

Reﬂow^[2]

BGA, HTSSON..T^[3], LBGA, LFBGA, SQFP,

SSOP..T^[3], TFBGA, USON, VFBGA

not suitable

suitable

DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable^[4]

HSQFP, HSSON, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

suitable

PLCC^[5], SO, SOJ

suitable

LQFP, QFP, TQFP

not recommended^[5][6]

not recommended^[7]

not suitable

suitable

SSOP, TSSOP, VSO, VSSOP

CWQCCN..L^[8], PMFP^[9], WQCCN..L^[8]

suitable

not suitable

[1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note

(AN01026); order a copy from your Philips Semiconductors sales ofﬁce.

[2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the

maximum temperature (with respect to time) and body size of the package, there is a risk that internal

or external package cracks may occur due to vaporization of the moisture in them (the so called

popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated

Circuit Packages; Section: Packing Methods.

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[3] These transparent plastic packages are extremely sensitive to reﬂow soldering conditions and must

on no account be processed through more than one soldering cycle or subjected to infrared reﬂow

soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reﬂow

oven. The package body peak temperature must be kept as low as possible.

[4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom

side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with

the heatsink on the top side, the solder might be deposited on the heatsink surface.

[5] If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave

direction. The package footprint must incorporate solder thieves downstream and at the side corners.

[6] Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it

is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

[7] Wave soldering is suitable for SSOP, TSSOP, VSO and VSOP packages with a pitch (e) equal to or

larger than 0.65 mm; it is deﬁnitely not suitable for packages with a pitch (e) equal to or smaller than

0.5 mm.

[8] Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered

pre-mounted on ﬂex foil. However, the image sensor package can be mounted by the client on a ﬂex

foil by using a hot bar soldering process. The appropriate soldering proﬁle can be provided on

request.

[9] Hot bar soldering or manual soldering is suitable for PMFP packages.

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19. Revision history

Table 82: Revision history

Rev Date

CPCN

Description

06 20041223 200412021 Product data (9397 750 13462)

Modiﬁcations:

• Changed: “interface device” to “peripheral controller”, where applicable

• Section 2 “Features”: updated the ﬁrst feature list item

• Table 2 “Pin description for LQFP64”: updated description for pins 11, 12, 13, 14 and 15

• Added Section 7.9 “Power-on reset”

• Table 4 “Register overview”: removed loop back

• Table 34 “DMA Conﬁguration register: bit description”: added table note 1

• Section 9.5.4 “Scratch register (address: 78H)”: updated

• Table 71 “Static characteristics: analog I/O pins (D+, D−)^[1]”: changed the value of C_IN

from 20 pF to 10 pF

• Removed old Section 14.1 on timing symbols.

Product data (9397 750 10766)

05 20030226

04 20020718

03 20020218

02 20001023

01 20001004

-

Product data (9397 750 09665)

Preliminary data (9397 750 09233)

Objective speciﬁcation (9397 750 07648)

Objective speciﬁcation (9397 750 07487)

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20. Data sheet status

Level Data sheet status^[1]

Product status^[2][3]

Deﬁnition

I

Objective data

Development

This data sheet contains data from the objective speciﬁcation for product development. Philips

Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

II

Preliminary data

Qualiﬁcation

This data sheet contains data from the preliminary speciﬁcation. Supplementary data will be published

at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in

order to improve the design and supply the best possible product.

III

Product data

Production

This data sheet contains data from the product speciﬁcation. Philips Semiconductors reserves the

right to make changes at any time in order to improve the design, manufacturing and supply. Relevant

changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

[1]

[2]

Please consult the most recently issued data sheet before initiating or completing a design.

The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.

[3]

For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

customers using or selling these products for use in such applications do so

at their own risk and agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

21. Deﬁnitions

Short-form speciﬁcation — The data in a short-form speciﬁcation is

extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.

Right to make changes — Philips Semiconductors reserves the right to

make changes in the products - including circuits, standard cells, and/or

software - described or contained herein in order to improve design and/or

performance. When the product is in full production (status ‘Production’),

relevant changes will be communicated via a Customer Product/Process

Change Notiﬁcation (CPCN). Philips Semiconductors assumes no

responsibility or liability for the use of any of these products, conveys no

licence or title under any patent, copyright, or mask work right to these

products, and makes no representations or warranties that these products are

free from patent, copyright, or mask work right infringement, unless otherwise

speciﬁed.

Limiting values deﬁnition — Limiting values given are in accordance with

the Absolute Maximum Rating System (IEC 60134). Stress above one or

more of the limiting values may cause permanent damage to the device.

These are stress ratings only and operation of the device at these or at any

other conditions above those given in the Characteristics sections of the

speciﬁcation is not implied. Exposure to limiting values for extended periods

may affect device reliability.

Application information — Applications that are described herein for any

of these products are for illustrative purposes only. Philips Semiconductors

make no representation or warranty that such applications will be suitable for

the speciﬁed use without further testing or modiﬁcation.

23. Trademarks

ACPI — is an open industry speciﬁcation for PC power management,

co-developed by Intel Corp., Microsoft Corp. and Toshiba

Jaz — is a registered trademark of Iomega Corp.

22. Disclaimers

OnNow — is a trademark of Microsoft Corp.

SoftConnect — is a trademark of Royal Philips Electronics

Zip — is a registered trademark of Iomega Corp.

Life support — These products are not designed for use in life support

appliances, devices, or systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips Semiconductors

Contact information

For additional information, please visit http://www.semiconductors.philips.com.

For sales ofﬁce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.

Fax: +31 40 27 24825

78 of 79

9397 750 13462

Product data

Rev. 06 — 23 December 2004

ISP1581

Hi-Speed USB peripheral controller

Philips Semiconductors

Contents

1

2

3

4

5

General description . . . . . . . . . . . . . . . . . . . . . . 1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 2

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

9.4.6

9.4.7

9.4.8

9.4.9

9.5

9.5.1

9.5.2

9.5.3

9.5.4

9.5.5

Task File registers (addresses: 40H to 4FH) . 37

DMA Interrupt Reason register (address: 50H) 40

DMA Interrupt Enable register (address: 54H) 41

DMA Endpoint register (address: 58H) . . . . . 42

General registers . . . . . . . . . . . . . . . . . . . . . . 42

Interrupt register (address: 18H) . . . . . . . . . . 42

Chip ID register (address: 70H) . . . . . . . . . . . 44

Frame Number register (address: 74H) . . . . . 45

Scratch register (address: 78H) . . . . . . . . . . . 45

Test Mode register (address: 84H). . . . . . . . . 46

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7

7.1

7.2

7.3

7.3.1

7.3.2

7.3.3

7.4

Functional description . . . . . . . . . . . . . . . . . . 11

Hi-Speed USB transceiver . . . . . . . . . . . . . . . 12

Philips Serial Interface Engine (SIE). . . . . . . . 12

Philips HS (High-Speed) Transceiver . . . . . . . 12

Philips Parallel Interface Engine . . . . . . . . . . . 12

Peripheral circuit . . . . . . . . . . . . . . . . . . . . . . . 12

HS detection . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Voltage regulators. . . . . . . . . . . . . . . . . . . . . . 13

Memory Management Unit (MMU) and

integrated RAM . . . . . . . . . . . . . . . . . . . . . . . 13

SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Microcontroller/Processor Interface

and Microcontroller/Processor Handler . . . . . 13

DMA Interface and DMA Handler . . . . . . . . . . 14

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 14

10

11

12

13

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 48

Recommended operating conditions . . . . . . 48

Static characteristics . . . . . . . . . . . . . . . . . . . 48

14

14.1

Dynamic characteristics. . . . . . . . . . . . . . . . . 50

Register access timing . . . . . . . . . . . . . . . . . 53

Generic Processor mode (BUS_CONF = 1) . 53

Split Bus mode (BUS_CONF = 0) . . . . . . . . . 55

DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

PIO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

GDMA slave mode . . . . . . . . . . . . . . . . . . . . . 61

MDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . 65

UDMA mode. . . . . . . . . . . . . . . . . . . . . . . . . . 66

14.1.1

14.1.2

14.2

14.2.1

14.2.2

14.2.3

14.2.4

7.5

7.6

7.7

7.8

7.9

15

Application information . . . . . . . . . . . . . . . . . 71

Test information. . . . . . . . . . . . . . . . . . . . . . . . 72

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 73

8

Modes of operation . . . . . . . . . . . . . . . . . . . . . 16

16

9

9.1

9.2

Register descriptions . . . . . . . . . . . . . . . . . . . 16

Register access . . . . . . . . . . . . . . . . . . . . . . . 18

Initialization registers . . . . . . . . . . . . . . . . . . . 18

Address register (address: 00H). . . . . . . . . . . 18

Mode register (address: 0CH) . . . . . . . . . . . . 19

Interrupt Conﬁguration register (address: 10H) 19

Interrupt Enable register (address: 14H) . . . . 20

DMA Conﬁguration register (address: 38H) . . 22

DMA Hardware register (address: 3CH). . . . . 22

Data ﬂow registers . . . . . . . . . . . . . . . . . . . . . 22

Endpoint Index register (address: 2CH) . . . . . 22

Control Function register (address: 28H) . . . . 23

Data Port register (address: 20H). . . . . . . . . . 24

Buffer Length register (address: 1CH) . . . . . . 25

Endpoint MaxPacketSize register (address:

17

18

18.1

Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Introduction to soldering surface mount

packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 74

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 74

Manual soldering . . . . . . . . . . . . . . . . . . . . . . 75

Package related soldering information. . . . . . 75

9.2.1

9.2.2

9.2.3

9.2.4

9.2.5

9.2.6

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

18.2

18.3

18.4

18.5

19

20

21

22

23

Revision history . . . . . . . . . . . . . . . . . . . . . . . 77

Data sheet status. . . . . . . . . . . . . . . . . . . . . . . 78

Deﬁnitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

04H). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Endpoint Type register (address: 08H) . . . . . . 27

Short Packet register (address: 24H) . . . . . . . 27

DMA registers. . . . . . . . . . . . . . . . . . . . . . . . . 28

DMA Command register (address: 30H) . . . . 30

DMA Transfer Counter register (address: 34H) 32

DMA Conﬁguration register (address: 38H) . . 33

DMA Hardware register (address: 3CH). . . . . 35

DMA Strobe Timing register (address: 60H). . 36

9.3.6

9.3.7

9.4

9.4.1

9.4.2

9.4.3

9.4.4

9.4.5

Printed in The Netherlands

All rights are reserved. Reproduction in whole or in part is prohibited without the prior

written consent of the copyright owner.

The information presented in this document does not form part of any quotation or

contract, is believed to be accurate and reliable and may be changed without notice. No

liability will be accepted by the publisher for any consequence of its use. Publication

thereof does not convey nor imply any license under patent- or other industrial or

intellectual property rights.

Date of release: 23 December 2004

Document order number: 9397 750 13462


型号：	ISP1581BD,557
厂家：	NXP
描述：	IC UNIVERSAL SERIAL BUS CONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64, Bus Controller 时钟数据传输外围集成电路
文件：	总80页 (文件大小：389K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1581BD,557 [NXP]

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