ISP1583BS,551_技术文档

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ISP1583

Hi-Speed USB peripheral controller

Rev. 07 — 22 September 2008

Product data sheet

1. General description

The ISP1583 is a cost-optimized and feature-optimized Hi-Speed Universal Serial Bus

(USB) peripheral controller. It fully complies with Ref. 1 “Universal Serial Bus Speciﬁcation

Rev. 2.0”, supporting data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s).

The ISP1583 provides high-speed USB communication capacity to systems based on

microcontrollers or microprocessors. It communicates with a microcontroller or

microprocessor of a system through a high-speed general-purpose parallel interface.

The ISP1583 supports automatic detection of Hi-Speed USB system operation. Original

USB fall-back mode allows the device to remain operational under full-speed conditions. It

is designed as a generic USB peripheral controller so that it can ﬁt into all existing device

classes, such as imaging class, mass storage devices, communication devices, printing

devices and human interface devices.

The ISP1583 is a low-voltage device, which supports I/O pad voltages from 1.65 V to

3.6 V.

The internal generic Direct Memory Access (DMA) block allows easy integration into data

streaming applications. In addition, the various conﬁgurations of the DMA block are

tailored for mass storage applications.

The modular approach to implementing a USB peripheral controller allows the designer to

select the optimum system microcontroller from the wide variety available. The ability to

reuse existing architecture and ﬁrmware shortens the development time, eliminates risk

and reduces cost. The result is fast and efﬁcient development of the most cost-effective

USB peripheral solution.

The ISP1583 also incorporates features such as SoftConnect, a reduced frequency

crystal oscillator and integrated termination resistors. These features allow signiﬁcant cost

savings in system design and easy implementation of advanced USB functionality into PC

peripherals.

2. Features

I Complies fully with:

N Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0”

N Most device class speciﬁcations

N ACPI, OnNow and USB power management requirements

I Supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s)

I Direct interface to ATA/ATAPI peripherals; applicable only in split bus mode

I High performance USB peripheral controller with integrated Serial Interface Engine

(SIE), Parallel Interface Engine (PIE), FIFO memory and data transceiver

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

I Automatic Hi-Speed USB mode detection and Original USB fall-back mode

I Supports sharing mode

I Supports I/O voltage range of 1.65 V to 3.6 V

I Supports V_BUSsensing

I High-speed DMA interface

I Conﬁgurable direct access data path from the microprocessor to an ATA device

I Fully autonomous and multiconﬁguration DMA operation

I Seven IN endpoints, seven OUT endpoints, and a ﬁxed control IN and OUT endpoint

I Integrated physical 8 kB of multiconﬁguration FIFO memory

I Endpoints with double buffering to increase throughput and ease real-time data

transfer

I Bus-independent interface with most microcontrollers and microprocessors

I 12 MHz crystal oscillator with integrated PLL for low EMI

I Software-controlled connection to the USB bus (SoftConnect)

I Low-power consumption in operation and power-down modes; suitable for use in

bus-powered USB devices

I Supports Session Request Protocol (SRP) that adheres to Ref. 2 “On-The-Go

Supplement to the USB Speciﬁcation Rev. 1.3”

I Internal power-on and low-voltage reset circuits; also supports software reset

I Operation over the extended USB bus voltage range (DP, DM and V_BUS

)

I 5 V tolerant I/O pads

I Operating temperature range from −40 °C to +85 °C

I Available in HVQFN64 and TFBGA64 halogen-free and lead-free packages

3. Applications

I Personal digital assistant

I Mass storage device, for example: CD, DVD, Magneto-Optical (MO) and Zip drives

I Digital video camera

I Digital still camera

I 3G mobile phone

I MP3 player

I Communication device, for example: router and modem

I Printer

I Scanner

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

2 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

4. Ordering information

Table 1.

Ordering information

Type number Package

Name

Description

Version

ISP1583BS

HVQFN64 plastic thermal enhanced very thin quad ﬂat package; no leads; 64 terminals; SOT804-1

body 9 × 9 × 0.85 mm

ISP1583ET

TFBGA64 plastic thin ﬁne-pitch ball grid array package; 64 balls; body 6 × 6 × 0.8 mm

SOT543-1

SOT969-1

SOT543-1

ISP1583ET1^[1]TFBGA64 plastic thin ﬁne-pitch ball grid array package; 64 balls; body 4 × 4 × 0.8 mm

ISP1583ET2^[1]TFBGA64 plastic thin ﬁne-pitch ball grid array package; 64 balls; body 6 × 6 × 0.8 mm

[1] Contains solder ball material SAC105.

5. Marking

Table 2.

Marking codes

Type number

ISP1583BS

ISP1583ET

ISP1583ET1

ISP1583ET2

Marking code^[1]

ISP1583BS

ISP1583

1583

1583ET2

[1] The package marking is the ﬁrst line of text on the IC package and can be used for IC identiﬁcation.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

3 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

7. Pinning information

7.1 Pinning

terminal 1

index area

DATA10

DATA9

DATA8

DATA7

DATA6

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AGND

RPU

DP

3

4

DM

5

AGND

RREF

6

DATA5

DATA4

7

RESET_N

EOT

V

8

CC(I/O)

ISP1583BS

DATA3

DATA2

9

DREQ

DACK

DIOR

10

11

12

13

14

15

16

DATA1

DIOW

DGND

DATA0

ALE/A0

DGND

INTRQ

READY/IORDY

INT

MODE1

n.c.

004aaa537

Transparent top view

Fig 2. Pin conﬁguration ISP1583BS (top view)

ball A1

index area

1 2 3 4 5 6 7 8 9 10

A

B

C

D

E

F

ISP1583ET;

ISP1583ET2

G

H

J

K

004aaa859

Transparent top view

Fig 3. Pin conﬁguration ISP1583ET and ISP1583ET2 (top view)

Rev. 07 — 22 September 2008

ISP1583_7

Product data sheet

5 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

ISP1583ET1

ball A1

index area

1

2 3 4 5 6 7 8

A

B

C

D

E

F

G

H

004aaa991

Transparent top view

Fig 4. Pin conﬁguration ISP1583ET1 (top view)

7.2 Pin description

Table 3.

Pin description

Symbol^[1]Pin

Type^[2]Description

ISP1583BS ISP1583ET; ISP1583ET1

ISP1583ET2

AGND

RPU

1

2

D2

A1

D2

A1

-

analog ground

A

pull-up resistor connection; this pin must be connected to

3.3 V through an external 1.5 kΩ resistor to pull up pin DP

DP

3

4

5

6

B1

C1

-

B1

C1

-

A

-

USB D+ line connection (analog)

USB D− line connection (analog)

analog ground

DM

AGND

RREF

D1

A

external bias resistor connection; this pin must be

connected to ground through a 12.0 kΩ ± 1 % resistor

RESET_N

7

E2

C3

I

reset input (500 µs); a LOW level produces an

asynchronous reset; connect to V_CC(3V3)for power-on

reset (internal POR circuit)

When the RESET_N pin is LOW, ensure that the WAKEUP

pin does not go from LOW to HIGH; otherwise the device

will enter test mode.

TTL; 5 V tolerant

EOT

8

9

E1

F2

D3

E1

I

end-of-transfer input (programmable polarity); used in

DMA slave mode only; when not in use, connect this pin to

V_CC(I/O)through a 10 kΩ resistor

input pad; TTL; 5 V tolerant

DREQ

I/O

DMA request input or output (programmable polarity); the

signal direction depends on bit MASTER in register DMA

Hardware (see Table 59):

• Input: DMA master mode if bit MASTER = 1

• Output: DMA slave mode if bit MASTER = 0

When not in use, in the default setting, this pin must be

connected to ground through a 10 kΩ resistor.

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

6 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 3.

Pin description …continued

Symbol^[1]Pin

Type^[2]Description

ISP1583BS ISP1583ET; ISP1583ET1

ISP1583ET2

DACK

DIOR

DIOW

10

11

12

F1

E2

E3

F1

I/O

DMA acknowledge input or output (programmable

polarity); the signal direction depends on bit MASTER in

register DMA Hardware (see Table 59):

• Input: DMA slave mode if bit MASTER = 0

• Output: DMA master mode if bit MASTER = 1

When not in use, in the default setting, this pin must be

connected to V_CC(I/O)through a 10 kΩ resistor.

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

G2

DMA read strobe input or output (programmable polarity);

the signal direction depends on bit MASTER in register

DMA Hardware (see Table 59):

• Input: DMA slave mode if bit MASTER = 0

• Output: DMA master mode if bit MASTER = 1

When not in use, in the default setting, this pin must be

connected to V_CC(I/O)through a 10 kΩ resistor.

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

G1

DMA write strobe input or output (programmable polarity);

the signal direction depends on bit MASTER in register

DMA Hardware (see Table 59):

• Input: DMA slave mode if bit MASTER = 0

• Output: DMA master mode if bit MASTER = 1

When not in use, in the default setting, this pin must be

connected to V_CC(I/O)through a 10 kΩ resistor.

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

digital ground

DGND

INTRQ

13

14

H2

H1

F2

-

I

G2

interrupt request input; from the ATA/ATAPI peripheral; use

a 10 kΩ resistor to pull down

input pad; TTL; 5 V tolerant

READY/

IORDY

15

J1

G1

I/O

Signal ready output — Used in generic processor mode:

• LOW: the ISP1583 is processing a previous command

or data and is not ready for the next command or data

transfer

• HIGH: the ISP1583 is ready for the next

microprocessor read or write

I/O ready input — Used in split bus mode to access

ATA/ATAPI peripherals (PIO mode only)

bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant

INT

16

17

18

K1

J2

H1

H2

E4

O

I

interrupt output; programmable polarity (active HIGH or

LOW) and signaling (edge or level triggered)

CMOS output; 8 mA drive

DA2^[3]

address output to select the Task File register of an

ATA/ATAPI device; see Table 61

CMOS output; 8 mA drive

chip selection input

CS_N

K2

input pad; TTL; 5 V tolerant

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

7 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 3.

Pin description …continued

Symbol^[1]Pin

Type^[2]Description

ISP1583BS ISP1583ET; ISP1583ET1

ISP1583ET2

RW_N/

RD_N

19

J3

F3

I

Read or write input — For the Freescale mode, this

function is determined by pin MODE0 = LOW during

power-up.

Read input — For the 8051 mode, this function is

determined by pin MODE0 = HIGH during power-up.

input pad; TTL; 5 V tolerant

DS_N/

WR_N

20

K3

H3

I

Data selection input — For the Freescale mode, this

function is determined by pin MODE0 = LOW at power-up.

Write input — For the 8051 mode, this function is

determined by pin MODE0 = HIGH at power-up.

input pad; TTL; 5 V tolerant

CS0_N^[3]

CS1_N^[3]

21

22

J4

G3

F4

O

chip selection output 0 for the ATA/ATAPI device; see

Table 61

CMOS output; 8 mA drive

K4

chip selection output 1 for the ATA/ATAPI device; see

Table 61

CMOS output; 8 mA drive

AD0

AD1

AD2

23

24

25

K5

J5

G4

H4

F5

I/O

bit 0 of the multiplexed address and data

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 1 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 2 of the multiplexed address and data bus

K6

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16

bit 3 of the multiplexed address and data bus

[4]

V_CC(I/O)

26

27

J6

E5

H5

-

AD3

AD4

AD5

AD6

AD7

K7

I/O

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 4 of the multiplexed address and data bus

28

29

30

31

J7

G5

G6

H6

H7

H8

I/O

-

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 5 of the multiplexed address and data bus

K8

J8

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 6 of the multiplexed address and data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 7 of the multiplexed address and data bus

K9

K10

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

VCC1V8^[4]32

voltage regulator output (1.8 V ± 0.15 V); tapped out

voltage from the internal regulator; this regulated voltage

cannot drive external devices; decouple this pin using a

0.1 µF capacitor; see Section 8.16

n.c.

33

-

not connected

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

8 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 3.

Pin description …continued

Symbol^[1]Pin

Type^[2]Description

ISP1583BS ISP1583ET; ISP1583ET1

ISP1583ET2

MODE1

34

J10

G8

I

mode selection input 1; used in split bus mode only:

• LOW: ALE function (address latch enable)

• HIGH (connect to V_CC(I/O)): A0 function (address/data

indicator)

Remark: When operating in generic processor mode, set

pin MODE1 as HIGH.

input pad; TTL; 5 V tolerant

digital ground

DGND

35

36

H9

F8

F7

-

I

ALE/A0

H10

Address latch enable input — When pin MODE1 = LOW

during power-up, a falling edge on this pin latches the

address on the multiplexed address and data bus AD[7:0].

Address and data selection input — When pin

MODE1 = HIGH during power-up, the function is

determined by the level on this pin (detected on the rising

edge of the WR_N pulse):

•

HIGH: bus AD[7:0] is a register address

LOW: bus AD[7:0] is register data; used in split bus

mode only

Remark: When operating in generic processor mode with

pin MODE1 = HIGH, this pin must be pulled down using a

10 kΩ resistor.

input pad; TTL; 5 V tolerant

DATA0

DATA1

DATA2

DATA3

37

38

39

40

G9

F6

E6

E7

E8

I/O

bit 0 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 1 of the bidirectional data bus

G10

F9

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 2 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 3 of the bidirectional data bus

F10

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16

bit 4 of the bidirectional data bus

[4]

V_CC(I/O)

DATA4

41

42

E9

D7

D6

-

E10

I/O

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 5 of the bidirectional data bus

DATA5

DATA6

DATA7

DATA8

DATA9

43

44

45

46

47

D10

D9

D8

D5

D4

C8

C7

I/O

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 6 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 7 of the bidirectional data bus

C10

C9

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 8 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 9 of the bidirectional data bus

B10

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

9 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 3.

Pin description …continued

Symbol^[1]Pin

Type^[2]Description

ISP1583BS ISP1583ET; ISP1583ET1

ISP1583ET2

DATA10

DATA11

DATA12

DATA13

DATA14

DATA15

48

49

50

51

52

53

A10

A8

C4

B7

A7

C6

C5

I/O

bit 10 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 11 of the bidirectional data bus

A9

B8

A8

B7

A7

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 12 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 13 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 14 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

bit 15 of the bidirectional data bus

bidirectional pad; 4 ns slew-rate control; TTL; 5 V tolerant

I/O pad supply voltage (1.65 V to 3.6 V); see Section 8.16

[4]

V_CC(I/O)

V_BUS

54

55

B6

B5

B6

A6

-

A

USB bus power sensing input — Used to detect

whether the host is connected or not; connect a 1 µF

electrolytic or tantalum capacitor and a 1 MΩ pull-down

resistor to ground; see Section 8.14

V_BUSpulsing output — In OTG mode; connect a 1 µF

electrolytic or tantalum capacitor and a 1 MΩ pull-down

resistor to ground; see Section 8.14

5 V tolerant

VCC1V8^[4]56

A6

B5

-

voltage regulator output (1.8 V ± 0.15 V); tapped out

voltage from the internal regulator; this regulated voltage

cannot drive external devices; decouple this pin using

4.7 µF and 0.1 µF capacitors; see Section 8.16

XTAL2

XTAL1

DGND

57

58

A5

A4

A5

A4

O

I

crystal oscillator output (12 MHz); connect a fundamental

parallel-resonant crystal; leave this pin open when using

an external clock source on pin XTAL1; see Table 100

crystal oscillator input (12 MHz); connect a fundamental

parallel-resonant crystal or an external clock source

(leaving pin XTAL2 unconnected); see Table 100

59

60

B4

A3

B4

C2

-

digital ground

MODE0/

DA1^[3]

I/O

Mode selection input 0 — Selects the read/write strobe

functionality in generic processor mode during power-up:

• LOW: for the Freescale mode; the function of pin 19 is

RW_N and pin 20 is DS_N

• HIGH (connect to V_CC(I/O)): for the 8051 mode; the

function of pin 19 is RD_N and pin 20 is WR_N

Address selection output — Selects the Task File

register of an ATA/ATAPI device during normal operation;

see Table 61

bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant

[4]

V_CC(3V3)

61

B3

-

regulator supply voltage (3.3 V ± 0.3 V); this pin supplies

the internal regulator; see Section 8.16

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

10 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 3.

Pin description …continued

Symbol^[1]Pin

Type^[2]Description

ISP1583BS ISP1583ET; ISP1583ET1

ISP1583ET2

BUS_

CONF/

DA0^[3]

62

B2

A3

I/O

Bus conﬁguration input — Selects bus mode during

power-up:

• LOW: split bus mode; multiplexed 8-bit address and

data bus on AD[7:0], separate DMA data bus

DATA[15:0]^[5]

• HIGH (connect to V_CC(I/O)): generic processor mode;

separate 8-bit address on AD[7:0], 16-bit processor

data bus on DATA[15:0]; DMA is multiplexed on

processor bus DATA[15:0]

Address selection output — Selects the Task File

register of an ATA/ATAPI device at normal operation; see

Table 61

bidirectional pad; 10 ns slew-rate control; TTL; 5 V tolerant

WAKEUP 63

A2

B2

I

wake-up input; when this pin is at the HIGH level, the chip

is prevented from going into the suspend state and

wake-up the chip when already in suspend mode; when

not in use, connect this pin to ground through a 10 kΩ

resistor

When the RESET_N pin is LOW, ensure that the WAKEUP

pin does not go from LOW to HIGH; otherwise the device

will enter test mode.

input pad; TTL; 5 V tolerant

SUSPEND 64

C2

B9

A2

O

suspend state indicator output; used as a power switch

control output to power-off or power-on external devices

when going into suspend mode or recovering from

suspend mode

CMOS output; 8 mA drive

digital ground

DGND

-

exposed die J9

pad

B8, G7

ground supply; down bonded to the exposed die pad (heat

sink); to be connected to DGND during the PCB layout

[1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals.

[2] All outputs and I/O pins can source 4 mA, unless otherwise speciﬁed.

[3] Control signals are not 3-stated.

[4] Add a decoupling capacitor (0.1 µF) to all the supply pins. For better EMI results, add a 0.01 µF capacitor in parallel to 0.1 µF.

[5] The DMA bus is in 3-state until a DMA command (see Section 9.4.1) is executed.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

11 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

8. Functional description

The ISP1583 is a high-speed USB peripheral controller. It implements the Hi-Speed USB

or the Original USB physical layer, and the packet protocol layer. It concurrently maintains

up to 16 USB endpoints (control IN, control OUT, and seven IN and seven OUT

conﬁgurable) along with endpoint EP0 set up, which accesses the set-up buffer. The Ref.

1 “Universal Serial Bus Speciﬁcation Rev. 2.0”, Chapter 9 protocol handling is executed

using the external ﬁrmware.

The ISP1583 has a fast general-purpose interface to communicate with most types of

microcontrollers and microprocessors. This microcontroller interface is conﬁgured using

pins BUS_CONF/DA0, MODE1 and MODE0/DA1 to accommodate most interface types.

Two bus conﬁgurations are available, selected using input BUS_CONF/DA0 during

power-up:

• Generic processor mode (pin BUS_CONF/DA0 = HIGH):

– AD[7:0]: 8-bit address bus (selects target register)

– DATA[15:0]: 16-bit data bus (shared by processor and DMA)

– Control signals: RW_N and DS_N or RD_N and WR_N (selected using pin

MODE0/DA1), CS_N

– DMA interface (generic slave mode only): Uses lines DATA[15:0] as data bus,

DIOR and DIOW as dedicated read and write strobes

• Split bus mode (pin BUS_CONF/DA0 = LOW):

– AD[7:0]: 8-bit local microprocessor bus (multiplexed address and data)

– DATA[15:0]: 16-bit DMA data bus

– Control signals: CS_N, ALE or A0 (selected using pin MODE1), RW_N and DS_N

or RD_N and WR_N (selected using pin MODE0/DA1)

– DMA interface (master or slave mode): Uses DIOR and DIOW as dedicated read

and write strobes

For high-bandwidth data transfer, the integrated DMA handler can be invoked to transfer

data to or from external memory or devices. The DMA interface can be conﬁgured by

writing to proper DMA registers (see Section 9.4).

The ISP1583 supports Hi-Speed USB and Original USB signaling. The USB signaling

speed is automatically detected.

The ISP1583 has 8 kB of internal FIFO memory, which is shared among enabled USB

endpoints, including control IN and control OUT endpoints, and set-up token buffer.

There are seven IN and seven OUT conﬁgurable endpoints, and two ﬁxed control

endpoints that are 64 bytes long. Any of the seven IN and seven OUT endpoints can be

separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and

packet size of these endpoints can be individually conﬁgured, depending on the

requirements of the application. Optional double buffering increases the data throughput

of these data endpoints.

The ISP1583 requires 3.3 V power supply. It has 5 V tolerant I/O pads and an internal

1.8 V regulator to power the digital logic. The I/O voltage can range from 1.65 V to 3.6 V.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

12 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 4.

Endpoint access and programmability

Endpoint

identiﬁer

Maximum packet

size

Double buffering Endpoint type

Direction

EP0SETUP

EP0RX

EP0TX

EP1RX

EP1TX

EP2RX

EP2TX

EP3RX

EP3TX

EP4RX

EP4TX

EP5RX

EP5TX

EP6RX

EP6TX

EP7RX

EP7TX

8 bytes (ﬁxed)

64 bytes (ﬁxed)

programmable

no

set-up token

OUT

IN

no

control OUT

no

control IN

yes

programmable

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

The ISP1583 operates on a 12 MHz crystal oscillator. An integrated 40 × PLL clock

multiplier generates the internal sampling clock of 480 MHz.

8.1 DMA interface, DMA handler and DMA registers

The DMA block can be subdivided into two blocks: DMA handler and DMA interface.

The ﬁrmware writes to the DMA Command register to start a DMA transfer (see Table 51).

The command opcode determines whether a generic DMA, Parallel I/O (PIO) or

Multi-word DMA (MDMA) transfer will start. The handler interfaces to the same FIFO

(internal RAM) as used by the USB core. On receiving the DMA command, the DMA

handler directs the data from the endpoint FIFO to the external DMA device or from the

external DMA device to the endpoint FIFO.

The DMA interface conﬁgures the timing and the DMA handshake. Data can be

transferred using either the DIOR and DIOW strobes or the DACK and DREQ

handshakes. DMA conﬁgurations are set up by writing to the DMA Conﬁguration register

(see Table 56 and Table 57).

For an IDE-based storage interface, applicable DMA modes are PIO and MDMA

(Multi-word DMA; ATA).

For a generic DMA interface, DMA modes that can be used are Generic DMA (GDMA)

slave.

Remark: The DMA endpoint buffer length must be a multiple of 4 bytes.

For details on DMA registers, see Section 9.4.

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ISP1583

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Hi-Speed USB peripheral controller

8.2 Hi-Speed USB transceiver

The analog transceiver directly interfaces to the USB cable through integrated termination

resistors. The high-speed transceiver requires an external resistor (12.0 kΩ ± 1 %)

between pin RREF and ground to ensure an accurate current mirror that generates the

Hi-Speed USB current drive. A full-speed transceiver is integrated as well. This makes the

ISP1583 compliant to Hi-Speed USB and Original USB, supporting both the high-speed

and full-speed physical layers. After automatic speed detection, the NXP Serial Interface

Engine (SIE) sets the transceiver to use either high-speed or full-speed signaling.

8.3 MMU and integrated RAM

The Memory Management Unit (MMU) manages the access to the integrated RAM that is

shared by the USB, microcontroller handler and DMA handler. Data from the USB bus is

stored in the integrated RAM, which is cleared only when the microcontroller has read the

corresponding endpoint, or the DMA controller has written all data from the RAM of the

corresponding endpoint to the DMA bus. The OUT endpoint buffer can also be forcibly

cleared by setting bit CLBUF in the Control Function register. A total of 8 kB RAM is

available for buffering.

8.4 Microcontroller interface and microcontroller handler

The microcontroller interface allows direct interfacing to most microcontrollers and

microprocessors. The interface is conﬁgured at power-up through pins BUS_CONF/DA0,

MODE1 and MODE0/DA1.

When pin BUS_CONF/DA0 = HIGH, the microcontroller interface switches to generic

processor mode in which AD[7:0] is the 8-bit address bus and DATA[15:0] is the separate

16-bit data bus. If pin BUS_CONF/DA0 = LOW, the interface is in split bus mode, where

AD[7:0] is the local microprocessor bus (multiplexed address and data) and DATA[15:0] is

solely used as the DMA bus.

When pin MODE0/DA1 = HIGH, pins RW_N/RD_N and DS_N/WR_N are the read and

write strobes (8051 mode). If pin MODE0/DA1 = LOW, pins RW_N/RD_N and

DS_N/WR_N represent the direction and data strobes (Freescale mode).

When pin MODE1 = LOW, pin ALE/A0 is used to latch the multiplexed address on pins

AD[7:0]. When pin MODE1 = HIGH, pin ALE/A0 is used to indicate address or data. Pin

MODE1 is only used in split bus mode; in generic processor mode, it must be tied to

V_CC(I/O)

.

The microcontroller handler allows the external microcontroller to access the register set

in the NXP SIE, as well as the DMA handler. The initialization of the DMA conﬁguration is

done through the microcontroller handler.

8.5 OTG SRP module

The OTG supplement deﬁnes a Session Request Protocol (SRP), which allows a B-device

to request the A-device to turn on V_BUSand start a session. This protocol allows the

A-device, which may be battery-powered, to conserve power by turning off V_BUSwhen

there is no bus activity while still providing a means for the B-device to initiate bus activity.

Any A-device, including a PC or laptop, can respond to SRP. Any B-device, including a

standard USB peripheral, can initiate SRP.

ISP1583_7

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ISP1583

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Hi-Speed USB peripheral controller

The ISP1583 is a device that can initiate SRP.

8.6 NXP high-speed transceiver

8.6.1 NXP Parallel Interface Engine (PIE)

In the High-Speed (HS) transceiver, the NXP PIE interface uses a 16-bit parallel

bidirectional data interface. The functions of the HS module also include bit-stufﬁng or

de-stufﬁng and Non-Return-to-Zero Inverted (NRZI) encoding or decoding logic.

8.6.2 Peripheral circuit

To maintain a constant current driver for HS transmit circuits and to bias other analog

circuits, an internal band gap reference circuit and an RREF resistor form the reference

current. This circuit requires an external precision resistor (12.0 kΩ ± 1 %) connected to

the analog ground.

8.6.3 HS detection

The ISP1583 handles more than one electrical state, Full-Speed (FS) or High-Speed

(HS), under the USB speciﬁcation. When the USB cable is connected from the peripheral

to the host controller, the ISP1583 defaults to the FS state, until it sees a bus reset from

the host controller.

During the bus reset, the peripheral initiates an HS chirp to detect whether the host

controller supports Hi-Speed USB or Original USB. If the HS handshake shows that there

is an HS host connected, then the ISP1583 switches to the HS state.

In the HS state, the ISP1583 must observe the bus for periodic activity. If the bus remains

inactive for 3 ms, the peripheral switches to the FS state to check for a Single-Ended Zero

(SE0) condition on the USB bus. If an SE0 condition is detected for the designated time

(100 µs to 875 µs; refer to Ref. 1 “Universal Serial Bus Speciﬁcation Rev. 2.0”,

Section 7.1.7.6), the ISP1583 switches to the HS chirp state to perform an HS detection

handshake. Otherwise, the ISP1583 remains in the FS state, adhering to the bus-suspend

speciﬁcation.

8.6.4 Isolation

Ensure that the DP and DM lines are maintained in a clean state, without any residual

voltage or glitches. Once the ISP1583 is reset and the clock is available, ensure that there

are no erroneous pulses or glitches even of very small amplitude on the DP and DM lines.

Remark: If there are any erroneous unwanted pulses or glitches detected by the ISP1583

DP and DM lines, there is a possibility of the ISP1583 clocking this state into the internal

core, causing unknown behaviors.

8.7 NXP Serial Interface Engine (SIE)

The NXP SIE implements the full USB protocol layer. It is completely hardwired for speed

and needs no ﬁrmware intervention. The functions of this block include: synchronization

pattern recognition, parallel or serial conversion, bit-stufﬁng or de-stufﬁng, CRC checking

or generation, Packet IDentiﬁer (PID) veriﬁcation or generation, address recognition,

handshake evaluation or generation.

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ISP1583

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Hi-Speed USB peripheral controller

8.8 SoftConnect

The USB connection is established by pulling pin DP (for full-speed devices) to HIGH

through a 1.5 kΩ pull-up resistor. In the ISP1583, an external 1.5 kΩ pull-up resistor must

be connected between pin RPU and 3.3 V. The RPU pin connects the pull-up resistor to

pin DP, when bit SOFTCT in the Mode register is set (see Table 24 and Table 25). After a

hardware reset, the pull-up resistor is disconnected by default (bit SOFTCT = 0). The USB

bus reset does not change the value of bit SOFTCT.

When V_BUSis not present, the SOFTCT bit must be set to logic 0 to comply with the

back-drive voltage.

8.9 Reconﬁguring endpoints

The ISP1583 endpoints have a limitation when implementing a composite device with at

least two functionalities that require the support of alternate settings, for example, the

video class and audio class devices. The ISP1583 endpoints cannot be reconﬁgured on

the ﬂy because it is implemented as a FIFO base. The internal RAM partition will be

corrupted if there is a need to reconﬁgure endpoints on the ﬂy because of alternate

settings request, causing data corruption.

For details and work-around, refer to Ref. 3 “Using ISP1582/3 in a composite device

application with alternate settings (AN10071)”.

8.10 System controller

The system controller implements the USB power-down capabilities of the ISP1583.

Registers are protected against data corruption during wake-up following a resume (from

the suspend state) by locking the write access, until an unlock code is written to the

Unlock Device register (see Table 90 and Table 91).

8.11 Modes of operation

The ISP1583 has two bus conﬁguration modes, selected using pin BUS_CONF/DA0 at

power-up:

• Split bus mode (BUS_CONF/DA0 = LOW): 8-bit multiplexed address and data bus,

and separate 8-bit or 16-bit DMA bus

• Generic processor mode (BUS_CONF/DA0 = HIGH): separate 8-bit address and

16-bit data bus

Details of bus conﬁgurations for each mode are given in Table 5. Typical interface circuits

for each mode are given in Section 14.

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ISP1583

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Hi-Speed USB peripheral controller

Table 5.

Bus conﬁguration modes

BUS_CONF/

DA0

PIO width

DMA width

WIDTH = 0

Description

WIDTH = 1

LOW

AD[7:0]

D[7:0]

D[15:0]

split bus mode:

• Multiplexed address and data on pins AD[7:0]

• Separate 8-bit or 16-bit DMA bus on pins DATA[15:0]

generic processor mode:

HIGH

A[7:0] and

D[15:0]

D[7:0]

D[15:0]

• Separate 8-bit address on pins AD[7:0]

• 16-bit data (PIO and DMA) on pins DATA[15:0]

8.12 Pins status

Table 6 illustrates the behavior of ISP1583 pins with V_CC(I/O)and V_CC(3V3)in various

operating conditions.

Table 6.

V_CC(3V3)

ISP1583 pin status

V_CC(I/O)

State

Input

Output

unknown

output

I/O

0 V

dead^[1]

unknown

high-Z

unknown

high-Z

1.65 V to 3.6 V plug-out^[2]

0 V → 3.3 V 1.65 V to 3.6 V plug-in^[3]

3.3 V

1.65 V to 3.6 V reset

state depends on how

the pin is driven

3.3 V

1.65 V to 3.6 V after reset

state depends on how

the pin is driven

output

state depends on how the

pin is conﬁgured

[1] Dead: the USB cable is plugged out, and V_CC(I/O)is not available.

[2] Plug-out: the USB cable is not present, but V_CC(I/O)is available.

[3] Plug-in: the USB cable is being plugged in, and V_CC(I/O)is available.

Table 7 illustrates the behavior of output pins with V_CC(I/O)and V_CC(3V3)in various

operating conditions.

Table 7.

V_CC(3V3)

0 V

ISP1583 output pin status

V_CC(I/O)

State

dead^[1]

plug-out^[2]

plug-in^[3]

reset

INT

SUSPEND

HIGH

0 V

LOW

HIGH

0 V

1.65 V to 3.6 V

HIGH

0 V → 3.3 V

3.3 V

HIGH

LOW

3.3 V

after reset

LOW

[1] Dead: the USB cable is plugged out, and V_CC(I/O)is not available.

[2] Plug-out: the USB cable is not present, but V_CC(I/O)is available.

[3] Plug-in: the USB cable is being plugged in, and V_CC(I/O)is available.

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ISP1583

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Hi-Speed USB peripheral controller

8.13 Interrupt

8.13.1 Interrupt output pin

The Interrupt Conﬁguration register of the ISP1583 controls the behavior of the INT output

pin. The polarity and signaling mode of the INT pin can be programmed by setting bits

INTPOL and INTLVL of the Interrupt Conﬁguration register (R/W: 10h); see Table 28. Bit

GLINTENA of the Mode register (R/W: 0Ch) is used to enable pin INT; see Table 25.

Default settings after reset are active LOW and level mode. When pulse mode is selected,

a pulse of 60 ns is generated when the OR-ed combination of all interrupt bits changes

from logic 0 to logic 1.

Figure 5 shows the relationship between interrupt events and pin INT.

Each of the indicated USB and DMA events is logged in a status bit of the Interrupt

register and the DMA Interrupt Reason register, respectively. Corresponding bits in the

Interrupt Enable register and the DMA Interrupt Enable register determine whether an

event will generate an interrupt.

Interrupts can be masked globally by means of bit GLINTENA of the Mode register.

Field CDBGMOD[1:0] of the Interrupt Conﬁguration register controls the generation of INT

signals for the control pipe. Field DDBGMODIN[1:0] of the Interrupt Conﬁguration register

controls the generation of INT signals for the IN pipe. Field DDBGMODOUT[1:0] of the

Interrupt Conﬁguration register controls the generation of INT signals for the OUT pipe;

see Table 29.

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ISP1583

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Hi-Speed USB peripheral controller

8.13.2 Interrupt control

Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior

of this bit is given in Figure 6.

The following illustrations are only applicable for level trigger.

Event A: When an interrupt event occurs (for example, SOF interrupt) with bit GLINTENA

set to logic 0, an interrupt will not be generated at pin INT. It will, however, be registered in

the corresponding Interrupt register bit.

Event B: When bit GLINTENA is set to logic 1, pin INT is asserted because bit SOF in the

Interrupt register is already set.

Event C: If the ﬁrmware sets bit GLINTENA to logic 0, pin INT will still be asserted. The

bold line shows the desired behavior of pin INT.

Deassertion of pin INT can be achieved either by clearing all the bits in the Interrupt

register or the DMA Interrupt Reason register, depending on the event.

Remark: When clearing an interrupt event, perform write to all the bytes of the register.

For more information on interrupt control, see Section 9.2.2, Section 9.2.5 and

Section 9.5.1.

A

B

C

INT pin

GLINTENA = 0

SOF asserted

GLINTENA = 0

(during this time,

an interrupt event

occurs, for example,

SOF asserted)

GLINTENA = 1

SOF asserted

004aaa394

Pin INT: HIGH = deassert; LOW = assert (individual interrupts are enabled).

Fig 6. Behavior of bit GLINTENA

8.14 V_BUSsensing

The V_BUSpin is one of the ways to wake up the clock when the ISP1583 is suspended

with bit CLKAON set to logic 0 (clock off option).

To detect whether the host is connected or not, that is V_BUSsensing, a 1 MΩ resistor and

a 1 µF electrolytic or tantalum capacitor must be added to damp the overshoot on plug in.

ISP1583_7

Product data sheet

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ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

55

USB

CONNECTOR

ISP1583

1 µF

1 MΩ

004aaa449

The ﬁgure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2

ballouts, see Table 3.

Fig 7. Resistor and electrolytic or tantalum capacitor needed for V_BUSsensing

001aaf440

Fig 8. Oscilloscope reading: no resistor and capacitor in the network

001aaf441

Fig 9. Oscilloscope reading: with resistor and capacitor in the network

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ISP1583

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Hi-Speed USB peripheral controller

8.15 Power-on reset

The ISP1583 requires a minimum pulse width of 500 µs.

The RESET_N pin can either be connected to V_CC(3V3)(using the internal POR circuit) or

externally controlled (by the microcontroller, ASIC, and so on). When V_CC(3V3)is directly

connected to the RESET_N pin, internal pulse width t_PORPwill typically be 200 ns.

The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5

on the V_CC(POR)curve (Figure 10).

t0 — The internal POR starts with a HIGH level.

t1 — The detector will see the passing of the trip level and a delay element will add

another t_PORPbefore it drops to LOW.

t2 to t3 — The internal POR pulse will be generated whenever V_CC(POR)drops below V_trip

for more than 11 µs.

t4 to t5 — The dip is too short (< 11 µs) and the internal POR pulse will not react and will

remain LOW.

V

CC(POR)

V

trip

t4

t0

t1

t

t3

t5

t2

(1)

PORP

t

PORP

004aab162

(1) PORP = Power-On Reset Pulse.

Fig 10. POR timing

Figure 11 shows the availability of the clock with respect to the external POR.

V

CC(3V3)

500 µs

external

clock

2 ms

RESET_N

004aaa906

A

B

C

Power on V_CC(3V3)at A.

Stable external clock is to be available at B.

The ISP1583 is operational at C.

Fig 11. Clock with respect to the external POR

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ISP1583

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Hi-Speed USB peripheral controller

8.16 Power supply

The ISP1583 can be powered by 3.3 V ± 0.3 V, and from 1.65 V to 3.6 V at the interface.

For details, see Figure 12. If the ISP1583 is powered by V_CC(3V3)= 3.3 V, an integrated

3.3 V-to-1.8 V voltage regulator provides a 1.8 V supply voltage for the internal logic.

In sharing mode (that is, when V_CC(3V3)is not present and V_CC(I/O)is present), all I/O pins

are input type, the interrupt pin is connected to ground, and the suspend pin is connected

to V_CC(I/O). See Table 7.

3.3 V ± 0.3 V

V

CC(3V3)

61

0.1 µF

0.01 µF

1.65 V to 3.6 V

CC(I/O)

26

41

0.01 µF

0.1 µF

V

CC(I/O)

0.01 µF

0.1 µF

ISP1583

CC(I/O)

54

56

0.01 µF

0.1 µF

VCC1V8

(1)

0.1 µF

4.7 µF

VCC1V8

32

0.1 µF

004aaa271

(1) At the V_CCinput (3.3 V) to the USB controller, if the ripple voltage is less than 20 mV, then 4.7 µF

standard electrolytic or tantalum capacitors (tested ESR up to 10 Ω) should be OK at the VCC1V8

output. If the ripple voltage at the input is higher than 20 mV, then use 4.7 µF LOW ESR capacitors

(ESR from 0.2 Ω to 2 Ω) at the VCC1V8 output. This is to improve the high-speed signal quality at

the USB side.

The ﬁgure shows the ISP1583BS pinout. For the ISP1583ET, ISP1583ET1 and ISP1583ET2

ballouts, see Table 3.

Fig 12. ISP1583 with a 3.3 V supply

Table 8 shows power modes in which the ISP1583 can be operated.

Table 8.

V_CC(3V3)

Power modes

V_CC(I/O)

Power mode

[1]

[2]

V_BUS

bus-powered

System-powered

system-powered

self-powered

[1]

V_BUS

power-sharing (hybrid)

[1] The power supply to the IC (V_CC(3V3)) is 3.3 V. Therefore, if the application is bus-powered, a 3.3 V regulator

needs to be used.

[2] V_CC(I/O)can range from 1.65 V to 3.6 V. If the application is bus-powered, a voltage regulator must be used.

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ISP1583

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Hi-Speed USB peripheral controller

8.16.1 Power-sharing mode

to GPIO of processor

for sensing V

BUS

5 V-to-3.3 V

VOLTAGE

REGULATOR

1.5 kΩ

RPU

V

BUS

V

USB

CC(3V3)

BUS

ISP1583

1 µF

1 MΩ

CC(I/O)

004aaa458

V_CC(I/O)is system powered.

Fig 13. Power-sharing mode

As can be seen in Figure 13, in power-sharing mode, V_CC(3V3)is supplied by the output of

the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V_BUS. V_CC(I/O)is

supplied through the power source of the system. When the USB cable is plugged in, the

ISP1583 goes through the power-on reset cycle. In this mode, OTG is disabled.

The processor will experience continuous interrupt because the default status of the

interrupt pin when operating in sharing mode with V_BUSnot present is LOW. To overcome

this, implement external V_BUSsensing circuitry. The output from the voltage regulator can

be connected to pin GPIO of the processor to qualify the interrupt from the ISP1583.

Remark: When the core power is applied, the ISP1583 must be reset using the RESET_N

pin. The minimum width of the reset pulse width must be 2 ms.

V

CC(I/O)

V

CC(3V3)

INT

power off

004aaa459

Fig 14. Interrupt pin status during power off in power-sharing mode

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ISP1583

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Hi-Speed USB peripheral controller

Table 9.

Operation truth table for SoftConnect

ISP1583 operation

Power supply

Bit SOFTCT in

Mode register

V_CC(3V3)V_CC(I/O)RPU

V_BUS

(3.3 V)

3.3 V

0 V

Normal bus operation

Core power is lost

3.3 V

0 V

3.3 V

5 V

0 V

enabled

not applicable

Table 10. Operation truth table for clock off during suspend

ISP1583 operation

Power supply

Clock off

during

suspend

V_CC(3V3)V_CC(I/O)

RPU

V_BUS

(3.3 V)

Clock will wake up:

After a resume and

After a bus reset

Core power is lost

3.3 V

0 V

5 V

enabled

0 V

not applicable

Table 11. Operation truth table for back voltage compliance

ISP1583 operation

Power supply

Bit SOFTCT

in Mode

register

V_CC(3V3)

3.3 V

0 V

V_CC(I/O)RPU

V_BUS

(3.3 V)

Back voltage is not measured in this

mode

3.3 V

5 V

0 V

enabled

Back voltage is not an issue because

core power is lost

0 V

not applicable

Table 12. Operation truth table for OTG

ISP1583 operation

Power supply

V_CC(I/O)RPU

OTG register

V_CC(3V3)

V_BUS

(3.3 V)

3.3 V

0 V

SRP is not applicable

3.3 V

5 V

0 V

not applicable

OTG is not possible because V_BUSis not 0 V

present and so core power is lost

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ISP1583

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Hi-Speed USB peripheral controller

8.16.2 Self-powered mode

1.5 kΩ

RPU

V

BUS

V

USB

V

BUS

CC(3V3)

ISP1583

1 µF

1 MΩ

V

CC(I/O)

004aaa461

V_CC(I/O)and V_CC(3V3)are system powered.

Fig 15. Self-powered mode

In self-powered mode, V_CC(3V3)and V_CC(I/O)are supplied by the system. See Figure 15.

Table 13. Operation truth table for SoftConnect

ISP1583 operation

Power supply

Bit SOFTCT

in Mode

register

V_CC(3V3)V_CC(I/O)RPU

(3.3 V)

V_BUS

Normal bus operation

No pull up on DP

3.3 V

5 V

0 V^[1]

enabled

disabled

[1] When the USB cable is removed, SoftConnect is disabled.

Table 14. Operation truth table for clock off during suspend

ISP1583 operation

Power supply

V_CC(3V3)V_CC(I/O)RPU

(3.3 V)

3.3 V

Clock off

during

suspend

V_BUS

Clock will wake up:

3.3 V

5 V

enabled

After a resume and

After a bus reset

Clock will wake up:

3.3 V

0 V → 5 V enabled

After detecting the presence of V_BUS

Table 15. Operation truth table for back voltage compliance

ISP1583 operation

Power supply

Bit SOFTCT in

Mode register

V_CC(3V3)V_CC(I/O)RPU

V_BUS

(3.3 V)

Back voltage is not measured in this

mode

3.3 V

5 V

0 V

enabled

disabled

Back voltage is not an issue because pull 3.3 V

up on DP will not be present when V_BUS

is not present

3.3 V

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Table 16. Operation truth table for OTG

ISP1583 operation

Power supply

OTG register

V_CC(3V3)V_CC(I/O)RPU

V_BUS

(3.3 V)

3.3 V

SRP is not applicable

SRP is possible

3.3 V

5 V

0 V

not applicable

operational

8.16.3 Bus-powered mode

5 V-to-3.3 V

VOLTAGE

REGULATOR

V

BUS

V

CC(3V3)

USB

BUS

1.65 V to 3.6 V

ISP1583

1 µF

1 MΩ

V

CC(I/O)

1.5 kΩ

RPU

004aaa463

V_CC(I/O)is powered by V_BUS

.

Fig 16. Bus-powered mode

In bus-powered mode (see Figure 16), V_CC(3V3)and V_CC(I/O)are supplied by the output of

the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V_BUS. On plugging the

USB cable, the ISP1583 goes through the power-on reset cycle. In this mode, OTG is

disabled.

Table 17. Operation truth table for SoftConnect

ISP1583 operation

Power supply

Bit SOFTCT in

Mode register

V_CC(3V3)V_CC(I/O)RPU

V_BUS

(3.3 V)

3.3 V

0 V

Normal bus operation

Power is lost

3.3 V

0 V

3.3 V

0 V

5 V

0 V

enabled

not applicable

Table 18. Operation truth table for clock off during suspend

ISP1583 operation

Power supply

Clock off

during suspend

V_CC(3V3)V_CC(I/O)RPU

V_BUS

(3.3 V)

Clock will wake up:

After a resume and

After a bus reset

Power is lost

3.3 V

0 V

3.3 V

5 V

enabled

0 V

not applicable

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

27 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 19. Operation truth table for back voltage compliance

ISP1583 operation

Power supply

Bit SOFTCT in

Mode register

V_CC(3V3)V_CC(I/O)RPU

V_BUS

5 V

(3.3 V)

Back voltage is not measured in this

mode

3.3 V

0 V

3.3 V

0 V

3.3 V

enabled

Power is lost

0 V

not applicable

Table 20. Operation truth table for OTG

ISP1583 operation

Power supply

OTG register

V_CC(3V3)V_CC(I/O)RPU

V_BUS

(3.3 V)

3.3 V

0 V

SRP is not applicable

Power is lost

3.3 V

0 V

5 V

0 V

not applicable

0 V

ISP1583_7

Product data sheet

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ISP1583

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Hi-Speed USB peripheral controller

9. Register description

Table 21. Register overview

Name

Destination

Address Description

Size

Reference

(bytes)

Initialization registers

Address

device

00h

0Ch

10h

12h

14h

USB device address and enable

1

2

1

4

Section 9.2.1

on page 31

Mode

power-down options, global interrupt

enable, SoftConnect

Section 9.2.2

on page 31

Interrupt Conﬁguration

OTG

interrupt sources, trigger mode,

output polarity

Section 9.2.3

on page 33

OTG implementation

Section 9.2.4

on page 34

Interrupt Enable

interrupt source enabling

Section 9.2.5

on page 36

Data ﬂow registers

Endpoint Index

endpoints

endpoint

2Ch

28h

20h

1Ch

1Eh

04h

08h

endpoint selection, data ﬂow direction

endpoint buffer management

data access to endpoint FIFO

packet size counter

1

2

1

2

Section 9.3.1

on page 38

Control Function

Data Port

Section 9.3.2

on page 39

Section 9.3.3

on page 40

Buffer Length

Buffer Status

Section 9.3.4

on page 41

buffer status for each endpoint

maximum packet size

Section 9.3.5

on page 42

Endpoint MaxPacketSize endpoint

Section 9.3.6

on page 43

Endpoint Type

endpoint

selects endpoint type: isochronous,

bulk or interrupt

Section 9.3.7

on page 44

DMA registers

DMA Command

DMA controller

30h

34h

38h

controls all DMA transfers

1

4

1

Section 9.4.1

on page 47

DMA Transfer Counter

DMA Conﬁguration

sets byte count for DMA transfer

Section 9.4.2

on page 49

byte 0: sets GDMA conﬁguration

(counter enable, data strobing, bus

width)

Section 9.4.3

on page 50

39h

3Ch

byte 1: sets ATA conﬁguration (IORDY

enable, mode selection: ATA, MDMA,

PIO)

1

DMA Hardware

DMA controller

endian type, master or slave

selection, signal polarity for DACK,

DREQ, DIOW, DIOR, EOT

Section 9.4.4

on page 52

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

29 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 21. Register overview …continued

Name

Destination

Address Description

Size

Reference

(bytes)

Task File 1F0

ATAPI peripheral

40h

single address word register: byte 0

2

Section 9.4.5

on page 53

(lower byte) is accessed ﬁrst

IDE device access

Task File 1F1

Task File 1F2

Task File 1F3

Task File 1F4

Task File 1F5

Task File 1F6

Task File 1F7

ATAPI peripheral

48h

49h

4Ah

4Bh

4Ch

4Dh

44h

1

IDE device access (write only; reading

returns FFh)

Task File 3F6

ATAPI peripheral

DMA controller

4Eh

4Fh

50h

IDE device access

1

2

Task File 3F7

DMA Interrupt Reason

shows reason (source) for DMA

interrupt

Section 9.4.6

on page 56

DMA Interrupt Enable

DMA Endpoint

DMA controller

54h

58h

60h

64h

enables DMA interrupt sources

2

1

2

Section 9.4.7

on page 57

selects endpoint FIFO, data ﬂow

direction

Section 9.4.8

on page 57

DMA Strobe Timing

DMA Burst Counter

strobe duration in MDMA mode

Section 9.4.9

on page 58

DMA burst length

Section 9.4.10

on page 59

General registers

Interrupt

device

18h

70h

74h

shows interrupt sources

4

Section 9.5.1

on page 59

Chip ID

product ID code and hardware version 3

Section 9.5.2

on page 61

Frame Number

last successfully received

Start-Of-Frame: lower byte (byte 0) is

accessed ﬁrst

2

Section 9.5.3

on page 62

Scratch

device

PHY

78h

7Ch

84h

allows save or restore of ﬁrmware

status during suspend

2

1

Section 9.5.4

on page 62

Unlock Device

Test Mode

re-enables register write access after

suspend

Section 9.5.5

on page 63

direct setting of the DP and DM

states, internal transceiver test (PHY)

Section 9.5.6

on page 63

9.1 Register access

Register access depends on the bus width used:

• 8-bit bus: multi-byte registers are accessed lower byte (LSByte) ﬁrst

• 16-bit bus: for single-byte registers, the upper byte (MSByte) must be ignored

Endpoint speciﬁc registers are indexed using the Endpoint Index register. The target

endpoint must be selected before accessing the following registers:

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

30 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

• Buffer Length

• Buffer Status

• Control Function

• Data Port

• Endpoint MaxPacketSize

• Endpoint Type

Remark: Write zero to all reserved bits, unless otherwise speciﬁed.

9.2 Initialization registers

9.2.1 Address register (address: 00h)

This register sets the USB assigned address and enables the USB device. Table 22

shows the Address register bit allocation.

Bits DEVADDR[6:0] will be cleared whenever a bus reset, a power-on reset or a soft reset

occurs. Bit DEVEN will be cleared whenever a power-on reset or a soft reset occurs.

In response to standard USB request SET_ADDRESS, the ﬁrmware must write the

(enabled) device address to the Address register, followed by sending an empty packet to

the host. The new device address is activated when the device receives an

acknowledgment from the host for the empty packet token.

Table 22. Address register: bit allocation

Bit

7

DEVEN

0

6

5

4

3

2

1

0

Symbol

Reset

DEVADDR[6:0]

0

Bus reset

Access

unchanged

R/W

Table 23. Address register: bit description

Bit

Symbol

Description

7

DEVEN

Device Enable: Logic 1 enables the device. The device will not

respond to the host, unless this bit is set.

6 to 0

DEVADDR[6:0] Device Address: This ﬁeld speciﬁes the USB device address.

9.2.2 Mode register (address: 0Ch)

This register consists of 2 bytes (bit allocation: see Table 24).

The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft

reset, clock signals and SoftConnect operation.

ISP1583_7

Product data sheet

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ISP1583

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Hi-Speed USB peripheral controller

Table 24. Mode register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

TEST2

TEST1

TEST0

reserved

DMA

VBUSSTAT

CLKON

[1]

Reset

-

0

-

[1]

Bus reset

Access

Bit

-

0

-

R

-

R/W

R

7

CLKAON

0

6

5

4

3

2

1

PWRON

0

SOFTCT

0

Symbol

Reset

SNDRSU

GOSUSP

SFRESET GLINTENA WKUPCS

0

Bus reset

Access

unchanged

R/W

unchanged

R/W

unchanged unchanged

R/W R/W

R/W

[1] Value depends on the status of the V_BUSpin.

Table 25. Mode register: bit description

Bit

15

14

13

Symbol

TEST2

TEST1

TEST0

Description

This bit reﬂects the MODE1 pin setting. Only for test purposes.

This bit reﬂects the MODE0/DA1 pin setting. Only for test purposes.

This bit reﬂects the BUS_CONF/DA0 pin setting. Only for test purposes.

12 to 10 -

reserved

9

DMACLKON

DMA Clock On:

0 — Power save mode; the DMA circuit will stop completely to save

power.

1 — Supply clock to the DMA circuit.

8

7

VBUSSTAT

CLKAON

V_BUSPin Status: This bit reﬂects the V_BUSpin status.

Clock Always On: Logic 1 indicates that internal clocks are always

running when in the suspend state. Logic 0 switches off the internal

oscillator and PLL when the device goes into suspend mode. The

device will consume less power if this bit is set to logic 0. The clock is

stopped about 2 ms after bit GOSUSP is set and then cleared.

6

SNDRSU

Send Resume: Writing logic 1, followed by logic 0 will generate a 10 ms

upstream resume signal.

Remark: The upstream resume signal is generated 5 ms after this bit is

set to logic 0.

5

4

GOSUSP

SFRESET

Go Suspend: Writing logic 1, followed by logic 0 will activate suspend

mode.

Soft Reset: Writing logic 1, followed by logic 0 will enable a

software-initiated reset to the ISP1583. A soft reset is similar to a

hardware-initiated reset (using the RESET_N pin).

ISP1583_7

Product data sheet

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ISP1583

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Hi-Speed USB peripheral controller

Table 25. Mode register: bit description …continued

Bit

Symbol

Description

3

GLINTENA

Global Interrupt Enable: Logic 1 enables all interrupts. Individual

interrupts can be masked by clearing the corresponding bits in the

Interrupt Enable register.

When this bit is not set, an unmasked interrupt will not generate an

interrupt trigger on the interrupt pin. If global interrupt, however, is

enabled while there is any pending unmasked interrupt, an interrupt

signal will be immediately generated on the interrupt pin. (If the interrupt

is set to pulse mode, the interrupt events that were generated before the

global interrupt is enabled will not appear on the interrupt pin.)

2

1

WKUPCS

PWRON

Wake-up on Chip selection: Logic 1 enables wake-up from suspend

mode through a valid register read on the ISP1583. (A read will invoke

the chip clock to restart. If you write to the register before the clock gets

stable, it may cause malfunctioning.)

Power On: The SUSPEND pin output control.

0 — The SUSPEND pin is HIGH when the ISP1583 is in the suspend

state. Otherwise, the SUSPEND pin is LOW.

1 — When the device is woken up from the suspend state, there will be

a 1 ms active HIGH pulse on the SUSPEND pin. The SUSPEND pin will

remain LOW in all other states.

0

SOFTCT

SoftConnect: Logic 1 enables the connection of the 1.5 kΩ pull-up

resistor on pin RPU to the DP pin.

The status of the chip is shown in Table 26.

Table 26. Status of the chip

Bus state

SoftConnect = on

SoftConnect = off

V_BUSon

pull-up resistor on pin DP

pull-up resistor on pin DP is removed;

suspend interrupt is generated after 3 ms of

no bus activity

V_BUSoff

pull-up resistor on pin DP is present; pull-up resistor on pin DP is removed;

suspend interrupt is generated after suspend interrupt is generated after 3 ms of

3 ms of no bus activity

no bus activity

9.2.3 Interrupt Conﬁguration register (address: 10h)

This 1-byte register determines the behavior and polarity of the INT output. The bit

allocation is shown in Table 27. When the USB SIE receives or generates an ACK, NAK or

NYET, it will generate interrupts, depending on three Debug mode ﬁelds.

CDBGMOD[1:0] — interrupts for control endpoint 0

DDBGMODIN[1:0] — interrupts for DATA IN endpoints 1 to 7

DDBGMODOUT[1:0] — interrupts for DATA OUT endpoints 1 to 7

The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you

to individually conﬁgure when the ISP1583 sends an interrupt to the external

microprocessor. Table 29 lists available combinations.

Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or

falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to

logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

33 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 27. Interrupt Conﬁguration register: bit allocation

Bit

7

6

5

4

3

2

1

INTLVL

0

INTPOL

0

Symbol

Reset

CDBGMOD[1:0]

DDBGMODIN[1:0]

DDBGMODOUT[1:0]

1

Bus reset

Access

unchanged unchanged

R/W R/W

R/W

Table 28. Interrupt Conﬁguration register: bit description

Bit

Symbol

Description

7 to 6

5 to 4

3 to 2

1

CDBGMOD[1:0]

DDBGMODIN[1:0]

Control Endpoint 0 Debug Mode: For values, see Table 29

Data Debug Mode IN: For values, see Table 29

DDBGMODOUT[1:0] Data Debug Mode OUT: For values, see Table 29

INTLVL

Interrupt Level: Selects signaling mode on output INT (0 = level;

1 = pulsed). In pulsed mode, an interrupt produces a 60 ns pulse.

0

INTPOL

Interrupt Polarity: Selects signal polarity on output INT (0 =

active LOW, 1 = active HIGH).

Table 29. Debug mode settings

Value

CDBGMOD

DDBGMODIN

DDBGMODOUT

00h

interrupt on all ACK and

NAK

interrupt on all ACK and

NAK

interrupt on all ACK, NYET

and NAK

01h

1Xh

interrupt on all ACK

interrupt on ACK

interrupt on ACK and NYET

interrupt on all ACK and

ﬁrst NAK^[1]

interrupt on all ACK and

ﬁrst NAK^[1]

interrupt on all ACK, NYET

and ﬁrst NAK^[1]

[1] First NAK: the ﬁrst NAK on an IN or OUT token is generated after a set-up token and an ACK sequence.

9.2.4 OTG register (address: 12h)

The bit allocation of the OTG register is given in Table 30.

Table 30. OTG register: bit allocation

Bit

7

6

5

DP

0

4

3

2

DISCV

0

1

VP

0

OTG

0

Symbol

Reset

reserved

BSESSVALID INITCOND

-

Bus reset

Access

0

R/W

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

34 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 31. OTG register: bit description

Bit

7 to 6

5

Symbol Description^[1]

-

reserved

DP

Data Pulsing: Used for data-line pulsing to toggle DP to generate the required

data-line pulsing signal. The default value of this bit is logic 0. This bit must be

cleared when data-line pulsing is completed.

4

BSESS B-Session Valid: The device can initiate another V_BUSdischarge sequence

VALID

after data-line pulsing and V_BUSpulsing, and before it clears this bit and detects

a session valid.

This bit is latched to logic 1 once V_BUSexceeds the B-device session valid

threshold. Once set, it remains at logic 1. To clear this bit, write logic 1. (The

ISP1583 continuously updates this bit to logic 1 when the B-session is valid. If

the B-session is valid after it is cleared, it is set back to logic 1 by the ISP1583).

0 — It implies that SRP has failed. To proceed to a normal operation, the device

can restart SRP, clear bit OTG or proceed to an error handling process.

1 — It implies that the B-session is valid. The device clears bit OTG, goes into

normal operation mode, and sets bit SOFTCT (DP pull-up) in the Mode register.

The OTG host has a maximum of 5 s before it responds to a session request.

During this period, the ISP1583 may request to suspend. Therefore, the device

ﬁrmware must wait for some time if it wishes to know the SRP result (success: if

there is minimum response from the host within 5 s; failure: if there is no

response from the host within 5 s).

3

INIT

COND

Initial Condition: Write logic 1 to clear this bit. Wait for more than 2 ms and

check the bit status. If it reads logic 0, it means that V_BUSremains lower than

0.8 V, and DP or DM are at SE0 during the elapsed time. The device can then

start a B-device SRP. If it reads logic 1, it means that the initial condition of SRP

is violated. So, the device must abort SRP.

The bit is set to logic 1 by the ISP1583 when initial conditions are not met, and

only writing logic 1 clears the bit. (If initial conditions are not met after this bit

has been cleared, it will be set again).

Remark: This implementation does not cover the case if an initial SRP condition

is violated when this bit is read and data-line pulsing is started.

2

DISCV

Discharge V_BUS: Set to logic 1 to discharge V_BUS. The device discharges V_BUS

before starting a new SRP. The discharge can take as long as 30 ms for V_BUSto

be charged less than 0.8 V. This bit must be cleared (write logic 0) before a

session end.

1

0

VP

V

_BUSPulsing: Used for V_BUSpulsing to toggle VP to generate the required

V_BUSpulsing signal. This bit must be set for more than 16 ms and must be

cleared before 26 ms.

OTG

On-The-Go:

1 — Enables the OTG function. The V_BUSsensing functionality will be disabled.

0 — Normal operation. All OTG control bits will be masked. Status bits are

undeﬁned.

[1] No interrupt is designed for OTG. The V_BUSinterrupt, however, may assert as a side effect during the V_BUS

pulsing.

When OTG is in progress, the V_BUSinterrupt may be set because V_BUSis charged over the V_BUSsensing

threshold or the OTG host has turned on the V_BUSsupply to the device. Even if the V_BUSinterrupt is found

during SRP, the device must complete data-line pulsing and V_BUSpulsing before starting the

B_SESSION_VALID detection.

OTG implementation applies to the device with self-power capability. If the device works in sharing mode, it

must provide a switch circuit to supply power to the ISP1583 core during SRP.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

35 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

9.2.4.1 Session Request Protocol (SRP)

The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing,

followed by V_BUSpulsing. The A-device can detect either data-line pulsing or V_BUS

pulsing.

The ISP1583 can initiate the B-device SRP by performing the following steps:

1. Set the OTG bit to start SRP.

2. Detect initial conditions by following the instructions given in bit INITCOND of the OTG

register.

3. Start data-line pulsing: set bit DP of the OTG register to logic 1.

4. Wait for 5 ms to 10 ms.

5. Stop data-line pulsing: set bit DP of the OTG register to logic 0.

6. Start V_BUSpulsing: set bit VP of the OTG register to logic 1.

7. Wait for 10 ms to 20 ms.

8. Stop V_BUSpulsing: set bit VP of the OTG register to logic 0.

9. Discharge V_BUSfor about 30 ms: optional by using bit DISCV of the OTG register.

10. Detect bit BSESSVALID of the OTG register for a successful SRP with bit OTG

cleared.

11. Once bit BSESSVALID is detected, turn on the SOFTCT bit to start normal bus

enumeration.

The B-device must complete both data-line pulsing and V_BUSpulsing within 100 ms.

Remark: When disabling OTG, data-line pulsing bit DP and V_BUSpulsing bit VP must be

cleared by writing logic 0.

9.2.5 Interrupt Enable register (address: 14h)

This register enables or disables individual interrupt sources. The interrupt for each

endpoint can individually be controlled using the associated bits IEPnRX or IEPnTX, here

n represents the endpoint number. All interrupts can be globally disabled using bit

GLINTENA in the Mode register (see Table 24).

An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the

USB bus. The interrupt generation depends on Debug mode settings of bit ﬁelds

CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0] in the Interrupt

Conﬁguration register.

All data IN transactions use the Transmit buffers (TX), which are handled by bits

DDBGMODIN[1:0]. All data OUT transactions go through the Receive buffers (RX), which

are handled by bits DDBGMODOUT[1:0]. Transactions on control endpoint 0 (IN, OUT

and SETUP) are handled by bits CDBGMOD[1:0].

Interrupts caused by events on the USB bus (SOF, suspend, resume, bus reset, set up

and high-speed status) can also be individually controlled. A bus reset disables all

enabled interrupts, except bit IEBRST (bus reset), which remains logic 1.

The Interrupt Enable register consists of 4 bytes. The bit allocation is given in Table 32.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

36 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 32. Interrupt Enable register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

reserved

IEP7TX

IEP7RX

-

0

Bus reset

Access

Bit

-

0

R/W

17

0

R/W

16

-

23

22

21

20

19

18

Symbol

Reset

IEP6TX

IEP6RX

IEP5TX

IEP5RX

IEP4TX

IEP4RX

IEP3TX

0

IEP3RX

0

Bus reset

Access

Bit

0

R/W

9

R/W

8

15

14

13

12

11

10

Symbol

Reset

IEP2TX

IEP2RX

IEP1TX

IEP1RX

IEP0TX

IEP0RX

reserved IEP0SETUP

0

-

0

Bus reset

Access

Bit

0

R/W

6

0

-

0

R/W

-

R/W

7

5

4

3

2

1

IESOF

0

IEBRST

0

Symbol

Reset

IEVBUS

IEDMA

0

IEHS_STA

IERESM

IESUSP

IEPSOF

0

Bus reset

Access

0

1

R/W

Table 33. Interrupt Enable register: bit description

Bit

31 to 26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

Symbol

-

Description

reserved

IEP7TX

IEP7RX

IEP6TX

IEP6RX

IEP5TX

IEP5RX

IEP4TX

IEP4RX

IEP3TX

IEP3RX

IEP2TX

IEP2RX

IEP1TX

IEP1RX

IEP0TX

IEP0RX

-

Logic 1 enables interrupt from the indicated endpoint.

Logic 1 enables interrupt from control IN endpoint 0.

Logic 1 enables interrupt from control OUT endpoint 0.

reserved

8

IEP0SETUP Logic 1 enables interrupt for the set-up data received on endpoint 0.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

37 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 33. Interrupt Enable register: bit description …continued

Bit

7

Symbol

IEVBUS

IEDMA

Description

Logic 1 enables interrupt for V_BUSsensing.

6

Logic 1 enables interrupt on the DMA Interrupt Reason register change

detection.

5

4

3

2

1

0

IEHS_STA

IERESM

IESUSP

IEPSOF

IESOF

Logic 1 enables interrupt on detecting a high-speed status change.

Logic 1 enables interrupt on detecting a resume state.

Logic 1 enables interrupt on detecting a suspend state.

Logic 1 enables interrupt on detecting a pseudo SOF.

Logic 1 enables interrupt on detecting an SOF.

IEBRST

Logic 1 enables interrupt on detecting a bus reset.

9.3 Data ﬂow registers

9.3.1 Endpoint Index register (address: 2Ch)

The Endpoint Index register selects a target endpoint for register access by the

microcontroller. The register consists of 1 byte, and the bit allocation is shown in Table 34.

The following registers are indexed:

• Buffer length

• Buffer status

• Control function

• Data port

• Endpoint MaxPacketSize

• Endpoint type

For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the

Endpoint Index register must ﬁrst be written with 02h.

Remark: The Endpoint Index register and the DMA Endpoint register must not point to the

same endpoint, irrespective of IN and OUT.

Remark: The delay time from the Write Endpoint Index register to the Read Data Port

register must be at least 190 ns.

Remark: The delay time from the Write Endpoint Index register to the Write Data Port

register must be at least 100 ns.

Table 34. Endpoint Index register: bit allocation

Bit

7

6

5

EP0SETUP

1

4

3

2

1

0

DIR

0

Symbol

Reset

reserved

ENDPIDX[3:0]

-

0

Bus reset

Access

unchanged

R/W

0

R/W

ISP1583_7

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ISP1583

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Hi-Speed USB peripheral controller

Table 35. Endpoint Index register: bit description

Bit

7 to 6

5

Symbol

Description

-

reserved

EP0SETUP

Endpoint 0 Setup: Selects the SETUP buffer for endpoint 0.

0 — Data buffer

1 — SETUP buffer

Must be logic 0 for access to endpoints other than set-up token buffer.

4 to 1

0

ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of

buffer length, buffer status, control function, data port, endpoint type

and MaxPacketSize.

DIR

Direction: Sets the target endpoint as IN or OUT.

0 — Target endpoint refers to OUT (RX) FIFO

1 — Target endpoint refers to IN (TX) FIFO

Table 36. Addressing of endpoint buffers

Buffer name

SETUP

EP0SETUP

ENDPIDX

00h

DIR

0

1

0

Control OUT

Control IN

Data OUT

Data IN

00h

0

00h

1

0Xh

0

0Xh

1

9.3.2 Control Function register (address: 28h)

The Control Function register performs the buffer management on endpoints. It consists

of 1 byte, and the bit conﬁguration is given in Table 37. Register bits can stall, clear or

validate any enabled endpoint. Before accessing this register, the Endpoint Index register

must ﬁrst be written to specify the target endpoint.

Table 37. Control Function register: bit allocation

Bit

7

6

5

4

CLBUF

0

3

VENDP

0

2

DSEN

0

1

0

STALL

0

Symbol

Reset

reserved

STATUS

-

0

Bus reset

Access

0

R/W

W

R/W

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Table 38. Control Function register: bit description

Bit

7 to 5

4

Symbol Description

reserved.

-

CLBUF Clear Buffer: Logic 1 clears the TX or RX buffer of the indexed endpoint. The

RX buffer is automatically cleared once the endpoint is completely read. This bit

is set only when it is necessary to forcefully clear the buffer.

Remark: If using double buffer, to clear both the buffers issue the CLBUF

command two times. For details on clearing buffers, refer to Ref. 5 “ISP1582/83

and ISP1761 clearing an IN buffer (AN10045)”.

3

2

VENDP Validate Endpoint: Logic 1 validates data in the TX FIFO of an IN endpoint to

send on the next IN token. In general, the endpoint is automatically validated

when its FIFO byte count has reached endpoint MaxPacketSize. This bit is set

only when it is necessary to validate the endpoint with the FIFO byte count,

which is below endpoint MaxPacketSize.

Remark: Use either bit VENDP or register Buffer Length to validate endpoint

FIFO with FIFO bytes.

DSEN

Data Stage Enable: This bit controls the response of the ISP1583 to a control

transfer. After the completion of the set-up stage, ﬁrmware must determine

whether a data stage is required. For control OUT, ﬁrmware will set this bit and

the ISP1583 goes into the data stage. Otherwise, the ISP1583 will NAK the data

stage transfer. For control IN, ﬁrmware will set this bit before writing data to the

TX FIFO and validate the endpoint. If no data stage is required, ﬁrmware can

immediately set the STATUS bit after the set-up stage.

Remark: The DSEN bit is cleared once the OUT token is acknowledged by the

device and the IN token is acknowledged by the PC host. This bit cannot be

read back and reading this bit will return logic 0.

1

STATUS Status Acknowledge: Only applicable for control IN or OUT.

This bit controls the generation of ACK or NAK during the status stage of a

SETUP transfer. It is automatically cleared when the status stage is completed,

or when a SETUP token is received. No interrupt signal will be generated.

0 — Sends NAK

1 — Sends an empty packet following the IN token (peripheral-to-host) or ACK

following the OUT token (host-to-peripheral)

Remark: The STATUS bit is cleared to zero once the zero-length packet is

acknowledged by the device or the PC host.

Remark: Data transfers preceding the status stage must ﬁrst be fully completed

before the STATUS bit can be set.

0

STALL

Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for

isochronous transfers.

Remark: Stalling a data endpoint will confuse the Data Toggle bit about the

stalled endpoint because the internal logic picks up from where it is stalled.

Therefore, the Data Toggle bit must be reset by disabling and re-enabling the

corresponding endpoint (by setting bit ENABLE to logic 0, followed by logic 1 in

the Endpoint Type register) to reset the PID.

9.3.3 Data Port register (address: 20h)

This 2-byte register provides direct access for a microcontroller to the FIFO of the indexed

endpoint. The bit allocation is shown in Table 39.

Peripheral-to-host (IN endpoint): After each write action, an internal counter is auto

incremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in

the TX FIFO. When all bytes are written (FIFO byte count = endpoint MaxPacketSize), the

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buffer is automatically validated. The data packet will then be sent on the next IN token.

When it is necessary to validate the endpoint whose byte count is less than

MaxPacketSize, it can be done using the Control Function register (bit VENDP) or the

Buffer Length register.

Remark: The buffer can automatically be validated by using the Buffer Length register

(see Table 41).

Host-to-peripheral (OUT endpoint): After each read action, an internal counter is auto

decremented (by two for a 16-bit access, by one for an 8-bit access) to the next location in

the RX FIFO. When all bytes are read, buffer contents are automatically cleared. A new

data packet can then be received on the next OUT token. Buffer contents can also be

cleared using the Control Function register (bit CLBUF), when it is necessary to forcefully

clear contents.

Remark: The delay time from the Write Endpoint Index register to the Read Data Port

register must be at least 190 ns.

Remark: The delay time from the Write Endpoint Index register to the Write Data Port

register must be at least 100 ns.

Table 39. Data Port register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

DATAPORT[15:8]

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

DATAPORT[7:0]

0

Bus reset

Access

R/W

Table 40. Data Port register: bit description

Bit Symbol Description

15 to 8 DATAPORT[15:8] data (upper byte)

7 to 0 DATAPORT[7:0] data (lower byte)

9.3.4 Buffer Length register (address: 1Ch)

This register determines the current packet size (DATACOUNT) of the indexed endpoint

FIFO. The bit allocation is given in Table 41.

The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint

MaxPacketSize register is written (see Table 45). A smaller value can be written when

required. After a bus reset, the Buffer Length register is made zero.

IN endpoint: When data transfer is performed in multiples of MaxPacketSize, the Buffer

Length register is not signiﬁcant. This register is useful only when transferring data that is

not a multiple of MaxPacketSize. The following two examples demonstrate the

signiﬁcance of the Buffer Length register.

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Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register need not be ﬁlled. This is because the

transfer size is a multiple of MaxPacketSize, and MaxPacketSize packets will be

automatically validated because the last packet is also of MaxPacketSize.

Example 2: Consider that the transfer size is 510 bytes and the MaxPacketSize is

programmed as 64 bytes, the Buffer Length register must be ﬁlled with 62 bytes just

before the microprocessor writes the last packet of 62 bytes. This ensures that the last

packet, which is a short packet of 62 bytes, is automatically validated.

Use bit VENDP in the Control register if you are not using the Buffer Length register.

This is applicable only to PIO mode access.

OUT endpoint: The DATACOUNT value is automatically initialized to the number of data

bytes sent by the host on each ACK.

Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is

output as the lower byte (LSByte).

Remark: Buffer Length is valid only after an interrupt is generated for the OUT endpoint.

Table 41. Buffer Length register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

DATACOUNT[15:8]

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

DATACOUNT[7:0]

0

Bus reset

Access

R/W

Table 42. Buffer Length register: bit description

Bit Symbol Description

15 to 0 DATACOUNT[15:0] Data Count: Determines the current packet size of the indexed

endpoint FIFO.

9.3.5 Buffer Status register (address: 1Eh)

This register is accessed using index. The endpoint index must ﬁrst be set before

accessing this register for the corresponding endpoint. It reﬂects the status of the double

buffered endpoint FIFO.

Remark: This register is not applicable to the control endpoint.

Remark: For endpoint IN data transfer, ﬁrmware must ensure a 200 ns delay between

writing of the data packet and reading the Buffer Status register. For endpoint OUT data

transfer, ﬁrmware must also ensure a 200 ns delay between receiving the endpoint

interrupt and reading the Buffer Status register. For more information, refer to Ref. 3

“Using ISP1582/3 in a composite device application with alternate settings (AN10071)”.

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Table 43 shows the bit allocation of the Buffer Status register.

Table 43. Buffer Status register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

reserved

BUF1

BUF0

-

0

Bus reset

Access

R

Table 44. Buffer Status register: bit description

Bit

Symbol

-

Description

7 to 2

1 to 0

reserved

BUF[1:0]

Buffer:

00 — Buffers are not ﬁlled.

01 — One of the buffers is ﬁlled.

10 — One of the buffers is ﬁlled.

11 — Both the buffers are ﬁlled.

9.3.6 Endpoint MaxPacketSize register (address: 04h)

This register determines the maximum packet size for all endpoints, except set-up token

buffer, control IN and control OUT. The register contains 2 bytes, and the bit allocation is

given in Table 45.

Each time the register is written, the Buffer Length register of the corresponding endpoint

is re-initialized to the FFOSZ ﬁeld value. Bits NTRANS control the number of transactions

allowed in a single microframe (for high-speed isochronous and interrupt endpoints only).

Table 45. Endpoint MaxPacketSize register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved

NTRANS[1:0]

FFOSZ[10:8]

-

0

Bus reset

Access

Bit

-

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

7

6

5

Symbol

Reset

FFOSZ[7:0]

0

Bus reset

Access

R/W

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Table 46. Endpoint MaxPacketSize register: bit description

Bit

Symbol

Description

15 to 13

12 to 11

-

reserved

NTRANS[1:0] Number of Transactions (HS mode only).

00 — 1 packet per microframe

01 — 2 packets per microframe

10 — 3 packets per microframe

11 — reserved

These bits are applicable only for isochronous or interrupt

transactions.

10 to 0

FFOSZ[10:0]

FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint.

Applies to both high-speed and full-speed operations.

The ISP1583 supports all the transfers given in Ref. 1 “Universal Serial Bus Speciﬁcation

Rev. 2.0”.

Each programmable FIFO can be independently conﬁgured using its Endpoint

MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN

plus OUT), including set-up token buffer, control IN and control OUT, must not exceed

8192 bytes.

9.3.7 Endpoint Type register (address: 08h)

This register sets the endpoint type of the indexed endpoint: isochronous, bulk or

interrupt. It also serves to enable the endpoint and conﬁgure it for double buffering.

Automatic generation of an empty packet for a zero-length TX buffer can be disabled using

bit NOEMPKT. The register contains 2 bytes, and the bit allocation is shown in Table 47.

Table 47. Endpoint Type register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved

-

Bus reset

Access

Bit

-

7

6

5

4

3

2

1

0

Symbol

Reset

reserved

NOEMPKT

ENABLE

DBLBUF

ENDPTYP[1:0]

-

0

Bus reset

Access

R/W

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Table 48. Endpoint Type register: bit description

Bit

Symbol

Description

15 to 5

4

-

reserved

NOEMPKT

No Empty Packet: Logic 0 causes the ISP1583 to return a null length

packet for the IN token after the DMA IN transfer is complete. For ATA

mode or the DMA IN transfer, which does not require a null length

packet after DMA completion, set to logic 1 to disable the generation of

the null length packet.

3

ENABLE

Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint.

The memory size is allocated as speciﬁed in the Endpoint

MaxPacketSize register. Logic 0 disables the FIFO.

Remark: Stalling a data endpoint will confuse the Data Toggle bit on the

stalled endpoint because the internal logic picks up from where it has

stalled. Therefore, the Data Toggle bit must be reset by disabling and

re-enabling the corresponding endpoint (by setting bit ENABLE to

logic 0, followed by logic 1 in the Endpoint Type register) to reset the

PID.

2

DBLBUF

Double Buffering: Logic 1 enables double buffering for the indexed

endpoint. Logic 0 disables double buffering.

Remark: When performing a write to two empty buffers, ensure that a

minimum of 200 ns delay is provided from the last write of the ﬁrst buffer

to the ﬁrst write of the second buffer. Otherwise, the ﬁrst few data bytes

may not be written to the second buffer, causing data corruption.

1 to 0

ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type.

00 — not used

01 — Isochronous

10 — Bulk

11 — Interrupt

9.4 DMA registers

Two types of Generic DMA transfers and three types of IDE-speciﬁed transfers can be

done by writing the proper opcode in the DMA Command register.

Control bits are given in Table 49 (Generic DMA transfers) and Table 50 (IDE-speciﬁed

transfers).

GDMA read/write (opcode = 00h/01h) — Generic DMA slave mode. Depending on the

MODE[1:0] bits set in the DMA Conﬁguration register, the DACK, DIOR or DIOW signal

strobes data. These signals are driven by the external DMA controller.

GDMA slave mode can operate in either counter mode or EOT-only mode.

In counter mode, bit DIS_XFER_CNT in the DMA Conﬁguration register must be set to

logic 0. The DMA Transfer Counter register must be programmed before any DMA

command is issued. The DMA transfer counter is set by writing from the LSByte to the

MSByte (address: 34h to 37h). The DMA transfer count is internally updated only after the

MSByte is written. Once the DMA transfer is started, the transfer counter starts

decrementing and on reaching 0, bit DMA_XFER_OK is set and an interrupt is generated

by the ISP1583. If the DMA master wishes to terminate the DMA transfer, it can issue an

EOT signal to the ISP1583. This EOT signal overrides the transfer counter and can

terminate the DMA transfer at any time.

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In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer

counter can still be programmed, it will not have any effect on the DMA transfer. The DMA

transfer will start once the DMA command is issued. Any of the following three ways will

terminate this DMA transfer:

• Detecting an external EOT

• Detecting an internal EOT (short packet on an OUT token)

• Issuing a GDMA stop command

There are three interrupts programmable to differentiate the method of DMA termination:

bits INT_EOT, EXT_EOT and DMA_XFER_OK in the DMA Interrupt Reason register (see

Table 74).

MDMA (master) read/write (opcode = 06h/07h) — Generic DMA master mode.

Depending on the MODE[1:0] bits set in the DMA Conﬁguration register, the DACK, DIOR

or DIOW signal strobes data. These signals are driven by the ISP1583.

In master mode, BURSTCOUNTER[12:0] in the DMA Burst Counter register,

DIS_XFER_CNT in the DMA Conﬁguration register and the external EOT signal are not

applicable. The DMA transfer counter is always enabled and bit DMA_XFER_OK is set to

1 once the counter reaches 0.

MDMA read/write (opcode = 06h/07h) — Multi-word DMA mode for IDE transfers. The

speciﬁcation of this mode can be obtained from Ref. 4 “AT Attachment with Packet

Interface Extension (ATA/ATAPI-4), ANSI INCITS 317-1998 (R2003)”. DIOR and DIOW

are used as data strobes, while DREQ and DACK serve as handshake signals.

Table 49. Control bits for Generic DMA transfers

Control bits

Description

Reference

GDMA read/write

(opcode = 00h/01h)

MDMA (master) read/write

(opcode = 06h/07h)

DMA Conﬁguration register

ATA_MODE

set to logic 0 (non-ATA

set to logic 1 (ATA transfer)

Table 56

transfer)

DMA_MODE[1:0]

-

determines MDMA timing for

DIOR and DIOW strobes

DIS_XFER_CNT disables use of DMA transfer disables use of DMA transfer

counter counter

MODE[1:0]

determines active read/write determines active data

data strobe signals strobe(s)

WIDTH

selects DMA bus width: 8 or selects DMA bus width: 8 or

16 bits 16 bits

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Table 49. Control bits for Generic DMA transfers …continued

Control bits

Description

Reference

GDMA read/write

(opcode = 00h/01h)

MDMA (master) read/write

(opcode = 06h/07h)

DMA Hardware register

ENDIAN[1:0]

determines whether data is determines whether data is to Table 58

to be byte swapped or

normal; applicable only in

16-bit mode

be byte swapped or normal;

applicable only in 16-bit mode

EOT_POL

MASTER

selects polarity of the EOT

signal

input EOT is not used

set to logic 1 (master)

set to logic 0 (slave)

ACK_POL,

selects polarity of DMA

handshake signals

selects polarity of DMA

handshake signals

DREQ_POL,

WRITE_POL,

READ_POL

Table 50. Control bits for IDE-speciﬁed DMA transfers

Control bits

Description

Reference

MDMA read/write (opcode = 06h/07h)

DMA Conﬁguration register

ATA_MODE

set to logic 1 (ATA transfer)

Table 56

DMA_MODE[1:0]

PIO_MODE[2:0]

selects MDMA mode; timing are ATA(PI) compatible

selects PIO mode; timing are ATA(PI) compatible

DMA Hardware register

MASTER set to logic 0

Table 58

Remark: The DMA bus defaults to 3-state, until a DMA command is executed. All the

other control signals are not 3-stated.

9.4.1 DMA Command register (address: 30h)

The DMA Command register is a 1-byte register (for bit allocation, see Table 51) that

initiates all DMA transfer activity on the DMA controller. The register is write-only: reading

it will return FFh.

Remark: The DMA bus will be in 3-state, until a DMA command is executed.

Table 51. DMA Command register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

DMA_CMD[7:0]

1

Bus reset

Access

W

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Table 52. DMA Command register: bit description

Bit

Symbol

Description

7 to 0

DMA_CMD[7:0]

DMA command code, see Table 53.

PIO read or write that started using the DMA Command register

only performs a 16-bit transfer.

Table 53. DMA commands

Code

Name

Description

00h

GDMA Read

Generic DMA IN token transfer (slave mode only): Data is

transferred from the external DMA bus to the internal buffer.

Strobe: DIOW by the external DMA controller.

01h

GDMA Write

Generic DMA OUT token transfer (slave mode only): Data is

transferred from the internal buffer to the external DMA bus.

Strobe: DIOR by the external DMA controller.

02h to 05h

06h

-

reserved

MDMA Read

Multi-word DMA Read: Data is transferred from the external

DMA bus to the internal buffer.

07h

0Ah

MDMA Write

Read 1F0

Multi-word DMA Write: Data is transferred from the internal

buffer to the external DMA bus.

Read at address 1F0h: Initiates a PIO read cycle from Task File

1F0. Before issuing this command, the task ﬁle byte count must

be programmed at address 1F4h (LSByte) and 1F5h (MSByte).

0Bh

0Ch

Poll BSY

Poll BSY status bit for ATAPI device: Starts repeated PIO read

commands to poll the BSY status bit of the ATAPI device. When

BSY = 0, polling is terminated and an interrupt is generated. The

interrupt can be masked but the interrupt bit will still be set.

Therefore, you can manually poll this interrupt bit.

Read Task Files Read Task Files: Reads all task ﬁles. When Task File Index is

set to logic 0, this command reads all registers, except 1F0h and

1F7h. If Task File Index is not logic 0, the Task register of the

address set in the Task File register will be read. When the

reading is completed, an interrupt is generated. The interrupt

can be masked off, however, the interrupt bit will still be set.

Therefore, you can manually poll this interrupt bit.

0Dh

0Eh

-

reserved

Validate Buffer

Validate Buffer (for debugging only): Request from the

microcontroller to validate the endpoint buffer, following an

ATA-to-USB data transfer.

0Fh

Clear Buffer

Clear Buffer: Request from the microcontroller to clear the

endpoint buffer, after a DMA-to-USB data transfer. Logic 1 clears

the TX buffer of the indexed endpoint; the RX buffer is not

affected. The TX buffer is automatically cleared once data is

sent on the USB bus. This bit is set only when it is necessary to

forcefully clear the buffer.

Remark: If using double buffer, to clear both the buffers issue

the Clear Buffer command two times, that is, set and clear this

bit two times.

10h

Restart

Restart: Request from the microcontroller to move the buffer

pointers to the beginning of the endpoint FIFO.

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Table 53. DMA commands …continued

Code

Name

Description

11h

Reset DMA

Reset DMA: Initializes the DMA core to its power-on reset state.

Remark: When the DMA core is reset during the Reset DMA

command, the DREQ, DACK, DIOW and DIOR handshake pins

will temporarily be asserted. This can confuse the external DMA

controller. To prevent this, start the external DMA controller only

after the DMA reset.

12h

13h

MDMA stop

GDMA stop

MDMA stop: This command immediately stops the MDMA data

transfer. This is applicable for commands 06h and 07h only.

GDMA stop: This command stops the GDMA data transfer. Any

data in the OUT endpoint that is not transferred by the DMA will

remain in the buffer. The FIFO data for the IN endpoint will be

written to the endpoint buffer. An interrupt bit will be set to

indicate the completion of the DMA Stop command.

Remark: For the DMA OUT transfer, if the DMA Burst Counter

register is programmed to some value, for example 512 bytes,

and if a GDMA Stop command is issued in the middle of a

transfer, the transfer will continue until the end of the burst size

(512 bytes). Issuing a GDMA Stop command does not allow the

ISP1583 to stop in the middle of the burst. It can only be stopped

in between bursts.

14h to 20h

21h

-

reserved

Read Task File

register 1F1h

Read Task File register 1F1h: When reading is completed, an

interrupt is generated.

22h

Read Task File

register 1F2h

Read Task File register 1F2h: When reading is completed, an

interrupt is generated.

23h

Read Task File

register 1F3h

Read Task File register 1F3h: When reading is completed, an

interrupt is generated.

24h

Read Task File

register 1F4h

Read Task File register 1F4h: When reading is completed, an

interrupt is generated.

25h

Read Task File

register 1F5h

Read Task File register 1F5h: When reading is completed, an

interrupt is generated.

26h

Read Task File

register 1F6h

Read Task File register 1F6h: When reading is completed, an

interrupt is generated.

27h

Read Task File

register 3F6h

Read Task File register 3F6h: When reading is completed, an

interrupt is generated.

28h

Read Task File

register 3F7h

Read Task File register 3F7h: When reading is completed, an

interrupt is generated.

29h to FFh

-

reserved

9.4.2 DMA Transfer Counter register (address: 34h)

This 4-byte register sets up the total byte count for a DMA transfer (DMACR). It indicates

the remaining number of bytes left for transfer. The bit allocation is given in Table 54.

For IN endpoint — Because there is a FIFO in the ISP1583 DMA controller, some data

may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 bytes, and

the maximum delay time for data to be shifted to endpoint buffer is 60 ns.

For OUT endpoint — Data will not be cleared from the endpoint buffer, until all the data is

read from the DMA FIFO.

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If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when

it reaches zero.

Table 54. DMA Transfer Counter register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

DMACR4 = DMACR[31:24]

0

Bus reset

Access

Bit

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

DMACR3 = DMACR[23:16]

0

Bus reset

Access

Bit

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

R/W

8

Symbol

Reset

DMACR2 = DMACR[15:8]

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

4

R/W

3

R/W

2

R/W

1

R/W

0

Symbol

Reset

DMACR1 = DMACR[7:0]

0

Bus reset

Access

R/W

Table 55. DMA Transfer Counter register: bit description

Bit

Symbol

Description

31 to 24

23 to 16

15 to 8

7 to 0

DMACR4 = DMACR[31:24]

DMACR3 = DMACR[23:16]

DMACR2 = DMACR[15:8]

DMACR1 = DMACR[7:0]

DMA transfer counter byte 4 (MSByte)

DMA transfer counter byte 3

DMA transfer counter byte 2

DMA transfer counter byte 1 (LSByte)

9.4.3 DMA Conﬁguration register (address: 38h)

This register deﬁnes the DMA conﬁguration for GDMA mode. The DMA Conﬁguration

register consists of 2 bytes. The bit allocation is given in Table 56.

Table 56. DMA Conﬁguration register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

reserved

ATA_

DMA_MODE[1:0]

PIO_MODE[2:0]

MODE

Reset

-

0

Bus reset

Access

R/W

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Bit

7

6

5

4

3

2

1

0

Symbol

DIS_

reserved

MODE[1:0]

reserved

WIDTH

XFER_CNT

Reset

0

-

0

-

1

Bus reset

Access

R/W

Table 57. DMA Conﬁguration register: bit description

Bit

Symbol

Description^[1]

15 to 14

13

-

reserved

ATA_MODE

ATA Mode: Mode selection of the DMA core.

0 — Conﬁgures the DMA core for non-ATA mode. Used when issuing

DMA commands 00h and 01h.

1 — Conﬁgures the DMA core for ATA or MDMA mode. Used when

issuing DMA commands 02h to 07h, 0Ah and 0Ch; also used when

directly accessing Task File registers.

12 to 11 DMA_MODE

[1:0]

DMA Mode: These bits affect the timing for MDMA mode.

00 — MDMA mode 0: ATA(PI) compatible timing

01 — MDMA mode 1: ATA(PI) compatible timing

10 — MDMA mode 2: ATA(PI) compatible timing

11 — MDMA mode 3: enables the DMA Strobe Timing register (see

Table 78 and Table 79) for non-standard strobe durations; only used in

MDMA mode

10 to 8

PIO_MODE

[2:0]^[2]

PIO Mode: These bits affect the PIO timing.

000 to 100 — PIO mode 0 to 4: ATA(PI) compatible timing

101 to 111 — reserved

7

DIS_XFER_

CNT

Disable Transfer Count: Logic 1 disables the DMA Transfer Counter

(see Table 54). The transfer counter can be disabled only in GDMA

slave mode; in master mode the counter is always enabled.

6 to 4

3 to 2

-

reserved

MODE[1:0]

Mode: These bits only affect GDMA (slave) and MDMA (master)

handshake signals.

00 — DIOR (master) or DIOW (slave): strobes data from the DMA bus

into the ISP1583; DIOW (master) or DIOR (slave): puts data from the

ISP1583 on the DMA bus.

01 — DIOR (master) or DACK (slave): strobes data from the DMA bus

into the ISP1583; DACK (master) or DIOR (slave): puts data from the

ISP1583 on the DMA bus.

10 — DACK (master and slave): strobes data from the DMA bus into

the ISP1583 and also puts data from the ISP1583 on the DMA bus.

11 — reserved

1

0

-

reserved

WIDTH

Width: This bit selects the DMA bus width for GDMA (slave) and

MDMA (master).

0 — 8-bit data bus

1 — 16-bit data bus

[1] The DREQ pin will be driven only after performing a write access to the DMA Conﬁguration register (that is,

after conﬁguring the DMA Conﬁguration register).

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[2] PIO read or write that started using the DMA Command register only performs 16-bit transfer.

9.4.4 DMA Hardware register (address: 3Ch)

The DMA Hardware register consists of 1 byte. The bit allocation is shown in Table 58.

This register determines the polarity of bus control signals (EOT, DACK, DREQ, DIOR and

DIOW) and DMA mode (master or slave). It also controls whether the upper and lower

parts of the data bus are swapped (bits ENDIAN[1:0]), for modes GDMA (slave) and

MDMA (master) only.

Table 58. DMA Hardware register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

ENDIAN[1:0]

EOT_POL

MASTER

ACK_POL

DREQ_

POL

WRITE_

POL

READ_

POL

Reset

0

1

0

Bus reset

Access

R/W

Table 59. DMA Hardware register: bit description

Bit Symbol Description

7 to 6 ENDIAN[1:0] Endian: These bits determine whether the data bus is swapped between

the internal RAM and the DMA bus. This only applies for modes GDMA

(slave) and MDMA (master).

00 — Normal data representation; 16-bit bus: MSByte on DATA[15:8] and

LSByte on DATA[7:0].

01 — Swapped data representation; 16-bit bus: MSByte on DATA[7:0] and

LSByte on DATA[15:8].

10 — reserved

11 — reserved

Remark: While operating with the 8-bit data bus, bits ENDIAN[1:0] must

always be set to logic 00.

5

EOT_POL

EOT Polarity: Selects the polarity of the End-Of-Transfer input; used in

GDMA slave mode only.

0 — EOT is active LOW

1 — EOT is active HIGH

4

3

MASTER

ACK_POL

Master or Slave Selection: Selects DMA master or slave mode.

0 — GDMA slave mode

1 — MDMA master mode

Acknowledgment Polarity: Selects the DMA acknowledgment polarity.

0 — DACK is active LOW

1 — DACK is active HIGH

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Table 59. DMA Hardware register: bit description …continued

Bit

Symbol

Description

2

DREQ_POL DREQ Polarity: Selects the DMA request polarity.

0 — DREQ is active LOW

1 — DREQ is active HIGH

1

0

WRITE_POL Write Polarity: Selects the DIOW strobe polarity.

0 — DIOW is active LOW

1 — DIOW is active HIGH

READ_POL Read Polarity: Selects the DIOR strobe polarity.

0 — DIOR is active LOW

1 — DIOR is active HIGH

9.4.5 Task File registers (addresses: 40h to 4Fh)

These registers allow direct access to the internal registers of an ATAPI peripheral using

PIO mode. The supported Task File registers and their functions are shown in Table 60.

The correct peripheral register is automatically addressed using pins CS1_N, CS0_N,

DA2, MODE0/DA1 and BUS_CONF/DA0 (see Table 61).

Table 60. Task File register functions

Task ﬁle

1F0

ATA function

ATAPI function

data (16-bit)

1F1

error/feature

1F2

sector count

interrupt reason

reserved

1F3

sector number/LBA[7:0]

cylinder low/LBA[15:8]

cylinder high/LBA[23:16]

drive/head/LBA[27:24]

command

1F4

cylinder low

1F5

cylinder high

drive select

1F6

1F7

status/command

alternate status/command

reserved

3F6

alternate status/command

drive address

3F7

Table 61. ATAPI peripheral register addressing

Task ﬁle

1F0

CS1_N

HIGH

LOW

CS0_N

LOW

HIGH

DA2

MODE0/DA1 BUS_CONF/DA0

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

1F1

1F2

1F3

1F4

1F5

1F6

1F7

3F6

3F7

LOW

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In 8-bit bus mode, 16-bit Task File register 1F0 requires two consecutive write/read

accesses before the proper PIO write/read is generated on the IDE interface. The ﬁrst

byte is always the lower byte (LSByte). Other Task File registers can directly be accessed.

Writing to Task File registers can be done in any order, except for the Task File register

1F7, which must be written last.

Table 62. Task File 1F0 register (address: 40h): bit allocation

CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = LOW, BUS_CONF/DA0 = LOW.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

data (ATA or ATAPI)

0

Bus reset

Access

R/W

Table 63. Task File 1F1 register (address: 48h): bit allocation

CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = LOW, BUS_CONF/DA0 = HIGH.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

error/feature (ATA or ATAPI)

0

Bus reset

Access

R/W

Table 64. Task File 1F2 register (address: 49h): bit allocation

CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

sector count (ATA) or interrupt reason (ATAPI)

0

Bus reset

Access

R/W

Table 65. Task File 1F3 register (address: 4Ah): bit allocation

CS1_N = HIGH, CS0_N = LOW, DA2 = LOW, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

sector number/LBA[7:0] (ATA), reserved (ATAPI)

0

Bus reset

Access

R/W

Table 66. Task File 1F4 register (address: 4Bh): bit allocation

CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = LOW, BUS_CONF/DA0 = LOW.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

cylinder low/LBA[15:8] (ATA) or cylinder low (ATAPI)

0

Bus reset

Access

R/W

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Table 67. Task File 1F5 register (address: 4Ch): bit allocation

CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = LOW, BUS_CONF/DA0 = HIGH.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

cylinder high/LBA[23:16] (ATA) or cylinder high (ATAPI)

0

Bus reset

Access

R/W

Table 68. Task File 1F6 register (address: 4Dh): bit allocation

CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

drive/head/LBA[27:24] (ATA) or drive (ATAPI)

0

Bus reset

Access

R/W

Table 69. Task File 1F7 register (address: 44h): bit allocation

CS1_N = HIGH, CS0_N = LOW, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

command (ATA) or status^[1]/command (ATAPI)

0

Bus reset

Access

W

[1] Task File register 1F7 is a write-only register; a read will return FFh.

Table 70. Task File 3F6 register (address: 4Eh): bit allocation

CS1_N = LOW, CS0_N = HIGH, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = LOW.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

alternate status/command (ATA or ATAPI)

0

Bus reset

Access

R/W

Table 71. Task File 3F7 register (address: 4Fh): bit allocation

CS1_N = LOW, CS0_N = HIGH, DA2 = HIGH, MODE0/DA1 = HIGH, BUS_CONF/DA0 = HIGH.

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

drive address (ATA) or reserved (ATAPI)

0

Bus reset

Access

R/W

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9.4.6 DMA Interrupt Reason register (address: 50h)

This 2-byte register shows the source(s) of DMA interrupt. Each bit is refreshed after a

DMA command is executed. An interrupt source is cleared by writing logic 1 to the

corresponding bit. On detecting the interrupt, the external microprocessor must read the

DMA Interrupt Reason register and mask it with the corresponding bits in the DMA

Interrupt Enable register to determine the source of the interrupt.

The bit allocation is given in Table 72.

Table 72. DMA Interrupt Reason register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

TEST3

reserved

GDMA_

STOP

EXT_EOT

INT_EOT

INTRQ_

PENDING XFER_OK

DMA_

Reset

0

-

0

Bus reset

Access

Bit

0

R/W

0

R/W

R

7

-

R/W

3

R/W

2

R/W

1

6

5

4

0

Symbol

reserved

READ_1F0

BSY_

DONE

TF_RD_

DONE

CMD_

INTRQ_OK

reserved

Reset

-

0

-

Bus reset

Access

R/W

Table 73. DMA Interrupt Reason register: bit description

Bit

Symbol

Description

15

TEST3

This bit is set when a DMA transfer for a packet (OUT transfer)

terminates before the whole packet is transferred. This bit is a

status bit, and the corresponding mask bit of this register is always

0. Writing any value other than 0 has no effect.

14 to 13

12

-

reserved

GDMA_STOP

GDMA Stop: When the GDMA_STOP command is issued to DMA

Command registers, it means the DMA transfer has successfully

terminated.

11

10

9

EXT_EOT

INT_EOT

External EOT: Logic 1 indicates that an external EOT is detected.

This is applicable only in GDMA slave mode.

Internal EOT: Logic 1 indicates that an internal EOT is detected;

see Table 74.

INTRQ_

Interrupt Pending: Logic 1 indicates that a pending interrupt was

PENDING

detected on pin INTRQ.

8

DMA_XFER_OK

DMA Transfer OK: Logic 1 indicates that the DMA transfer is

completed (DMA Transfer Counter has become zero). This bit is

only used in GDMA (slave) mode and MDMA (master) mode.

7 to 5

4

-

reserved

READ_1F0

Read 1F0: Logic 1 indicates that the 1F0 FIFO contains unread

data and the microcontroller can start reading data.

3

BSY_DONE

Busy Done: Logic 1 indicates that the BSY status bit has become

zero and polling has been stopped.

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Table 73. DMA Interrupt Reason register: bit description …continued

Bit

Symbol

Description

2

TF_RD_DONE

Task File Read Done: Logic 1 indicates that the Read Task Files

command has been completed.

1

0

CMD_INTRQ_OK Command Interrupt OK: Logic 1 indicates that all bytes from the

FIFO have been transferred (DMA Transfer Count zero) and an

interrupt on pin INTRQ was detected.

-

reserved

Table 74. Internal EOT-functional relation with DMA_XFER_OK bit

INT_EOT DMA_XFER_OK Description

1

0

1

During the DMA transfer, there is a premature termination with

short packet.

DMA transfer is completed with short packet and the DMA

transfer counter has reached 0.

DMA transfer is completed without any short packet and the DMA

transfer counter has reached 0.

9.4.7 DMA Interrupt Enable register (address: 54h)

This 2-byte register controls the interrupt generation of the source bits in the DMA

Interrupt Reason register (see Table 72). The bit allocation is given in Table 75. The bit

description is given in Table 73.

Logic 1 enables the interrupt generation. After a bus reset, interrupt generation is

disabled, with values turning to logic 0.

Table 75. DMA Interrupt Enable register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

TEST4

reserved

IE_GDMA_

STOP

IE_EXT_

EOT

IE_INT_

EOT

IE_INTRQ_ IE_DMA_

PENDING XFER_OK

Reset

0

-

0

Bus reset

Access

Bit

0

R/W

0

R/W

R

7

-

R/W

4

R/W

3

R/W

2

6

5

1

0

Symbol

reserved

IE_

READ_1F0

IE_BSY_

DONE

IE_TF_

RD_DONE INTRQ_OK

IE_CMD_

reserved

Reset

-

0

-

Bus reset

Access

R/W

9.4.8 DMA Endpoint register (address: 58h)

This 1-byte register selects a USB endpoint FIFO as a source or destination for DMA

transfers. The bit allocation is given in Table 76.

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Table 76. DMA Endpoint register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

reserved

EPIDX[2:0]

DMADIR

-

0

Bus reset

Access

R/W

Table 77. DMA Endpoint register: bit description

Bit

Symbol

-

Description

7 to 4

3 to 1

0

reserved

EPIDX[2:0]

DMADIR

Endpoint Index: selects the indicated endpoint for DMA access

DMA Direction:

0 — Selects the RX/OUT FIFO for DMA read transfers

1 — Selects the TX/IN FIFO for DMA write transfers

The DMA Endpoint register must not reference the endpoint that is indexed by the

Endpoint Index register (2Ch) at any time. Doing so will result in data corruption.

Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the

DMA Endpoint register, however, is pointed to an active endpoint, the ﬁrmware must not

reference the same endpoint on the Endpoint Index register.

9.4.9 DMA Strobe Timing register (address: 60h)

This 1-byte register controls the strobe timing for MDMA mode, when bits

DMA_MODE[1:0] in the DMA Conﬁguration register have been set to 03h.

The bit allocation is given in Table 78.

Table 78. DMA Strobe Timing register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

Reset

reserved

DMA_STROBE_CNT[4:0]

-

1

Bus reset

Access

R/W

Table 79. DMA Strobe Timing register: bit description

Bit

Symbol

Description

7 to 5

-

reserved

4 to 0 DMA_STROBE_ DMA Strobe Count: These bits select the strobe duration for

CNT[4:0]

DMA_MODE = 03h (see Table 56). The strobe duration is (N + 1)

cycles^[1], with N representing the value of DMA_STROBE_CNT (see

Figure 17).

[1] The cycle duration indicates the internal clock cycle (33.3 ns/cycle).

ISP1583_7

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x

(N + 1) cycles

004aaa125

Fig 17. Programmable strobe timing

9.4.10 DMA Burst Counter register (address: 64h)

Table 80 shows the bit allocation of the 2-byte register.

Table 80. DMA Burst Counter register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved

BURSTCOUNTER[12:8]

-

0

Bus reset

Access

Bit

-

R/W

4

R/W

1

R/W

0

7

6

5

3

2

Symbol

Reset

BURSTCOUNTER[7:0]

0

1

0

Bus reset

Access

R/W

Table 81. DMA Burst Counter register: bit description

Bit

Symbol

Description

15 to 13

12 to 0

-

reserved

BURSTCOUNTER Burst Counter: This register deﬁnes the burst length. The

[12:0]

counter must be programmed to be a multiple of two in 16-bit

mode. The value of the burst counter must be programmed so

that the burst counter is a factor of the buffer size.

It is used to determine the assertion and deassertion of DREQ.

9.5 General registers

9.5.1 Interrupt register (address: 18h)

The Interrupt register consists of 4 bytes. The bit allocation is given in Table 82.

When a bit is set in the Interrupt register, it indicates that the hardware condition for an

interrupt has occurred. When the Interrupt register content is nonzero, the INT output will

be asserted corresponding to the Interrupt Enable register. On detecting the interrupt, the

external microprocessor must read the Interrupt register and mask it with the

corresponding bits in the Interrupt Enable register to determine the source of the interrupt.

Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various

bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset.

The DMA controller only has one interrupt bit: the source for a DMA interrupt is shown in

the DMA Interrupt Reason register (see Table 72 and Table 73).

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Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can

be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt

Reason register, followed by writing logic 1 to the DMA bit of the Interrupt register.

Table 82. Interrupt register: bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

reserved

EP7TX

EP7RX

-

0

Bus reset

Access

Bit

-

0

-

R/W

23

22

21

20

19

18

17

16

Symbol

Reset

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

EP3TX

EP3RX

0

Bus reset

Access

Bit

0

R/W

10

0

R/W

15

R/W

14

R/W

11

R/W

13

12

9

8

Symbol

Reset

EP2TX

0

EP2RX

0

EP1TX

EP1RX

EP0TX

0

EP0RX

0

reserved

EP0SETUP

0

-

0

Bus reset

Access

Bit

0

-

0

R/W

7

R/W

6

R/W

3

R/W

2

R/W

5

4

1

0

Symbol

Reset

VBUS

0

DMA

0

HS_STAT

RESUME

SUSP

0

PSOF

0

SOF

0

BRESET

0

1

Bus reset

Access

0

R/W

Table 83. Interrupt register: bit description

Bit

31 to 26

25

Symbol

-

Description

reserved

EP7TX

EP7RX

EP6TX

EP6RX

EP5TX

EP5RX

EP4TX

EP4RX

EP3TX

EP3RX

EP2TX

EP2RX

EP1TX

EP1RX

EP0TX

logic 1 indicates the endpoint 7 TX buffer as interrupt source

logic 1 indicates the endpoint 7 RX buffer as interrupt source

logic 1 indicates the endpoint 6 TX buffer as interrupt source

logic 1 indicates the endpoint 6 RX buffer as interrupt source

logic 1 indicates the endpoint 5 TX buffer as interrupt source

logic 1 indicates the endpoint 5 RX buffer as interrupt source

logic 1 indicates the endpoint 4 TX buffer as interrupt source

logic 1 indicates the endpoint 4 RX buffer as interrupt source

logic 1 indicates the endpoint 3 TX buffer as interrupt source

logic 1 indicates the endpoint 3 RX buffer as interrupt source

logic 1 indicates the endpoint 2 TX buffer as interrupt source

logic 1 indicates the endpoint 2 RX buffer as interrupt source

logic 1 indicates the endpoint 1 TX buffer as interrupt source

logic 1 indicates the endpoint 1 RX buffer as interrupt source

logic 1 indicates the endpoint 0 data TX buffer as interrupt source

24

23

22

21

20

19

18

17

16

15

14

13

12

11

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Table 83. Interrupt register: bit description …continued

Bit

10

9

Symbol

EP0RX

-

Description

logic 1 indicates the endpoint 0 data RX buffer as interrupt source

reserved

8

EP0SETUP logic 1 indicates that a SETUP token was received on endpoint 0

7

VBUS

DMA

logic 1 indicates a transition from LOW to HIGH on V_BUS

6

DMA status: Logic 1 indicates a change in the DMA Interrupt Reason

register.

5

HS_STAT

High-Speed Status: Logic 1 indicates a change from full-speed to

high-speed mode (HS connection). This bit is not set, when the system

goes into full-speed suspend.

4

3

2

RESUME

SUSP

Resume Status: Logic 1 indicates that a status change from suspend

to resume (active) was detected.

Suspend Status: Logic 1 indicates that a status change from active to

suspend was detected on the bus.

PSOF

Pseudo SOF Interrupt: Logic 1 indicates that a pseudo SOF or µSOF

was received. Pseudo SOF is an internally generated clock signal

(full-speed: 1 ms period, high-speed: 125 µs period) that is not

synchronized to the USB bus SOF or µSOF.

1

0

SOF

SOF Interrupt: Logic 1 indicates that a SOF or µSOF was received.

BRESET

Bus Reset: Logic 1 indicates that a USB bus reset was detected. When

bit OTG in the OTG register is set, BRESET will not be set, instead, this

interrupt bit will report SE0 on DP and DM for 2 ms.

9.5.2 Chip ID register (address: 70h)

This read-only register contains the chip identiﬁcation and hardware version numbers.

The ﬁrmware must check this information to determine functions and features supported.

The register contains 3 bytes, and the bit allocation is shown in Table 84.

Table 84. Chip ID register: bit allocation

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

CHIPID[15:8]

0

1

0

1

0

1

Bus reset

Access

Bit

R

9

R

8

15

14

13

12

11

10

Symbol

Reset

CHIPID[7:0]

1

0

1

0

Bus reset

Access

Bit

R

7

R

6

R

5

R

4

R

3

R

2

R

1

R

0

Symbol

Reset

VERSION[7:0]

0

1

0

Bus reset

Access

R

ISP1583_7

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Hi-Speed USB peripheral controller

Table 85. Chip ID register: bit description

Bit

Symbol

Description

23 to 16

15 to 8

7 to 0

CHIPID[15:8]

CHIPID[7:0]

VERSION[7:0]

Chip ID: lower byte (15h)

Chip ID: upper byte (82h)

Version: version number (30h)

9.5.3 Frame Number register (address: 74h)

This read-only register contains the frame number of the last successfully received

Start-Of-Frame (SOF). The register contains 2 bytes, and the bit allocation is given in

Table 86. In case of 8-bit access, the register content is returned lower byte ﬁrst.

Table 86. Frame Number register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

reserved

MICROSOF[2:0]

SOFR[10:8]

-

0

Bus reset

Access

Bit

-

R

5

R

4

R

3

R

2

R

1

R

0

7

6

Symbol

Reset

SOFR[7:0]

0

Bus reset

Access

R

Table 87. Frame Number register: bit description

Bit

Symbol

Description

15 to 14

13 to 11

10 to 0

-

reserved

MICROSOF[2:0]

SOFR[10:0]

microframe number

frame number

9.5.4 Scratch register (address: 78h)

This 16-bit register can be used by the ﬁrmware to save and restore information. For

example, the device status before it enters the suspend state. The bit allocation is given in

Table 88.

Table 88. Scratch register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

SFIRH[7:0]

0

Bus reset

Access

Bit

R/W

7

R/W

6

R/W

5

R/W

3

R/W

2

R/W

1

R/W

0

4

Symbol

Reset

SFIRL[7:0]

0

Bus reset

Access

R/W

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

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ISP1583

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Hi-Speed USB peripheral controller

Table 89. Scratch register: bit description

Bit

Symbol

Description

15 to 8

7 to 0

SFIRH[7:0]

SFIRL[7:0]

Scratch ﬁrmware information register (higher byte)

Scratch ﬁrmware information register (lower byte)

9.5.5 Unlock Device register (address: 7Ch)

To protect registers from getting corrupted when the ISP1583 goes into suspend, the write

operation is disabled if bit PWRON in the Mode register is set to logic 0. In this case, when

the chip resumes, the Unlock Device command must ﬁrst be issued to this register before

attempting to write to the rest of the registers. This is done by writing unlock code (AA37h)

to this register. The bit allocation of the Unlock Device register is given in Table 90.

Table 90. Unlock Device register: bit allocation

Bit

15

14

13

12

11

10

9

8

Symbol

Reset

ULCODE[15:8] = AAh

not applicable

Bus reset

Access

Bit

not applicable

W

7

6

5

4

3

2

1

0

Symbol

Reset

ULCODE[7:0] = 37h

not applicable

Bus reset

Access

not applicable

W

Table 91. Unlock Device register: bit description

Bit

Symbol

Description

15 to 0

ULCODE[15:0]

Unlock Code: Writing data AA37h unlocks internal registers and

FIFOs for writing, following a resume.

When bit PWRON in the Mode register is logic 1, the chip is powered. In such a case, you

do not need to issue the Unlock command because the microprocessor is powered and

therefore, the RW_N/RD_N, DS_N/WR_N and CS_N signals maintain their states.

When bit PWRON is logic 0, the RW_N/RD_N, DS_N/WR_N and CS_N signals are

ﬂoating because the microprocessor is not powered. To protect the ISP1583 registers

from being corrupted during suspend, register write is locked when the chip goes into

suspend. Therefore, you need to issue the Unlock command to unlock the ISP1583

registers.

9.5.6 Test Mode register (address: 84h)

This 1-byte register allows the ﬁrmware to set the DP and DM pins to predetermined

states for testing purposes. The bit allocation is given in Table 92.

Remark: Only one bit can be set at a time. Either bit FORCEHS or FORCEFS must be set

to logic 1 at a time. Of the four bits PRBS, KSTATE, JSTATE and SE0_NAK only one bit

must be set at a time. This must be implemented for the Hi-Speed USB logo compliance

testing. To exit test mode, power cycle is required.

ISP1583_7

Product data sheet

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ISP1583

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Hi-Speed USB peripheral controller

Table 92. Test Mode register: bit allocation

Bit

7

FORCEHS

0

6

5

4

FORCEFS

0

3

PRBS

0

2

1

JSTATE

0

Symbol

Reset

reserved

KSTATE

SE0_NAK

-

0

Bus reset

Access

unchanged

R/W

unchanged

R/W

0

R/W

Table 93. Test Mode register: bit description

Bit

Symbol

Description

7

FORCEHS Force High-Speed: Logic 1 forces the hardware to high-speed mode only

and disables the chirp detection logic.

6 to 5

4

-

reserved

FORCEFS Force Full-Speed: Logic 1 forces the physical layer to full-speed mode only

and disables the chirp detection logic.

3

PRBS

Predetermined Random Pattern: Logic 1 sets the DP and DM pins to

toggle in a predetermined random pattern.

2

1

0

KSTATE

JSTATE

K-State: Logic 1 sets the DP and DM pins to the K state.

J-State: Logic 1 sets the DP and DM pins to the J state.

SE0_NAK

SE0 NAK: Logic 1 sets the DP and DM pins to a high-speed quiescent

state. The device only responds to a valid high-speed IN token with a NAK.

ISP1583_7

Product data sheet

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ISP1583

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Hi-Speed USB peripheral controller

10. Limiting values

Table 94. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC(3V3)

V_CC(I/O)

V_I

Parameter

Conditions

Min

−0.5

-

Max

Unit

V

supply voltage (3.3 V)

input/output supply voltage

input voltage

+4.6

V

[1]

V_CC(3V3)+ 0.5

100

V

I_lu

latch-up current

V_I< 0 V or V_I> V_CC(3V3)

mA

V_esd

electrostatic discharge voltage

I_LI< 1 µA

pins DP, DM, V_BUS, AGND

and DGND

−4000

+4000

V

other pins

−2000

−40

+2000

+125

V

T_stg

storage temperature

°C

[1] The maximum value for 5 V tolerant pins is 6 V.

11. Recommended operating conditions

Table 95. Recommended operating conditions

Symbol Parameter

Conditions

Min

3.0

1.65

0

Typ

Max

3.6

Unit

V_CC(3V3)supply voltage (3.3 V)

-

V

V_CC(I/O)

V_I

input/output supply voltage

input voltage

3.6

V_CC(3V3)= 3.3 V

V_CC(I/O)

3.6

V_IA(I/O)

input voltage on analog I/O

pins

on pins DP and DM

0

V_(pu)OD

T_amb

T_j

open-drain pull-up voltage

ambient temperature

junction temperature

0

-

V_CC(3V3)

+85

V

−40

°C

+125

12. Static characteristics

Table 96. Static characteristics: supply pins

V_CC(3V3)= 3.3 V ± 0.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; typical values at T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Supply voltage

V_CC(3V3)supply voltage (3.3 V)

Parameter

Conditions

Min

Typ

Max

Unit

3.0

3.3

47

3.6

60

25

-

V

I_{CC(3V3)(oper)}operating supply current (3.3 V) high-speed

full-speed

-

mA

µA

19

I_{CC(3V3)(susp)}suspend mode supply current

(3.3 V)

160

I/O pad supply voltage

V_CC(I/O)

input/output supply voltage

1.65

3.3

3.6

V

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

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ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 96. Static characteristics: supply pins …continued

V_CC(3V3)= 3.3 V ± 0.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; typical values at T_amb= +25 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

[1]

I_CC(I/O)

supply current on pin V_CC(I/O)

-

3

-

mA

Regulated supply voltage

V_CC(1V8)supply voltage (1.8 V)

with voltage converter

1.65

1.8

1.95

V

[1] I_CC(I/O)test condition: device set up under the test mode vector and I/O is subjected to external conditions.

Table 97. Static characteristics: digital pins

V_CC(I/O)= 1.65 V to 3.6 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Input levels

V_IL

Parameter

Conditions

Min

Typ

Max

Unit

LOW-level input voltage

HIGH-level input voltage

-

0.3V_CC(I/O)

-

V

V_IH

0.7V_CC(I/O)

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

I_OL= rated drive

I_OH= rated drive

-

0.15V_CC(I/O)

-

V

V_OH

0.8V_CC(I/O)

Leakage current

I_LIinput leakage current

[1]

−5

-

+5

µA

[1] This value is applicable to transistor input only. The value will be different if internal pull-up or pull-down resistors are used.

Table 98. Static characteristics: OTG detection

V_CC(I/O)= 1.65 V to 3.6 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Charging and discharging resistor

R_DN(VBUS)

R_UP(DP)

pull-down resistance on pin

V_BUS

only when bit DISCV is

set in the OTG register

680

300

800

550

1030

780

Ω

pull-up resistance on pin DP

only when bit DP is set

in the OTG register

Comparator levels

V_BVALID

V_BUSvalid detection

V_BUSB-session end detection

2.0

0.2

-

4.0

0.8

V

V_SESEND

Table 99. Static characteristics: analog I/O pins DP and DM

V_CC(3V3)= 3.3 V ± 0.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.^[1]

Symbol

Input levels

V_DI

Parameter

Conditions

Min

Typ

Max

Unit

differential input sensitivity voltage |V_I(DP)− V_I(DM)

|

0.2

0.8

-

V

V_CM

differential common mode voltage includes V_DIrange

range

2.5

V_SE

V_IL

single-ended receiver threshold

LOW-level input voltage

0.8

-

2.0

0.8

-

V

V_IH

HIGH-level input voltage

2.0

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

66 of 99

ISP1583

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Hi-Speed USB peripheral controller

Table 99. Static characteristics: analog I/O pins DP and DM …continued

V_CC(3V3)= 3.3 V ± 0.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.^[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Schmitt-trigger inputs

V_th(LH)

V_th(HL)

V_hys

positive-going threshold voltage

1.4

0.9

0.4

-

1.9

1.5

0.7

V

negative-going threshold voltage

hysteresis voltage

Output levels

V_OL

LOW-level output voltage

HIGH-level output voltage

R_L= 1.5 kΩ to 3.6 V

R_L= 15 kΩ to GND

-

0.4

3.6

V

V_OH

2.8

Leakage current

I_LZ

OFF-state leakage current

0 V < V_I< 3.3 V

pin to GND

−10

-

+10

10

µA

Capacitance

C_in

input capacitance

-

pF

Resistance

Z_DRV

driver output impedance for driver steady-state drive

which is not high-speed capable

40.5

10

-

49.5

-

Ω

Z_INP

input impedance exclusive of

pull-up/pull-down (for

low-/full-speed)

MΩ

[1] Pin DP is the USB positive data pin, and pin DM is the USB negative data pin.

13. Dynamic characteristics

Table 100. Dynamic characteristics

V_CC(3V3)= 3.3 V ± 0.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Reset

Parameter

Conditions

Min

Typ

Max

Unit

t_{W(RESET_N)}external RESET_N pulse width

crystal oscillator running

500

-

µs

Crystal oscillator

f_XTAL1

R_S

frequency on pin XTAL1

series resistance

-

12

-

MHz

Ω

100

-

C_L

load capacitance

18

pF

External clock input

t_J

δ

external clock jitter

-

500

55

3

ps

%

ns

V

clock duty cycle

rise time

45

50

-

t_r

-

t_f

fall time

-

3

V_I

input voltage

1.65

1.8

1.95

ISP1583_7

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ISP1583

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Hi-Speed USB peripheral controller

Table 101. Dynamic characteristics: analog I/O pins DP and DM

V_CC(3V3)= 3.3 V ± 0.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; C_L= 50 pF; R_PU= 1.5 kΩ on DP to V_TERM; test circuit of

Figure 38; unless otherwise speciﬁed.

Symbol Parameter

Driver characteristics

Full-speed mode

Conditions

Min

Typ

Max

Unit

t_FR

rise time

C_L= 50 pF; 10 % to 90 % of |V_OH

−

4

-

20

ns

%

V

V_OL

C_L= 50 pF; 90 % to 10 % of |V_OH

V_OL

|

t_FF

fall time

4

20

|

[1]

FRFM

V_CRS

differential rise time/fall time

matching

t_FR/t_FF

90

1.3

111.11

2.0

[1][2]

output signal crossover voltage

High-speed mode

t_HSRrise time (10 % to 90 %)

t_HSFfall time (10 % to 90 %)

with captive cable

500

-

ps

Data source timing

Full-speed mode

[2]

t_FEOPT

t_FDEOP

source SE0 interval of EOP

see Figure 18

160

-

175

+5

ns

source jitter for differential

transition to SE0 transition

−2

Receiver timing

Full-speed mode

[2]

t_JR1

receiver jitter to next transition

see Figure 19

−18.5

−9

-

+18.5

+9

ns

t_JR2

receiver jitter for paired transitions see Figure 19

t_FEOPR

t_FST

receiver SE0 interval of EOP

accepted as EOP; see Figure 18

rejected as EOP; see Figure 20

82

-

width of SE0 interval during

differential transition

-

14

[1] Excluding the ﬁrst transition from the idle state.

[2] Characterized only, not tested. Limits guaranteed by design.

T

PERIOD

+3.3 V

crossover point

extended

crossover point

differential

data lines

0 V

differential data to

SE0/EOP skew

N × T + t

source EOP width: t

EOPT

receiver EOP width: t

EOPR

mgr776

PERIOD

DEOP

T_PERIODis the bit duration corresponding to the USB data rate.

Full-speed timing symbols have a subscript preﬁx ‘F’, low-speed timing symbols have a preﬁx ‘L’.

Fig 18. Source differential data-to-EOP transition skew and EOP width

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

68 of 99

ISP1583

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Hi-Speed USB peripheral controller

T

PERIOD

+3.3 V

differential

data lines

0 V

mgr871

t

JR2

JR

JR1

consecutive

transitions

N × T

+ t

PERIOD

JR1

paired

transitions

N × T

+ t

PERIOD

JR2

T_PERIODis the bit duration corresponding to the USB data rate.

Fig 19. Receiver differential data jitter

t

FST

+3.3 V

V

IH(min)

differential

data lines

0 V

mgr872

Fig 20. Receiver SE0 width tolerance

13.1 Register access timing

Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and

ALE/A0 refer to the ISP1583 pin.

13.1.1 Generic processor mode

BUS_CONF/DA0 = HIGH: generic processor mode

13.1.1.1 8051 mode

MODE0/DA1 = HIGH: 8051 mode; see Table 3

Table 102. ISP1583 register access timing parameters: separate address and data buses

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Reading

t_RLRH

Parameter

Conditions

Min

Typ

Max

Unit

RW_N/RD_N LOW pulse width

> t_RLDV

-

ns

t_AVRL

address set-up time before RW_N/RD_N LOW

address hold time after RW_N/RD_N HIGH

RW_N/RD_N LOW to data valid delay

RW_N/RD_N HIGH to data outputs 3-state delay

RW_N/RD_N HIGH to CS_N HIGH delay

0

-

t_RHAX

-

t_RLDV

26

15

-

t_RHDZ

0

t_RHSH

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

69 of 99

ISP1583

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Hi-Speed USB peripheral controller

Table 102. ISP1583 register access timing parameters: separate address and data buses …continued

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_SLRL

Parameter

Conditions

Min

Typ

Max

Unit

CS_N LOW to RW_N/RD_N LOW delay

2

-

ns

Writing

t_WLWH

t_AVWL

DS_N/WR_N LOW pulse width

15

0

-

ns

address set-up time before DS_N/WR_N LOW

address hold time after DS_N/WR_N HIGH

data set-up time before DS_N/WR_N HIGH

data hold time after DS_N/WR_N HIGH

DS_N/WR_N HIGH to CS_N HIGH delay

CS_N LOW to DS_N/WR_N LOW delay

t_WHAX

t_DVWH

t_WHDZ

t_WHSH

t_SLWL

0

11

5

0

2

General

T_cy(RW)

t_RDY1

read or write cycle time

50

-

ns

READY/IORDY HIGH to RW_N/RD_N or

DS_N/WR_N HIGH of the last access

91

T

cy(RW)

t

WHSH

t

SLWL

t

RHSH

CS_N

t

WHAX

t

SLRL

t

RHAX

[

]

A 7:0

t

RLDV

RHDZ

[

]

(read) DATA 15:0

t

AVRL

RLRH

RW_N/RD_N

t

WHDZ

AVWL

[

]

(write) DATA 15:0

t

DVWH

t

WLWH

DS_N/WR_N

004aaa301

Fig 21. ISP1583 register access timing: separate address and data buses (8051 mode)

ISP1583_7

Product data sheet

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ISP1583

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DS_N/WR_N,

RW_N/RD_N

READY/IORDY

004aaa920

t

RDY1

Fig 22. ISP1583 ready signal timing

13.1.1.2 Freescale mode

MODE0/DA1 = LOW: Freescale mode; see Table 3

Table 103. ISP1583 register access timing parameters: separate address and data buses

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Reading or writing

Conditions

Min

Typ

Max

Unit

t_WLWH

t_AVWL

DS_N/WR_N LOW pulse width

15

0

-

ns

address set-up time before DS_N/WR_N LOW

address hold time after DS_N/WR_N HIGH

data set-up time before DS_N/WR_N HIGH

data hold time after DS_N/WR_N HIGH

t_WHAX

t_DVWH

t_WHDZ

t_WHSH

t_I1VI2L

t_I2HI1X

General

0

11

5

DS_N/WR_N HIGH to CS_N HIGH delay

RW_N/RD_N set-up time before DS_N/WR_N LOW

RW_N/RD_N hold time after DS_N/WR_N HIGH

0

T_cy(RW)read or write cycle time

50

-

ns

t_RDY1

READY/IORDY HIGH to DS_N/WR_N HIGH of the last

access

91

ISP1583_7

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Hi-Speed USB peripheral controller

T

cy(RW)

t

WHSH

WHAX

CS_N

[

]

AD 7:0

[

]

(read) DATA 15:0

t

WHDZ

AVWL

[

]

(write) DATA 15:0

t

DVWH

I1VI2L

t

WLWH

DS_N/WR_N

RW_N/RD_N

t

I2HI1X

read

write

004aaa379

Fig 23. ISP1583 register access timing: separate address and data buses (Freescale mode)

DS_N/WR_N

READY/IORDY

004aaa380

t

RDY1

Fig 24. ISP1583 ready signal timing

ISP1583_7

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72 of 99

ISP1583

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Hi-Speed USB peripheral controller

RW_N/RD_N or

DS_N/WR_N

36 ns (min)

(1)

EOT

DREQ

t

h1

004aaa378

(1) Programmable polarity: shown as active LOW.

Remark: EOT must be valid for 36 ns (minimum) when pins RW_N/RD_N and DS_N/WR_N are

active.

Fig 25. EOT timing in generic processor mode

13.1.2 Split bus mode

13.1.2.1 ALE function

8051 mode

• BUS_CONF/DA0 = LOW: split bus mode

• MODE1 = LOW: ALE function

– MODE0/DA1 = HIGH: 8051 mode; see Table 3

Table 104. ISP1583 register access timing parameters: multiplexed address/data bus

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Reading

t_RLRH

Parameter

Conditions

Min

Typ

Max

Unit

RW_N/RD_N LOW pulse width

> t_RLDV

-

ns

t_RLDV

RW_N/RD_N LOW to data valid delay

-

25

15

-

t_RHDZ

RW_N/RD_N HIGH to data outputs 3-state delay

RW_N/RD_N HIGH to CS_N HIGH delay

ALE/A0 LOW set-up time before RW_N/RD_N LOW

0

t_RHSH

t_LLRL

-

Writing

t_WLWH

t_DVWH

t_LLWL

DS_N/WR_N LOW pulse width

15

5

-

ns

data set-up time before DS_N/WR_N HIGH

ALE/A0 LOW to DS_N/WR_N LOW delay

data hold time after DS_N/WR_N HIGH

DS_N/WR_N HIGH to CS_N HIGH delay

0

t_WHDZ

t_WHSH

General

T_cy(RW)

t_AVLL

5

0

read or write cycle time

80

0

-

ns

address set-up time before ALE/A0 LOW

ISP1583_7

Product data sheet

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ISP1583

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Hi-Speed USB peripheral controller

T

cy(RW)

t

WHSH

CS_N

t

RHDZ

RLDV

[

]

(read) AD 7:0

data

address

t

RLRH

LLRL

RHSH

RW_N/RD_N

t

WHDZ

[

]

(write) AD 7:0

data

DVWH

address

t

LLWL

t

WLWH

DS_N/WR_N

ALE/A0

t

AVLL

004aaa382

Fig 26. ISP1583 register access timing: multiplexed address/data bus (8051 mode)

Freescale mode

• BUS_CONF/DA0 = LOW: split bus mode

• MODE1 = LOW: ALE function

– MODE0/DA1 = LOW: Freescale mode; see Table 3

Table 105. ISP1583 register access timing parameters: multiplexed address/data bus

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Reading or writing

Conditions

Min

Typ

Max

Unit

t_WLWH

t_DVWH

t_WHDZ

t_WHSH

General

T_cy(RW)

t_I1VLL

DS_N/WR_N LOW pulse width

15

5

-

ns

data set-up time before DS_N/WR_N HIGH

data hold time after DS_N/WR_N HIGH

DS_N/WR_N HIGH to CS_N HIGH delay

5

0

read or write cycle time

80

5

-

ns

RW_N/RD_N set-up time before ALE/A0 LOW

ALE/A0 LOW to DS_N/WR_N LOW delay

RW_N/RD_N hold time after DS_N/WR_N HIGH

t_LLI2L

5

t_I2HI1X

5

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

74 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

T

cy(RW)

t

WHSH

CS_N

[

]

data

(read) AD 7:0

address

t

WHDZ

address

[

(write) AD 7:0

t

I1VLL

DVWH

t

LLI2L

t

WLWH

DS_N/WR_N

RW_N/RD_N

t

I2HI1X

ALE/A0

004aaa381

Fig 27. ISP1583 register access timing: multiplexed address/data bus (Freescale mode)

13.1.2.2 A0 function

8051 mode

• BUS_CONF/DA0 = LOW: split bus mode

• MODE1 = HIGH: A0 function

– MODE0/DA1 = HIGH: 8051 mode; see Table 3

Table 106. ISP1583 register access timing parameters: multiplexed address/data bus

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Reading

Conditions

Min

Typ

Max

Unit

t_RLDV

RW_N/RD_N LOW to data valid delay

-

26

15

-

ns

t_RHDZ

t_RHSH

t_RLRH

t_WHRH

Writing

t_A0WL

t_AVWH

t_DVWH

t_WHDZ

t_WHSH

t_WLWH

RW_N/RD_N HIGH to data outputs 3-state delay

RW_N/RD_N HIGH to CS_N HIGH delay

RW_N/RD_N LOW pulse width

0

> t_RLDV

40

-

DS_N/WR_N HIGH to RW_N/RD_N HIGH delay

-

ALE/A0 set-up time before DS_N/WR_N LOW

address set-up time before DS_N/WR_N HIGH

data set-up time before DS_N/WR_N HIGH

data hold time after DS_N/WR_N HIGH

DS_N/WR_N HIGH to CS_N HIGH delay

DS_N/WR_N LOW pulse width

0

-

ns

5

0

15

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

75 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 106. ISP1583 register access timing parameters: multiplexed address/data bus …continued

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

t_WHWH

DS_N/WR_N HIGH (address) to DS_N/WR_N

40

-

ns

HIGH (data) delay

General

T_cy(RW)

read or write cycle time

50

-

ns

t

A0WL

ALE/A0

CS_N

T

cy(RW)

t

WHSH

t

RHDZ

RLDV

[

]

data

(read) AD 7:0

address

t

RLRH

RHSH

RW_N/RD_N

DS_N/WR_N

t

AVWH

WHRH

t

WHDZ

[

]

(write) AD 7:0

data

address

t

DVWH

t

WLWH

DS_N/WR_N

t

WHWH

004aaa383

RW_N/RD_N

Fig 28. ISP1583 register access timing: multiplexed address/data bus (A0 function and 8051 mode)

Freescale mode

• BUS_CONF/DA0 = LOW: split bus mode

• MODE1 = HIGH: A0 function

– MODE0/DA1 = LOW: Freescale mode; see Table 3

Table 107. ISP1583 register access timing parameters: multiplexed address/data bus

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Reading

Conditions

Min

Typ

Max

Unit

t_RLDV

t_RHDZ

DS_N/WR_N LOW to data valid delay

DS_N/WR_N HIGH to data outputs 3-state delay

-

26

15

ns

0

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

76 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

Table 107. ISP1583 register access timing parameters: multiplexed address/data bus …continued

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

0

Typ

Max

Unit

ns

t_RHSH

t_RLRH

t_WHRH

DS_N/WR_N HIGH to CS_N HIGH delay

-

DS_N/WR_N LOW pulse width

> t_RLDV

40

ns

DS_N/WR_N HIGH (address) to DS_N/WR_N

HIGH (data read) delay

ns

Writing

t_A0WL

ALE/A0 set-up time before DS_N/WR_N LOW

address set-up time before DS_N/WR_N HIGH

data set-up time before DS_N/WR_N HIGH

data hold time after DS_N/WR_N HIGH

DS_N/WR_N HIGH to CS_N HIGH delay

DS_N/WR_N LOW pulse width

0

-

ns

t_AVWH

t_DVWH

t_WHDZ

t_WHSH

t_WLWH

t_WHWH

5

0

15

40

DS_N/WR_N HIGH (address) to DS_N/WR_N

HIGH (data written) delay

General

T_cy(RW)read or write cycle time

50

5

-

ns

t_I2HI1X

RW_N/RD_N hold time after DS_N/WR_N HIGH

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

77 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

t

A0WL

ALE/A0

CS_N

T

cy(RW)

t

WHSH

t

RHDZ

RLDV

data

address

[

]

(read) AD 7:0

t

RLRH

RHSH

RW_N/RD_N

DS_N/WR_N

t

AVWH

WHRH

t

WHDZ

[

]

(write) AD 7:0

data

address

t

DVWH

t

WLWH

DS_N/WR_N

RW_N/RD_N

t

I2HI1X

t

WHWH

004aaa384

Fig 29. ISP1583 register access timing: multiplexed address/data bus (A0 function and Freescale mode)

(1)

DIOR, DIOW

36 ns (min)

(1)

EOT

DREQ

t

h1

004aaa926

(1) Programmable polarity: shown as active LOW.

Remark: EOT must be valid for 36 ns (minimum) when DIOR or DIOW is active.

Fig 30. EOT timing in split bus mode

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

78 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

13.2 DMA timing

13.2.1 PIO mode

Remark: In the following subsections, RW_N/RD_N, DS_N/WR_N, READY/IORDY and

ALE/A0 refer to the ISP1583 pin.

Table 108. PIO mode timing parameters

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Unit

[1]

T_cy1(min)read or write cycle time

600

70

383

50

240

30

180

30

120

25

ns

t_su1(min)address to DIOR or DIOW on set-up

time

[1]

t_w1(min)

t_w2(min)

DIOR or DIOW pulse width

DIOR/DIOW recovery time

165

-

125

-

100

-

80

70

30

10

20

5

70

25

20

10

20

5

ns

t_su2(min)data set-up time before DIOW off

t_h2(min)data hold time after DIOW off

t_su3(min)data set-up time before DIOR on

t_h3(min)data hold time after DIOR off

t_d2(max)data to 3-state delay after DIOR off

60

30

50

5

45

20

35

5

30

15

20

5

[2]

30

20

30

15

30

10

30

10

30

10

t_h1(min)

address hold time after DIOR or DIOW

off

[3]

t_su4(min)READY/IORDY after DIOR or DIOW on

set-up time

35

ns

t_su5(min)read data to READY/IORDY HIGH

set-up time

0

t_w3(max)READY/IORDY LOW pulse width

1250

[1] T_cy1is the total cycle time, consisting of command active time t_w1and command recovery (inactive) time t_w2, that is, T_cy1= t_w1+ t_w2

Minimum timing requirements for T_cy1, t_w1and t_w2must all be met. As T_cy1(min)is greater than the sum of t_w1(min)and t_w2(min), a host

.

implementation must lengthen t_w1and/or t_w2to ensure that T_cy1is equal to or greater than the value reported in the IDENTIFY DEVICE

data. A device implementation shall support any legal host implementation.

[2] t_d2speciﬁes the time after DIOR is negated, when the data bus is no longer driven by the device (3-state).

[3] If READY/IORDY is LOW at t_su4, the host waits until READY/IORDY is made HIGH before the PIO cycle is completed. In that case, t_su5

must be met for reading (t_su3does not apply). When READY/IORDY is HIGH at t_su4, t_su3must be met for reading (t_su5does not apply).

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

79 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

T

cy1

(1)

device

address

valid

t

h1

su1

(4)

DIOR, DIOW

t

w2

w1

(2)

[

]

(write) DATA 7:0

t

su2

h2

(2)

[

]

(read) DATA 7:0

t

su3

h3(min)

t

d2

(3a)

(3b)

(3c)

HIGH

READY/IORDY

t

su4

t

su5

004aaa921

t

w3

su4

(1) The device address consists of signals CS1_N, CS0_N, DA2, DA1 and DA0.

(2) The data bus width depends on the PIO access command used. The Task File register access uses 8 bits (DATA[7:0]), except

for Task File register 1F0 that uses 16 bits (DATA[15:0]). DMA commands 04h and 05h also use a 16-bit data bus.

(3) The device can negate READY/IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend

the current cycle after t_su4, following the assertion of DIOR or DIOW. The following three cases are distinguished:

a) Device keeps READY/IORDY released (high-impedance): no wait state is generated.

b) Device negates READY/IORDY during t_su4, but re-asserts READY/IORDY before t_su4expires: no wait state is generated.

c) Device negates READY/IORDY during t_su4and keeps READY/IORDY negated for at least 5 ns after t_su4expires: a wait state

is generated. The cycle is completed as soon as READY/IORDY is re-asserted. For extended read cycles (DIOR asserted), the

read data on lines DATAn must be valid at t_d1before READY/IORDY is asserted.

(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.

Fig 31. PIO mode timing

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

80 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

13.2.2 GDMA slave mode

• Bits MODE[1:0] = 00: data strobes DIOR (read) and DIOW (write); see Figure 32

• Bits MODE[1:0] = 01: data strobes DIOR (read) and DACK (write); see Figure 33

• Bits MODE[1:0] = 10: data strobes DACK (read and write); see Figure 34

Table 109. GDMA slave mode timing parameters

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

75

10

33.33

0

Typ

Max

Unit

ns

T_cy1

t_su1

t_d1

read or write cycle time

-

DREQ set-up time before ﬁrst DACK on

DREQ on delay after last strobe off

DREQ hold time after last strobe on

DIOR or DIOW pulse width

-

t_h1

53

600

-

t_w1

t_w2

t_d2

39

36

-

DIOR or DIOW recovery time

read data valid delay after strobe on

read data hold time after strobe off

write data hold time after strobe off

write data set-up time before strobe off

DACK set-up time before DIOR/DIOW assertion

DACK deassertion after DIOR/DIOW deassertion

20

5

t_h2

-

t_h3

1

-

t_su2

t_su3

t_a1

10

0

-

0

30

(2)

DREQ

t

su1

t

T

w1

h1

cy1

(1)

DACK

t

d1

t

su3

DIOR or DIOW

t

w2

t

h2

d2

t

a1

[

]

(read) DATA 15:0

t

h3

su2

[

(write) DATA 15:0

mgt500

DREQ is continuously asserted, until the last transfer is done or the FIFO is full.

Data strobes: DIOR (read), DIOW (write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 32. GDMA slave mode timing: DIOR (master) and DIOW (slave)

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

81 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

(2)

DREQ

t

su3

t

h1

T

d1

w1

cy1

t

su1

(1)

DACK

t

d2

a1

DIOR or DIOW

t

h2

[

]

(read) DATA 15:0

t

h3

su2

[

(write) DATA 15:0

mgt502

DREQ is asserted for every transfer.

Data strobes: DIOR (read), DACK (write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 33. GDMA slave mode timing: DIOR (master) or DACK (slave)

(2)

DREQ

t

T

cy1

t

su1

w1

h1

(1)

DACK

t

d1

t

w2

d2

HIGH

DIOR or DIOW

t

h2

[

]

(read) DATA 15:0

t

su2

h3

[

]

(write) DATA 15:0

mgt501

DREQ is continuously asserted, until the last transfer is done or the FIFO is full.

Data strobe: DACK (read/write).

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 34. GDMA slave mode timing: DACK (master and slave)

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

82 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

13.2.3 MDMA mode

Table 110. MDMA mode timing parameters

V_CC(I/O)= 1.65 V to 3.6 V; V_CC(3V3)= 3.3 V; V_GND= 0 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

T_cy1(min)

t_w1(min)

t_d1(max)

t_h3(min)

t_su2(min)

t_h2(min)

t_su1(min)

t_h1(min)

t_w2(min)

Parameter

Conditions

Mode 0

480

215

150

5

Mode 1

150

80

60

5

Mode 2

120

70

50

5

Unit

ns

[1]

read/write cycle time

DIOR or DIOW pulse width

data valid delay after DIOR on

data hold time after DIOR off

data set-up time before DIOR or DIOW off

data hold time after DIOW off

DACK set-up time before DIOR or DIOW on

DACK hold time after DIOR or DIOW off

DIOR recovery time

100

20

30

15

0

20

10

0

20

5

[1]

50

40

25

35

25

DIOW recovery time

215

120

40

t_d2(max)

DIOR on to DREQ off delay

DIOW on to DREQ off delay

DACK off to data lines 3-state delay

t_d3(max)

20

[1] T_cy1is the total cycle time, consisting of command active time t_w1and command recovery (inactive) time t_w2, that is, T_cy1= t_w1+ t_w2

Minimum timing requirements for T_cy1, t_w1and t_w2must all be met. As T_cy1(min)is greater than the sum of t_w1(min)and t_w2(min), a host

.

implementation must lengthen t_w1and/or t_w2to ensure that T_cy1is equal to or greater than the value reported in the IDENTIFY DEVICE

data. A device implementation shall support any legal host implementation.

(2)

DREQ

T

cy1

(1)

DACK

t

d2

su1

t

h1

w2

w1

DIOR or DIOW

t

d3

t

d1

[

]

(write) DATA 15:0

t

su2

t

h3

h2

[

(read) DATA 15:0

mgt506

t

su2

(1) Programmable polarity: shown as active LOW.

(2) Programmable polarity: shown as active HIGH.

Fig 35. MDMA master mode timing

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

83 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

14. Application information

ISP1583

address

8

AD[7:0]

ALE/A0

data 16

DATA[15:0]

CPU

read strobe

write strobe

chip select

RW_N/RD_N

DS_N/WR_N

CS_N

004aaa273

Fig 36. Typical interface connections for generic processor mode

[

]

DATA 15:0

DREQ

DACK

DIOW

DIOR

DMA

ISP1583

RW_N/RD_N

AD[7:0]

8

ALE/A0

INT

DS_N/WR_N

address

latch

enable

read

strobe

write

strobe

address

or data

interrupt

P0.7/AD7

to

ALE

INTn_N

RD_N

WR_N

8051

P0.0/AD0

MICROCONTROLLER

004aaa274

Fig 37. Typical interface connections for split bus mode (slave mode)

15. Test information

The dynamic characteristics of analog I/O ports DP and DM are determined using the

circuit shown in Figure 38.

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

84 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

test point

DUT

C

50 pF

L

15 kΩ

mgt495

In full-speed mode, an internal 1.5 kΩ pull-up resistor is connected to pin DP.

Fig 38. Load impedance for the DP and DM pins (full-speed mode)

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

85 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

16. Package outline

HVQFN64: plastic thermal enhanced very thin quad flat package; no leads; 64 terminals;

body 9 x 9 x 0.85 mm

SOT804-1

B

D

1

A

terminal 1

index area

A

4

A

E

1

c

A

1

detail X

C

e

1

y

v

M

C

A

B

C

1

b

e

1/2 e

w M

17

32

L

33

16

e

E

2

h

1/2 e

1

48

terminal 1

index area

49

64

X

D

h

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

c

D

E

e

L

v

w

y

1

2

1

4

1

h

1

h

max.

0.05 0.80 0.30

0.00 0.65 0.18

9.05 8.95 4.85 9.05 8.95 4.85

8.95 8.55 4.55 8.95 8.55 4.55

0.5

0.3

mm

1

0.2

0.5

7.5

0.1

0.05 0.05

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

03-03-26

SOT804-1

- - -

MO-220

- - -

Fig 39. Package outline SOT804-1 (HVQFN64)

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

86 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm

SOT543-1

D

A

B

ball A1

index area

A

2

A

E

A

1

detail X

C

e

1

y

e

1/2 e

v M

b

C

A

B

C

1

w M

K

J

H

G

F

e

2

E

D

C

B

A

1/2 e

ball A1

index area

1

2

3

4

5

6

7

8

9 10

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

b

e

y

D

E

e

v

w

y

1

2

1

2

1

max.

0.25 0.85 0.35

0.15 0.75 0.25

6.1

5.9

6.1

5.9

mm

1.1

0.08

0.5

4.5

0.15 0.05

0.1

REFERENCES

JEDEC JEITA

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

00-11-22

02-04-09

SOT543-1

- - -

MO-195

- - -

Fig 40. Package outline SOT543-1 (TFBGA64)

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

87 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 4 x 4 x 0.8 mm

SOT969-1

D

B

A

E

ball A1

index area

A

2

A

1

detail X

e

1

1/2 e

C

M

v

C

A

B

b

e

y

w

C

1

H

G

F

e

E

D

C

B

A

e

2

1/2 e

ball A1

index area

1

2 3 4 5 6 7 8

X

0

2.5

scale

5 mm

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

2

v

w

y

1

max

0.25 0.85

0.15 0.75

0.3

0.2

4.1

3.9

4.1

3.9

mm

1.1

0.4

2.8

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

- - -

JEDEC

JEITA

06-09-22

06-09-27

SOT969-1

- - -

Fig 41. Package outline SOT969-1 (TFBGA64)

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17. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

17.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

17.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

17.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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17.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 42) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 111 and 112

Table 111. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 112. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 42.

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 42. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

18. Abbreviations

Table 113. Abbreviations

Acronym

ACK

Description

Acknowledgement

ACPI

ASIC

ATA

Advanced Conﬁguration and Power Interface

Application-Speciﬁc Integrated Circuit

Advanced Technology Attachment

Advanced Technology Attachment Peripheral Interface

Cyclic Redundancy Code

Direct Memory Access

ATAPI

CRC

DMA

EMI

ElectroMagnetic Interference

Equivalent Series Resistance

Full-Speed

ESR

FS

GDMA

HS

Generic DMA

High-Speed

IDE

Integrated Development Environment

Multi-word DMA

MDMA

MMU

MO

Memory Management Unit

Magneto-Optical

NAK

NRZI

NYET

Not Acknowledged

Non-Return-to-Zero Inverted

Not Yet

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Table 113. Abbreviations …continued

Acronym

Description

OTG

PCB

PHY

PID

On-The-Go

Printed-Circuit Board

Physical

Packet IDentiﬁer

PIE

Parallel Interface Engine

Parallel Input/Output

Phase-Locked Loop

Power-On Reset

PIO

PLL

POR

SE0

SIE

Single-Ended Zero

Serial Interface Engine

Session Request Protocol

Transistor-Transistor Logic

Universal Serial Bus

SRP

TTL

USB

19. References

[1] Universal Serial Bus Speciﬁcation Rev. 2.0

[2] On-The-Go Supplement to the USB Speciﬁcation Rev. 1.3

[3] Using ISP1582/3 in a composite device application with alternate settings

(AN10071)

[4] AT Attachment with Packet Interface Extension (ATA/ATAPI-4), ANSI INCITS

317-1998 (R2003)

[5] ISP1582/83 and ISP1761 clearing an IN buffer (AN10045)

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20. Revision history

Table 114. Revision history

Document ID

ISP1583_7

Release date

Data sheet status

Change notice

Supersedes

20080922

Product data sheet

-

ISP1583_6

Modiﬁcations:

• Added ISP1583ET2.

• Added Section 5 “Marking”.

• Added Table 4 “Endpoint access and programmability”.

• Figure 16 “Bus-powered mode”: updated the voltage range for V_CC(I/O)

• Removed Section 7.9 “Clear buffer”.

.

• Table 24 “Mode register: bit allocation”: updated the bus reset value for bits CLKAON and PWRON.

• Table 34 “Endpoint Index register: bit allocation”: updated the reset and bus reset values for

bit EP0SETUP.

• Table 38 “Control Function register: bit description”: updated description for bit CLBUF.

• Section 9.3.6 “Endpoint MaxPacketSize register (address: 04h)”: updated the ﬁrst paragraph.

• Table 48 “Endpoint Type register: bit description”: added a remark to the DBLBUF bit description.

• Figure 32 “GDMA slave mode timing: DIOR (master) and DIOW (slave)”: updated.

• Table 53 “DMA commands”: added a remark to GDMA stop.

• Section 19 “References”: updated Ref. 3.

ISP1583_6

ISP1583_5

20070820

20070209

20050104

Product data sheet

Product data

-

ISP1583_5

ISP1583-04

ISP1583-03

-

ISP1583-04

200412038

(9397 750 14335)

ISP1583-03

(9397 750 13461)

20040712

20040503

20040225

Product data

Preliminary data

-

ISP1583-02

ISP1583-01

-

ISP1583-02

(9397 750 12978)

ISP1583-01

(9397 750 11497)

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Rev. 07 — 22 September 2008

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21. Legal information

21.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

to result in personal injury, death or severe property or environmental

21.2 Deﬁnitions

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

21.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

SoftConnect — is a trademark of NXP B.V.

22. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

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23. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3

Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 4. Endpoint access and programmability . . . . . . .13

Table 5. Bus conﬁguration modes . . . . . . . . . . . . . . . . .17

Table 6. ISP1583 pin status . . . . . . . . . . . . . . . . . . . . . .17

Table 7. ISP1583 output pin status . . . . . . . . . . . . . . . .17

Table 8. Power modes . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 9. Operation truth table for SoftConnect . . . . . . .25

Table 10. Operation truth table for clock off

Table 43. Buffer Status register: bit allocation . . . . . . . . 43

Table 44. Buffer Status register: bit description . . . . . . . 43

Table 45. Endpoint MaxPacketSize register:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 46. Endpoint MaxPacketSize register:

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 47. Endpoint Type register: bit allocation . . . . . . . 44

Table 48. Endpoint Type register: bit description . . . . . . 45

Table 49. Control bits for Generic DMA transfers . . . . . . 46

Table 50. Control bits for IDE-speciﬁed DMA transfers . . 47

Table 51. DMA Command register: bit allocation . . . . . . 47

Table 52. DMA Command register: bit description . . . . . 48

Table 53. DMA commands . . . . . . . . . . . . . . . . . . . . . . . 48

Table 54. DMA Transfer Counter register: bit allocation . 50

Table 55. DMA Transfer Counter register: bit description 50

Table 56. DMA Conﬁguration register: bit allocation . . . . 50

Table 57. DMA Conﬁguration register: bit description . . . 51

Table 58. DMA Hardware register: bit allocation . . . . . . . 52

Table 59. DMA Hardware register: bit description . . . . . 52

Table 60. Task File register functions . . . . . . . . . . . . . . . 53

Table 61. ATAPI peripheral register addressing . . . . . . . 53

Table 62. Task File 1F0 register (address: 40h):

during suspend . . . . . . . . . . . . . . . . . . . . . . . .25

Table 11. Operation truth table for back voltage

compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 12. Operation truth table for OTG . . . . . . . . . . . . .25

Table 13. Operation truth table for SoftConnect . . . . . . .26

Table 14. Operation truth table for clock off

during suspend . . . . . . . . . . . . . . . . . . . . . . . .26

Table 15. Operation truth table for back voltage

compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table 16. Operation truth table for OTG . . . . . . . . . . . . .27

Table 17. Operation truth table for SoftConnect . . . . . . .27

Table 18. Operation truth table for clock off during

suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 19. Operation truth table for back voltage

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 63. Task File 1F1 register (address: 48h):

compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 64. Task File 1F2 register (address: 49h):

Table 20. Operation truth table for OTG . . . . . . . . . . . . .28

Table 21. Register overview . . . . . . . . . . . . . . . . . . . . . .29

Table 22. Address register: bit allocation . . . . . . . . . . . .31

Table 23. Address register: bit description . . . . . . . . . . .31

Table 24. Mode register: bit allocation . . . . . . . . . . . . . . .32

Table 25. Mode register: bit description . . . . . . . . . . . . .32

Table 26. Status of the chip . . . . . . . . . . . . . . . . . . . . . . .33

Table 27. Interrupt Conﬁguration register: bit allocation .34

Table 28. Interrupt Conﬁguration register: bit description 34

Table 29. Debug mode settings . . . . . . . . . . . . . . . . . . . .34

Table 30. OTG register: bit allocation . . . . . . . . . . . . . . .34

Table 31. OTG register: bit description . . . . . . . . . . . . . .35

Table 32. Interrupt Enable register: bit allocation . . . . . .37

Table 33. Interrupt Enable register: bit description . . . . .37

Table 34. Endpoint Index register: bit allocation . . . . . . .38

Table 35. Endpoint Index register: bit description . . . . . .39

Table 36. Addressing of endpoint buffers . . . . . . . . . . . .39

Table 37. Control Function register: bit allocation . . . . . .39

Table 38. Control Function register: bit description . . . . .40

Table 39. Data Port register: bit allocation . . . . . . . . . . .41

Table 40. Data Port register: bit description . . . . . . . . . .41

Table 41. Buffer Length register: bit allocation . . . . . . . .42

Table 42. Buffer Length register: bit description . . . . . . .42

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 65. Task File 1F3 register (address: 4Ah):

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 66. Task File 1F4 register (address: 4Bh):

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 67. Task File 1F5 register (address: 4Ch):

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 68. Task File 1F6 register (address: 4Dh):

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 69. Task File 1F7 register (address: 44h):

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 70. Task File 3F6 register (address: 4Eh):

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 71. Task File 3F7 register (address: 4Fh):

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 72. DMA Interrupt Reason register: bit allocation . 56

Table 73. DMA Interrupt Reason register: bit description 56

Table 74. Internal EOT-functional relation with

DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . . 57

Table 75. DMA Interrupt Enable register: bit allocation . . 57

Table 76. DMA Endpoint register: bit allocation . . . . . . . 58

Table 77. DMA Endpoint register: bit description . . . . . . 58

continued >>

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Table 78. DMA Strobe Timing register: bit allocation . . .58

Table 79. DMA Strobe Timing register: bit description . .58

Table 80. DMA Burst Counter register: bit allocation . . .59

Table 81. DMA Burst Counter register: bit description . .59

Table 82. Interrupt register: bit allocation . . . . . . . . . . . .60

Table 83. Interrupt register: bit description . . . . . . . . . . .60

Table 84. Chip ID register: bit allocation . . . . . . . . . . . . .61

Table 85. Chip ID register: bit description . . . . . . . . . . . .62

Table 86. Frame Number register: bit allocation . . . . . . .62

Table 87. Frame Number register: bit description . . . . . .62

Table 88. Scratch register: bit allocation . . . . . . . . . . . . .62

Table 89. Scratch register: bit description . . . . . . . . . . . .63

Table 90. Unlock Device register: bit allocation . . . . . . . .63

Table 91. Unlock Device register: bit description . . . . . . .63

Table 92. Test Mode register: bit allocation . . . . . . . . . . .64

Table 93. Test Mode register: bit description . . . . . . . . . .64

Table 94. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .65

Table 95. Recommended operating conditions . . . . . . . .65

Table 96. Static characteristics: supply pins . . . . . . . . . .65

Table 97. Static characteristics: digital pins . . . . . . . . . . .66

Table 98. Static characteristics: OTG detection . . . . . . .66

Table 99. Static characteristics: analog I/O pins

DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 100.Dynamic characteristics . . . . . . . . . . . . . . . . . .67

Table 101.Dynamic characteristics: analog I/O pins

DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 102.ISP1583 register access timing parameters:

separate address and data buses . . . . . . . . . .69

Table 103.ISP1583 register access timing parameters:

separate address and data buses . . . . . . . . . .71

Table 104.ISP1583 register access timing parameters:

multiplexed address/data bus . . . . . . . . . . . . .73

Table 105.ISP1583 register access timing parameters:

multiplexed address/data bus . . . . . . . . . . . . .74

Table 106.ISP1583 register access timing parameters:

multiplexed address/data bus . . . . . . . . . . . . .75

Table 107.ISP1583 register access timing parameters:

multiplexed address/data bus . . . . . . . . . . . . .76

Table 108.PIO mode timing parameters . . . . . . . . . . . . . .79

Table 109.GDMA slave mode timing parameters . . . . . . .81

Table 110.MDMA mode timing parameters . . . . . . . . . . .83

Table 111.SnPb eutectic process (from J-STD-020C) . . .90

Table 112.Lead-free process (from J-STD-020C) . . . . . .90

Table 113.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .91

Table 114.Revision history . . . . . . . . . . . . . . . . . . . . . . . .93

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24. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin conﬁguration ISP1583BS (top view) . . . . . . . .5

Fig 3. Pin conﬁguration ISP1583ET and ISP1583ET2

(top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Fig 4. Pin conﬁguration ISP1583ET1 (top view) . . . . . . .6

Fig 5. Interrupt logic. . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 6. Behavior of bit GLINTENA. . . . . . . . . . . . . . . . . .20

Fig 7. Resistor and electrolytic or tantalum capacitor

needed for V_BUSsensing . . . . . . . . . . . . . . . . . . .21

Fig 8. Oscilloscope reading: no resistor and

(full-speed mode) . . . . . . . . . . . . . . . . . . . . . . . . 85

Fig 39. Package outline SOT804-1 (HVQFN64) . . . . . . . 86

Fig 40. Package outline SOT543-1 (TFBGA64) . . . . . . . 87

Fig 41. Package outline SOT969-1 (TFBGA64) . . . . . . . 88

Fig 42. Temperature proﬁles for large and small

components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

capacitor in the network. . . . . . . . . . . . . . . . . . . .21

Fig 9. Oscilloscope reading: with resistor and

capacitor in the network. . . . . . . . . . . . . . . . . . . .21

Fig 10. POR timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Fig 11. Clock with respect to the external POR . . . . . . . .22

Fig 12. ISP1583 with a 3.3 V supply . . . . . . . . . . . . . . . .23

Fig 13. Power-sharing mode . . . . . . . . . . . . . . . . . . . . . .24

Fig 14. Interrupt pin status during power off in

power-sharing mode . . . . . . . . . . . . . . . . . . . . . .24

Fig 15. Self-powered mode . . . . . . . . . . . . . . . . . . . . . . .26

Fig 16. Bus-powered mode . . . . . . . . . . . . . . . . . . . . . . .27

Fig 17. Programmable strobe timing . . . . . . . . . . . . . . . .59

Fig 18. Source differential data-to-EOP transition

skew and EOP width . . . . . . . . . . . . . . . . . . . . . .68

Fig 19. Receiver differential data jitter . . . . . . . . . . . . . . .69

Fig 20. Receiver SE0 width tolerance . . . . . . . . . . . . . . .69

Fig 21. ISP1583 register access timing: separate

address and data buses (8051 mode) . . . . . . . . .70

Fig 22. ISP1583 ready signal timing . . . . . . . . . . . . . . . .71

Fig 23. ISP1583 register access timing: separate

address and data buses (Freescale mode) . . . . .72

Fig 24. ISP1583 ready signal timing . . . . . . . . . . . . . . . .72

Fig 25. EOT timing in generic processor mode . . . . . . . .73

Fig 26. ISP1583 register access timing: multiplexed

address/data bus (8051 mode) . . . . . . . . . . . . . .74

Fig 27. ISP1583 register access timing: multiplexed

address/data bus (Freescale mode) . . . . . . . . . .75

Fig 28. ISP1583 register access timing: multiplexed

address/data bus (A0 function and 8051 mode) .76

Fig 29. ISP1583 register access timing:

multiplexed address/data bus

(A0 function and Freescale mode). . . . . . . . . . . .78

Fig 30. EOT timing in split bus mode . . . . . . . . . . . . . . . .78

Fig 31. PIO mode timing . . . . . . . . . . . . . . . . . . . . . . . . .80

Fig 32. GDMA slave mode timing:

DIOR (master) and DIOW (slave) . . . . . . . . . . . .81

Fig 33. GDMA slave mode timing:

DIOR (master) or DACK (slave). . . . . . . . . . . . . .82

Fig 34. GDMA slave mode timing:

DACK (master and slave). . . . . . . . . . . . . . . . . . .82

Fig 35. MDMA master mode timing . . . . . . . . . . . . . . . . .83

Fig 36. Typical interface connections for generic

processor mode . . . . . . . . . . . . . . . . . . . . . . . . . .84

Fig 37. Typical interface connections for split bus mode

(slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Fig 38. Load impedance for the DP and DM pins

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

97 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

25. Contents

1

2

3

4

5

6

General description . . . . . . . . . . . . . . . . . . . . . . 1

9.2.5

9.3

Interrupt Enable register (address: 14h) . . . . 36

Data ﬂow registers . . . . . . . . . . . . . . . . . . . . . 38

Endpoint Index register (address: 2Ch) . . . . . 38

Control Function register (address: 28h) . . . . 39

Data Port register (address: 20h). . . . . . . . . . 40

Buffer Length register (address: 1Ch) . . . . . . 41

Buffer Status register (address: 1Eh). . . . . . . 42

Endpoint MaxPacketSize register

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

7

7.1

7.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

(address: 04h) . . . . . . . . . . . . . . . . . . . . . . . . 43

Endpoint Type register (address: 08h) . . . . . . 44

DMA registers . . . . . . . . . . . . . . . . . . . . . . . . 45

DMA Command register (address: 30h) . . . . 47

DMA Transfer Counter register (address: 34h) 49

DMA Conﬁguration register (address: 38h) . . 50

DMA Hardware register (address: 3Ch). . . . . 52

Task File registers (addresses: 40h to 4Fh). . 53

DMA Interrupt Reason register (address: 50h) 56

DMA Interrupt Enable register (address: 54h) 57

DMA Endpoint register (address: 58h). . . . . . 57

DMA Strobe Timing register (address: 60h). . 58

DMA Burst Counter register (address: 64h). . 59

General registers . . . . . . . . . . . . . . . . . . . . . . 59

Interrupt register (address: 18h). . . . . . . . . . . 59

Chip ID register (address: 70h) . . . . . . . . . . . 61

Frame Number register (address: 74h) . . . . . 62

Scratch register (address: 78h) . . . . . . . . . . . 62

Unlock Device register (address: 7Ch). . . . . . 63

Test Mode register (address: 84h) . . . . . . . . . 63

9.3.7

9.4

8

8.1

Functional description . . . . . . . . . . . . . . . . . . 12

DMA interface, DMA handler and

DMA registers. . . . . . . . . . . . . . . . . . . . . . . . . 13

Hi-Speed USB transceiver . . . . . . . . . . . . . . . 14

MMU and integrated RAM . . . . . . . . . . . . . . . 14

Microcontroller interface and

9.4.1

9.4.2

9.4.3

9.4.4

9.4.5

9.4.6

9.4.7

9.4.8

9.4.9

9.4.10

9.5

9.5.1

9.5.2

9.5.3

9.5.4

9.5.5

9.5.6

8.2

8.3

8.4

microcontroller handler . . . . . . . . . . . . . . . . . . 14

OTG SRP module. . . . . . . . . . . . . . . . . . . . . . 14

NXP high-speed transceiver. . . . . . . . . . . . . . 15

NXP Parallel Interface Engine (PIE) . . . . . . . . 15

Peripheral circuit . . . . . . . . . . . . . . . . . . . . . . . 15

HS detection . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

NXP Serial Interface Engine (SIE) . . . . . . . . . 15

SoftConnect . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Reconﬁguring endpoints. . . . . . . . . . . . . . . . . 16

System controller . . . . . . . . . . . . . . . . . . . . . . 16

Modes of operation. . . . . . . . . . . . . . . . . . . . . 16

Pins status . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Interrupt output pin . . . . . . . . . . . . . . . . . . . . . 18

Interrupt control . . . . . . . . . . . . . . . . . . . . . . . 20

8.5

8.6

8.6.1

8.6.2

8.6.3

8.6.4

8.7

8.8

8.9

8.10

8.11

8.12

8.13

8.13.1

8.13.2

8.14

8.15

8.16

8.16.1

8.16.2

8.16.3

10

11

12

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 65

Recommended operating conditions . . . . . . 65

Static characteristics . . . . . . . . . . . . . . . . . . . 65

13

13.1

13.1.1

Dynamic characteristics. . . . . . . . . . . . . . . . . 67

Register access timing. . . . . . . . . . . . . . . . . . 69

Generic processor mode . . . . . . . . . . . . . . . . 69

V_BUSsensing . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 22

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 23

Power-sharing mode. . . . . . . . . . . . . . . . . . . . 24

Self-powered mode. . . . . . . . . . . . . . . . . . . . . 26

Bus-powered mode. . . . . . . . . . . . . . . . . . . . . 27

13.1.1.1 8051 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

13.1.1.2 Freescale mode . . . . . . . . . . . . . . . . . . . . . . . 71

13.1.2

13.1.2.1 ALE function. . . . . . . . . . . . . . . . . . . . . . . . . . 73

13.1.2.2 A0 function . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

13.2

13.2.1

13.2.2

13.2.3

Split bus mode . . . . . . . . . . . . . . . . . . . . . . . . 73

9

9.1

9.2

9.2.1

9.2.2

9.2.3

Register description . . . . . . . . . . . . . . . . . . . . 29

Register access . . . . . . . . . . . . . . . . . . . . . . . 30

Initialization registers . . . . . . . . . . . . . . . . . . . 31

Address register (address: 00h) . . . . . . . . . . . 31

Mode register (address: 0Ch). . . . . . . . . . . . . 31

Interrupt Conﬁguration register

(address: 10h). . . . . . . . . . . . . . . . . . . . . . . . . 33

OTG register (address: 12h). . . . . . . . . . . . . . 34

Session Request Protocol (SRP) . . . . . . . . . . 36

DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 79

PIO mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

GDMA slave mode . . . . . . . . . . . . . . . . . . . . . 81

MDMA mode . . . . . . . . . . . . . . . . . . . . . . . . . 83

14

15

16

Application information . . . . . . . . . . . . . . . . . 84

Test information. . . . . . . . . . . . . . . . . . . . . . . . 84

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 86

9.2.4

9.2.4.1

continued >>

ISP1583_7

Product data sheet

Rev. 07 — 22 September 2008

98 of 99

ISP1583

NXP Semiconductors

Hi-Speed USB peripheral controller

17

Soldering of SMD packages . . . . . . . . . . . . . . 89

17.1

17.2

17.3

17.4

Introduction to soldering . . . . . . . . . . . . . . . . . 89

Wave and reﬂow soldering . . . . . . . . . . . . . . . 89

Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 89

Reﬂow soldering . . . . . . . . . . . . . . . . . . . . . . . 90

18

19

20

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 91

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Revision history. . . . . . . . . . . . . . . . . . . . . . . . 93

21

Legal information. . . . . . . . . . . . . . . . . . . . . . . 94

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 94

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 94

21.1

21.2

21.3

21.4

22

23

24

25

Contact information. . . . . . . . . . . . . . . . . . . . . 94

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 22 September 2008

Document identifier: ISP1583_7


型号：	ISP1583BS,551
厂家：	NXP
描述：	USB Bus Controller, CMOS, PQCC64, 9 X 9 MM, 0.85 MM HEIGHT, LEAD FREE, PLASTIC, MO-220, SOT-804-1, HVQFN-64
文件：	总100页 (文件大小：509K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISP1583BS,551 [NXP]

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