ISP1703A [NXP]

ISP1703A;
ISP1703A
型号: ISP1703A
厂家: NXP    NXP
描述:

ISP1703A

文件: 总2页 (文件大小:134K)
中文:  中文翻译
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NXP family of ULPI  
Hi-Speed USB transceivers  
ISP150x, ISP170x  
Best-in-class ULPI transceivers for  
mobile and portable applications  
Designed for use with ASICs, FPGAs, and system chipsets that interface with the physical layer  
of the USB connection, these first- and second-generation transceivers provide reliable USB  
performance in a low-pin format and support a full range of portable applications,  
including mobile phones.  
Key features  
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Input power supply: 3.0 to 4.5 V  
Charger detection  
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Fully compliant with:  
- Universal Serial Bus Specification Revision 2.0  
- On-The-Go Supplement to the USB Specification  
Revision 1.2  
ULPI SDR and DDR modes available  
UART pass-through mode  
Space-saving packages (HVQFN32/24, TFBGA36, WLCSP25)  
- UTMI+ Low Pin Interface (ULPI) Specification Revision 1.1  
High-speed (480 Mbps), full-speed (12 Mbps) and low-speed  
(1.5 Mbps) data rates  
NXP offers two generations of UTMI+ Low Pin Interface (ULPI)  
Hi-Speed USB transceivers. Both generations build on  
the proven, fully compliant NXP architecture for ULPI, which  
allows USB ASICs, FPGAs, and system chipsets to interface  
with the physical layer of the USB connection. All offer very  
small form factor and very low power.  
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Interfaces to Hi-Speed USB host, peripheral, and dual-role  
device cores  
Highly optimized ULPI-compliant interface  
- 60-MHz, 4- or 8-bit interface between ASIC and transceiver  
- Integrated PLL supports 60-MHz input clock and a wide  
spectrum of crystal or clock frequencies.  
- Fully programmable ULPI-compliant register set  
- Internal power-on reset circuit  
The core architecture supports high-speed (480 Mbps),  
full-speed (12 Mbps), and low-speed (1.5 Mbps) data rates,  
and includes a highly optimized interface that operates at  
60 MHz and uses only eight (DDR) or twelve (SDR) signals  
between the ASIC and the transceiver.  
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Integrated resistors: 45-Ω high-speed terminations, 1.5-kΩ  
full-speed device pull-up, and 15-kΩ host terminations  
Guaranteed VBUS impedance of 80 to 100 kΩ for  
ISP1702, ISP1703  
An integrated phase-locked loop (PLL) supports a 60-MHz  
input clock and a range of crystal or clock frequencies.  
The architecture also includes a fully programmable,  
Support for bus reset, suspend, resume, and high-speed  
detection handshake (chirp)  
Low suspend current (50 µA) and low power-down mode  
current (0.5 µA)  
ULPI-compliant register set. An internal power-on reset circuit  
removes the need for system reset and simplifies PCB design.  
can be entered by setting the chip select pin to be inactive–  
when, for example, the transceiver is turned off by the mobile  
phone or when there is no connection to a PC, PDA, or PMP.  
Each transceiver has integrated resistors that support  
45-Ω high-speed terminations, 1.5-kΩ full-speed device pull-up,  
and 15-kΩ host terminations. Each also supports bus reset,  
suspend, resume, and high-speed detection handshake (chirp).  
To support the miniaturization of mobile phones, the second-  
generation transceivers are housed in TFBGA36 (3.5 x 3.5 x  
0.8 mm) and WLCSP25 (2.2 x 2.25 x 0.6 mm) packages.  
First generation:  
All the second-generation transceivers have host, device  
(peripheral) and On-The-Go (OTG) capability. The ISP1508,  
ISP1702, and the ISP1703 support lower levels of I/O interface  
voltage (VCC(I/O) = 1.4 to 1.95 V), and the ISP1508 and ISP1703 can  
be pin-selected to use Single Data Rate (SDR) or Double Data  
Rate (DDR) interface operation.  
Portable and standalone consumer electronics  
The first-generation transceivers (ISP1504, ISP1505, ISP1506)  
are designed for portable and standalone consumer electronics  
such as portable media players (PMPs), MP3 players, digital still  
cameras (DSCs), digital video cameras (DVCs), set-top boxes  
(STBs), and storage devices such as Flash disks.  
NXP’s second-generation ULPI transceivers are simple to  
integrate, fitting easily into any customer application without the  
need for additional components or expensive ASIC redesigns.  
Second generation:  
Mobile phones and portable applications  
The second-generation transceivers (ISP1504x1, ISP1508,  
ISP1702, ISP1703), cater to the special needs of mobile phones.  
They offer a greater range of crystal and clock frequencies,  
including 13, 26, 19.2, and 38.4 MHz, targeting CDMA,  
WCDMA and GSM systems. The typical frequency for consumer  
electronics, 24 MHz, is also available.  
They support the mobile phone’s wider range of input supply  
voltage (3.0 to 4.5 V), and offer a power-down mode with  
ultra-low power consumption (0.5 µA). The power-down mode  
The transceivers also support HIGH and LOW chip polarity.  
First-generation transceivers for portable and  
standalone consumer electronics  
Second-generation transceivers for mobile phones  
ISP1504  
HVQFN32  
5 x 5 x 1.0  
-
ISP1505  
HVQFN24  
4 x 4 x 1.0  
-
ISP1506  
HVQFN24  
4 x 4 x 1.0  
-
ISP1504x1  
TFBGA36  
3.5 x 3.5 x 0.8  
0.5  
ISP1508  
TFBGA36  
3.5 x 3.5 x 0.8  
0.5  
ISP1702  
TFBGA36  
3.5 x 3.5 x 0.8  
0.5  
ISP1703  
Package type  
WLCSP25  
2.2 x 2.25 x 0.6  
0.4  
Package dimensions (mm)  
Ball pitch (mm)  
USB application  
Host/device/OTG Host/device  
Host/device/OTG Host/device/OTG Host/device/OTG Host/device/OTG Host/device/OTG  
ULPI mode  
SDR  
Yes  
-
SDR  
DDR  
SDR  
Yes  
-
SDR, DDR  
Yes  
SDR  
SDR, DDR  
Pending  
Yes  
USB certification received  
Transparent UART mode  
Chip Select pin polarity (active HIGH/LOW)  
Yes  
Pending  
Pending  
Yes  
-
-
-
-
Yes  
LOW  
LOW  
A version: HIGH  
B version: LOW  
A version: LOW  
A version: LOW  
B version: HIGH  
USB charger detection  
-
-
-
-
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
VBUS charge and discharge resistors  
Yes  
Yes  
Yes  
Yes  
Dataline and VBUS pulsing  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Crystals and clocks supported (MHz)  
A version: 19.2  
C version: 26  
Both: 60  
A version: 19.2 A version: 19.2  
A1 version: 19.2  
C1 version: 26  
13, 19.2, 24, 26, 60 A version: 19.2  
A version: 19.2, 38.4  
B version: 26  
Both: 60  
C version: 26  
Both: 60  
C version: 26  
Main supply input voltage, VCC (V)  
Digital I/O input voltage, VCC(I/O) (V)  
3.0 to 3.6  
3.0 to 3.6  
3.0 to 3.6  
3.0 to 4.5  
3.0 to 4.5  
1.4 to 1.95  
3.0 to 4.5  
1.4 to 1.95  
3.0 to 4.5  
1.4 to 1.95  
1.65 to 3.6  
1.65 to 3.6  
1.65 to 1.95  
1.65 to 3.6  
VBUS 5-V output: VBUS impedance (kΩ)  
VBUS 5-V output: charge pump (mA)  
40 to 100  
50  
40 to 100  
40 to 100  
50  
40 to 100  
40 to 100  
80 to 100  
80 to 100  
-
-
-
-
-
VBUS 5-V output: control external charge  
pump/switch  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
VBUS 5-V output: input for  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
-
external VBUS FAULT detector  
Current consumption: power-down mode (µA)  
Current consumption: low-power mode (µA)  
-
-
-
0.5  
50  
0.5  
50  
0.5  
50  
0.5  
50  
35  
35  
35  
www.nxp.com  
© 2007 NXP B.V.  
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and  
reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use.  
Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.  
Date of release: February 2007  
Document order number: 9397 750 15936  
Printed in the Netherlands  

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