ISP1760ET-T_技术文档

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ISP1760

Hi-Speed Universal Serial Bus host controller for embedded

applications

Rev. 04 — 4 February 2008

Product data sheet

1. General description

The ISP1760 is a Hi-Speed Universal Serial Bus (USB) host controller with a generic

processor interface. It integrates one Enhanced Host Controller Interface (EHCI), one

Transaction Translator (TT) and three transceivers. The host controller portion of the

ISP1760 and the three transceivers comply to Ref. 1 “Universal Serial Bus Speciﬁcation

Rev. 2.0”. The EHCI portion of the ISP1760 is adapted from Ref. 2 “Enhanced Host

Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0”.

The integrated high-performance Hi-Speed USB transceivers enable the ISP1760 to

handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed

(12 Mbit/s) and low-speed (1.5 Mbit/s). The three downstream ports allow simultaneous

connection of three devices at different speeds (high-speed, full-speed and low-speed).

The generic processor interface allows the ISP1760 to be connected to various

processors as a memory-mapped resource. The ISP1760 is a slave host: it does not

require ‘bus-mastering’ capabilities of the host system bus. The interface can be

conﬁgured, ensuring compatibility with a variety of processors. Data transfer can be

performed on 16 bits or 32 bits, using Programmed Input/Output (PIO) or Direct Memory

Access (DMA) with major control signals conﬁgurable as active LOW or active HIGH.

Integration of the TT allows connection to full-speed and low-speed devices, without the

need of integrating Open Host Controller Interface (OHCI) or Universal Host Controller

Interface (UHCI). Instead of dealing with two sets of software drivers, EHCI and OHCI or

UHCI, you need to deal with only one set, EHCI, that dramatically reduces software

complexity and IC cost.

2. Features

I The host controller portion of the ISP1760 complies with Ref. 1 “Universal Serial Bus

Speciﬁcation Rev. 2.0”

I The EHCI portion of the ISP1760 is adapted from Ref. 2 “Enhanced Host Controller

Interface Speciﬁcation for Universal Serial Bus Rev. 1.0”

I Contains three integrated Hi-Speed USB transceivers that support high-speed,

full-speed and low-speed modes

I Integrates a TT for Original USB (full-speed and low-speed) device support

I Up to 64 kB internal memory (8 k × 64 bits) accessible through a generic processor

interface; operation in multitasking environments is made possible by the

implementation of virtual segmentation mechanism with bank switching on task

request

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

I Generic processor interface, non-multiplexed and variable latency, with a conﬁgurable

32-bit or 16-bit external data bus; the processor interface can be deﬁned as

variable-latency or SRAM type (memory mapping)

I Slave DMA support to reduce the load of the host system CPU during the data transfer

to or from the memory

I Integrated Phase-Locked Loop (PLL) with a 12 MHz crystal or an external clock input

I Integrated multi-conﬁguration FIFO

I Optimized ‘msec-based’ or ‘multi-msec-based’ Philips Transfer Descriptor (PTD)

interrupt

I Tolerant I/O for low voltage CPU interface (1.65 V to 3.6 V)

I 3.3 V-to-5.0 V external power supply input

I Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for

low-power core)

I Internal power-on reset and low-voltage reset

I Supports suspend and remote wake-up

I Target current consumption:

N Normal operation; one port in high-speed active: I_CC< 100 mA

N Suspend mode: I_CC(susp)< 150 µA at room temperature

I Built-in conﬁgurable overcurrent circuitry (digital or analog overcurrent protection)

I Available in LQFP128 and TFBGA128 packages

3. Applications

The ISP1760 can be used to implement a Hi-Speed USB compliant host controller

connected to most of the CPUs present in the market today, having a generic processor

interface with de-multiplexed address and data bus. This is because of the efﬁcient

slave-type interface of the ISP1760.

The internal architecture of the ISP1760 is such that it can be used in a large spectrum of

applications requiring a high-performance internal host controller.

3.1 Examples of a multitude of possible applications

I Set-top box: for connecting external high-performance mass storage devices

I Mobile phone: for connecting various USB devices

I Personal Digital Assistant (PDA): for connecting a large variety of USB devices

I Printer: for connecting external memory card readers, allowing direct printing

I Digital Still Camera (DSC): for printing to an external USB printer, for direct printing

I Mass storage: for connecting external memory card readers or other mass storage

devices, for direct back-up

The low power consumption and deep power management modes of the ISP1760

make it particularly suitable for use in portable devices.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

2 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

4. Ordering information

Table 1.

Ordering information

Type number Package

Name

Description

plastic low proﬁle quad ﬂat package; 128 leads; body 14 × 20 × 1.4 mm

TFBGA128 plastic thin ﬁne-pitch ball grid array package; 128 balls; body 9 × 9 × 0.8 mm

Version

ISP1760BE

ISP1760ET

LQFP128

SOT425-1

SOT857-1

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

3 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

5. Block diagram

V

CC(I/O)

37 to 39, 41 to 43,

45 to 47, 49, 51,

52, 54, 56 to 58,

60 to 62, 64 to 66,

68 to 70, 72 to 74,

76 to 78, 80

10, 40, 48, 59, 67,

75, 83, 94, 104, 115

ISP1760BE

11

12

13

XTAL1

XTAL2

CLKIN

PLL

HC PTD MEMORY

(3 kB)

RISC PROCESSOR

INTERFACE:

16-bit

or

30 MHz

60 MHz

DATA[15:0]/DATA[31:0]

32-bit

HC PAYLOAD

MEMORY (60 kB)

MEMORY

82, 84, 86, 87,

89, 91 to 93,

95 to 98,

MANAGEMENT

UNIT

+

122

119

100 to 103, 105

17

RESET_N

GLOBAL CONTROL

AND POWER

MANAGEMENT

INTERRUPT

CONTROL

+

A[17:1]

SUSPEND/

WAKEUP_N

106

107

108

112

114

116

CS_N

RD_N

WR_N

IRQ

MEMORY

ARBITER

AND FIFO

SLAVE DMA

CONTROLLER

POWER-ON RESET

110

+

BAT_ON_N

AND V

ON

BAT

HARDWARE

CONFIGURATION

REGISTERS

DREQ

DACK

5, 50,

85, 118

5 V-TO-1.8 V

VOLTAGE

REGULATOR

REG1V8

EHCI AND

OPERATIONAL

REGISTERS

6, 7

V

CC(5V0)

TRANSACTION

TRANSLATOR

AND RAM

5 V-TO-3.3 V

VOLTAGE

PIE

9

REG3V3

REGULATOR

USB FULL-SPEED AND LOW-SPEED DATA PATH

USB HIGH-SPEED DATA PATH

DIGITAL

AND ANALOG

OVERCURRENT

DETECTION

2

8

REF5V

PORT ROUTING OR CONTROL LOGIC + HOST AND HUB PORT STATUS

GND(OSC)

4, 17, 24,

31, 123

HI-SPEED

USB ATX3

HI-SPEED

USB ATX2

HI-SPEED

USB ATX1

GNDA

GNDC

53, 88, 121

14, 36, 44, 55, 63,

71, 79, 90, 99, 109

16

18 21 127

23

30

1

15

22 27

28 128

33 32 35

29 34

20 19

26 25

DM2

004aaa435

GNDD

DP2

RREF3

DP1

GNDA

DP3

RREF1

DM1

DM3

RREF2

GNDA

OC3_N

GND

(RREF1)

OC2_N

PSW2_N

GND

(RREF3)

OC1_N

PSW1_N

GND

(RREF2)

GNDA

PSW3_N

The ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

All ground pins should normally be connected to a common ground plane.

Fig 1. Block diagram

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

4 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

6. Pinning information

6.1 Pinning

1

102

ISP1760BE

38

65

004aaa505

Fig 2. Pin conﬁguration (LQFP128); top view

ball A1

index area

2

4

6

8

10 12 14 16

9 11 13 15

1

3

5

7

A

B

C

D

E

F

G

H

J

ISP1760ET

K

L

M

N

P

R

T

004aaa550

Fig 3. Pin conﬁguration (TFBGA128); top view

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

5 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

6.2 Pin description

Table 2.

Pin description

Symbol^[1][2]

LQFP128

Type^[3]Description

TFBGA128

OC3_N

1

C2

AI

port 3 analog (5 V input) and digital overcurrent input; if not used,

connect to V_CC(I/O)through a 10 kΩ resistor

input, 5 V tolerant

REF5V

2

A2

5 V reference input for analog OC detector; connect a 100 nF

decoupling capacitor

TEST1

GNDA

3

4

5

B2

A1

B1

-

connect to ground

analog ground

-

REG1V8

P

core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor; for details on additional

capacitor placement, see Section 7.8

V_CC(5V0)

6

7

C1

D2

P

input to internal regulators (3.0 V to 5.5 V); connect a 100 nF

decoupling capacitor; see Section 7.8

input to internal regulators (3.0 V to 5.5 V); connect a 100 nF

decoupling capacitor; see Section 7.8

GND(OSC)

REG3V3

8

9

E3

D1

-

oscillator ground

P

regulator output (3.3 V); for decoupling only; connect a 100 nF

capacitor and a 4.7 µF-to-10 µF capacitor; see Section 7.8

V_CC(I/O)

XTAL1

10

11

E2

E1

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

AI

12 MHz crystal connection input; connect to ground if an external

clock is used; see Table 88

XTAL2

CLKIN

GNDD

12

13

14

F2

F1

G3

G2

G1

AO

12 MHz crystal connection output

I

12 MHz oscillator or clock input; when not in use, connect to V_CC(I/O)

-

digital ground

GND(RREF1) 15

-

RREF1 ground

RREF1

16

AI

reference resistor connection; connect a 12 kΩ ± 1 % resistor

between this pin and the RREF1 ground

GNDA^[4]

DM1

17

18

19

20

21

H2

H1

J3

J2

J1

-

analog ground

AI/O

-

downstream data minus port 1

analog ground

GNDA

DP1

AI/O

OD

downstream data plus port 1

power switch port 1, active LOW

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

RREF2 ground

PSW1_N

GND(RREF2) 22

K2

K1

-

RREF2

23

AI

reference resistor connection; connect a 12 kΩ ± 1 % resistor

between this pin and the RREF2 ground

GNDA^[5]

DM2

24

25

26

27

L3

L1

L2

M2

-

analog ground

AI/O

-

downstream data minus port 2

analog ground

GNDA

DP2

AI/O

downstream data plus port 2

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

6 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]Description

LQFP128

28

TFBGA128

PSW2_N

M1

OD

power switch port 2, active LOW

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

RREF3 ground

GND(RREF3) 29

N2

N1

-

RREF3

30

AI

reference resistor connection; connect a 12 kΩ ± 1 % resistor

between this pin and the RREF3 ground

GNDA^[6]

DM3

31

32

33

34

35

P2

P1

R2

R1

T1

-

analog ground

AI/O

-

downstream data minus port 3

analog ground

GNDA

DP3

AI/O

OD

downstream data plus port 3

power switch port 3, active LOW

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

digital ground

PSW3_N

GNDD

DATA0

36

37

T2

R3

-

I/O

data bit 0 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA1

DATA2

38

39

T3

R4

I/O

data bit 1 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 2 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

DATA3

40

41

T4

P5

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

I/O

data bit 3 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA4

DATA5

42

43

T5

R5

I/O

data bit 4 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 5 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

DATA6

44

45

T6

R6

-

digital ground

I/O

data bit 6 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA7

DATA8

46

47

48

P7

T7

R7

I/O

P

data bit 7 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 8 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

7 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]Description

LQFP128

49

TFBGA128

DATA9

T8

I/O

data bit 9 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

REG1V8

DATA10

50

51

R8

P9

P

core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor; for details on additional

capacitor placement, see Section 7.8

I/O

data bit 10 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA11

52

T9

I/O

data bit 11 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDC

53

54

R9

-

core ground

DATA12

T10

I/O

data bit 12 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

55

56

R10

P11

-

digital ground

DATA13

I/O

data bit 13 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA14

DATA15

57

58

T11

R11

I/O

data bit 14 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 15 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

DATA16

59

60

T12

R12

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

I/O

data bit 16 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA17

DATA18

61

62

T13

R13

I/O

data bit 17 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 18 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

63

64

R14

T14

-

digital ground

DATA19

I/O

data bit 19 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA20

65

T15

I/O

data bit 20 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

8 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]Description

LQFP128

66

TFBGA128

DATA21

R15

I/O

data bit 21 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

DATA22

67

68

P15

T16

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

I/O

data bit 22 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA23

DATA24

69

70

R16

P16

I/O

data bit 23 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 24 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

71

72

N16

N15

-

digital ground

DATA25

I/O

data bit 25 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA26

DATA27

73

74

M15

M16

I/O

data bit 26 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 27 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

V_CC(I/O)

DATA28

75

76

M14

L16

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

I/O

data bit 28 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

DATA29

DATA30

77

78

L15

K16

I/O

data bit 29 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

data bit 30 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

GNDD

79

80

K15

K14

-

digital ground

DATA31

I/O

data bit 31 input and output

bidirectional pad, push-pull input, 3-state output, 4 mA output drive,

3.3 V tolerant

TEST2

A1

81

82

J16

-

I

connect to ground

address pin 1

H16

input, 3.3 V tolerant

V_CC(I/O)

83

J15

P

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

9 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]Description

LQFP128

84

TFBGA128

A2

H15

I

address pin 2

input, 3.3 V tolerant

REG1V8

85

G16

P

core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor and a 4.7 µF-to-10 µF

capacitor; see Section 7.8

A3

A4

86

87

H14

F16

I

address pin 3

input, 3.3 V tolerant

address pin 4

input, 3.3 V tolerant

core ground

GNDC

A5

88

89

G15

F15

-

I

address pin 5

input, 3.3 V tolerant

digital ground

GNDD

A6

90

91

E16

F14

-

I

address pin 6

input, 3.3 V tolerant

address pin 7

A7

A8

92

93

E15

D16

I

input, 3.3 V tolerant

address pin 8

input, 3.3 V tolerant

V_CC(I/O)

A9

94

95

D15

C16

P

I

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

address pin 9

input, 3.3 V tolerant

address pin 10

A10

A11

A12

96

97

98

C15

B16

B15

I

input, 3.3 V tolerant

address pin 11

input, 3.3 V tolerant

address pin 12

input, 3.3 V tolerant

digital ground

GNDD

A13

99

A16

A15

-

I

100

address pin 13

input, 3.3 V tolerant

address pin 14

A14

A15

A16

101

102

103

B14

A14

A13

I

input, 3.3 V tolerant

address pin 15

input, 3.3 V tolerant

address pin 16

input, 3.3 V tolerant

V_CC(I/O)

A17

104

105

B13

C12

P

I

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

address pin 17

input, 3.3 V tolerant

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

10 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]Description

LQFP128

106

TFBGA128

CS_N

A12

I

chip select signal assertion indicates the ISP1760 being accessed;

active LOW

input, 3.3 V tolerant

read enable; active LOW

input, 3.3 V tolerant

write enable; active LOW

input, 3.3 V tolerant

digital ground

RD_N

WR_N

107

108

B12

B11

I

GNDD

109

110

A11

C10

-

BAT_ON_N

OD

to indicate the presence of a minimum 3.3 V on pins 6 and 7

(open-drain); connect to V_CC(I/O)through a 10 kΩ pull-up resistor

output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant

not connected

n.c.

111

112

A10

B10

-

IRQ

O

host controller interrupt signal

output pad, 4 mA drive, 3.3 V tolerant

not connected

n.c.

113

114

A9

B9

-

DREQ

O

DMA controller request for the host controller

output pad, 4 mA drive, 3.3 V tolerant

V_CC(I/O)

DACK

115

116

C8

A8

P

I

digital supply voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling

capacitor; see Section 7.8

host controller DMA request acknowledgment; when not in use,

connect to V_CC(I/O)through a 10 kΩ pull-up resistor

input, 3.3 V tolerant

TEST3

117

118

B8

B7

-

connect to V_CC(I/O)through a 10 kΩ pull-up resistor

REG1V8

P

core power output (1.8 V); internal 1.8 V for the digital core; used for

decoupling; connect a 100 nF capacitor; for details on additional

capacitor placement, see Section 7.8

SUSPEND/

WAKEUP_N

119

A7

I/OD

host controller suspend and wake-up; 3-state suspend output (active

LOW) and wake-up input circuits are connected together

• HIGH = output is 3-state; ISP1760 is in suspend mode

• LOW = output is LOW; ISP1760 is not in suspend mode

connect to V_CC(I/O)through an external 10 kΩ pull-up resistor

output pad, open-drain, 4 mA output drive, 3.3 V tolerant

pull up to V_CC(I/O)

TEST4

120

121

122

C6

A6

B6

-

I

GNDC

core ground

RESET_N

external power-up reset; active LOW; when reset is asserted, it is

expected that bus signals are idle, that is, not toggling

input, 3.3 V tolerant

Remark: During reset, ensure that all the input pins to the ISP1760

are not toggling and are in their inactive states.

GNDA

TEST5

TEST6

123

124

125

B5

A5

B4

-

analog ground

connect a 220 nF capacitor between this pin and pin 125

connect a 220 nF capacitor between this pin and pin 124

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Table 2.

Pin description …continued

Symbol^[1][2]

Type^[3]Description

LQFP128

126

TFBGA128

TEST7

OC1_N

A4

B3

-

connect to 3.3 V

127

AI

port 1 analog (5 V input) and digital overcurrent input; if not used,

connect to V_CC(I/O)through a 10 kΩ resistor

input, 5 V tolerant

OC2_N

128

A3

AI

port 2 analog (5 V input) and digital overcurrent input; if not used,

connect to V_CC(I/O)through a 10 kΩ resistor

input, 5 V tolerant

[1] Symbol names ending with underscore N, for example, NAME_N, represent active LOW signals.

[2] All ground pins should normally be connected to a common ground plane.

[3] I = input only; O = output only; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; AI = analog input; P =

power.

[4] For port 1.

[5] For port 2.

[6] For port 3.

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7. Functional description

7.1 ISP1760 internal architecture: advanced NXP slave host controller

and hub

The EHCI block and the Hi-Speed USB hub block are the main components of the

advanced NXP slave host controller.

The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the

ISP1760 is adapted from Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

The internal Hi-Speed USB hub block replaces the companion host controller block used

in the original PCI Hi-Speed USB host controllers to handle full-speed and low-speed

modes. The hardware architecture in the ISP1760 is simpliﬁed to help reduce cost and

development time, by eliminating the additional work involved in implementing the OHCI

software required to support full-speed and low-speed modes.

Figure 4 shows the internal architecture of the ISP1760. The ISP1760 implements the

EHCI that has an internal port, the root hub port (not available externally), on which the

internal hub is connected. The three external ports are always routed to the internal hub.

The internal hub is a Hi-Speed USB (USB 2.0) hub, including the TT.

Remark: The root hub must be enabled and the internal hub must be enumerated.

Enumerate the internal hub as if it is externally connected. For details, refer to Ref. 5

“Interfacing the ISP176x to the Intel PXA25x processor (AN10037)”.

At the host controller reset and initialization, the internal root hub port will be polled until a

new connection is detected, showing the connection of the internal hub.

The internal Hi-Speed USB hub is enumerated using a sequence similar to a standard

Hi-Speed USB hub enumeration sequence, and the polling on the root hub is stopped

because the internal Hi-Speed USB hub will never be disconnected. When enumerated,

the internal hub will report the three externally available ports.

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EHCI

ROOT HUB

PORTSC1

ENUMERATION

AND POLLING USING

ACTUAL PTDs

INTERNAL HUB (TT)

PORT2

PORT1

PORT3

EXTERNAL

PORTS

004aaa513

Fig 4. Internal hub

7.1.1 Internal clock scheme and port selection

The ISP1760 has three ports. Figure 5 shows the internal clock scheme of the ISP1760.

host clock:

DIGITAL CORE

48 MHz,

30 MHz,

60 MHz

PORT 2

ATX

HOST

CORE

PORT 1

ATX

XOSC

PORT 3

ATX

PLL 12 MHz IN

004aaa535

Fig 5. ISP1760 clock scheme

Figure 5 shows that the host clock is derived from port 2. Port 2 does not need to be

enabled by software, if only port 1 or port 3 is used. No port needs to be disabled by

external pull-up resistors, if not used. The DP and DM of the unused ports need not be

externally pulled HIGH because there are internal pull-down resistors on each port that

are enabled by default.

Table 3 lists the various port connection scenarios.

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Table 3.

Port connection scenarios

Port conﬁguration Port 1

Port 2

Port 3

One port (port 1)

One port (port 2)

One port (port 3)

DP and DM are routed to USB DP and DM are not connected

connector (left open)

DP and DM are not connected

(left open)

DP and DM are not connected DP and DM are routed to USB

(left open) connector

DP and DM are not connected

(left open)

DP and DM are not connected DP and DM are not connected

(left open) (left open)

DP and DM are routed to USB

connector

Two ports (ports 1

and 2)

DP and DM are routed to USB DP and DM are routed to USB

connector connector

DP and DM are not connected

(left open)

Two ports (ports 2

and 3)

DP and DM are not connected DP and DM are routed to USB

(left open) connector

DP and DM are routed to USB

connector

Two ports (ports 1

and 3)

DP and DM are routed to USB DP and DM are not connected

connector (left open)

DP and DM are routed to USB

connector

Three ports (ports 1, DP and DM are routed to USB DP and DM are routed to USB

DP and DM are routed to USB

connector

2 and 3)

connector

7.2 Host controller buffer memory block

7.2.1 General considerations

The internal addressable host controller buffer memory is 63 kB. The 63 kB effective

memory size is the result of subtracting the size of the registers (1 kB) from the total

addressable memory space deﬁned in the ISP1760 (64 kB). This is the optimized value to

achieve the highest performance with minimal cost.

The ISP1760 is a slave host controller. This means that it does not need access to the

local bus of the system to transfer data from the system memory to the ISP1760 internal

memory, unlike the case of the original PCI Hi-Speed USB host controllers. Therefore,

correct data must be transferred to both the PTD area and the payload area by PIO (using

CPU access) or programmed DMA.

The ‘slave-host’ architecture ensures better compatibility with most of the processors

present in the market today because not all processors allow a ‘bus-master’ on the local

bus. It also allows better load balancing of the processor’s local bus because only the

internal bus arbiter of the processor controls the transfer of data dedicated to USB. This

prevents the local bus from being busy when other more important transfers may be in the

queue; and therefore achieving a ‘linear’ system data ﬂow that has less impact on other

processes running at the same time.

The considerations mentioned are also the main reason for implementing the pre-fetching

technique, instead of using a READY signal. The resulting architecture avoids ‘freezing’ of

the local bus, by asserting READY, enhancing the ISP1760 memory access time, and

avoiding introduction of programmed additional wait states. For details, see Section 7.3

and Section 8.3.8.

The total amount of memory allocated to the payload determines the maximum transfer

size speciﬁed by a PTD, a larger internal memory size results in less CPU interruption for

transfer programming. This means less time spent in context switching, resulting in better

CPU usage.

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A larger buffer also implies a larger amount of data can be transferred. The transfer,

however, can be done over a longer period of time, to maintain the overall system

performance. Each transfer of the USB data on the USB bus can span for up to a few

milliseconds before requiring further CPU intervention for data movement.

The internal architecture of the ISP1760 allows a ﬂexible deﬁnition of the memory buffer

for optimization of the data transfer on the CPU extension bus and the USB. It is possible

to implement various data transfer schemes, depending on the number and type of USB

devices present. For example: push-pull; data can be written to half of the memory while

data in the other half is being accessed by the host controller and sent on the USB bus.

This is useful especially when a high-bandwidth ‘continuous or periodic’ data ﬂow is

required.

Through an analysis of the hardware and software environment regarding the usual data

ﬂow and performance requirements of most embedded systems, NXP has determined the

optimal size for the internal buffer as approximately 64 kB.

7.2.2 Structure of the ISP1760 host controller memory

The 63 kB internal memory consists of the PTD area and the payload area.

PTD memory zone is divided into three dedicated areas for each main type of USB

transfer: Isochronous (ISO), Interrupt (INT) and Asynchronous Transfer List (ATL). As

shown in Table 4, the PTD areas for ISO, INT and ATL are grouped at the beginning of the

memory, occupying the address range 0400h to 0FFFh, following the register address

space. The payload or data area occupies the next memory address range 1000h to

FFFFh, meaning that 60 kB of memory are allocated for the payload data.

A maximum of 32 PTD areas and their allocated payload areas can be deﬁned for each

type of transfer. The structure of a PTD is similar for every transfer type and consists of

eight Double Words (DWs) that must be correctly programmed for a correct USB data

transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the

PTD structure can be found in Section 9.

The transfer size speciﬁed by the PTD determines the contiguous USB data transfer that

can be performed without any CPU intervention. The respective payload memory area

must be equal to the transfer size deﬁned. The maximum transfer size is ﬂexible and can

be optimized, depending on the number and nature of USB devices or PTDs deﬁned and

their respective MaxPacketSize.

The CPU will program the DMA to transfer the necessary data in the payload memory.

The next CPU intervention will be required only when the current transfer is completed

and DMA programming is necessary to transfer the next data payload. This is normally

signaled by the IRQ that is generated by the ISP1760 on completing the current PTD,

meaning all the data in the payload area was sent on the USB bus. The external IRQ

signal is asserted according to the settings in the IRQ Mask OR or IRQ Mask AND

registers, see Section 8.4.

The RAM is structured in blocks of PTDs and payloads so that while the USB is executing

on an active transfer-based PTD, the processor can simultaneously ﬁll up another block

area in the RAM. A PTD and its payload can then be updated on-the-ﬂy without stopping

or delaying any other USB transaction or corrupting the RAM data.

Some of the design features are:

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• The address range of the internal RAM buffer is from 0400h to FFFFh.

• The internal memory contains isochronous, interrupt and asynchronous PTDs, and

respective deﬁned payloads.

• All accesses to the internal memory are double word aligned.

• Internal memory address range calculation:

Memory address = (CPU address − 0400h) (shift right >> 3). Base address is 0400h.

Table 4.

Memory address

Memory map

ISO

CPU address

Memory address

0000h to 007Fh

0080h to 00FFh

0100h to 017Fh

0180h to 1FFFh

0400h to 07FFh

0800h to 0BFFh

0C00h to 0FFFh

1000h to FFFFh

INT

ATL

Payload

PTD1

PTD2

63 kB

ISOCHRONOUS

PTD32

PTD1

PTD2

INTERRUPT

PTD32

PTD1

PTD2

REGISTERS

ASYNC

PTD32

D[15:0]/D[31:0]

A[17:1]

PAYLOAD

USB HIGH-SPEED

USB BUS

MEMORY MAPPED

INPUT/OUTPUT,

MEMORY

MANAGEMENT

UNIT,

SLAVE DMA

CONTROLLER

AND

HOST AND

TRANSACTION

TRANSLATOR

(FULL-SPEED

PAYLOAD

CS_N

RD_N

MICRO-

PROCESSOR

AND LOW-SPEED)

PAYLOAD

WR_N

IRQ

INTERRUPT

CONTROL

address

data (64 bits)

240 MB/s

DREQ

DACK

ARBITER

004aaa436

control signals

Fig 6. Memory segmentation and access block diagram

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Both the CPU interface logic and the USB host controller require access to the internal

ISP1760 RAM at the same time. The internal arbiter controls these accesses to the

internal memory, organized internally on a 64-bit data bus width, allowing a maximum

bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the

CPU interface and the internal USB host controller.

7.3 Accessing the ISP1760 host controller memory: PIO and DMA

The CPU interface of the ISP1760 can be conﬁgured for a 16-bit or 32-bit data bus width.

When the ISP1760 is conﬁgured for a 16-bit data bus width, the upper unused 16 data

lines must be pulled up to V_CC(I/O). This can be achieved by connecting DATA[31:16] lines

together to a single 10 kΩ pull-up resistor. The 16-bit or 32-bit data bus width

conﬁguration is done by programming bit 8 of the HW Mode Control register. This will

determine the register and memory access types in both PIO and DMA modes. All

accesses must be word-aligned for 16-bit mode and double word aligned for 32-bit mode,

where one word = 16 bits. When accessing the host controller registers in 16-bit mode,

the register access must always be completed using two subsequent accesses. In the

case of a DMA transfer, the 16-bit or 32-bit data bus width conﬁguration will determine the

number of bursts that will complete a certain transfer length.

In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA

mode, the data validation is performed by DACK, instead of CS_N, together with the

WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the

ISP1760 DMA is enabled.

7.3.1 PIO mode access, memory read cycle

The following method has been implemented to reduce the read access timing in the case

of a memory read:

• The Memory register contains the starting address and the bank selection to read

from the memory. Before every new read cycle of the same or different banks, an

appropriate value is written to this register.

• Once a value is written to this register, the address is stored in the FIFO of that bank

and is then used to pre-fetch data for the memory read of that bank.

For every subsequent read operation executed at a contiguous address, the address

pointer corresponding to that bank is automatically incremented to pre-fetch the next

data to be sent to the CPU.

Memory read accesses for multiple banks can be interleaved. The FIFO block

handles the multiplexing of appropriate data to the CPU.

• The address written to the Memory register is incremented and used to successively

pre-fetch data from the memory irrespective of the value on the address bus for each

bank, until a new value for a bank is written to the Memory register. This is valid only

when the address refers to the memory space (400h to FFFFh).

For example, consider the following sequence of operations:

– Write the starting (read) address 4000h and bank1 = 01 to the Memory register.

When RD_N is asserted for three cycles with A[17:16] = 01, the returned data

corresponds to addresses 4000h, 4004h and 4008h.

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Remark: Once 4000h is written to the Memory register for bank1, the bank select

value determines the successive incremental addresses used to fetch data. That

is, the fetching of data is independent of the address on A[15:0] lines.

– Write the starting (read) address 4100h and bank2 = 10 to the Memory register.

When RD_N is asserted for four cycles with A[17:16] = 10, the returned data

corresponds to addresses 4100h, 4104h, 4108h and 410Ch.

Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch

because the bank1 read stopped there in the previous cycle. Also, RD_N

assertions with A[17:16] = 10 will now return data from 4110h because the bank2

read stopped there in the previous cycle.

7.3.2 PIO mode access, memory write cycle

The PIO memory write access is similar to a normal memory access. It is not necessary

to set the pre-fetching address before a write cycle to the memory.

The ISP1760 internal write address will not be automatically incremented during

consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The

memory write address must be incremented before every access.

7.3.3 PIO mode access, register read cycle

The PIO register read access is similar to a general register access. It is not necessary to

set a pre-fetching address before a register read.

The ISP1760 register read address will not be automatically incremented during

consecutive read accesses, unlike in a series of ISP1760 memory read cycles. The

ISP1760 register read address must be correctly speciﬁed before every access.

7.3.4 PIO mode access, register write cycle

The PIO register write access is similar to a general register access. It is not necessary to

set a pre-fetching address before a register write.

The ISP1760 register write address will not be automatically incremented during

consecutive write accesses, unlike in a series of ISP1760 memory read cycles. The

ISP1760 register write address must be correctly speciﬁed before every access.

7.3.5 DMA mode, read and write operations

The internal ISP1760 host controller DMA is a slave DMA. The host system processor or

DMA must ensure the data transfer to or from the ISP1760 memory.

The ISP1760 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles for both the 16-bit

and 32-bit data bus width. DREQ will be asserted at the beginning of the ﬁrst burst of a

DMA transfer and will be de-asserted on the last cycle, RD_N or WR_N active pulse, of

that burst. It will be reasserted shortly after the DACK de-assertion, as long as the DMA

transfer counter was not reached. DREQ will be de-asserted on the last cycle when the

DMA transfer counter is reached and will not be reasserted until the DMA reprogramming

is performed. Both the DREQ and DACK signals are programmable as active LOW or

active HIGH, according to the system requirements.

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The DMA start address must be initialized in the respective register, and the subsequent

transfers will automatically increment the internal ISP1760 memory address. A register or

memory access or access to other system memory can occur in between DMA bursts,

whenever the bus is released because DACK is de-asserted, without affecting the DMA

transfer counter or the current address.

Any memory area can be accessed by the system’s DMA at any starting address because

there are no predeﬁned memory blocks. The DMA transfer must start on a word or double

word address, depending on whether the data bus width is set to 16 bit or 32 bit. DMA is

the most efﬁcient method to initialize the payload area, to reduce the CPU usage and

overall system loading.

The ISP1760 does not implement EOT to signal the end of a DMA transfer. If

programmed, an interrupt may be generated by the ISP1760 at the end of the DMA

transfer.

The slave DMA of the ISP1760 will issue a DREQ to the DMA controller of the system to

indicate that it is programmed for transfer and data is ready. The system DMA controller

may also start a transfer without the need of the DREQ, if the ISP1760 memory is

available for the data transfer and the ISP1760 DMA programming is completed.

It is also possible that the system’s DMA will perform a memory-to-memory type of

transfer between the system memory and the ISP1760 memory. The ISP1760 will be

accessed in PIO mode. Consequently, memory read operations must be preceded by

initializing the Memory register (address 033Ch), as described in Section 7.3.1. No IRQ

will be generated by the ISP1760 on completing the DMA transfer but an internal

processor interrupt may be generated to signal that the DMA transfer is completed. This is

mainly useful in implementing the double-buffering scheme for data transfer to optimize

the USB bandwidth.

The ISP1760 DMA programming involves:

• Set the active levels of signals DREQ and DACK in the HW Mode Control register.

• The DMA Start Address register contains the ﬁrst memory address at which the data

transfer will start. It must be word-aligned in 16-bit data bus mode and double word

aligned in 32-bit data bus mode.

• The programming of the DMA Conﬁguration register speciﬁes:

– The type of transfer that will be performed: read or write.

– The burst size, expressed in bytes, is speciﬁed, regardless of the data bus width.

For the same burst size, a double number of cycles will be generated in 16-bit

mode data bus width as compared to 32-bit mode.

– The transfer length, expressed in number of bytes, deﬁnes the number of bursts.

The DREQ will be de-asserted and asserted to generate the next burst, as long as

there are bytes to be transferred. At the end of a transfer, the DREQ will be

de-asserted and an IRQ can be generated if DMAEOTINT (bit 3 in the Interrupt

register) is set. The maximum DMA transfer size is equal to the maximum memory

size. The transfer size can be an odd or even number of bytes, as required. If the

transfer size is an odd number of bytes, the number of bytes transferred by the

system’s DMA is equal to the next multiple of two for the 16-bit data bus width or

four for the 32-bit data bus width. For a write operation, however, only the speciﬁed

odd number of bytes in the ISP1760 memory will be affected.

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– Enable ENABLE_DMA (bit 1) of the DMA Conﬁguration register to determine the

assertion of DREQ immediately after setting the bit.

After programming the preceding parameters, the system’s DMA may be enabled, waiting

for the DREQ to start the transfer or immediate transfer may be started.

The programming of the system’s DMA must match the programming of the ISP1760

DMA parameters. Only one DMA transfer may take place at a time. PIO mode data

transfer may occur simultaneously with a DMA data transfer, in the same or a different

memory area.

7.4 Interrupts

The ISP1760 will assert an IRQ according to the source or event in the Interrupt register.

The main steps to enable the IRQ assertion are:

1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register.

2. Deﬁne the IRQ active as level or edge in INTR_LEVEL (bit 1) of the HW Mode Control

register.

3. Deﬁne the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW

Mode Control register. These settings must match the IRQ settings of the host

processor.

By default, interrupt is level-triggered and active LOW.

4. Program the individual interrupt enable bits in the Interrupt Enable register. The

software will need to clear the interrupt status bits in the Interrupt register before

enabling individual interrupt enable bits.

Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as

necessary, applicable only when IRQ is set to be edge-active; a pulse of a deﬁned width is

generated every time IRQ is active.

Bits 15 to 0 of the Edge Interrupt Count register deﬁne the IRQ pulse width. The maximum

pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This

setting is necessary for certain processors that may require a different minimum IRQ

pulse width from the default value. The default IRQ pulse width set at power-on is

approximately 500 ns.

Bits 31 to 24 of the Edge Interrupt Count register deﬁne the minimum interval between two

interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed to

these bits determines the normal IRQ generation, without any delay. When a delay is

programmed and the IRQ becomes active after the respective delay, several IRQ events

may have already occurred.

All the interrupt events are represented by the respective bits allocated in the Interrupt

register. There is no mechanism to show the order or the moment of occurrence of an

interrupt.

The asserted bits in the Interrupt register can be cleared by writing back the same value to

the Interrupt register. This means that writing logic 1 to each of the set bits will reset the

corresponding bits to the initial inactive state.

The IRQ generation rules that apply according to the preceding settings are:

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• If an event of interrupt occurs but the respective bit in the Interrupt Enable register is

not set, then the respective Interrupt register bit is set but the interrupt signal is not

asserted.

An interrupt will be generated when interrupt is enabled and the respective bit in the

Interrupt Enable register is set.

• For a level trigger, an interrupt signal remains asserted until the processor clears the

Interrupt register by writing logic 1 to clear the Interrupt register bits that are set.

• If an interrupt is made edge-sensitive and is asserted, writing to clear the Interrupt

register will not have any effect because the interrupt will be asserted for a prescribed

amount of clock cycles.

• The clock stopping mechanism does not affect the generation of an interrupt. This is

useful during the suspend and resume cycles, when an interrupt is generated to

signal a wake-up event.

The IRQ generation can also be conditioned by programming the IRQ Mask OR and IRQ

Mask AND registers.

With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer

(ISO, INT and bulk), software can determine which PTDs get priority and an interrupt will

be generated when the AND or OR conditions are met. The PTDs that are set will wait

until the respective bits of the remaining PTDs are set and then all PTDs generate an

interrupt request to the CPU together.

The registers deﬁnition shows that the AND or OR conditions are applicable to the same

category of PTDs: ISO, INT, ATL.

When an IRQ is generated, the PTD Done Map registers and the respective V bits will

show which PTDs were completed.

The rules that apply to the IRQ Mask AND or IRQ Mask OR settings are:

• The OR mask has a higher priority over the AND mask. An IRQ is generated if bit n of

the done map is set and the corresponding bit n of the OR Mask register is set.

• If the OR mask for any done bit is not set, then the AND mask comes into picture. An

IRQ is generated if all the corresponding done bits of the AND Mask register are set.

For example: If bits 2, 4 and 10 are set in the AND Mask register, an IRQ is generated

only if bits 2, 4, 10 of the done map are set.

• If using the IRQ interval setting for the bulk PTD, an interrupt will only occur at the

regular time interval as programmed in the ATL Done Timeout register. Even if an

interrupt event occurs before the time-out of the register, no IRQ will be generated

until the time is up.

For an example on using the IRQ Mask AND or IRQ Mask OR registers without the ATL

Done Timeout register, see Table 5.

The AND function: Activate the IRQ only if PTDs 1, 2 and 4 are done.

The OR function: If any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be

raised.

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Table 5.

Using the IRQ Mask AND or IRQ Mask OR registers

PTD

1

AND register OR register

Time

1 ms

-

PTD done

IRQ

1

0

1

0

1

-

2

-

3

-

4

3 ms

-

1

-

active because of AND

5

-

6

-

7

5 ms

6 ms

7 ms

1

active because of OR

8

9

7.5 Phase-Locked Loop (PLL) clock multiplier

The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz

clock already existing in the system with a precision better than 50 ppm. This allows the

use of a low-cost 12 MHz crystal that also minimizes ElectroMagnetic Interference (EMI).

When an external crystal is used, make sure the CLKIN pin is connected to V_CC(I/O)

.

The PLL block generates all the main internal clocks required for normal functionality of

various blocks: 30 MHz, 48 MHz and 60 MHz.

No external components are required for the PLL operation.

7.6 Power management

The ISP1760 implements a ﬂexible power management scheme, allowing various power

saving stages.

The usual powering scheme implies programming EHCI registers and the internal

Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed

USB host controller with a Hi-Speed USB hub attached.

When the ISP1760 is in suspend mode, the main internal clocks will be stopped to ensure

minimum power consumption. An internal LazyClock of 100 kHz ± 40 % will continue

running. This allows initiating a resume on one of these events:

• External USB device connect or disconnect

• CS_N signal asserted when the ISP1760 is accessed

• Driving the SUSPEND/WAKEUP_N pin to a LOW level

The SUSPEND/WAKEUP_N pin is a bidirectional pin. This pin must be connected to one

of the GPIO pins of a processor.

The awake state can be veriﬁed by reading the LOW level of this pin. If the level is HIGH,

it means that the ISP1760 is in the suspend state.

The SUSPEND/WAKEUP_N pin requires a pull-up because in the ISP1760 suspended

state the pin becomes 3-state and can be pulled down, driving it externally by switching

the processor’s GPIO line to output mode to generate the ISP1760 wake-up.

ISP1760_4

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The SUSPEND/WAKEUP_N pin is a 3-state output. It is also an input to the internal

wake-up logic.

When in suspend mode, the ISP1760 internal wake-up circuitry will sense the status of

the SUSPEND/WAKEUP_N pin:

• If it remains pulled-up, no wake-up is generated because a HIGH is sensed by the

internal wake-up circuit.

• If the pin is externally pulled LOW, for example, by the GPIO line or just as a test by

jumper, the input to the wake-up circuitry becomes LOW and the wake-up is internally

initiated.

The resume state has a clock-off count timer deﬁned by bits 31 to 16 of the Power Down

Control register. The default value of this timer is 10 ms, meaning that the resume state

will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD

register is set to logic 1, the host controller will go into a permanent resume; the normal

functional state. If the RUN/STOP bit is not set during the time determined by the clock-off

count, the ISP1760 will switch back to suspend mode after the speciﬁed time. The

maximum delay that can be programmed in the clock-off count ﬁeld is approximately

500 ms.

Additionally, the Power Down Control register allows the ISP1760 internal blocks to be

disabled for lower power consumption as deﬁned in Table 51.

The lowest suspend current, I_CC(susp), that can be achieved is approximately 150 µA at

room temperature. The suspend current will increase with the increase in temperature,

with approximately 300 µA at 40 °C and up to a typical 1 mA at 85 °C. The system is not in

suspend mode when its temperature increases above 40 °C. Therefore, even a 1 mA

current consumption by the ISP1760 in suspend mode can be considered negligible. In

normal environmental conditions, when the system is in suspend mode, the maximum

ISP1760 temperature will be approximately 40 °C determined by the ambient temperature

so the ISP1760 maximum suspend current will be below 300 µA. An alternative solution to

achieve a very low suspend current is to completely switch off the V_CC(5V0)power input by

using an external PMOS transistor, controlled by one of the GPIO pins of the processor.

This is possible because the ISP1760 can be used in hybrid mode, which allows only the

V_CC(I/O)powered on to avoid loading of the system bus.

When the ISP1760 power is always on, the time from wake-up to suspend will be

approximately 100 ms.

It is necessary to wait for the CLKREADY interrupt assertion before programming the

ISP1760 because internal clocks are stopped during deep-sleep suspend and restarted

after the ﬁrst wake-up event. The occurrence of the CLKREADY interrupt means that

internal clocks are running and the normal functionality is achieved.

It is estimated that the CLKREADY interrupt will be generated less than 100 µs after the

wake-up event, if the power to the ISP1760 was on during suspend.

If the ISP1760 is used in hybrid mode and V_CC(5V0)is off during suspend, a 2 ms reset

pulse is required when the power is switched back on, before the resume programming

sequence starts. This will ensure that internal clocks are running and all logics reach a

stable initial state.

ISP1760_4

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7.7 Overcurrent detection

The ISP1760 can implement a digital or analog overcurrent detection scheme. Bit 15 of

the HW Mode Control register can be programmed to select the analog or digital

overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The

main features of this circuit are self reporting, automatic resetting, low-trip time and low

cost. This circuit offers an easy solution at no extra hardware cost on the board. The port

power will automatically be disabled by the ISP1760 on an overcurrent event occurrence,

by de-asserting the PSWn_N signal without any software intervention.

When using the integrated analog overcurrent detection, the range of the overcurrent

detection voltage for the ISP1760 is 45 mV to 100 mV. Calculation of external components

should be based on the 45 mV value, with the actual overcurrent detection threshold

usually positioned in the middle of the interval.

For an overcurrent limit of 500 mA per port, a PMOS with R_DSonof approximately 100 mΩ

is required. If a PMOS with a lower R_DSonis used, analog overcurrent detection can be

adjusted using a series resistor; see Figure 7.

∆V_PMOS= ∆V_trip(OC)= ∆V_trip(int)− (I_OC(nom)× R_adj(oc)), where:

∆V_PMOS= voltage drop on PMOS

I_OC(nom)= 1 µA

5 V

I

OC

(1)

R

adj(oc)

PSWn_N

OCn_N

REF5V

ISP1760

004aaa662

(1) R_adj(oc)is optional.

Fig 7. Adjusting analog overcurrent detection limit (optional)

The digital overcurrent scheme requires using an external power switch with integrated

overcurrent detection, such as LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These

devices are controlled by PSWn_N signals corresponding to each port. In the case of

overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion,

the ISP1760 cuts off the port power by de-asserting PSWn_N. The external integrated

power switch will also automatically cut off the port power in the case of an overcurrent

event, by implementing thermal shutdown. An internal delay ﬁlter will prevent false

overcurrent reporting because of in-rush currents when plugging a USB device. Because

of this internal delay, as soon as OCn_N is asserted, PSWn_N will switch off the external

PMOS in less than 15 ms.

ISP1760_4

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7.8 Power supply

Figure 8 shows the ISP1760 power supply connection.

ISP1760BE

V

CC(5V0)

CC(I/O)

3.3 V to 5 V

100 nF

6, 7

10, 40, 48,

59, 67, 75,

83, 94,

1.65 V to 3.6 V

100 nF

104, 115

REG1V8

85

100 nF

10 µF

5, 50, 118

9

100 nF

REG3V3

10 µF

100 nF

004aaa533

The ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

A 4.7 µF-to-10 µF electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.

All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 Ω to 2 Ω).

Fig 8. ISP1760 power supply connection

Figure 9 shows the most commonly used power supply connection.

ISP1760BE

6, 7, 10,

40, 48, 59,

67, 75, 83,

94, 104, 115

V

, V

)

CC(5V0) CC(I/O

3.3 V

100 nF

REG1V8

85

100 nF

10 µF

5, 50, 118

9

100 nF

REG3V3

10 µF

100 nF

004aaa534

The ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

A 4.7 µF-to-10 µF electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.

All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 Ω to 2 Ω).

Fig 9. Most commonly used power supply connection

7.8.1 Hybrid mode

Table 6 shows the description of hybrid mode.

ISP1760_4

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Table 6.

Hybrid mode

Voltage

V_CC(5V0)

V_CC(I/O)

Status

off

on

In hybrid mode (see Figure 10), V_CC(5V0)can be switched off using an external PMOS

transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the

suspend current, I_CC(I/O), below 100 µA. If the ISP1760 is used in hybrid mode and

V_CC(5V0)is off during suspend, a 2 ms reset pulse is required when power is switched

back on, before the resume programming sequence starts.

controlled by the CPU

ISP1760BE

V

CC(5V0)

3.3 V to 5 V

100 nF

6, 7

10, 40, 48,

59, 67, 75,

83, 94,

1.65 V to 3.6 V

100 nF

CC(I/O)

104, 115

REG1V8

85

100 nF

10 µF

5, 50, 118

9

100 nF

REG3V3

10 µF

100 nF

004aaa677

The ﬁgure shows the LQFP pinout. For the TFBGA ballout, see Table 2.

A 4.7 µF-to-10 µF electrolytic or tantalum capacitor is required on any one of the pins 5, 50 or 118.

All the electrolytic or tantalum capacitors must be of LOW ESR type (0.2 Ω to 2 Ω).

Fig 10. Hybrid mode

Table 7 shows the status of output pins during hybrid mode.

Table 7.

Pins

Pin status in hybrid mode

V_CC(I/O)

V_CC(5V0)

Status

normal

high-Z

DATA[31:0], A[17:1], TEST1, TEST2, TEST3, on

TEST4, TEST5, TEST6, TEST7, DREQ,

DACK, IRQ, SUSPEND/WAKEUP_N

off

on

off

X

on

undeﬁned

input

CS_N, RESET_N, RD_N, WR_N

on

off

X

undeﬁned

7.9 Power-On Reset (POR)

When V_CC(I/O)is directly connected to the RESET_N pin, the internal POR pulse width,

t_PORP, will typically be 800 ns. The pulse is started when V_CC(5V0)rises above V_TRIPof

1.2 V.

ISP1760_4

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ISP1760

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To give a better view of the functionality, Figure 11 shows a possible curve of V_CC(5V0)with

dips at t2 to t3 and t4 to t5. If the dip at t4 to t5 is too short, that is, < 11 µs, the internal

POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1,

the detector will see the passing of the trip level and a delay element will add another

t_PORPbefore it drops to 0.

The internal POR pulse will be generated whenever V_CC(5V0)drops below V_TRIPfor more

than 11 µs.

V

CC(5V0)

TRIP

t4

t0

t1

t

t3

t5

t2

(1)

PORP

t

PORP

004aaa584

(1) PORP = Power-On Reset Pulse.

Fig 11. Internal power-on reset timing

The recommended RESET input pulse length at power-on must be at least 2 ms to ensure

that internal clocks are stable.

The RESET_N pin can be either connected to V_CC(I/O)using the internal POR circuit or

externally controlled by the microcontroller, ASIC, and so on. Figure 12 shows the

availability of the clock with respect to the external POR.

RESET_N

EXTERNAL CLOCK

004aaa583

A

Stable external clock is available at A.

Fig 12. Clock with respect to the external power-on reset

ISP1760_4

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ISP1760

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8. Registers

Table 8 shows the bit description of the registers.

• All registers range from 0000h to 03FFh. These registers can be read or written as

double word, that is 32-bit data. In the case of a 16-bit data bus width, two subsequent

accesses are necessary to complete the register read or write cycle.

• Operational registers range from 0000h to 01FFh. Conﬁguration registers range from

0300h to 03FFh.

Table 8.

Address

Register overview

Register

Reset value

References

EHCI capability registers

0000h

0002h

0004h

0008h

CAPLENGTH

20h

Section 8.1.1 on page 30

Section 8.1.2 on page 30

Section 8.1.3 on page 30

Section 8.1.4 on page 31

HCIVERSION

HCSPARAMS

HCCPARAMS

0100h

0000 0011h

0000 0086h

EHCI operational registers

0020h

0024h

0028h

002Ch

0060h

0064h

0130h

0134h

0138h

0140h

0144h

0148h

0150h

0154h

0158h

USBCMD

0008 0B00h

0000 0000h

0000 2000h

0000 0000h

FFFF FFFFh

0000 0000h

FFFF FFFFh

0000 0000h

FFFF FFFFh

0000 0000h

-

Section 8.2.1 on page 32

Section 8.2.2 on page 33

Section 8.2.3 on page 34

Section 8.2.4 on page 34

Section 8.2.5 on page 35

Section 8.2.6 on page 36

Section 8.2.7 on page 37

Section 8.2.8 on page 37

Section 8.2.9 on page 38

Section 8.2.10 on page 38

Section 8.2.11 on page 38

Section 8.2.12 on page 39

Section 8.2.13 on page 39

Section 8.2.14 on page 39

Section 8.2.15 on page 40

-

USBSTS

USBINTR

FRINDEX

CONFIGFLAG

PORTSC1

ISO PTD Done Map

ISO PTD Skip Map

ISO PTD Last PTD

INT PTD Done Map

INT PTD Skip Map

INT PTD Last PTD

ATL PTD Done Map

ATL PTD Skip Map

ATL PTD Last PTD

0200h to 02FFh reserved

Conﬁguration registers

0300h

0304h

0308h

030Ch

0330h

0334h

0338h

033Ch

0340h

HW Mode Control

0000 0100h

0001 1761h

0000 0000h

0000 000Fh

Section 8.3.1 on page 40

Section 8.3.2 on page 41

Section 8.3.3 on page 42

Section 8.3.4 on page 42

Section 8.3.5 on page 43

Section 8.3.6 on page 44

Section 8.3.7 on page 45

Section 8.3.8 on page 45

Section 8.3.9 on page 46

Chip ID

Scratch

SW Reset

DMA Conﬁguration

Buffer Status

ATL Done Timeout

Memory

Edge Interrupt Count

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

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ISP1760

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Embedded Hi-Speed USB host controller

Table 8.

Register overview …continued

Register

Address

0344h

Reset value

References

DMA Start Address

Power Down Control

Port 1 Control

0000 0000h

03E8 1BA0h

0086 0086h

Section 8.3.10 on page 47

Section 8.3.11 on page 48

Section 8.3.12 on page 50

0354h

0374h

Interrupt registers

0310h

0314h

0318h

031Ch

0320h

0324h

0328h

032Ch

Interrupt

0000 0000h

Section 8.4.1 on page 51

Section 8.4.2 on page 53

Section 8.4.3 on page 54

Section 8.4.4 on page 55

Section 8.4.5 on page 55

Section 8.4.6 on page 55

Section 8.4.7 on page 55

Section 8.4.8 on page 56

Interrupt Enable

ISO IRQ Mask OR

INT IRQ Mask OR

ATL IRQ Mask OR

ISO IRQ Mask AND

INT IRQ Mask AND

ATL IRQ Mask AND

8.1 EHCI capability registers

8.1.1 CAPLENGTH register

The bit description of the Capability Length (CAPLENGTH) register is given in Table 9.

Table 9.

Bit

CAPLENGTH - Capability Length register (address 0000h) bit description

Symbol

Access Value Description

7 to 0

CAPLENGTH[7:0] R

20h

Capability Length: This is used as an offset. It is added to the register

base to ﬁnd the beginning of the operational register space.

8.1.2 HCIVERSION register

Table 10 shows the bit description of the Host Controller Interface Version Number

(HCIVERSION) register.

Table 10. HCIVERSION - Host Controller Interface Version Number register (address 0002h) bit description

Bit

Symbol

Access Value

0100h

Description

15 to 0

HCIVERSION[15:0] R

Host Controller Interface Version Number: It contains a BCD

encoding of the version number of the interface to which the host

controller interface conforms.

8.1.3 HCSPARAMS register

The Host Controller Structural Parameters (HCSPARAMS) register is a set of ﬁelds that

are structural parameters. The bit allocation is given in Table 11.

Table 11. HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

0

R

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Bit

23

22

21

20

19

18

17

16

Symbol

DPN[3:0]

reserved

P_INDICAT

OR

Reset

Access

Bit

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

N_CC[3:0]

reserved

N_PCC[3:0]

0

R

0

R

6

0

R

5

0

R

0

R

3

0

R

2

0

R

1

0

R

0

7

4

Symbol

Reset

Access

PRR

0

PPC

1

N_PORTS[3:0]

0

1

R

Table 12. HCSPARAMS - Host Controller Structural Parameters register (address 0004h) bit

description

Bit

Symbol

Description^[1]

31 to 24

-

reserved; write logic 0

23 to 20 DPN[3:0]

Debug Port Number: This ﬁeld identiﬁes which of the host controller

ports is the debug port.

19 to 17

16

-

reserved; write logic 0

P_INDICATOR Port Indicators: This bit indicates whether the ports support port

indicator control.

15 to 12 N_CC[3:0]

Number of Companion Controller: This ﬁeld indicates the number

of companion controllers associated with this Hi-Speed USB host

controller.

11 to 8

7

N_PCC[3:0]

PRR

Number of Ports per Companion Controller: This ﬁeld indicates

the number of ports supported per companion host controller.

Port Routing Rules: This ﬁeld indicates the method used to map

ports to companion controllers.

6 to 5

4

-

reserved; write logic 0

PPC

Port Power Control: This ﬁeld indicates whether the host controller

implementation includes port power control.

3 to 0

N_PORTS[3:0] N_Ports: This ﬁeld speciﬁes the number of physical downstream

ports implemented on this host controller.

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.1.4 HCCPARAMS register

The Host Controller Capability Parameters (HCCPARAMS) register is a four-byte register,

and the bit allocation is given in Table 13.

Table 13. HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved

0

R

ISP1760_4

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Embedded Hi-Speed USB host controller

Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved

0

R

0

R

0

R

0

R

0

R

0

R

0

R

9

0

R

8

15

14

13

12

11

10

Symbol

Reset

Access

Bit

EECP[7:0]

0

R

7

0

R

6

0

R

5

0

R

4

0

R

3

0

R

0

R

2

ASPC

1

0

Symbol

Reset

Access

IST[3:0]

reserved

PFLF

1

reserved

1

0

R

Table 14. HCCPARAMS - Host Controller Capability Parameters register (address 0008h) bit

description

Bit

Symbol

Description^[1]

31 to 16

15 to 8

-

reserved; write logic 0

EECP[7:0] EHCI Extended Capabilities Pointer: Default = implementation

dependent. This optional ﬁeld indicates the existence of a capabilities list.

7 to 4

IST[3:0]

Isochronous Scheduling Threshold: Default = implementation

dependent. This ﬁeld indicates, relative to the current position of the

executing host controller, where software can reliably update the

isochronous schedule.

3

2

-

reserved; write logic 0

ASPC

Asynchronous Schedule Park Capability: Default = implementation

dependent. If this bit is set to logic 1, the host controller supports the park

feature for high-speed Transfer Descriptors in the Asynchronous

Schedule.

1

PFLF

Programmable Frame List Flag: Default = implementation dependent. If

this bit is cleared, the system software must use a frame list length of

1024 elements with this host controller.

If PFLF is set, the system software can specify and use a smaller frame

list and conﬁgure the host through the Frame List Size (FLS) ﬁeld of the

USBCMD register.

0

-

reserved; write logic 0

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2 EHCI operational registers

8.2.1 USBCMD register

The USB Command (USBCMD) register indicates the command to be executed by the

serial host controller. Writing to this register causes a command to be executed. Table 15

shows the USBCMD register bit allocation.

ISP1760_4

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Table 15. USBCMD - USB Command register (address 0020h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

1

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

1

R/W

3

0

R/W

2

1

R/W

0

R/W

4

reserved^[1]

0

1

HCRESET

0

Symbol

Reset

Access

LHCR

0

RS

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 16. USBCMD - USB Command register (address 0020h) bit description

Bit

Symbol

-

Description^[1]

31 to 8

7

reserved

LHCR

Light Host Controller Reset (optional): If implemented, it allows the

driver software to reset the EHCI controller without affecting the state of

the ports or the relationship to the companion host controllers. If not

implemented, a read of this ﬁeld will always return logic 0.

6 to 2

1

-

reserved

HCRESET Host Controller Reset: This control bit is used by the software to reset

the host controller.

0

RS

Run/Stop: 1 = Run, 0 = Stop. When set, the host controller executes the

schedule.

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2.2 USBSTS register

The USB Status (USBSTS) register indicates pending interrupts and various states of the

host controller. The status resulting from a transaction on the serial bus is not indicated in

this register. Software clears register bits by writing ones to them. The bit allocation is

given in Table 17.

Table 17. USBSTS - USB Status register (address 0024h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1760_4

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Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

11

R/W

10

12

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

reserved^[1]

FLR

0

PCD

0

reserved^[1]

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 18. USBSTS - USB Status register (address 0024h) bit description

Bit

Symbol Description^[1]

31 to 4 - reserved; write logic 0

3

FLR

Frame List Rollover: The host controller sets this bit to logic 1 when the frame

list Index rolls over from its maximum value to zero.

2

PCD

Port Change Detect: The host controller sets this bit to logic 1 when any port,

where the PO bit is cleared, has a change to a one or a FPR bit changes to a

one as a result of a J-K transition detected on a suspended port.

1 to 0

-

reserved

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2.3 USBINTR register

The USB Interrupt (USBINTR) register is a read or write register located at 0028h. All the

bits in this register are reserved.

8.2.4 FRINDEX register

The Frame Index (FRINDEX) register is used by the host controller to index into the

periodic frame list. The register updates every 125 µs (once each microframe). Bits n to 3

are used to select a particular entry in the periodic frame list during periodic schedule

execution. The number of bits used for the index depends on the size of the frame list as

set by the system software in the Frame List Size (FLS) ﬁeld of the USBCMD register.

This register must be written as a double word. A word-only write (16-bit mode) produces

undeﬁned results. A write to this register while the RS (Run/Stop) bit is set produces

undeﬁned results. Writes to this register also affect the SOF value. The bit allocation is

given in Table 19.

Table 19. FRINDEX - Frame Index register (address: 002Ch) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

reserved^[1]

0

R/W

ISP1760_4

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Bit

23

22

21

20

19

18

17

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

11

R/W

10

12

Symbol

Reset

Access

Bit

reserved^[1]

FRINDEX[13:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

FRINDEX[7:0]

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 20. FRINDEX - Frame Index register (address: 002Ch) bit description

Bit

Symbol Description^[1]

reserved

FRINDEX Frame Index: Bits in this register are used for the frame number in the SOF

31 to 14

13 to 0

-

[13:0]

packet and as the index into the frame list. The value in this register

increments at the end of each time frame. For example, microframe.

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2.5 CONFIGFLAG register

The bit allocation of the Conﬁgure Flag (CONFIGFLAG) register is given in Table 21.

Table 21. CONFIGFLAG - Conﬁgure Flag register (address 0060h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

R/W

4

reserved^[1]

0

Symbol

Reset

Access

CF

0

R/W

[1] The reserved bits should always be written with the reset value.

ISP1760_4

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Table 22. CONFIGFLAG - Conﬁgure Flag register (address 0060h) bit description

Bit

Symbol

Description^[1]

31 to 1

0

-

reserved

CF

Conﬁgure Flag: The host software sets this bit as the last action when it is

conﬁguring the host controller. This bit controls the default port-routing

control logic.

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

8.2.6 PORTSC1 register

The Port Status and Control (PORTSC) register (bit allocation: Table 23) is in the power

well. It is reset by hardware only when the auxiliary power is initially applied or in response

to a host controller reset. The initial conditions of a port are:

• No peripheral connected

• Port disabled

If the port has power control, software cannot change the state of the port until it sets port

power bits. Software must not attempt to change the state of the port until the power is

stable on the port (maximum delay is 20 ms from the transition).

Table 23. PORTSC1 - Port Status and Control 1 register (address 0064h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

PTC[3:0]

0

R/W

13

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

11

R/W

10

12

Symbol

Reset

Access

Bit

PIC[1:0]

PO

1

PP

LS[1:0]

reserved^[1]

PR

0

R

0

R

0

R/W

3

0

R/W

2

0

R/W

1

R/W

5

R/W

R

7

6

4

reserved^[1]

0

Symbol

Reset

Access

SUSP

0

FPR

0

PED

0

ECSC

0

ECCS

0

R/W

R

[1] The reserved bits should always be written with the reset value.

ISP1760_4

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Table 24. PORTSC1 - Port Status and Control 1 register (address 0064h) bit description

Bit

Symbol

Description^[1]

31 to 20

-

reserved

19 to 16 PTC[3:0]

Port Test Control: When this ﬁeld is zero, the port is not operating in test

mode. A nonzero value indicates that it is operating in test mode indicated

by the value.

15 to 14 PIC[1:0]

Port Indicator Control: Writing to this ﬁeld has no effect if the

P_INDICATOR bit in the HCSPARAMS register is logic 0.

For a description on how these bits are implemented, refer to Ref. 1

“Universal Serial Bus Speciﬁcation Rev. 2.0”.^[2]

13

12

PO

PP

Port Owner: This bit unconditionally goes to logic 0 when the conﬁgured

bit in the CONFIGFLAG register makes a logic 0 to logic 1 transition. This

bit unconditionally goes to logic 1 whenever the conﬁgured bit is logic 0.

Port Power: The function of this bit depends on the value of the PPC (Port

Power Control) ﬁeld in the HCSPARAMS register.

11 to 10 LS[1:0]

Line Status: This ﬁeld reﬂects the current logical levels of the DP (bit 11)

and DM (bit 10) signal lines.

9

8

-

reserved

PR

Port Reset: Logic 1 means the port is in the reset state. Logic 0 means

the port is not in reset.^[2]

7

6

SUSP

FPR

Suspend: Logic 1 means the port is in the suspend state. Logic 0 means

the port is not suspended.^[2]

Force Port Resume: Logic 1 means resume detected or driven on the

port. Logic 0 means no resume (K-state) detected or driven on the port.^[2]

5 to 3

-

reserved

2

1

PED

ECSC

Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable.^[2]

Connect Status Change: Logic 1 means change in ECCS. Logic 0

means no change.^[2]

0

ECCS

Current Connect Status: Logic 1 indicates a device is present on the

port. Logic 0 indicates no device is present.^[2]

[1] For details on register bit description, refer to Ref. 2 “Enhanced Host Controller Interface Speciﬁcation for

Universal Serial Bus Rev. 1.0”.

[2] These ﬁelds read logic 0, if the PP (Port Power) bit in register PORTSC1 is logic 0.

8.2.7 ISO PTD Done Map register

The bit description of the register is given in Table 25.

Table 25. ISO PTD Done Map register (address 0130h) bit description

Bit

Symbol

Access

Value

Description

31 to 0

ISO_PTD_DONE

_MAP[31:0]

R

0000 0000h

ISO PTD Done Map: Done map for each of the 32 PTDs for

the ISO transfer

This register represents a direct map of the done status of the 32 PTDs. The bit

corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is

completed. Reading the Done Map register will clear all the bits that are set to logic 1, and

the next reading will reﬂect the updated status of new executed PTDs.

8.2.8 ISO PTD Skip Map register

Table 26 shows the bit description of the register.

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Table 26. ISO PTD Skip Map register (address 0134h) bit description

Bit

Symbol

Access

Value

Description

31 to 0

ISO_PTD_SKIP R/W

_MAP[31:0]

FFFF FFFFh

ISO PTD Skip Map: Skip map for each of the 32 PTDs for the

ISO transfer.

When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit

may be set. The information in that PTD is not processed. For example, NextPTDPointer

will not affect the order of processing of PTDs. The Skip bit should not normally be set on

the position indicated by NextPTDPointer.

8.2.9 ISO PTD Last PTD register

Table 27 shows the bit description of the ISO PTD Last PTD register.

Table 27. ISO PTD Last PTD register (address 0138h) bit description

Bit

Symbol

Access Value

Description

31 to 0

ISO_PTD_LAST R/W

_PTD[31:0]

0000 0000h ISO PTD last PTD: Last PTD of the 32 PTDs is indicated by the 32

bitmap.

1h — One PTD in ISO

2h — Two PTDs in ISO

4h — Three PTDs in ISO

Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed

(checking V = 1) in that PTD category. Subsequently, the process will restart with the ﬁrst

PTD of that group. This is useful to reduce the time in which all the PTDs, the respective

memory space, would be checked, especially if only a few PTDs are deﬁned. The

LastPTD bit must be normally set to a higher position than any other position indicated by

the NextPTDPointer from an active PTD.

8.2.10 INT PTD Done Map register

The bit description of the register is given in Table 28.

Table 28. INT PTD Done Map register (address 0140h) bit description

Bit

Symbol

Access Value

Description

31 to 0

INT_PTD_DONE_ R

MAP[31:0]

0000 0000h INT PTD Done Map: Done map for each of the 32 PTDs for the

INT transfer

This register represents a direct map of the done status of the 32 PTDs. The bit

corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is

completed. Reading the Done Map register will clear all the bits that are set to logic 1, and

the next reading will reﬂect the updated status of new executed PTDs.

8.2.11 INT PTD Skip Map register

Table 29 shows the bit description of the INT PTD Skip Map register.

Table 29. INT PTD Skip Map register (address 0144h) bit description

Bit

Symbol

Access

Value

Description

31 to 0

INT_PTD_SKIP R/W

_MAP[31:0]

FFFF FFFFh INT PTD Skip Map: Skip map for each of the 32 PTDs for the INT

transfer

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When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit

may be set. The information in that PTD is not processed. For example, NextPTDPointer

will not affect the order of processing of PTDs. The Skip bit must not be normally set on

the position indicated by NextPTDPointer.

8.2.12 INT PTD Last PTD register

The bit description of the register is given in Table 30.

Table 30. INT PTD Last PTD register (address 0148h) bit description

Bit

Symbol

Access Value

Description

31 to 0 INT_PTD_LAST R/W

_PTD[31:0]

0000 0000h INT PTD Last PTD: Last PTD of the 32 PTDs as indicated by the 32

bitmap.

1h — One PTD in INT

2h — Two PTDs in INT

3h — Three PTDs in INT

Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed

(checking V = 1) in that PTD category. Subsequently, the process will restart with the ﬁrst

PTD of that group. This is useful to reduce the time in which all the PTDs, the respective

memory space, would be checked, especially if only a few PTDs are deﬁned. The

LastPTD bit must be normally set to a higher position than any other position indicated by

the NextPTDPointer from an active PTD.

8.2.13 ATL PTD Done Map register

Table 31 shows the bit description of the ATL PTD Done Map register.

Table 31. ATL PTD Done Map register (address 0150h) bit description

Bit

Symbol

Access

Value

Description

31 to 0

ATL_PTD_DONE_ R

MAP[31:0]

0000 0000h

ATL PTD Done Map: Done map for each of the 32 PTDs for

the ATL transfer

This register represents a direct map of the done status of the 32 PTDs. The bit

corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is

completed. Reading the Done Map register will clear all the bits that are set to logic 1, and

the next reading will reﬂect the updated status of new executed PTDs.

8.2.14 ATL PTD Skip Map register

The bit description of the register is given in Table 32.

Table 32. ATL PTD Skip Map register (address 0154h) bit description

Bit

Symbol

Access

Value

Description

31 to 0

ATL_PTD_SKIP_ R/W

MAP[31:0]

FFFF FFFFh

ATL PTD Skip Map: Skip map for each of the 32 PTDs for the

ATL transfer

When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit

may be set. The information in that PTD is not processed. For example, NextPTDPointer

will not affect the order of processing of PTDs. The Skip bit must not normally be set on

the position indicated by NextPTDPointer.

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8.2.15 ATL PTD Last PTD register

The bit description of the ATL PTD Last PTD register is given in Table 33.

Table 33. ATL PTD Last PTD register (address 0158h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ATL_PTD_LAST R/W

_PTD[31:0]

0000 0000h ATL PTD Last PTD: Last PTD of the 32 PTDs as indicated by the 32

bitmap.

1h — One PTD in ATL

2h — Two PTDs in ATL

4h — Three PTDs in ATL

Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed

(checking V = 1) in that PTD category. Subsequently, the process will restart with the ﬁrst

PTD of that group. This is useful to reduce the time in which all the PTDs, the respective

memory space, would be checked, especially if only a few PTDs are deﬁned. The

LastPTD bit must normally be set to a higher position than any other position indicated by

the NextPTDPointer from an active PTD.

8.3 Conﬁguration registers

8.3.1 HW Mode Control register

Table 34 shows the bit allocation of the register.

Table 34. HW Mode Control - Hardware Mode Control register (address 0300h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

ALL_ATX_

RESET

reserved^[1]

Reset

Access

Bit

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

ANA_DIGI_

OC

reserved^[1]

DATA_BUS

_WIDTH

Reset

Access

Bit

0

R/W

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

0

R/W

1

R/W

0

7

2

Symbol

reserved

DACK_

POL

DREQ_

POL

reserved^[1]

INTR_POL

INTR_

LEVEL

GLOBAL_

INTR_EN

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

ISP1760_4

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Table 35. HW Mode Control - Hardware Mode Control register (address 0300h) bit

description

Bit

Symbol

Description

31

ALL_ATX_RESET

All ATX Reset: For debugging purposes (not used normally).

1 — Enable reset, then write back logic 0

0 — No reset

30 to 16

15

-

reserved; write logic 0

ANA_DIGI_OC

Analog Digital Overcurrent: This bit selects analog or digital

overcurrent detection on pins OC1_N, OC2_N and OC3_N.

0 — Digital overcurrent

1 — Analog overcurrent

14 to 9

8

-

reserved; write logic 0

DATA_BUS_WIDTH Data Bus Width:

0 — Deﬁnes a 16-bit data bus width

1 — Sets a 32-bit data bus width

7

6

-

reserved; write logic 0

DACK_POL

DACK Polarity:

1 — Indicates that the DACK input is active HIGH

0 — Indicates active LOW

5

DREQ_POL

DREQ Polarity:

1 — Indicates that the DREQ output is active HIGH

0 — Indicates active LOW

4 to 3

2

-

reserved; write logic 0

Interrupt Polarity:

0 — Active LOW

INTR_POL

1 — Active HIGH

1

0

INTR_LEVEL

Interrupt Level:

0 — INT is level triggered.

1 — INT is edge triggered. A pulse of certain width is generated.

GLOBAL_INTR_EN Global Interrupt Enable: This bit must be set to logic 1 to

enable the IRQ signal assertion.

0 — IRQ assertion is disabled. IRQ will never be asserted,

regardless of other settings or IRQ events.

1 — IRQ assertion is enabled. IRQ will be asserted according to

the Interrupt Enable register, and events setting and occurrence.

8.3.2 Chip ID register

Read this register to get the ID of the ISP1760. The upper word of the register contains

the hardware version number and the lower word contains the chip ID. Table 36 shows the

bit description of the register.

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Table 36. Chip ID - Chip Identiﬁer register (address 0304h) bit description

Bit

Symbol

Access Value

Description

31 to 0 CHIPID[31:0] R

0001 1761h Chip ID: This register represents the hardware version number (0001h) and

the chip ID (1761h).

Remark: The chip ID is for internal use to identify the ISP176x product

family.

8.3.3 Scratch register

This register is for testing and debugging purposes only. The value read back must be the

same as the value that was written. The bit description of this register is given in Table 37.

Table 37. Scratch register (address 0308h) bit description

Bit

Symbol

Access Value

0000 0000h

Description

31 to 0

SCRATCH[31:0] R/W

Scratch: For testing and debugging purposes

8.3.4 SW Reset register

Table 38 shows the bit allocation of the register.

Table 38. SW Reset - Software Reset register (address 030Ch) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

reserved^[1]

RESET_

HC

RESET_

ALL

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

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Table 39. SW Reset - Software Reset register (address 030Ch) bit description

Bit

Symbol

Description

31 to 2

1

-

reserved; write logic 0

RESET_HC Reset Host Controller: Reset only the host controller-speciﬁc registers

(only registers with address below 300h).

0 — No reset

1 — Enable reset

0

RESET_ALL Reset All: Reset all the host controller and CPU interface registers.

0 — No reset

1 — Enable reset

8.3.5 DMA Conﬁguration register

The bit allocation of the DMA Conﬁguration register is given in Table 40.

Table 40. DMA Conﬁguration register (address 0330h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

DMA_COUNTER[23:16]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

DMA_COUNTER[15:8]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

DMA_COUNTER[7:0]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

reserved^[1]

BURST_LEN[1:0]

ENABLE_ DMA_READ

DMA

_WRITE_

SEL

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

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Table 41. DMA Conﬁguration register (address 0330h) bit description

Bit Symbol Description

31 to 8 DMA_COUNTER[23:0] DMA Counter: The number of bytes to be transferred (read or

write).

Remark: Different number of bursts will be generated for the

same transfer length programmed in 16-bit and 32-bit modes

because DMA_COUNTER is in number of bytes.

7 to 4

3 to 2

-

reserved

BURST_LEN[1:0]

DMA Burst Length:

00 — Single DMA burst

01 — 4-cycle DMA burst

10 — 8-cycle DMA burst

11 — 16-cycle DMA burst

1

0

ENABLE_DMA

Enable DMA:

0 — Terminate DMA

1 — Enable DMA

DMA_READ_WRITE_ DMA Read/Write Select: Indicates if the DMA operation is a

SEL

write or read to or from the ISP1760.

0 — DMA write to the ISP1760 internal RAM is set

1 — DMA read from the ISP1760 internal RAM

8.3.6 Buffer Status register

The Buffer Status register is used to indicate the HC that a particular PTD buffer (that is,

ATL, INT and ISO) contains at least one PTD that must be scheduled. Once software sets

the Buffer Filled bit of a particular transfer in the Buffer Status register, the HC will start

traversing through PTD headers that are not marked for skipping and are valid PTDs.

Remark: Software can set these bits during the initialization.

Table 42 shows the bit allocation of the Buffer Status register.

Table 42. Buffer Status register (address 0334h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

reserved^[1]

0

R/W

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Bit

7

6

5

4

3

2

1

0

Symbol

reserved^[1]

ISO_BUF_ INT_BUF_ ATL_BUF_

FILL

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

Table 43. Buffer Status register (address 0334h) bit description

Bit

Symbol

Description

31 to 3

2

-

reserved

ISO_BUF_ ISO Buffer Filled:

FILL

1 — Indicates one of the ISO PTDs is ﬁlled, and the ISO PTD area will be

processed.

0 — Indicates there is no PTD in this area. Therefore, processing of the ISO

PTDs will completely be skipped.

1

0

INT_BUF_ INT Buffer Filled:

FILL

1 — Indicates one of the INT PTDs is ﬁlled, and the INT PTD area will be

processed.

0 — Indicates there is no PTD in this area. Therefore, processing of the INT

PTDs will completely be skipped.

ATL_BUF_ ATL Buffer Filled:

FILL

1 — Indicates one of the ATL PTDs is ﬁlled, and the ATL PTD area will be

processed.

0 — Indicates there is no PTD in this area. Therefore, processing of the ATL

PTDs will completely be skipped.

8.3.7 ATL Done Timeout register

The bit description of the ATL Done Timeout register is given in Table 44.

Table 44. ATL Done Timeout register (address 0338h) bit description

Bit

Symbol

Access

Value

Description

31 to 0

ATL_DONE_

TIMEOUT[31:0]

R/W

0000 0000h ATL Done Timeout: This register determines the ATL done

time-out interrupt. This register deﬁnes the time-out in

milliseconds after which the ISP1760 asserts the INT line, if

enabled. It is applicable to ATL done PTDs only.

8.3.8 Memory register

The Memory register contains the base memory read address and the respective bank.

This register needs to be set only before a ﬁrst memory read cycle. Once written, the

address will be latched for the bank and will be incremented for every read of that bank,

until a new address for that bank is written to change the address pointer.

The bit description of the register is given in Table 45.

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Table 45. Memory register (address 033Ch) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

MEM_BANK_SEL[1:0]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

START_ADDR_MEM_READ[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

START_ADDR_MEM_READ[7:0]

0

R/W

[1] The reserved bits should always be written with the reset value.

Table 46. Memory register (address 033Ch) bit description

Bit

Symbol

Description

31 to 18

17 to 16

-

reserved

MEM_BANK_ Memory Bank Select: Up to four memory banks can be selected.

SEL[1:0]

For details on internal memory read description, see Section 7.3.1.

Applicable to PIO mode memory read or write data transfers only.

15 to 0

START_ADDR Start Address for Memory Read Cycles: The start address for a

_MEM_READ series of memory read cycles at incremental addresses in a

[15:0]

contiguous space. Applicable to PIO mode memory read data

transfers only.

8.3.9 Edge Interrupt Count register

Table 47 shows the bit allocation of the register.

Table 47. Edge Interrupt Count register (address 0340h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

MIN_WIDTH[7:0]

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

reserved^[1]

0

R/W

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Bit

15

14

13

12

11

10

9

8

Symbol

Reset

Access

Bit

NO_OF_CLK[15:8]

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

Reset

Access

NO_OF_CLK[7:0]

0

1

R/W

[1] The reserved bits should always be written with the reset value.

Table 48. Edge Interrupt Count register (address 0340h) bit description

Bit

Symbol

Description

31 to 24

MIN_WIDTH[7:0]

Minimum Width: Indicates the minimum width between two edge

interrupts in µSOFs (1 µSOF = 125 µs). This is not valid for level

interrupts. A count of zero means that interrupts occur as and

when an event occurs.

23 to 16

15 to 0

-

reserved

NO_OF_CLK[15:0] Number of Clocks: Count in number of clocks that the edge

interrupt must be kept asserted on the interface. The default IRQ

pulse width is approximately 500 ns.

8.3.10 DMA Start Address register

This register deﬁnes the start address select for the DMA read and write operations. See

Table 49 for the bit allocation.

Table 49. DMA Start Address register (address 0344h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

W

23

W

22

W

21

W

20

W

19

W

18

W

17

W

16

Symbol

Reset

Access

Bit

0

W

9

0

W

8

W

15

W

14

W

13

W

12

W

11

W

10

Symbol

Reset

Access

Bit

START_ADDR_DMA[15:8]

0

W

7

0

W

6

0

W

5

0

W

4

0

W

3

0

W

2

0

W

1

0

W

0

Symbol

Reset

Access

START_ADDR_DMA[7:0]

0

W

[1] The reserved bits should always be written with the reset value.

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Table 50. DMA Start Address register (address 0344h) bit description

Bit

Symbol

Description

31 to 16

15 to 0

-

reserved

START_ADDR Start Address for DMA: The start address for DMA read or write

_DMA[15:0] cycles.

8.3.11 Power Down Control register

This register is used to turn off power to the internal blocks of the ISP1760 to obtain

maximum power savings. Table 51 shows the bit allocation of the register.

Table 51. Power Down Control register (address 0354h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

CLK_OFF_COUNTER[15:8]

0

1

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

Reset

Access

Bit

CLK_OFF_COUNTER[7:0]

1

R/W

1

0

1

R/W

11

0

R/W

10

0

R/W

9

0

R/W

8

R/W

15

R/W

13

R/W

12

14

Symbol

reserved^[1]

PORT3_

PD

PORT2_

PD

VBATDET_

PWR

reserved^[1]

Reset

Access

Bit

0

R/W

7

0

R/W

6

0

R/W

5

1

R/W

4

1

R/W

3

0

R/W

2

1

R/W

1

R/W

0

Symbol

Reset

Access

reserved^[1]

BIASEN

1

VREG_ON OC3_PWR OC2_PWR OC1_PWR HC_CLK_EN

1

0

R/W

[1] The reserved bits should always be written with the reset value.

ISP1760_4

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Table 52. Power Down Control register (address 0354h) bit description

Bit^[1]

Symbol Description

31 to 16 CLK_OFF_ Clock Off Counter: Determines the wake-up status duration after any

COUNTER wake-up event before the ISP1760 goes back into suspend mode. This

[15:0]

time-out is applicable only if, during the given interval, the host controller is

not programmed back to the normal functionality.

03E8h — The default value. It determines the default wake-up interval of

10 ms. A value of zero implies that the host controller never wakes up on

any of the events. This may be useful when using the ISP1760 as a

peripheral to save power by permanently programming the host controller

in suspend.

FFFFh — The maximum value. It determines a maximum wake-up time of

500 ms.

The setting of this register is based on the 100 kHz ± 40 % LazyClock

frequency. It is a multiple of 10 µs period.

Remark: In 16-bit mode, the default value is 17E8h. A write operation to

these bits with any value ﬁxes the clock off counter at 1400h. This value is

equivalent to a ﬁxed wake-up time of 50 ms.

15 to 13 -

reserved

12

11

10

PORT3_PD Port 3 Pull-Down: Controls port 3 pull-down resistors.

0 — Port 3 internal pull-down resistors are not connected.

1 — Port 3 internal pull-down resistors are connected.

PORT2_PD Port 2 Pull-Down: Controls port 2 pull-down resistors.

0 — Port 2 internal pull-down resistors are not connected.

1 — Port 2 internal pull-down resistors are connected.

VBATDET_

PWR

V

_BATDetector Powered: Controls the power to the V_BATdetector.

0 — V_BATdetector is powered or enabled in suspend.

1 — V_BATdetector is not powered or disabled in suspend.

9 to 6

5

-

reserved; write reset value

BIASEN

Bias Circuits Powered: Controls the power to internal bias circuits.

0 — Internal bias circuits are not powered in suspend.

1 — Internal bias circuits are powered in suspend.

4

3

VREG_ON

V_REGPowered: Enables or disables the internal 3.3 V and 1.8 V

regulators when the ISP1760 is in suspend.

0 — Internal regulators are normally powered in suspend.

1 — Internal regulators switch to low power mode (in suspend mode).

OC3_PWR OC3_N Powered: Controls the powering of the overcurrent detection

circuitry for port 3.

0 — Overcurrent detection is powered on or enabled during suspend.

1 — Overcurrent detection is powered off or disabled during suspend.

This may be useful when connecting a faulty device while the system is in

standby.

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Table 52. Power Down Control register (address 0354h) bit description …continued

Bit^[1]

Symbol

Description

2

OC2_PWR OC2_N Powered: Controls the powering of the overcurrent detection

circuitry for port 2.

0 — Overcurrent detection is powered-on or enabled during suspend.

1 — Overcurrent detection is powered-off or disabled during suspend.

This may be useful when connecting a faulty device while the system is in

standby.

1

0

OC1_PWR OC1_N Powered: Controls the powering of the overcurrent detection

circuitry for port 1.

0 — Overcurrent detection is powered-on or enabled during suspend.

1 — Overcurrent detection is powered-off or disabled during suspend.

This may be useful when connecting a faulty device while the system is in

standby.

HC_CLK_

EN

Host Controller Clock Enabled: Controls internal clocks during suspend.

0 — Clocks are disabled during suspend. This is the default value. Only

the LazyClock of 100 kHz ± 40 % will be left running in suspend if this bit

is logic 0. If clocks are stopped during suspend, CLKREADY IRQ will be

generated when all clocks are running stable.

1 — All clocks are enabled even in suspend.

[1] For a 32-bit operation, the default wake-up counter value is 10 µs. For a 16-bit operation, the wake-up

counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.

8.3.12 Port 1 Control register

The values read from the lower 16 bits and the upper 16 bits of this register are always the

same. Table 53 shows the bit allocation of the register.

Table 53. Port 1 Control register (address 0374h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved

0

R/W

23

R/W

22

R/W

21

R/W

20

R/W

19

R/W

18

R/W

17

R/W

16

Symbol

PORT1_

INIT2

reserved

Reset

Access

Bit

1

0

1

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

Reset

Access

Bit

reserved

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

0

R/W

0

1

Symbol

PORT1_

INIT1

reserved

PORT1_POWER[1:0]

reserved

Reset

0

1

0

1

0

Access

R/W

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Table 54. Port 1 Control register (address 0374h) bit description

Bit^[1]

Symbol Description

31 to 24 -

reserved; write reset value

23

PORT1_INIT2

Port 1 Initialization 2: Write logic 1 at the ISP1760 initialization. It

will clear both this bit and bit 7. Affects only port 1.

22 to 8

7

-

reserved

PORT1_INIT1

Port 1 Initialization 1: Must be reset to logic 0 at power-up

initialization for correct operation of port 1. Correct host controller

functionality is not ensured if set to logic 1 (affects only port 1). To

clear this bit, logic 1 must be written to bit 23 during the ISP1760

initialization.

This is not required for the normal functionality of port 2 and port 3.

reserved

6 to 5

4 to 3

-

PORT1_POWER Port 1 Power: Set these bits to 11b. These bits must be set to enable

[1:0]

port 1 power.

2 to 0

-

reserved; write reset value

[1] For correct port 1 initialization, write 0080 0018h to this register after power-on.

8.4 Interrupt registers

8.4.1 Interrupt register

The bits of this register indicate the interrupt source, deﬁning the events that determined

the INT generation. Clearing the bits that were set because of the events listed is done by

writing back logic 1 to the respective position. All bits must be reset before enabling new

interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN

in the HW Mode Control register. Table 55 shows the bit allocation of the Interrupt register.

Table 55. Interrupt register (address 0310h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

R/W

9

8

Symbol

Reset

Access

Bit

reserved^[1]

ISO_IRQ

ATL_IRQ

0

R/W

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

7

Symbol

INT_IRQ

CLK

READY

HC_SUSP reserved^[1]

DMAEOT

INT

reserved^[1]SOFITLINT reserved^[1]

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

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Table 56. Interrupt register (address 0310h) bit description

Bit

31 to 10 -

ISO_IRQ

Symbol

Description

reserved; write reset value

9

8

7

ISO IRQ: Indicates that an ISO PTD was completed, or the PTDs

corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ Mask

OR register bits combination were completed. The IRQ line will be

asserted if the respective enable bit in the HCInterruptEnable register is

set.

0 — No ISO PTD event occurred.

1 — ISO PTD event occurred.

For details, see Section 7.4.

ATL_IRQ

ATL IRQ: Indicates that an ATL PTD was completed, or the PTDs

corresponding to the bits set in the ATL IRQ Mask AND or ATL IRQ Mask

OR register bits combination were completed. The IRQ line will be

asserted if the respective enable bit in the HCInterruptEnable register is

set.

0 — No ATL PTD event occurred.

1 — ATL PTD event occurred.

For details, see Section 7.4.

INT_IRQ

INT IRQ: Indicates that an INT PTD was completed, or the PTDs

corresponding to the bits set in the INT IRQ Mask AND or INT IRQ Mask

OR register bits combination were completed. The IRQ line will be

asserted if the respective enable bit in the HCInterruptEnable register is

set.

0 — No INT PTD event occurred.

1 — INT PTD event occurred.

For details, see Section 7.4.

6

5

CLKREADY Clock Ready: Indicates that internal clock signals are running stable. The

IRQ line will be asserted if the respective enable bit in the

HCInterruptEnable register is set.

0 — No CLKREADY event has occurred.

1 — CLKREADY event occurred.

HC_SUSP

Host Controller Suspend: Indicates that the host controller has entered

suspend mode. The IRQ line will be asserted if the respective enable bit

in the HCInterruptEnable register is set.

0 — The host controller did not enter suspend mode.

1 — The host controller entered suspend mode.

If the ISR accesses the ISP1760, it will wake up for the time speciﬁed in

bits 31 to 16 of the Power Down Control register.

4

3

-

reserved; write reset value

DMAEOT

INT

DMA EOT Interrupt: Indicates the DMA transfer completion. The IRQ line

will be asserted if the respective enable bit in the HCInterruptEnable

register is set.

0 — No DMA transfer is completed.

1 — DMA transfer is complete.

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Table 56. Interrupt register (address 0310h) bit description …continued

Bit

Symbol

Description

2

-

reserved; write reset value; value is zero just after reset and changes to

one after a short while

1

0

SOFITLINT SOT ITL Interrupt: The IRQ line will be asserted if the respective enable

bit in the HCInterruptEnable register is set.

0 — No SOF event has occurred.

1 — An SOF event has occurred.

-

reserved; write reset value; value is zero just after reset and changes to

one after a short while

8.4.2 Interrupt Enable register

This register allows enabling or disabling of the IRQ generation because of various events

as described in Table 57.

Table 57. Interrupt Enable register (address 0314h) bit allocation

Bit

31

30

29

28

27

26

25

24

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

23

R/W

22

R/W

21

R/W

19

R/W

18

R/W

17

R/W

16

20

Symbol

Reset

Access

Bit

reserved^[1]

0

R/W

9

0

R/W

8

R/W

15

R/W

14

R/W

13

R/W

12

R/W

11

R/W

10

Symbol

reserved^[1]

ISO_IRQ_E ATL_IRQ

_E

Reset

Access

Bit

0

R/W

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

Symbol

INT_IRQ_E CLKREADY HCSUSP_E reserved^[1]

_E

DMAEOT

INT_E

reserved^[1]SOFITLINT reserved^[1]

_E

Reset

0

Access

R/W

[1] The reserved bits should always be written with the reset value.

ISP1760_4

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Table 58. Interrupt Enable register (address 0314h) bit description

Bit

Symbol

Description

31 to 10

9

-

reserved; write logic 0

ISO_IRQ_E

ISO IRQ Enable: Controls the IRQ assertion when one or more ISO

PTDs matching the ISO IRQ Mask AND or ISO IRQ Mask OR

register bits combination are completed.

0 — No IRQ will be asserted when ISO PTDs are completed.

1 — IRQ will be asserted.

For details, see Section 7.4.

8

7

ATL_IRQ_E

INT_IRQ_E

ATL IRQ Enable: Controls the IRQ assertion when one or more ATL

PTDs matching the ATL IRQ Mask AND or ATL IRQ Mask OR

register bits combination are completed.

0 — No IRQ will be asserted when ATL PTDs are completed.

1 — IRQ will be asserted.

For details, see Section 7.4.

INT IRQ Enable: Controls the IRQ assertion when one or more INT

PTDs matching the INT IRQ Mask AND or INT IRQ Mask OR register

bits combination are completed.

0 — No IRQ will be asserted when INT PTDs are completed.

1 — IRQ will be asserted.

For details, see Section 7.4.

6

5

CLKREADY_ Clock Ready Enable: Enables the IRQ assertion when internal clock

E

signals are running stable. Useful after wake-up.

0 — No IRQ will be generated after a CLKREADY_E event.

1 — IRQ will be generated after a CLKREADY_E event.

HCSUSP_E Host Controller Suspend Enable: Enables the IRQ generation

when the host controller enters suspend mode.

0 — No IRQ will be generated when the host controller enters

suspend mode.

1 — IRQ will be generated when the host controller enters suspend

mode.

4

3

-

reserved; write logic 0

DMAEOTINT DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA

_E

transfer completion.

0 — No IRQ will be generated when a DMA transfer is completed.

1 — IRQ will be asserted when a DMA transfer is completed.

2

1

-

reserved; must be written with logic 0

SOFITLINT_ SOT ITL Interrupt Enable: Controls the IRQ generation at every

E

SOF occurrence.

0 — No IRQ will be generated on an SOF occurrence.

1 — IRQ will be asserted at every SOF.

0

-

reserved; must be written with logic 0

8.4.3 ISO IRQ Mask OR register

Each bit of this register corresponds to one of the 32 ISO PTDs deﬁned, and is a

hardware IRQ mask for each PTD done map. See Table 59 for bit description. For details,

see Section 7.4.

ISP1760_4

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Table 59. ISO IRQ Mask OR register (address 0318h) bit description

Bit

Symbol

Access Value

Description

31 to 0 ISO_IRQ_MASK R/W

_OR[31:0]

0000 0000h ISO IRQ Mask OR: Represents a direct map for ISO PTDs 31 to 0.

0 — No OR condition deﬁned between ISO PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain OR condition.

8.4.4 INT IRQ Mask OR register

Each bit of this register (see Table 60) corresponds to one of the 32 INT PTDs deﬁned,

and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.

Table 60. INT IRQ Mask OR register (address 031Ch) bit description

Bit

Symbol

Access Value

Description

31 to 0 INT_IRQ_MASK R/W

_OR[31:0]

0000 0000h INT IRQ Mask OR: Represents a direct map for INT PTDs 31 to 0.

0 — No OR condition deﬁned between INT PTDs 31 to 0.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain OR condition.

8.4.5 ATL IRQ Mask OR register

Each bit of this register corresponds to one of the 32 ATL PTDs deﬁned, and is a

hardware IRQ mask for each PTD done map. See Table 61 for bit description. For details,

see Section 7.4.

Table 61. ATL IRQ Mask OR register (address 0320h) bit description

Bit

Symbol

Access Value

Description

31 to 0

ATL_IRQ_MASK R/W

_OR[31:0]

0000 0000h ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0.

0 — No OR condition deﬁned between the ATL PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain OR condition.

8.4.6 ISO IRQ Mask AND register

Each bit of this register corresponds to one of the 32 ISO PTDs deﬁned, and is a

hardware IRQ mask for each PTD done map. For details, see Section 7.4.

Table 62 provides the bit description of the register.

Table 62. ISO IRQ Mask AND register (address 0324h) bit description

Bit

Symbol

Access Value

Description

31 to 0

ISO_IRQ_MASK R/W

_AND[31:0]

0000 0000h ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0.

0 — No AND condition deﬁned between ISO PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain AND condition between the 32 INT PTDs.

8.4.7 INT IRQ Mask AND register

Each bit of this register (see Table 63) corresponds to one of the 32 INT PTDs deﬁned,

and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.

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Table 63. INT IRQ Mask AND register (address 0328h) bit description

Bit

Symbol

Access Value

Description

31 to 0

INT_IRQ_MASK R/W

_AND[31:0]

0000 0000h INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0.

0 — No OR condition deﬁned between INT PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain AND condition between the 32 INT PTDs.

8.4.8 ATL IRQ Mask AND register

Each bit of this register corresponds to one of the 32 ATL PTDs deﬁned, and is a

hardware IRQ mask for each PTD done map. For details, see Section 7.4.

Table 64 shows the bit description of the register.

Table 64. ATL IRQ Mask AND register (address 032Ch) bit description

Bit

Symbol

Access Value

Description

31 to 0

ATL_IRQ_MASK R/W

_AND[31:0]

0000 0000h ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0.

0 — No OR condition deﬁned between ATL PTDs.

1 — The bits corresponding to certain PTDs are set to logic 1 to

deﬁne a certain AND condition between the 32 ATL PTDs.

9. Philips Transfer Descriptor (PTD)

The standard EHCI data structures as described in Ref. 2 “Enhanced Host Controller

Interface Speciﬁcation for Universal Serial Bus Rev. 1.0” are optimized for the bus master

operation that is managed by the hardware state machine.

The PTD structures of the ISP1760 are translations of the EHCI data structures that are

optimized for the ISP1760. It, however, still follows the basic EHCI architecture. This

optimized form of EHCI data structures is necessary because the ISP1760 is a slave host

controller and has no bus master capability.

EHCI manages schedules in two lists: periodic and asynchronous. The data structures

are designed to provide the maximum ﬂexibility required by USB, minimize memory trafﬁc,

and reduce hardware and software complexity. The ISP1760 controller executes

transactions for devices by using a simple shared-memory schedule. This schedule

consists of data structures organized into three lists.

qISO — Isochronous transfer

qINTL — Interrupt transfer

qATL — Asynchronous transfer; for the control and bulk transfers

The system software maintains two lists for the host controller: periodic and

asynchronous.

The ISP1760 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are

used as channels to transfer data from the shared memory to the USB bus. These

channels are allocated and de-allocated on receiving the transfer from the core USB

driver.

ISP1760_4

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ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Multiple transfers are scheduled to the shared memory for various endpoints by traversing

the next link pointer provided by endpoint data structures, until it reaches the end of the

endpoint list. There are three endpoint lists: one for ISO endpoints, and the other for INTL

and ATL endpoints. If the schedule is enabled, the host controller executes the ISO

schedule, followed by the INTL schedule, and then the ATL schedule.

These lists are traversed and scheduled by the software according to the EHCI traversal

rule. The host controller executes the scheduled ISO, INTL and ATL PTDs. The

completion of a transfer is indicated to the software by the interrupt that can be grouped

under various PTDs by using the AND or OR registers that are available for each schedule

type: ISO, INTL and ATL. These registers are simple logic registers to decide the

completion status of group and individual PTDs. When the logical conditions of the Done

bit is true in the shared memory, it means that PTD has completed.

There are four types of interrupts in the ISP1760: ISO, INTL, ATL and SOF. The latency

can be programmed in multiples of µSOF (125 µs).

The NextPTD pointer is a feature that allows the ISP1760 to jump unused and skip PTDs.

This will improve the PTD transversal latency time. The NextPTD pointer is not meant for

same or single endpoint. The NextPTD works only in forward direction.

The NextPTD traversal rules deﬁned by the ISP1760 hardware are:

1. Start the PTD memory vertical traversal, considering the skip and LastPTD

information, as follows.

2. If the current PTD is active and not done, perform the transaction.

3. Follow the NextPTD pointer as speciﬁed in bits 4 to 0 of DW4.

4. If combined with LastPTD, the LastPTD setting must be at a higher address than the

NextPTD speciﬁed. So both are set in a logical manner.

5. If combined with skip, the skip must not be set (logically) on the same position

corresponding to NextPTD, pointed by the NextPTD pointer.

6. If PTD is set for skip, it will be neglected and the next vertical PTD will be considered.

7. If the skipped PTD already has a setting including a NextPTD pointer that will not be

taken into consideration, the behavior will be just as described in the preceding step.

ISP1760_4

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Rev. 04 — 4 February 2008

57 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

START PTD

SCHEDULE

no

PTD

yes

SKIPPED?

GO TO

NEXTPTD

VERTICAL

CHECK FOR

VALID AND

ACTIVE BIT

SET?

yes

START PTD

EXECUTION

no

yes

FOLLOW NEXT

PTD POINTED

BY NEXTPTD

POINTER

IS PTD

POINTER

NULL?

no

004aaa883

Fig 13. NextPTD traversal rule

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

58 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 66. High-speed bulk IN and OUT: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 32 reserved

-

DW6

31 to 0

reserved

DW5

63 to 32 reserved

DW4

31 to 6

5

reserved

J

-

0

-

not applicable

SW — writes

Jump:

0 — To increment the PTD pointer.

1 — To enable the next PTD branching.

4 to 0

NextPTDPointer SW — writes

[4:0]

-

Next PTD Counter: Next PTD branching assigned by the PTD

pointer.

DW3

63

A

SW — sets

Active: Write the same value as that in V.

HW — resets

62

61

H

B

HW — writes

-

Halt: This bit corresponds to the Halt bit of the Status ﬁeld of TD.

Babble: This bit corresponds to the Babble Detected bit in the

Status ﬁeld of iTD, siTD or TD.

1 — When babbling is detected, A and V are set to 0.

60

X

HW — writes

-

Error: This bit corresponds to the Transaction Error bit in the Status

ﬁeld of iTD, siTD or TD (Exec_Trans, the signal name is xacterr).

0 — No PID error.

1 — If there are PID errors, this bit is set active. The A and V bits are

also set to inactive. This transaction is retried three times.

SW — writes

-

0 — Before scheduling.

59

58

reserved

P

-

SW — writes

Ping: For high-speed transactions, this bit corresponds to the Ping

state bit in the Status ﬁeld of a TD.

HW — updates

0 — Ping is not set.

1 — Ping is set.

For the ﬁrst time, software sets the Ping bit to 0. For the successive

asynchronous TD, software sets the bit in asynchronous TD based

on the state of the bit for the previous asynchronous TD of the same

transfer, that is:

• The current asynchronous TD is completed with the Ping bit

set.

• The next asynchronous TD will have its Ping bit set by the

software.

57

DT

HW — updates -

SW — writes

Data Toggle: This bit is ﬁlled by software to start a PTD. If

NrBytesToTransfer[14:0] is not complete, software needs to read this

value and then write back the same value to continue.

ISP1760_4

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ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 66. High-speed bulk IN and OUT: bit description …continued

Bit

Symbol

Access

Value Description

56 to 55 Cerr[1:0]

HW — writes

SW — writes

-

Error Counter: This ﬁeld corresponds to the Cerr[1:0] ﬁeld in TD.

The default value of this ﬁeld is zero for isochronous transactions.

00 — The transaction will not retry.

11 — The transaction will retry three times. Hardware will

decrement these values.

54 to 51 NakCnt[3:0]

50 to 47 reserved

HW — writes

SW — writes

-

NAK Counter: This ﬁeld corresponds to the NakCnt ﬁeld in TD.

Software writes for the initial PTD launch. The V bit is reset if

NakCnt decrements to zero and RL is a nonzero value. It reloads

from RL if transaction is ACK-ed.

-

46 to 32 NrBytes

Transferred

[14:0]

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number of

bytes sent or received for this transaction. If Mult[1:0] is greater than

one, it is possible to store intermediate results in this ﬁeld.

SW — writes

0000

DW2

31 to 29 reserved

28 to 25 RL[3:0]

-

Set to 0 for asynchronous TD.

SW — writes

Reload: If RL is set to 0h, hardware ignores the NakCnt value. RL

and NakCnt are set to the same value before a transaction.

24

reserved

-

Always 0 for asynchronous TD.

23 to 8

DataStart

Address[15:0]

SW — writes

Data Start Address: This is the start address for data that will be

sent or received on or from the USB bus. This is the internal

memory address and not the direct CPU address.

RAM address = (CPU address − 400h) / 8

7 to 0

reserved

-

DW1

63 to 47 reserved

46

-

Always 0 for asynchronous TD.

S

SW — writes

This bit indicates whether a split transaction has to be executed:

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

43 to 42 Token[1:0]

SW — writes

-

Transaction type:

00 — Control

10 — Bulk

Token: Identiﬁes the token Packet Identiﬁer (PID) for this

transaction:

00 — OUT

01 — IN

10 — SETUP

11 — PING (written by hardware only)

41 to 35 DeviceAddress

[6:0]

SW — writes

-

Device Address: This is the USB address of the function containing

the endpoint that is referred to by this buffer.

34 to 32 EndPt[3:1]

Endpoint: This is the USB address of the endpoint within the

function.

ISP1760_4

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ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 66. High-speed bulk IN and OUT: bit description …continued

Bit

Symbol

Access

Value Description

DW0

31

EndPt[0]

SW — writes

-

Endpoint: This is the USB address of the endpoint within the

function.

30 to 29 Mult[1:0]

Multiplier: This ﬁeld is a multiplier used by the host controller as the

number of successive packets the host controller may submit to the

endpoint in the current execution.

Set this ﬁeld to 01b. You can also set it to 11b and 10b depending on

your application. 00b is undeﬁned.

28 to 18 MaxPacket

Length[10:0]

SW — writes

-

Maximum Packet Length: This ﬁeld indicates the maximum

number of bytes that can be sent to or received from an endpoint in

a single data packet. The maximum packet size for a bulk transfer is

512 bytes. The maximum packet size for the isochronous transfer is

also variable at any whole number.

17 to 3

NrBytesTo

Number of Bytes to Transfer: This ﬁeld indicates the number of

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld (32 kB − 1 B).

Transfer[14:0]

2 to 1

0

reserved

V

-

SW — sets

Valid:

HW — resets

0 — This bit is deactivated when the entire PTD is executed, or

when a fatal error is encountered.

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

62 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 68. High-speed isochronous IN and OUT: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 52 ISOIN_7[11:0] HW — writes

51 to 40 ISOIN_6[11:0] HW — writes

39 to 32 ISOIN_5[11:4] HW — writes

-

Bytes received during µSOF7, if µSA[7] is set to 1 and frame number is

correct.

Bytes received during µSOF6, if µSA[6] is set to 1 and frame number is

correct.

Bytes received during µSOF5 (bits 11 to 4), if µSA[5] is set to 1 and

frame number is correct.

DW6

31 to 28 ISOIN_5[3:0] HW — writes

-

Bytes received during µSOF5 (bits 3 to 0), if µSA[5] is set to 1 and

frame number is correct.

27 to 16 ISOIN_4[11:0] HW — writes

Bytes received during µSOF4, if µSA[4] is set to 1 and frame number is

correct.

15 to 4

3 to 0

DW5

ISOIN_3[11:0] HW — writes

ISOIN_2[11:8] HW — writes

Bytes received during µSOF3, if µSA[3] is set to 1 and frame number is

correct.

Bytes received during µSOF2 (bits 11 to 8), if µSA[2] is set to 1 and

frame number is correct.

63 to 56 ISOIN_2[7:0] HW — writes

55 to 44 ISOIN_1[11:0] HW — writes

43 to 32 ISOIN_0[11:0] HW — writes

DW4

-

Bytes received during µSOF2 (bits 7 to 0), if µSA[2] is set to 1 and

frame number is correct.

Bytes received during µSOF1, if µSA[1] is set to 1 and frame number is

correct.

Bytes received during µSOF0, if µSA[0] is set to 1 and frame number is

correct.

31 to 29 Status7[2:0]

28 to 26 Status6[2:0]

25 to 23 Status5[2:0]

22 to 20 Status4[2:0]

19 to 17 Status3[2:0]

16 to 14 Status2[2:0]

13 to 11 Status1[2:0]

HW — writes

-

ISO IN or OUT status at µSOF7

ISO IN or OUT status at µSOF6

ISO IN or OUT status at µSOF5

ISO IN or OUT status at µSOF4

ISO IN or OUT status at µSOF3

ISO IN or OUT status at µSOF2

ISO IN or OUT status at µSOF1

10 to 8

Status0[2:0]

Status of the payload on the USB bus for this µSOF after ISO has been

delivered.

Bit 0 — Transaction error (IN and OUT)

Bit 1 — Babble (IN token only)

Bit 2 — Underrun (OUT token only)

7 to 0

µSA[7:0]

SW — writes

(0 → 1)

-

µSOF Active: When the frame number of bits DW1[7:3] match the

frame number of USB bus, these bits are checked for 1 before they are

sent for µSOF. For example: If µSA[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send

ISO every µSOF of the entire millisecond. If µSA[7:0] = 0, 1, 0, 1, 0, 1,

0, 1: send ISO only on µSOF0, µSOF2, µSOF4 and µSOF6.

HW — writes

(1 → 0)

After

processing

DW3

ISP1760_4

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64 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 68. High-speed isochronous IN and OUT: bit description …continued

Bit

Symbol

Access

Value Description

63

A

SW — sets

-

Active: This bit is the same as the Valid bit.

62

61

H

B

HW — writes

Halt: Only one bit for the entire millisecond. When this bit is set, the

Valid bit is reset. The device decides to stall an endpoint.

-

Babble: Not applicable here.

60 to 47 reserved

-

0

-

Set to 0 for isochronous.

46 to 32 NrBytes

Transferred

[14:0]

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number of

bytes sent or received for this transaction. If Mult[1:0] is greater than

one, it is possible to store intermediate results in this ﬁeld.

NrBytesTransferred[14:0] is 32 kB − 1 B per PTD.

DW2

31 to 24 reserved

-

0

-

Set to 0 for isochronous.

23 to 8

DataStart

SW — writes

Data Start Address: This is the start address for data that will be sent

or received on or from the USB bus. This is the internal memory

address and not the direct CPU address.

Address[15:0]

RAM address = (CPU address − 400h) / 8

Bits 2 to 0 — Don’t care

7 to 0

µFrame[7:0]

SW — writes

-

Bits 7 to 3 — Frame number that this PTD will be sent for ISO OUT or

IN

DW1

63 to 47 reserved

46

-

S

SW — writes

This bit indicates whether a split transaction has to be executed.

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

43 to 42 Token[1:0]

SW — writes

-

Endpoint type:

01 — Isochronous

Token: This ﬁeld indicates the token PID for this transaction:

00 — OUT

01 — IN

41 to 35 Device

Address[6:0]

SW — writes

-

Device Address: This is the USB address of the function containing

the endpoint that is referred to by this buffer.

34 to 32 EndPt[3:1]

Endpoint: This is the USB address of the endpoint within the function.

DW0

31

EndPt[0]

SW — writes

-

Endpoint: This is the USB address of the endpoint within the function.

30 to 29 Mult[1:0]

This ﬁeld is a multiplier counter used by the host controller as the

number of successive packets the host controller may submit to the

endpoint in the current execution.

For details, refer to Appendix D of Ref. 2 “Enhanced Host Controller

Interface Speciﬁcation for Universal Serial Bus Rev. 1.0”.

28 to 18 MaxPacket

Length[10:0]

SW — writes

-

Maximum Packet Length: This ﬁeld indicates the maximum number

of bytes that can be sent to or received from the endpoint in a single

data packet. The maximum packet size for an isochronous transfer is

1024 bytes. The maximum packet size for the isochronous transfer is

also variable at any whole number.

ISP1760_4

Product data sheet

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65 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 68. High-speed isochronous IN and OUT: bit description …continued

Bit

Symbol

Access

Value Description

17 to 3

NrBytesTo

SW — writes

-

Number of Bytes Transferred: This ﬁeld indicates the number of

Transfer[14:0]

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld (32 kB − 1 B).

2 to 1

0

reserved

V

-

HW — resets

SW — sets

0 — This bit is deactivated when the entire PTD is executed, or when a

fatal error is encountered.

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

66 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 70. High-speed interrupt IN and OUT: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 52 INT_IN_7[11:0] HW — writes

51 to 40 INT_IN_6[11:0] HW — writes

39 to 32 INT_IN_5[11:4] HW — writes

DW6

-

Bytes received during µSOF7, if µSA[7] is set to 1 and frame number

is correct.

Bytes received during µSOF6, if µSA[6] is set to 1 and frame number

is correct.

Bytes received during µSOF5 (bits 11 to 4), if µSA[5] is set to 1 and

frame number is correct.

31 to 28 INT_IN_5[3:0]

HW — writes

-

Bytes received during µSOF5 (bits 3 to 0), if µSA[5] is set to 1 and

frame number is correct.

27 to 16 INT_IN_4[11:0] HW — writes

Bytes received during µSOF4, if µSA[4] is set to 1 and frame number

is correct.

15 to 4

3 to 0

DW5

INT_IN_3[11:0] HW — writes

INT_IN_2[11:8] HW — writes

Bytes received during µSOF3, if µSA[3] is set to 1 and frame number

is correct.

Bytes received during µSOF2 (bits 11 to 8), if µSA[2] is set to 1 and

frame number is correct.

63 to 56 INT_IN_2[7:0]

HW — writes

-

Bytes received during µSOF2 (bits 7 to 0), if µSA[2] is set to 1 and

frame number is correct.

55 to 44 INT_IN_1[11:0] HW — writes

43 to 32 INT_IN_0[11:0] HW — writes

DW4

Bytes received during µSOF1, if µSA[1] is set to 1 and frame number

is correct.

Bytes received during µSOF0, if µSA[0] is set to 1 and frame number

is correct.

31 to 29 Status7[2:0]

28 to 26 Status6[2:0]

25 to 23 Status5[2:0]

22 to 20 Status4[2:0]

19 to 17 Status3[2:0]

16 to 14 Status2[2:0]

13 to 11 Status1[2:0]

HW — writes

-

INT IN or OUT status of µSOF7

INT IN or OUT status of µSOF6

INT IN or OUT status of µSOF5

INT IN or OUT status of µSOF4

INT IN or OUT status of µSOF3

INT IN or OUT status of µSOF2

INT IN or OUT status of µSOF1

10 to 8

Status0[2:0]

Status of the payload on the USB bus for this µSOF after INT has

been delivered.

Bit 0 — Transaction error (IN and OUT)

Bit 1 — Babble (IN token only)

Bit 2 — Underrun (OUT token only)

7 to 0

µSA[7:0]

SW — writes

(0 → 1)

-

When the frame number of bits DW2[7:3] match the frame number of

the USB bus, these bits are checked for 1 before they are sent for

µSOF. For example: When µSA[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send INT

for every µSOF of the entire millisecond. When µSA[7:0] = 0, 1, 0, 1,

0, 1, 0, 1: send INT for µSOF0, µSOF2, µSOF4 and µSOF6. When

µSA[7:0] = 1, 0, 0, 0, 1, 0, 0, 0: send INT for every fourth µSOF.

HW — writes

(1 → 0)

After

processing

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

68 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 70. High-speed interrupt IN and OUT: bit description …continued

Bit

Symbol

Access

Value Description

DW3

63

A

HW — writes

SW — writes

-

Active: Write the same value as that in V.

62

H

HW — writes

-

Halt: Transaction is halted.

61 to 58 reserved

57 DT

-

HW — writes

SW — writes

Data Toggle: Set the Data Toggle bit to start the PTD. Software

writes the current transaction toggle value. Hardware writes the next

transaction toggle value.

56 to 55 Cerr[1:0]

54 to 47 reserved

HW — writes

SW — writes

-

Error Counter. This ﬁeld corresponds to the Cerr[1:0] ﬁeld in the TD.

The default value of this ﬁeld is zero for isochronous transactions.

-

46 to 32 NrBytes

Transferred

[14:0]

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number of

bytes sent or received for this transaction. If Mult[1:0] is greater than

one, it is possible to store intermediate results in this ﬁeld.

DW2

31 to 24 reserved

-

23 to 8

DataStart

SW — writes

Data Start Address: This is the start address for data that will be

sent or received on or from the USB bus. This is the internal memory

address and not the direct CPU address.

Address[15:0]

RAM address = (CPU address − 400h) / 8

7 to 0

µFrame[7:0]

SW — writes

-

Bits 7 to 3 represent the polling rate in milliseconds.

The INT polling rate is deﬁned as 2^{(b − 1)}µSOF, where b is 1 to 9.

When b is 1, 2, 3 or 4, use µSA to deﬁne polling because the rate is

equal to or less than 1 ms. Bits 7 to 3 are set to 0. Polling checks µSA

bits for µSOF rates. See Table 71.

DW1

63 to 47 reserved

46

-

S

SW — writes

This bit indicates if a split transaction has to be executed:

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

43 to 42 Token[1:0]

SW — writes

-

Endpoint type:

11 — Interrupt

Token: This ﬁeld indicates the token PID for this transaction:

00 — OUT

01 — IN

41 to 35 DeviceAddress SW — writes

-

Device Address: This is the USB address of the function containing

the endpoint that is referred to by the buffer.

[6:0]

34 to 32 EndPt[3:1]

SW — writes

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

-

Endpoint: This is the USB address of the endpoint within the

function.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

69 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 70. High-speed interrupt IN and OUT: bit description …continued

Bit

Symbol

Access

Value Description

30 to 29 Mult[1:0]

SW — writes

-

Multiplier: This ﬁeld is a multiplier counter used by the host controller

as the number of successive packets the host controller may submit

to the endpoint in the current execution.

Set this ﬁeld to 01b. You can also set it to 11b and 10b, depending on

your application. 00b is undeﬁned.

28 to 18 MaxPacket

Length[10:0]

SW — writes

-

Maximum Packet Length: This ﬁeld indicates the maximum number

of bytes that can be sent to or received from the endpoint in a single

data packet.

17 to 3

NrBytesTo

Number of Bytes to Transfer: This ﬁeld indicates the number of

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld (32 kB − 1 B).

Transfer[14:0]

2 to 1

0

reserved

V

-

SW — sets

Valid:

HW — resets

0 — This bit is deactivated when the entire PTD is executed, or when

a fatal error is encountered.

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

Table 71. Microframe description

b

1

2

3

4

5

6

7

8

9

Rate

µFrame[7:3]

0 0000

µSA[7:0]

1 µSOF

2 µSOF

4 µSOF

1 ms

1111 1111

0 0000

1010 1010 or 0101 0101

any 2 bits set

any 1 bit set

0 0000

2 ms

0 0001

4 ms

0 0010 to 0 0011

0 0100 to 0 0111

0 1000 to 0 1111

1 0000 to 1 1111

8 ms

16 ms

32 ms

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

70 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 73. Start and complete split for bulk: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 32 reserved

-

DW6

31 to 0

reserved

DW5

63 to 32 reserved

DW4

31 to 6

5

reserved

J

-

SW — writes

0 — To increment the PTD pointer.

1 — To enable the next PTD branching.

4 to 0

NextPTDPointer

[4:0]

SW — writes

-

Next PTD branching assigned by the PTD pointer.

DW3

63

A

SW — sets

Active: Write the same value as that in V.

HW — resets

62

61

H

B

HW — writes

-

Halt: This bit corresponds to the Halt bit of the Status ﬁeld of TD.

Babble: This bit corresponds to the Babble Detected bit in the

Status ﬁeld of iTD, siTD or TD.

1 — When babbling is detected, A and V are set to 0.

60

59

X

HW — writes

SW — writes

-

Transaction Error: This bit corresponds to the Transaction Error

bit in the status ﬁeld.

-

0 — Before scheduling

SC

SW — writes 0

HW — updates

Start/Complete:

0 — Start split

1 — Complete split

58

57

reserved

DT

-

HW — writes

SW — writes

Data Toggle: Set the Data Toggle bit to start for the PTD.

56 to 55 Cerr[1:0]

HW — updates

SW — writes

-

Error Counter: This ﬁeld contains the error count for

asynchronous start and complete split (SS/CS) TD. When an error

has no response or bad response, Cerr[1:0] will be decremented

to zero and then Valid will be set to zero. A NAK or NYET will reset

Cerr[1:0]. For details, refer to Section 4.12.1.2 of Ref. 2 “Enhanced

Host Controller Interface Speciﬁcation for Universal Serial Bus

Rev. 1.0”.

If retry has insufﬁcient time at the beginning of a new SOF, the ﬁrst

PTD must be this retry. This can be accomplished if aperiodic PTD

is not advanced.

54 to 51 NakCnt[3:0]

50 to 47 reserved

HW — writes

SW — writes

-

NAK Counter: The V bit is reset if NakCnt decrements to zero and

RL is a nonzero value. Not applicable to isochronous split

transactions.

-

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

72 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 73. Start and complete split for bulk: bit description …continued

Bit

Symbol

Access

Value Description

46 to 32 NrBytesTransferred HW — writes

-

Number of Bytes Transferred: This ﬁeld indicates the number of

[14:0]

bytes sent or received for this transaction.

DW2

31 to 29 reserved

28 to 25 RL[3:0]

-

SW — writes

Reload: If RL is set to 0h, hardware ignores the NakCnt value. Set

RL and NakCnt to the same value before a transaction. For

full-speed and low-speed transactions, set this ﬁeld to 0000b. Not

applicable to isochronous start split and complete split.

24

reserved

-

23 to 8

DataStartAddress SW — writes

Data Start Address: This is the start address for data that will be

sent or received on or from the USB bus. This is the internal

memory address and not the direct CPU address.

[15:0]

RAM address = (CPU address − 400h) / 8

7 to 0

reserved

-

DW1

63 to 57 HubAddress[6:0]

56 to 50 PortNumber[6:0]

SW — writes

-

Hub Address: This indicates the hub address.

Port Number: This indicates the port number of the hub or

embedded TT.

49 to 48 SE[1:0]

SW — writes

-

This depends on the endpoint type and direction. It is valid only for

split transactions. Table 74 applies to start split and complete split

only.

47

46

reserved

S

-

SW — writes

This bit indicates whether a split transaction has to be executed:

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

43 to 42 Token[1:0]

SW — writes

-

Endpoint Type:

00 — Control

10 — Bulk

Token: This ﬁeld indicates the PID for this transaction.

00 — OUT

01 — IN

10 — SETUP

41 to 35 DeviceAddress[6:0] SW — writes

-

Device Address: This is the USB address of the function

containing the endpoint that is referred to by this buffer.

34 to 32 EndPt[3:1]

SW — writes

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

-

Endpoint: This is the USB address of the endpoint within the

function.

30 to 29 reserved

-

28 to 18 MaximumPacket

Length[10:0]

SW — writes

Maximum Packet Length: This ﬁeld indicates the maximum

number of bytes that can be sent to or received from an endpoint

in a single data packet. The maximum packet size for full-speed is

64 bytes as deﬁned in the Ref. 1 “Universal Serial Bus

Speciﬁcation Rev. 2.0”.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

73 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 73. Start and complete split for bulk: bit description …continued

Bit

Symbol

Access

Value Description

17 to 3

NrBytesToTransfer SW — writes

[14:0]

-

Number of Bytes to Transfer: This ﬁeld indicates the number of

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld.

2 to 1

0

reserved

V

-

SW — sets

Valid:

HW — resets

0 — This bit is deactivated when the entire PTD is executed, or

when a fatal error is encountered.

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

Table 74. SE description

Bulk

I/O

Control

I/O

S

1

0

E

0

Remarks

low-speed

full-speed

I/O

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

74 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 76. Start and complete split for isochronous: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 40 reserved

-

39 to 32 ISO_IN_7[7:0]

HW — writes

Bytes received during µSOF7, if µSA[7] is set to 1 and frame

number is correct.

DW6

31 to 24 ISO_IN_6[7:0]

HW — writes

-

Bytes received during µSOF6, if µSA[6] is set to 1 and frame

number is correct.

23 to 16 ISO_IN_5[7:0]

15 to 8 ISO_IN_4[7:0]

Bytes received during µSOF5, if µSA[5] is set to 1 and frame

number is correct.

Bytes received during µSOF4, if µSA[4] is set to 1 and frame

number is correct.

7 to 0

ISO_IN_3[7:0]

Bytes received during µSOF3, if µSA[3] is set to 1 and frame

number is correct.

DW5

63 to 56 ISO_IN_2[7:0]

55 to 48 ISO_IN_1[7:0]

47 to 40 ISO_IN_0[7:0]

39 to 32 µSCS[7:0]

HW — writes

-

Bytes received during µSOF2 (bits 7 to 0), if µSA[2] is set to 1 and

frame number is correct.

Bytes received during µSOF1, if µSA[1] is set to 1 and frame

number is correct.

Bytes received during µSOF0 if µSA[0] is set to 1 and frame

number is correct.

SW — writes

(0 → 1)

All bits can be set to one for every transfer. It speciﬁes which µSOF

the complete split needs to be sent. Valid only for IN. Start split and

complete split active bits, µSA = 0000 0001, µSCS = 0000 0100,

will cause SS to execute in µFrame0 and CS in µFrame2.

HW — writes

(1 → 0)

After processing

DW4

31 to 29 Status7[2:0]

HW — writes

-

Isochronous IN or OUT status of µSOF7

Isochronous IN or OUT status of µSOF6

Isochronous IN or OUT status of µSOF5

Isochronous IN or OUT status of µSOF4

Isochronous IN or OUT status of µSOF3

Isochronous IN or OUT status of µSOF2

Isochronous IN or OUT status of µSOF1

28 to 26 Status6[2:0]

25 to 23 Status5[2:0]

22 to 20 Status4[2:0]

19 to 17 Status3[2:0]

16 to 14 Status2[2:0]

13 to 11 Status1[2:0]

10 to 8 Status0[2:0]

Isochronous IN or OUT status of µSOF0

Bit 0 — Transaction error (IN and OUT)

Bit 1 — Babble (IN token only)

Bit 2 — Underrun (OUT token only)

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

76 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 76. Start and complete split for isochronous: bit description …continued

Bit

Symbol

Access

Value Description

- Speciﬁes which µSOF the start split needs to be placed.

7 to 0

µSA[7:0]

SW — writes

(0 → 1)

For OUT token: When the frame number of bits DW2[7:3] matches

the frame number of the USB bus, these bits are checked for one

before they are sent for the µSOF.

HW — writes

(1 → 0)

After processing

For IN token: Only µSOF0, µSOF1, µSOF2 or µSOF3 can be set

to 1. Nothing can be set for µSOF4 and above.

DW3

63

A

SW — sets

-

Active: Write the same value as that in V.

HW — resets

62

61

60

59

H

HW — writes

-

Halt: The Halt bit is set when any microframe transfer status has a

stalled or halted condition.

B

Babble: This bit corresponds to bit 1 of Status0 to Status7 for every

microframe transfer status.

X

Transaction Error: This bit corresponds to bit 0 of Status0 to

Status7 for every microframe transfer status.

SC

SW — writes 0

HW — updates

Start/Complete:

0 — Start split

1 — Complete split

58

57

reserved

DT

-

HW — writes

SW — writes

Data Toggle: Set the Data Toggle bit to start for the PTD.

56 to 44 reserved

43 to 32 NrBytes

-

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number of

Transferred[11:0]

bytes sent or received for this transaction.

DW2

31 to 24 reserved

-

23 to 8 DataStart

SW — writes

Data Start Address: This is the start address for data that will be

sent or received on or from the USB bus. This is the internal

memory address and not the CPU address.

Address[15:0]

µFrame[7:0]

7 to 0

SW — writes

-

Bits 7 to 3 determine which frame to execute.

DW1

63 to 57 HubAddress

[6:0]

SW — writes

-

Hub Address: This indicates the hub address.

56 to 50 PortNumber

[6:0]

Port Number: This indicates the port number of the hub or

embedded TT.

49 to 47 reserved

-

46

S

SW — writes

This bit indicates whether a split transaction has to be executed:

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

SW — writes

-

Transaction type:

01 — Isochronous

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

77 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 76. Start and complete split for isochronous: bit description …continued

Bit

Symbol

Access

Value Description

43 to 42 Token[1:0]

SW — writes

-

Token PID for this transaction:

00 — OUT

01 — IN

41 to 35 DeviceAddress

[6:0]

SW — writes

-

Device Address: This is the USB address of the function

containing the endpoint that is referred to by this buffer.

34 to 32 EndPt[3:1]

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

SW — writes

-

Endpoint: This is the USB address of the endpoint within the

function.

30 to 29 reserved

-

28 to 18 TT_MPS_Len

[10:0]

SW — writes

Transaction Translator Maximum Packet Size Length: This ﬁeld

indicates the maximum number of bytes that can be sent per start

split, depending on the number of total bytes needed. If the total

bytes to be sent for the entire millisecond is greater than 188 bytes,

this ﬁeld should be set to 188 bytes for an OUT token and

192 bytes for an IN token. Otherwise, this ﬁeld should be equal to

the total bytes sent.

17 to 3 NrBytesTo

Transfer[14:0]

SW — writes

-

Number of Bytes to Transfer: This ﬁeld indicates the number of

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld. This ﬁeld is restricted to

1023 bytes because in siTD the maximum allowable payload for a

full-speed device is 1023 bytes. This ﬁeld indirectly becomes the

maximum packet size of the downstream device.

2 to 1

0

reserved

V

-

SW — sets

0 — This bit is deactivated when the entire PTD is executed, or

when a fatal error is encountered.

HW — resets

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

78 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 78. Start and complete split for interrupt: bit description

Bit

Symbol

Access

Value Description

DW7

63 to 40 reserved

-

39 to 32 INT_IN_7[7:0]

HW — writes

Bytes received during µSOF7, if µSA[7] is set to 1 and frame

number is correct. The new value continuously overwrites the old

value.

DW6

31 to 24 INT_IN_6[7:0]

HW — writes

-

Bytes received during µSOF6, if µSA[6] is set to 1 and frame

number is correct. The new value continuously overwrites the old

value.

23 to 16 INT_IN_5[7:0]

Bytes received during µSOF5, if µSA[5] is set to 1 and frame

number is correct. The new value continuously overwrites the old

value.

15 to 8

7 to 0

DW5

INT_IN_4[7:0]

INT_IN_3[7:0]

Bytes received during µSOF4, if µSA[4] is set to 1 and frame

number is correct. The new value continuously overwrites the old

value.

Bytes received during µSOF3, if µSA[3] is set to 1 and frame

number is correct. The new value continuously overwrites the old

value.

63 to 56 INT_IN_2[7:0]

55 to 48 INT_IN_1[7:0]

47 to 40 INT_IN_0[7:0]

39 to 32 µSCS[7:0]

HW — writes

-

Bytes received during µSOF2 (bits 7 to 0), if µSA[2] is set to 1 and

frame number is correct. The new value continuously overwrites

the old value.

Bytes received during µSOF1, if µSA[1] is set to 1 and frame

number is correct. The new value continuously overwrites the old

value.

Bytes received during µSOF0 if µSA[0] is set to 1 and frame

number is correct. The new value continuously overwrites the old

value.

SW — writes

(0 → 1)

All bits can be set to one for every transfer. It speciﬁes which µSOF

the complete split needs to be sent. Valid only for IN. Start split and

complete split active bits, µSA = 0000 0001, µSCS = 0000 0100,

will cause SS to execute in µFrame0 and CS in µFrame2.

HW — writes

(1 → 0)

After

processing

DW4

31 to 29 Status7[2:0]

HW — writes

-

Interrupt IN or OUT status of µSOF7

Interrupt IN or OUT status of µSOF6

Interrupt IN or OUT status of µSOF5

Interrupt IN or OUT status of µSOF4

Interrupt IN or OUT status of µSOF3

Interrupt IN or OUT status of µSOF2

Interrupt IN or OUT status of µSOF1

28 to 26 Status6[2:0]

25 to 23 Status5[2:0]

22 to 20 Status4[2:0]

19 to 17 Status3[2:0]

16 to 14 Status2[2:0]

13 to 11 Status1[2:0]

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

80 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 78. Start and complete split for interrupt: bit description …continued

Bit

Symbol

Access

Value Description

10 to 8

Status0[2:0]

HW — writes

-

Interrupt IN or OUT status of µSOF0

Bit 0 — Transaction error (IN and OUT)

Bit 1 — Babble (IN token only)

Bit 2 — Underrun (OUT token only)

7 to 0

µSA[7:0]

SW — writes

(0 → 1)

-

Speciﬁes which µSOF the start split needs to be placed.

For OUT token: When the frame number of bits DW1[7:3]

matches the frame number of the USB bus, these bits are checked

for one before they are sent for the µSOF.

HW — writes

(1 → 0)

After

processing

For IN token: Only µSOF0, µSOF1, µSOF2 or µSOF3 can be set

to 1. Nothing can be set for µSOF4 and above.

DW3

63

A

SW — sets

-

Active: Write the same value as that in V.

HW — resets

62

61

60

59

H

HW — writes

-

Halt: The Halt bit is set when any microframe transfer status has a

stalled or halted condition.

B

Babble: This bit corresponds to bit 1 of Status0 to Status7 for

every microframe transfer status.

X

Transaction Error: This bit corresponds to bit 0 of Status0 to

Status7 for every microframe transfer status.

SC

SW — writes 0 -

HW — updates

Start/Complete:

0 — Start split

1 — Complete split

58

57

reserved

DT

-

HW — writes

SW — writes

Data Toggle: For an interrupt transfer, set correct bit to start the

PTD.

56 to 55 Cerr[1:0]

HW — writes

SW — writes

-

Error Counter: This ﬁeld corresponds to the Cerr[1:0] ﬁeld in TD.

00 — The transaction will not retry.

11 — The transaction will retry three times. Hardware will

decrement these values.

54 to 44 reserved

43 to 32 NrBytes

-

HW — writes

Number of Bytes Transferred: This ﬁeld indicates the number of

Transferred[11:0]

bytes sent or received for this transaction.

DW2

31 to 24 reserved

-

23 to 8

7 to 0

DW1

DataStart

Address[15:0]

SW — writes

Data Start Address: This is the start address for data that will be

sent or received on or from the USB bus. This is the internal

memory address and not the CPU address.

µFrame[7:0]

SW — writes

-

Bits 7 to 3 is the polling rate in milliseconds. Polling rate is deﬁned

as 2^{(b − 1)}µSOF; where b = 4 to 16. When b is 4, executed every

millisecond. See Table 79.

63 to 57 HubAddress

[6:0]

Hub Address: This indicates the hub address.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

81 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 78. Start and complete split for interrupt: bit description …continued

Bit Symbol Access Value Description

56 to 50 PortNumber[6:0] SW — writes

-

Port Number: This indicates the port number of the hub or

embedded TT.

49 to 48 SE[1:0]

SW — writes

This depends on the endpoint type and direction. It is valid only for

split transactions. Table 80 applies to start split and complete split

only.

47

46

reserved

S

-

SW — writes

This bit indicates whether a split transaction has to be executed:

0 — High-speed transaction

1 — Split transaction

45 to 44 EPType[1:0]

43 to 42 Token[1:0]

SW — writes

-

Transaction type:

11 — Interrupt

Token PID for this transaction:

00 — OUT

01 — IN

41 to 35 DeviceAddress

[6:0]

SW — writes

-

Device Address: This is the USB address of the function

containing the endpoint that is referred to by this buffer.

34 to 32 EndPt[3:1]

Endpoint: This is the USB address of the endpoint within the

function.

DW0

31

EndPt[0]

SW — writes

-

Endpoint: This is the USB address of the endpoint within the

function.

30 to 29 reserved

-

28 to 18 MaxPacketLength SW — writes

Maximum Packet Length: This ﬁeld indicates the maximum

number of bytes that can be sent to or received from an endpoint in

a single data packet. The maximum packet size for the full-speed

and low-speed devices is 64 bytes as deﬁned in Ref. 1 “Universal

Serial Bus Speciﬁcation Rev. 2.0”.

[10:0]

17 to 3

NrBytesTo

Transfer[14:0]

SW — writes

-

Number of Bytes to Transfer: This ﬁeld indicates the number of

bytes that can be transferred by this data structure. It is used to

indicate the depth of the DATA ﬁeld. The maximum total number of

bytes for this transaction is 4 kB.

2 to 1

0

reserved

V

-

SW — sets

0 — This bit is deactivated when the entire PTD is executed, or

when a fatal error is encountered.

HW — resets

1 — Software updates to one when there is payload to be sent or

received. The current PTD is active.

Table 79. Microframe description

b

5

6

7

8

9

Rate

2 ms

4 ms

8 ms

16 ms

32 ms

µFrame[7:3]

0 0001

0 0010 or 0 0011

0 0100 or 0 0111

0 1000 or 0 1111

1 0000 or 1 1111

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

82 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 80. SE description

Interrupt

S

1

0

E

0

Remarks

low-speed

full-speed

I/O

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

83 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

10. Power consumption

Table 81. Power consumption

Number of ports working

One port working (high-speed)

V_CC= 5.0 V, V_CC(I/O)= 3.3 V

V_CC= 3.3 V, V_CC(I/O)= 3.3 V

V_CC= 5.0 V, V_CC(I/O)= 1.8 V

V_CC= 3.3 V, V_CC(I/O)= 1.8 V

Two ports working (high-speed)

V_CC= 5.0 V, V_CC(I/O)= 3.3 V

V_CC= 3.3 V, V_CC(I/O)= 3.3 V

V_CC= 5.0 V, V_CC(I/O)= 1.8 V

V_CC= 3.3 V, V_CC(I/O)= 1.8 V

Three ports working (high-speed)

V_CC= 5.0 V, V_CC(I/O)= 3.3 V

V_CC= 3.3 V, V_CC(I/O)= 3.3 V

V_CC= 5.0 V, V_CC(I/O)= 1.8 V

V_CC= 3.3 V, V_CC(I/O)= 1.8 V

I_CC

90 mA

77 mA

82 mA

77 mA

110 mA

97 mA

102 mA

97 mA

130 mA

117 mA

122 mA

117 mA

The idle operating current, I_CC, that is, when the ISP1760 is in operational mode,

initialized and without any devices connected, is 70 mA. The additional current

consumption on I_CCis below 1 mA per port in the case of full-speed and low-speed

devices.

Deep-sleep suspend mode ensures the lowest power consumption when V_CCis always

supplied to the ISP1760. The suspend current I_CC(susp)is typically about 150 µA at room

temperature. The suspend current may increase if the ambient temperature increases. For

details, see Section 7.6.

In hybrid mode, when V_CCis disconnected, I_CC(I/O)will generally be below 100 µA. The

average value is 60 µA to 70 µA.

Under the condition of constant read and write accesses occurring on the 32-bit data bus,

the maximum I_CC(I/O)drawn from V_CC(I/O)is measured as 25 mA when the NXP ISP1760

evaluation board is connected to a BSQUARE PXA255 development platform. This

current will vary depending on the platform because of the different access timing, the

type of data patterns written on the data bus, and loading on the data bus.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

84 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

11. Limiting values

Table 82. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

V_CC(I/O)

V_CC(5V0)

I_lu

Parameter

Conditions

Min

−0.5

-

Max

+4.6

+5.6

100

Unit

V

input/output supply voltage

supply voltage (5.0 V)

latch-up current

V

V_I< 0 V or V_I> V_CC

mA

V

V_esd

electrostatic discharge voltage

storage temperature

I_LI< 1 µA (all pins)

−4000

−40

+4000

+125

T_stg

°C

12. Recommended operating conditions

Table 83. Recommended operating conditions

Symbol

Parameter

Conditions

Min

3.0

1.65

3.0

−40

-

Typ

3.3

1.8

-

Max

3.6

1.95

5.5

+85

-

Unit

V

V_CC(I/O)

input/output supply voltage

V_CC(I/O)= 3.3 V

V_CC(I/O)= 1.8 V

V

V_CC(5V0)

T_amb

supply voltage (5.0 V)

ambient temperature

suspend supply current

V

-

°C

µA

[1]

I_CC(susp)

T_amb= 25 °C;

150

V_CC(5V0)= 3.3 V

[1] Deep-sleep suspend mode.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

85 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

13. Static characteristics

Table 84. Static characteristics: digital pins

Digital pins: A[17:1], DATA[31:0], CS_N, RD_N, WR_N, DACK, DREQ, IRQ, RESET_N, SUSPEND/WAKEUP_N, CLKIN,

OC1_N, OC2_N, OC3_N.

OC1_N, OC2_N and OC3_N are used as digital overcurrent pins; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

V_IH

V_IL

HIGH-level input voltage

1.2

-

V

LOW-level input voltage

hysteresis voltage

-

0.5

V

V_hys

V_OL

V_OH

I_LI

0.4

-

0.7

V

LOW-level output voltage

HIGH-level output voltage

input leakage current

input capacitance

I_OL= 3 mA

-

0.22V_CC(I/O)

V

0.8V_CC(I/O)

-

V

V_I= 0 V to V_CC(I/O)

-

1

-

µA

pF

C_in

2.75

V_CC(I/O)= 3.0 V to 3.6 V

V_IH

V_IL

HIGH-level input voltage

2.0

-

V

LOW-level input voltage

hysteresis voltage

-

0.8

0.7

0.4

-

V

V_hys

V_OL

V_OH

I_LI

0.4

-

V

LOW-level output voltage

HIGH-level output voltage

input leakage current

input capacitance

I_OL= 3 mA

-

V

2.4

-

V

V_I= 0 V to V_CC(I/O)

-

1

µA

pF

C_in

2.75

-

Table 85. Static characteristics: PSW1_N, PSW2_N, PSW3_N

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

0.4

-

Unit

V

V_OL

V_OH

LOW-level output voltage I_OL= 8 mA; pull-up to V_CC(5V0)

HIGH-level output voltage pull-up to V_CC(I/O)

-

V_CC(I/O)

V

Table 86. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3)

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Input levels for high-speed

V_HSSQ

high-speed squelch detection

threshold voltage (differential signal

amplitude)

squelch detected

-

100

-

mV

no squelch detected

150

V_HSDSC

high-speed disconnect detection

threshold voltage (differential signal

amplitude)

disconnect detected

625

-

mV

disconnect not

detected

525

V_HSCM

high-speed data signaling common

mode voltage range (guideline for

receiver)

−50

-

+500

+10

mV

Output levels for high-speed

V_HSOI

high-speed idle level

−10

-

mV

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

86 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 86. Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3) …continued

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

V_HSOH

V_HSOL

V_CHIRPJ

high-speed data signaling

HIGH-level voltage

360

-

440

mV

high-speed data signaling

LOW-level voltage

−10

-

+10

mV

Chirp J level (differential voltage)

700^[1]

−900^[1]

-

1100

mV

V_CHIRPKChirp K level (differential voltage)

−500

Input levels for full-speed and low-speed

V_IH

HIGH-level input voltage

2.0

2.7

-

V

V_IHZ

V_IL

HIGH-level input voltage (ﬂoating)

LOW-level input voltage

3.6

0.8

-

V_DI

differential input sensitivity

|V_DP− V_DM

|

0.2

0.8

V_CM

differential common mode voltage

range

2.5

Output levels for full-speed and low-speed

V_OH

HIGH-level output voltage

LOW-level output voltage

SE1 output voltage

2.8

0

-

3.6

0.3

-

V

V_OL

V_OSE1

V_CRS

0.8

1.3

output signal crossover voltage

2.0

[1] The HS termination resistor is disabled, and the pull-up resistor is connected. Only during reset, when both the hub and the device are

capable of the high-speed operation.

Table 87. Static characteristics: REF5V

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

V_IH

HIGH-level input voltage

-

5

-

V

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

87 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

14. Dynamic characteristics

Table 88. Dynamic characteristics: system clock timing

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Crystal oscillator

[2]

f_clk

clock frequency

crystal^[1]

oscillator

-

12

-

MHz

External clock input

t_J

external clock jitter

-

500

ps

%

V

δ

clock duty cycle

input voltage on pin XTAL1

rise time

50

-

V_i(XTAL1)

V_CC(I/O)

-

t_r

t_f

-

3

ns

fall time

[1] Recommended values for external capacitors when using a crystal are 22 pF to 27 pF.

[2] Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. The oscillator used depends on V_CC(I/O)

.

Table 89. Dynamic characteristics: CPU interface block

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

SR slew rate

Conditions

Min

Typ

Max

Unit

standard load

1

-

4

V/ns

Table 90. Dynamic characteristics: high-speed source electrical characteristics

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Driver characteristics

Conditions

Min

Typ

Max

Unit

t_HSR

t_HSF

rise time (10 % to 90 %)

fall time (10 % to 90 %)

500

40.5

-

ps

Ω

-

[1]

Z_HSDRVdriver output impedance (which

also serves as high-speed

termination)

includes the R_Sresistor

45

49.5

Clock timing

t_HSDRAThigh-speed data rate

t_HSFRAMmicroframe interval

479.76

124.9375

1

-

480.24

Mbit/s

µs

125.0625

t_HSRFI

consecutive microframe interval

difference

four

high-speed

bit times

ns

[1] This also serves as a high-speed termination.

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

88 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 91. Dynamic characteristics: full-speed source electrical characteristics

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Driver characteristics

Conditions

Min

Typ

Max

Unit

t_FR

rise time

C_L= 50 pF; 10 % to 90 %

4

-

20

ns

%

Ω

of |V_OH− V_OL

C_L= 50 pF; 90 % to 10 %

of |V_OH− V_OL

|

t_FF

fall time

4

20

|

t_FRFM

Z_DRV

differential rise and fall time

matching

90

28

111.1

44

driver output impedance

for driver that is not

high-speed capable

Data timing: see Figure 14

t_FDEOP

source jitter for differential

full-speed timing

−2

-

+5

ns

transition to SE0 transition

source SE0 interval of EOP

receiver SE0 interval of EOP

t_FEOPT

t_FEOPR

t_LDEOP

160

82

-

175

-

ns

upstream facing port source

jitter for differential transition to

SE0 transition

low-speed timing

−40

+100

t_LEOPT

t_LEOPR

t_FST

source SE0 interval of EOP

receiver SE0 interval of EOP

1.25

670

-

1.5

-

µs

ns

width of SE0 interval during

differential transition

14

Table 92. Dynamic characteristics: low-speed source electrical characteristics

V_CC(I/O)= 1.65 V to 3.6 V; T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Driver characteristics

Conditions

Min

Typ

Max

Unit

t_LR

transition time: rise time

75

90

-

300

125

ns

%

t_LF

transition time: fall time

t_LRFM

rise and fall time matching

T

PERIOD

+3.3 V

crossover point

extended

crossover point

differential

data lines

0 V

differential data to

SE0/EOP skew

source EOP width: t

, t

FEOPT LEOPT

N × T

+ t

FDEOP

+ t

LDEOP

PERIOD

receiver EOP width: t

, t

FEOPR LEOPR

004aaa929

T_PERIODis the bit duration corresponding with the USB data rate.

Fig 14. USB source differential data-to-EOP transition skew and EOP width

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

89 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

14.1 PIO timing

14.1.1 Register or memory write

t

h31

A[17:1]

address 01

address 02

t

su21

t

h21

CS_N

t

su31

t

w11

WR_N

t

su11

t

h11

DATA

data 01

data 02

004aaa527

Fig 15. Register or memory write

Table 93. Register or memory write

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

Parameter

Min

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

t_h11

data hold after WR_N HIGH

2

-

ns

t_h21

CS_N hold after WR_N HIGH

address hold after WR_N HIGH

WR_N pulse width

1

t_h31

2

t_w11

t_su11

t_su21

t_su31

17

5

data set-up time before WR_N HIGH

address set-up time before WR_N HIGH

CS_N set-up time before WR_N HIGH

5

V_CC(I/O)= 3.3 V to 3.6 V

t_h11

data hold after WR_N HIGH

2

-

ns

t_h21

CS_N hold after WR_N HIGH

address hold after WR_N HIGH

WR_N pulse width

1

t_h31

2

t_w11

t_su11

t_su21

t_su31

17

5

data set-up time before WR_N HIGH

address set-up time before WR_N HIGH

CS_N set-up time before WR_N HIGH

5

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

90 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

14.1.2 Register read

t

su12

A[17:1]

address 01

address 02

t

su22

CS_N

RD_N

t

d22

t

w12

DATA

004aaa524

t

d12

Fig 16. Register read

Table 94. Register read

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

V_CC(I/O)= 1.65 V to 1.95 V

Min

Max

Unit

t_su12

t_su22

t_w12

t_d12

address set-up time before RD_N LOW

0

-

ns

CS_N set-up time before RD_N LOW

RD_N pulse width

0

-

> t_d12

-

data valid time after RD_N LOW

data valid time after RD_N HIGH

-

35

1

t_d22

V_CC(I/O)= 3.3 V to 3.6 V

t_su12

t_su22

t_w12

t_d12

address set-up time before RD_N LOW

0

-

ns

CS_N set-up time before RD_N LOW

RD_N pulse width

0

-

> t_d12

-

data valid time after RD_N LOW

data valid time after RD_N HIGH

-

22

1

t_d22

14.1.3 Register access

CS_N

WR_N

t

WHWL

RD_N

t

WHRL

t

RHRL

RHWL

004aaa983

Fig 17. Register access

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

91 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 95. Register access

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_WHRL

t_RHRL

Parameter

Min

25^[1]

25

Max

Unit

ns

WR_N HIGH to RD_N LOW time

RD_N HIGH to RD_N LOW time

RD_N HIGH to WR_N LOW time

WR_N HIGH to WR_N LOW time

-

ns

t_RHWL

t_WHWL

ns

25^[1]

ns

[1] For EHCI operational registers, minimum value is 195 ns.

14.1.4 Memory read

A[17:1]

address = 33C

address 1

address 2

address 3

data 3

t

su23

DATA

data

data 1

data 2

CS_N

t

d13

WR_N

t

p13

d23

RD_N

004aaa523

T

cy13

t

w13

t

su13

Fig 18. Memory read

Table 96. Memory read

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

V_CC(I/O)= 1.65 V to 1.95 V

Min

Max

Unit

t_p13

initial pre-fetch time

90

40

-

ns

T_cy13

t_d13

memory RD_N cycle time

-

data valid time after RD_N LOW

data available time after RD_N HIGH

RD_N pulse width

31

1

-

t_d23

-

t_w13

t_su13

t_su23

32

0

CS_N set-up time before RD_N LOW

address set-up time before RD_N LOW

-

0

-

V_CC(I/O)= 3.3 V to 3.6 V

t_p13

initial pre-fetch time

90

36

-

ns

T_cy13

t_d13

memory RD_N cycle time

-

data valid time after RD_N LOW

20

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

92 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 96. Memory read …continued

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_d23

Parameter

Min

-

Max

Unit

ns

data available time after RD_N HIGH

RD_N pulse width

1

-

t_w13

21

0

ns

t_su13

CS_N set-up time before RD_N LOW

address set-up time before RD_N LOW

-

ns

t_su23

0

-

ns

14.2 DMA timing

In the following sections:

• Polarity of DACK is active HIGH

• Polarity of DREQ is active HIGH.

14.2.1 Single cycle: DMA read

t

a44

DREQ

DACK

RD_N

DATA

t

a34

a14

t

w14

td14

t

a24

t

h14

004aaa530

Fig 19. DMA read (single cycle)

Table 97. DMA read (single cycle)

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

V_CC(I/O)= 1.65 V to 1.95 V

Min

Max

Unit

t_a14

t_a24

t_d14

t_w14

t_a34

t_a44

t_h14

DACK assertion time after DREQ assertion

0

-

ns

RD_N assertion time after DACK assertion

data valid time after RD_N assertion

RD_N pulse width

0

-

24

-

> t_d14

-

DREQ de-assertion time after RD_N assertion

29

56

5

DACK de-assertion to next DREQ assertion time -

data hold time after RD_N de-asserts

-

V_CC(I/O)= 3.3 V to 3.6 V

t_a14

t_a24

t_d14

DACK assertion time after DREQ assertion

0

-

ns

RD_N assertion time after DACK assertion

data valid time after RD_N assertion

-

20

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

93 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

Table 97. DMA read (single cycle) …continued

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol

t_w14

Parameter

Min

> t_d14

-

Max

-

Unit

ns

RD_N pulse width

t_a34

DREQ de-assertion time after RD_N assertion

18

56

5

ns

t_a44

DACK de-assertion to next DREQ assertion time -

data hold time after RD_N de-asserts

ns

t_h14

-

ns

14.2.2 Single cycle: DMA write

t

DREQ

cy15

t

a15

t

a35

DACK

t

w15

t

a25

h25

WR_N

DATA

t

su15

t

h15

data

data 1

004aaa525

DREQ and DACK are active HIGH.

Fig 20. DMA write (single cycle)

Table 98. DMA write (single cycle)

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Min

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

t_a15

t_a25

t_h15

t_h25

t_su15

t_a35

t_cy15

DACK assertion time after DREQ assertion

WR_N assertion time after DACK assertion

data hold time after WR_N de-assertion

DACK hold time after WR_N de-assertion

data set-up time before WR_N de-assertion

DREQ de-assertion time after WR_N assertion

0

1

3

0

5.5

-

ns

-

28

82

last DACK strobe de-assertion to next DREQ

assertion time

-

t_w15

WR_N pulse width

22

-

ns

V_CC(I/O)= 3.3 V to 3.6 V

t_a15

t_a25

t_h15

t_h25

t_su15

t_a35

t_cy15

DACK assertion time after DREQ assertion

0

1

2

0

5.5

-

ns

WR_N assertion time after DACK assertion

data hold time after WR_N de-assertion

DACK hold time after WR_N de-assertion

data set-up time before WR_N de-assertion

DREQ de-assertion time after WR_N assertion

-

16

82

last DACK strobe de-assertion to next DREQ

assertion time

-

t_w15

WR_N pulse width

22

-

ns

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

94 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

14.2.3 Multi-cycle: DMA read

t

a46

a36

DREQ

DACK

t

a16

t

T

a26

cy16

t

w16

RD_N

DATA

t

h16

data n-1

data n

data 1

data 0

004aaa531

t

d16

DREQ and DACK are active HIGH.

Fig 21. DMA read (multi-cycle burst)

Table 99. DMA read (multi-cycle burst)

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Min

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

t_a16

t_a26

t_d16

t_w16

T_cy16

t_a36

DACK assertion after DREQ assertion time

RD_N assertion after DACK assertion time

data valid time after RD_N assertion

RD_N pulse width

0

-

ns

0

-

31

-

38

46

-

read-to-read cycle time

-

DREQ de-assertion time after last burst RD_N

de-assertion

30

t_a46

DACK de-assertion to next DREQ assertion

time

-

82

5

ns

t_h16

data hold time after RD_N de-asserts

V_CC(I/O)= 3.3 V to 3.6 V

t_a16

t_a26

t_d16

t_w16

T_cy16

t_a36

DACK assertion after DREQ assertion time

0

-

ns

RD_N assertion after DACK assertion time

data valid time after RD_N assertion

RD_N pulse width

0

-

16

-

17

38

-

read-to-read cycle time

-

DREQ de-assertion time after last burst RD_N

de-assertion

20

t_a46

t_h16

DACK de-assertion to next DREQ assertion

time

-

82

5

ns

data hold time after RD_N de-asserts

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

95 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

14.2.4 Multi-cycle: DMA write

t

a57

DREQ

DACK

WR_N

DATA

t

a17

t

h27

t

T

a37

su17

cy17

t

w17

t

a47

t

a27

t

h17

data n-1

data 1

data 2

data n

004aaa526

Fig 22. DMA write (multi-cycle burst)

Table 100. DMA write (multi-cycle burst)

T_amb= −40 °C to +85 °C; unless otherwise speciﬁed.

Symbol Parameter

Min

Max

Unit

V_CC(I/O)= 1.65 V to 1.95 V

T_cy17

t_su17

t_h17

DMA write cycle time

51

5

2

0

2

-

ns

data set-up time before WR_N de-assertion

data hold time after WR_N de-assertion

DACK assertion time after DREQ assertion

WR_N assertion time after DACK assertion

-

t_a17

-

t_a27

-

t_a37

DREQ de-assertion time at last strobe (WR_N)

assertion

28

t_h27

t_a47

t_w17

t_a57

DACK hold time after WR_N de-assertion

0

-

ns

strobe de-assertion to next strobe assertion time 34

-

WR_N pulse width

17

-

DACK de-assertion to next DREQ assertion time

82

V_CC(I/O)= 3.3 V to 3.6 V

T_cy17

t_su17

t_h17

DMA write cycle time

51

5

2

0

1

-

ns

data set-up time before WR_N de-assertion

data hold time after WR_N de-assertion

DACK assertion time after DREQ assertion

WR_N assertion time after DACK assertion

-

t_a17

-

t_a27

-

t_a37

DREQ de-assertion time at last strobe (WR_N)

assertion

16

t_h27

t_a47

t_w17

t_a57

DACK hold time after WR_N de-assertion

0

-

ns

strobe de-assertion to next strobe assertion time 34

-

WR_N pulse width

17

-

DACK de-assertion to next DREQ assertion time

82

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

96 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

15. Package outline

LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm

SOT425-1

y

X

A

102

103

65

64

Z

E

e

H

A

E

2

A

E

(A )

3

A

1

θ

w M

p

L

p

b

pin 1 index

detail X

39

38

128

1

v

M

A

Z

w M

D

b

p

e

D

B

H

v

M

B

D

0

5

10 mm

scale

DIMENSIONS (mm are the original dimensions)

A

(1)

UNIT

A

b

c

D

E

e

H

D

H

L

v

w

y

Z

E

θ

1

2

3

p

E

p

D

max.

7^o

0^o

0.15 1.45

0.05 1.35

0.27 0.20 20.1 14.1

0.17 0.09 19.9 13.9

22.15 16.15

21.85 15.85

0.75

0.45

0.81 0.81

0.59 0.59

mm

1.6

0.25

1

0.2 0.12 0.1

0.5

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

REFERENCES

OUTLINE

EUROPEAN

PROJECTION

ISSUE DATE

VERSION

IEC

JEDEC

JEITA

00-01-19

03-02-20

SOT425-1

136E28

MS-026

Fig 23. Package outline SOT425-1 (LQFP128)

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

97 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 9 x 9 x 0.8 mm

SOT857-1

D

B

A

ball A1

index area

A

E

2

A

1

detail X

C

e

1

y

C

1

y

M

v

C

A

B

b

e

1/2 e

w

T

R

P

M

K

H

e

N

L

J

e

2

G

E

C

A

1/2 e

F

D

B

ball A1

index area

1

3

5

7

9

11 13 15

2

4

6

8

10 12 14 16

X

0

2.5

5 mm

scale

DIMENSIONS (mm are the original dimensions)

A

UNIT

A

1

A

2

b

D

E

e

v

w

y

1

2

max

0.25 0.85 0.35

0.15 0.75 0.25

9.1

8.9

9.1

8.9

mm

1.1

0.5

7.5

0.15 0.05 0.08

0.1

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEDEC

JEITA

04-05-05

04-06-22

SOT857-1

MO-195

Fig 24. Package outline SOT857-1 (TFBGA128)

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16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account

of soldering ICs can be found in Application Note AN10365 “Surface mount reﬂow

soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to

Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both

the mechanical and the electrical connection. There is no single soldering method that is

ideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not

suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high

densities that come with increased miniaturization.

16.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from

a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components

• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadless

packages which have solder lands underneath the body, cannot be wave soldered. Also,

leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,

due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed by

component placement and exposure to a temperature proﬁle. Leaded packages,

packages with solder balls, and leadless packages are all reﬂow solderable.

Key characteristics in both wave and reﬂow soldering are:

• Board speciﬁcations, including the board ﬁnish, solder masks and vias

• Package footprints, including solder thieves and orientation

• The moisture sensitivity level of the packages

• Package placement

• Inspection and repair

• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Key characteristics in wave soldering are:

• Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components are

exposed to the wave

• Solder bath speciﬁcations, including temperature and impurities

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16.4 Reﬂow soldering

Key characteristics in reﬂow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to

higher minimum peak temperatures (see Figure 25) than a SnPb process, thus

reducing the process window

• Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

• Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperature is high enough for the solder to make reliable solder joints (a solder paste

characteristic). In addition, the peak temperature must be low enough that the

packages and/or boards are not damaged. The peak temperature of the package

depends on package thickness and volume and is classiﬁed in accordance with

Table 101 and 102

Table 101. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

235

≥ 350

220

< 2.5

≥ 2.5

220

Table 102. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reﬂow temperature (°C)

Volume (mm³)

< 350

260

350 to 2000

> 2000

260

< 1.6

260

250

245

1.6 to 2.5

> 2.5

260

245

250

245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reﬂow

soldering, see Figure 25.

ISP1760_4

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maximum peak temperature

= MSL limit, damage level

temperature

minimum peak temperature

= minimum soldering temperature

peak

temperature

time

001aac844

MSL: Moisture Sensitivity Level

Fig 25. Temperature proﬁles for large and small components

For further information on temperature proﬁles, refer to Application Note AN10365

“Surface mount reﬂow soldering description”.

17. Soldering of through-hole mount packages

17.1 Introduction to soldering through-hole mount packages

This text gives a very brief insight into wave, dip and manual soldering.

Wave soldering is the preferred method for mounting of through-hole mount IC packages

on a printed-circuit board.

17.2 Soldering by dipping or by solder wave

Driven by legislation and environmental forces the worldwide use of lead-free solder

pastes is increasing. Typical dwell time of the leads in the wave ranges from

3 seconds to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb

or Pb-free respectively.

The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic

body must not exceed the speciﬁed maximum storage temperature (T_stg(max)). If the

printed-circuit board has been pre-heated, forced cooling may be necessary immediately

after soldering to keep the temperature within the permissible limit.

17.3 Manual soldering

Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the

seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is

less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is

between 300 °C and 400 °C, contact may be up to 5 seconds.

ISP1760_4

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Rev. 04 — 4 February 2008

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17.4 Package related soldering information

Table 103. Suitability of through-hole mount IC packages for dipping and wave soldering

Package

Soldering method

Dipping

Wave

CPGA, HCPGA

-

suitable

DBS, DIP, HDIP, RDBS, SDIP, SIL

PMFP^[2]

suitable

-

suitable^[1]

not suitable

[1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit

board.

[2] For PMFP packages hot bar soldering or manual soldering is suitable.

18. Abbreviations

Table 104. Abbreviations

Acronym

ACK

ASIC

ATL

Description

Acknowledgment

Application-Speciﬁc Integrated Circuit

Asynchronous Transfer List

Analog Transceiver

Complete Split

ATX

CS

DMA

DW

Direct Memory Access

Double Word

EHCI

EMI

EOP

EOT

ESD

ESR

FIFO

FLS

FS

Enhanced Host Controller Interface

ElectroMagnetic Interference

End-Of-Packet

End-Of-Transfer

ElectroStatic Discharge

Effective Series Resistance

First In, First Out

Frame List Size

Full-Speed

GPIO

HC

General-Purpose Input/Output

Host Controller

HNP

HS

Host Negotiation Protocol

High-Speed

iTD

isochronous Transfer Descriptor

Interrupt

INT

ISO

Isochronous

ISR

Interrupt Service Routine

Isochronous (ISO) Transfer List

Low-Speed

ITL

LS

NAK

NYET

Not Acknowledged

Not Yet

ISP1760_4

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Rev. 04 — 4 February 2008

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Table 104. Abbreviations …continued

Acronym

Description

OC

Overcurrent

OHCI

PCI

Open Host Controller Interface

Peripheral Component Interconnect

Personal Digital Assistant

Packer Identiﬁer

PDA

PID

PIO

Programmed Input/Output

Phase-Locked Loop

PLL

PMOS

POR

PORP

PTD

RISC

SE0

SE1

siTD

SOF

SRP

SS

Positive-channel Metal-Oxide Semiconductor

Power-On Reset

Power-On Reset Pulse

Philips Transfer Descriptor

Reduced Instruction Set Computer

Single Ended 0

Single Ended 1

split isochronous Transfer Descriptor

Start-Of-Frame

Session Request Protocol

Start Split

TT

Transaction Translator

UHCI

USB

Universal Host Controller Interface

Universal Serial Bus

19. References

[1] Universal Serial Bus Speciﬁcation Rev. 2.0

[2] Enhanced Host Controller Interface Speciﬁcation for Universal Serial Bus Rev. 1.0

[3] Embedded Systems Design with the ISP176x (AN10043)

[4] ISP176x Linux Programming Gui13de (AN10042)

[5] Interfacing the ISP176x to the Intel PXA25x processor (AN10037)

ISP1760_4

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Rev. 04 — 4 February 2008

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20. Revision history

Table 105. Revision history

Document ID

ISP1760_4

Release date

Data sheet status

Change notice

Supersedes

20080204

Product data sheet

-

ISP1760_3

Modiﬁcations:

• Section 7.3 “Accessing the ISP1760 host controller memory: PIO and DMA”: updated the second

paragraph.

• Table 52 “Power Down Control register (address 0354h) bit description”: updated description for

bits 12 and 11.

• Table 82 “Limiting values”: updated the conditions column of V_esd

.

• Section 19 “References”: Removed On-The-Go Supplement to the USB Speciﬁcation Rev. 1.2.

ISP1760_3

20070302

20051025

Product data sheet

-

ISP1760_2

ISP1760_1

ISP1760_2

(9397 750 15189)

ISP1760_1

20041108

Product data sheet

-

(9397 750 13257)

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

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Embedded Hi-Speed USB host controller

21. Legal information

21.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Deﬁnition

Objective [short] data sheet

This document contains data from the objective speciﬁcation for product development.

This document contains data from the preliminary speciﬁcation.

This document contains the product speciﬁcation.

Preliminary [short] data sheet Qualiﬁcation

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Deﬁnitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

21.2 Deﬁnitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

21.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

21.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

22. Contact information

For more information, please visit: http://www.nxp.com

For sales ofﬁce addresses, please send an email to: salesaddresses@nxp.com

ISP1760_4

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Rev. 04 — 4 February 2008

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23. Tables

Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6

Table 3. Port connection scenarios . . . . . . . . . . . . . . . .15

Table 4. Memory address . . . . . . . . . . . . . . . . . . . . . . .17

Table 5. Using the IRQ Mask AND or IRQ Mask OR

registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 6. Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 7. Pin status in hybrid mode . . . . . . . . . . . . . . . .27

Table 8. Register overview . . . . . . . . . . . . . . . . . . . . . .29

Table 9. CAPLENGTH - Capability Length register

(address 0000h) bit description . . . . . . . . . . . .30

Table 10. HCIVERSION - Host Controller Interface

Version Number register (address 0002h)

Table 30. INT PTD Last PTD register

(address 0148h) bit description . . . . . . . . . . . . 39

Table 31. ATL PTD Done Map register

(address 0150h) bit description . . . . . . . . . . . . 39

Table 32. ATL PTD Skip Map register

(address 0154h) bit description . . . . . . . . . . . . 39

Table 33. ATL PTD Last PTD register

(address 0158h) bit description . . . . . . . . . . . . 40

Table 34. HW Mode Control - Hardware Mode

Control register (address 0300h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 35. HW Mode Control - Hardware Mode

Control register (address 0300h) bit

bit description . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 11. HCSPARAMS - Host Controller Structural

Parameters register (address 0004h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 12. HCSPARAMS - Host Controller Structural

Parameters register (address 0004h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 13. HCCPARAMS - Host Controller Capability

Parameters register (address 0008h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 14. HCCPARAMS - Host Controller Capability

Parameters register (address 0008h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 36. Chip ID - Chip Identiﬁer register

(address 0304h) bit description . . . . . . . . . . . . 42

Table 37. Scratch register (address 0308h) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 38. SW Reset - Software Reset register

(address 030Ch) bit allocation . . . . . . . . . . . . 42

Table 39. SW Reset - Software Reset register

(address 030Ch) bit description . . . . . . . . . . . 43

Table 40. DMA Conﬁguration register

(address 0330h) bit allocation . . . . . . . . . . . . . 43

Table 41. DMA Conﬁguration register

description . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Table 15. USBCMD - USB Command register

(address 0020h) bit allocation . . . . . . . . . . . . .33

Table 16. USBCMD - USB Command register

(address 0020h) bit description . . . . . . . . . . . .33

Table 17. USBSTS - USB Status register

(address 0024h) bit allocation . . . . . . . . . . . . .33

Table 18. USBSTS - USB Status register

(address 0024h) bit description . . . . . . . . . . . .34

Table 19. FRINDEX - Frame Index register

(address 0330h) bit description . . . . . . . . . . . . 44

Table 42. Buffer Status register (address 0334h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 43. Buffer Status register (address 0334h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 44. ATL Done Timeout register (address 0338h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 45. Memory register (address 033Ch) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 46. Memory register (address 033Ch) bit

description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 47. Edge Interrupt Count register

(address: 002Ch) bit allocation . . . . . . . . . . . .34

Table 20. FRINDEX - Frame Index register

(address: 002Ch) bit description . . . . . . . . . . .35

Table 21. CONFIGFLAG - Conﬁgure Flag register

(address 0060h) bit allocation . . . . . . . . . . . . .35

Table 22. CONFIGFLAG - Conﬁgure Flag register

(address 0060h) bit description . . . . . . . . . . . .36

Table 23. PORTSC1 - Port Status and Control 1

register (address 0064h) bit allocation . . . . . . .36

Table 24. PORTSC1 - Port Status and Control 1

register (address 0064h) bit description . . . . .37

Table 25. ISO PTD Done Map register

(address 0340h) bit allocation . . . . . . . . . . . . . 46

Table 48. Edge Interrupt Count register

(address 0340h) bit description . . . . . . . . . . . . 47

Table 49. DMA Start Address register

(address 0344h) bit allocation . . . . . . . . . . . . . 47

Table 50. DMA Start Address register

(address 0344h) bit description . . . . . . . . . . . . 48

Table 51. Power Down Control register

(address 0354h) bit allocation . . . . . . . . . . . . . 48

Table 52. Power Down Control register

(address 0130h) bit description . . . . . . . . . . . .37

Table 26. ISO PTD Skip Map register

(address 0134h) bit description . . . . . . . . . . . .38

Table 27. ISO PTD Last PTD register

(address 0138h) bit description . . . . . . . . . . . .38

Table 28. INT PTD Done Map register

(address 0140h) bit description . . . . . . . . . . . .38

Table 29. INT PTD Skip Map register

(address 0354h) bit description . . . . . . . . . . . . 49

Table 53. Port 1 Control register (address 0374h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 54. Port 1 Control register (address 0374h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 55. Interrupt register (address 0310h)

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 56. Interrupt register (address 0310h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . . 52

(address 0144h) bit description . . . . . . . . . . . .38

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Table 57. Interrupt Enable register (address 0314h) bit

allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Table 58. Interrupt Enable register (address 0314h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .54

Table 59. ISO IRQ Mask OR register (address 0318h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 60. INT IRQ Mask OR register (address 031Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 61. ATL IRQ Mask OR register (address 0320h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 62. ISO IRQ Mask AND register (address 0324h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .55

Table 63. INT IRQ Mask AND register (address 0328h)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 64. ATL IRQ Mask AND register (address 032Ch)

bit description . . . . . . . . . . . . . . . . . . . . . . . . .56

Table 65. High-speed bulk IN and OUT:

source electrical characteristics . . . . . . . . . . . 88

Table 91. Dynamic characteristics: full-speed source

electrical characteristics . . . . . . . . . . . . . . . . . 89

Table 92. Dynamic characteristics: low-speed

source electrical characteristics . . . . . . . . . . . 89

Table 93. Register or memory write . . . . . . . . . . . . . . . . 90

Table 94. Register read . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Table 95. Register access . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 96. Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Table 97. DMA read (single cycle) . . . . . . . . . . . . . . . . . 93

Table 98. DMA write (single cycle) . . . . . . . . . . . . . . . . . 94

Table 99. DMA read (multi-cycle burst) . . . . . . . . . . . . . . 95

Table 100.DMA write (multi-cycle burst) . . . . . . . . . . . . . 96

Table 101.SnPb eutectic process (from J-STD-020C) . . 100

Table 102.Lead-free process (from J-STD-020C) . . . . . 100

Table 103.Suitability of through-hole mount

IC packages for dipping and wave soldering . 102

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Table 66. High-speed bulk IN and OUT:

Table 104.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 102

Table 105.Revision history . . . . . . . . . . . . . . . . . . . . . . . 104

bit description . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 67. High-speed isochronous IN and OUT:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Table 68. High-speed isochronous IN and OUT:

bit description . . . . . . . . . . . . . . . . . . . . . . . . .64

Table 69. High-speed interrupt IN and OUT:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 70. High-speed interrupt IN and OUT:

bit description . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 71. Microframe description . . . . . . . . . . . . . . . . . .70

Table 72. Start and complete split for bulk:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 73. Start and complete split for bulk:

bit description . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 74. SE description . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 75. Start and complete split for isochronous:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 76. Start and complete split for isochronous:

bit description . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 77. Start and complete split for interrupt:

bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 78. Start and complete split for interrupt:

bit description . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 79. Microframe description . . . . . . . . . . . . . . . . . .82

Table 80. SE description . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 81. Power consumption . . . . . . . . . . . . . . . . . . . . .84

Table 82. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 83. Recommended operating conditions . . . . . . . .85

Table 84. Static characteristics: digital pins . . . . . . . . . . .86

Table 85. Static characteristics:

PSW1_N, PSW2_N, PSW3_N . . . . . . . . . . . .86

Table 86. Static characteristics: USB interface block

(pins DM1 to DM3 and DP1 to DP3) . . . . . . . .86

Table 87. Static characteristics: REF5V . . . . . . . . . . . . .87

Table 88. Dynamic characteristics: system clock

timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 89. Dynamic characteristics: CPU interface

block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Table 90. Dynamic characteristics: high-speed

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

107 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

24. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin conﬁguration (LQFP128); top view . . . . . . . . .5

Fig 3. Pin conﬁguration (TFBGA128); top view . . . . . . . .5

Fig 4. Internal hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Fig 5. ISP1760 clock scheme . . . . . . . . . . . . . . . . . . . .14

Fig 6. Memory segmentation and access block

diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Fig 7. Adjusting analog overcurrent detection limit

(optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Fig 8. ISP1760 power supply connection. . . . . . . . . . . .26

Fig 9. Most commonly used power supply connection .26

Fig 10. Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 11. Internal power-on reset timing . . . . . . . . . . . . . . .28

Fig 12. Clock with respect to the external

power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 13. NextPTD traversal rule. . . . . . . . . . . . . . . . . . . . .58

Fig 14. USB source differential data-to-EOP

transition skew and EOP width . . . . . . . . . . . . . .89

Fig 15. Register or memory write. . . . . . . . . . . . . . . . . . .90

Fig 16. Register read . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Fig 17. Register access . . . . . . . . . . . . . . . . . . . . . . . . . .91

Fig 18. Memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Fig 19. DMA read (single cycle). . . . . . . . . . . . . . . . . . . .93

Fig 20. DMA write (single cycle) . . . . . . . . . . . . . . . . . . .94

Fig 21. DMA read (multi-cycle burst) . . . . . . . . . . . . . . . .95

Fig 22. DMA write (multi-cycle burst). . . . . . . . . . . . . . . .96

Fig 23. Package outline SOT425-1 (LQFP128) . . . . . . . .97

Fig 24. Package outline SOT857-1 (TFBGA128). . . . . . .98

Fig 25. Temperature proﬁles for large and small

components . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

108 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

25. Contents

1

General description . . . . . . . . . . . . . . . . . . . . . . 1

8.3

Conﬁguration registers. . . . . . . . . . . . . . . . . . 40

HW Mode Control register . . . . . . . . . . . . . . . 40

Chip ID register . . . . . . . . . . . . . . . . . . . . . . . 41

Scratch register . . . . . . . . . . . . . . . . . . . . . . . 42

SW Reset register . . . . . . . . . . . . . . . . . . . . . 42

DMA Conﬁguration register . . . . . . . . . . . . . . 43

Buffer Status register . . . . . . . . . . . . . . . . . . . 44

ATL Done Timeout register . . . . . . . . . . . . . . 45

Memory register . . . . . . . . . . . . . . . . . . . . . . . 45

Edge Interrupt Count register. . . . . . . . . . . . . 46

DMA Start Address register . . . . . . . . . . . . . . 47

Power Down Control register . . . . . . . . . . . . . 48

Port 1 Control register . . . . . . . . . . . . . . . . . . 50

Interrupt registers. . . . . . . . . . . . . . . . . . . . . . 51

Interrupt register. . . . . . . . . . . . . . . . . . . . . . . 51

Interrupt Enable register. . . . . . . . . . . . . . . . . 53

ISO IRQ Mask OR register. . . . . . . . . . . . . . . 54

INT IRQ Mask OR register. . . . . . . . . . . . . . . 55

ATL IRQ Mask OR register. . . . . . . . . . . . . . . 55

ISO IRQ Mask AND register . . . . . . . . . . . . . 55

INT IRQ Mask AND register. . . . . . . . . . . . . . 55

ATL IRQ Mask AND register . . . . . . . . . . . . . 56

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

8.3.7

8.3.8

8.3.9

8.3.10

8.3.11

8.3.12

8.4

8.4.1

8.4.2

8.4.3

8.4.4

8.4.5

8.4.6

8.4.7

8.4.8

2

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3

3.1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Examples of a multitude of possible

applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4

5

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6

6.1

6.2

Pinning information. . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6

7

7.1

Functional description . . . . . . . . . . . . . . . . . . 13

ISP1760 internal architecture: advanced

NXP slave host controller and hub . . . . . . . . . 13

Internal clock scheme and port selection . . . . 14

Host controller buffer memory block . . . . . . . . 15

General considerations. . . . . . . . . . . . . . . . . . 15

Structure of the ISP1760 host controller

7.1.1

7.2

7.2.1

7.2.2

memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Accessing the ISP1760 host controller

7.3

memory: PIO and DMA . . . . . . . . . . . . . . . . . 18

PIO mode access, memory read cycle. . . . . . 18

PIO mode access, memory write cycle . . . . . 19

PIO mode access, register read cycle . . . . . . 19

PIO mode access, register write cycle . . . . . . 19

DMA mode, read and write operations . . . . . . 19

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Phase-Locked Loop (PLL) clock multiplier . . . 23

Power management . . . . . . . . . . . . . . . . . . . . 23

Overcurrent detection . . . . . . . . . . . . . . . . . . . 25

Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 26

Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Power-On Reset (POR) . . . . . . . . . . . . . . . . . 27

7.3.1

7.3.2

7.3.3

7.3.4

7.3.5

7.4

7.5

7.6

7.7

7.8

9

Philips Transfer Descriptor (PTD) . . . . . . . . . 56

High-speed bulk IN and OUT . . . . . . . . . . . . . 59

High-speed isochronous IN and OUT . . . . . . 63

High-speed interrupt IN and OUT . . . . . . . . . 67

Start and complete split for bulk. . . . . . . . . . . 71

Start and complete split for isochronous . . . . 75

Start and complete split for interrupt . . . . . . . 79

9.1

9.2

9.3

9.4

9.5

9.6

10

11

12

13

Power consumption . . . . . . . . . . . . . . . . . . . . 84

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 85

Recommended operating conditions . . . . . . 85

Static characteristics . . . . . . . . . . . . . . . . . . . 86

7.8.1

7.9

8

8.1

8.1.1

8.1.2

8.1.3

8.1.4

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.2.7

8.2.8

8.2.9

8.2.10

8.2.11

8.2.12

8.2.13

8.2.14

8.2.15

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

EHCI capability registers . . . . . . . . . . . . . . . . 30

CAPLENGTH register. . . . . . . . . . . . . . . . . . . 30

HCIVERSION register . . . . . . . . . . . . . . . . . . 30

HCSPARAMS register . . . . . . . . . . . . . . . . . . 30

HCCPARAMS register . . . . . . . . . . . . . . . . . . 31

EHCI operational registers . . . . . . . . . . . . . . . 32

USBCMD register . . . . . . . . . . . . . . . . . . . . . . 32

USBSTS register . . . . . . . . . . . . . . . . . . . . . . 33

USBINTR register. . . . . . . . . . . . . . . . . . . . . . 34

FRINDEX register. . . . . . . . . . . . . . . . . . . . . . 34

CONFIGFLAG register . . . . . . . . . . . . . . . . . . 35

PORTSC1 register . . . . . . . . . . . . . . . . . . . . . 36

ISO PTD Done Map register. . . . . . . . . . . . . . 37

ISO PTD Skip Map register . . . . . . . . . . . . . . 37

ISO PTD Last PTD register . . . . . . . . . . . . . . 38

INT PTD Done Map register . . . . . . . . . . . . . . 38

INT PTD Skip Map register. . . . . . . . . . . . . . . 38

INT PTD Last PTD register. . . . . . . . . . . . . . . 39

ATL PTD Done Map register. . . . . . . . . . . . . . 39

ATL PTD Skip Map register . . . . . . . . . . . . . . 39

ATL PTD Last PTD register . . . . . . . . . . . . . . 40

14

14.1

Dynamic characteristics. . . . . . . . . . . . . . . . . 88

PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Register or memory write. . . . . . . . . . . . . . . . 90

Register read . . . . . . . . . . . . . . . . . . . . . . . . . 91

Register access . . . . . . . . . . . . . . . . . . . . . . . 91

Memory read . . . . . . . . . . . . . . . . . . . . . . . . . 92

DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Single cycle: DMA read . . . . . . . . . . . . . . . . . 93

Single cycle: DMA write . . . . . . . . . . . . . . . . . 94

Multi-cycle: DMA read . . . . . . . . . . . . . . . . . . 95

Multi-cycle: DMA write . . . . . . . . . . . . . . . . . . 96

14.1.1

14.1.2

14.1.3

14.1.4

14.2

14.2.1

14.2.2

14.2.3

14.2.4

15

Package outline . . . . . . . . . . . . . . . . . . . . . . . . 97

16

Soldering of SMD packages . . . . . . . . . . . . . . 99

Introduction to soldering. . . . . . . . . . . . . . . . . 99

Wave and reﬂow soldering . . . . . . . . . . . . . . . 99

Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 99

Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . 100

16.1

16.2

16.3

16.4

17

17.1

Soldering of through-hole mount packages 101

Introduction to soldering through-hole

mount packages. . . . . . . . . . . . . . . . . . . . . . 101

Soldering by dipping or by solder wave . . . . 101

17.2

ISP1760_4

Product data sheet

Rev. 04 — 4 February 2008

109 of 110

ISP1760

NXP Semiconductors

Embedded Hi-Speed USB host controller

17.3

17.4

Manual soldering . . . . . . . . . . . . . . . . . . . . . 101

Package related soldering information . . . . . 102

Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . 102

References . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Revision history. . . . . . . . . . . . . . . . . . . . . . . 104

18

19

20

21

Legal information. . . . . . . . . . . . . . . . . . . . . . 105

Data sheet status . . . . . . . . . . . . . . . . . . . . . 105

Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . 105

21.1

21.2

21.3

21.4

22

23

24

25

Contact information. . . . . . . . . . . . . . . . . . . . 105

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 February 2008

Document identifier: ISP1760_4


型号：	ISP1760ET-T
厂家：	NXP
描述：	Hi-Speed Universal Serial Bus host controller for embedded applications - Application: printer, STB, DVD recorder, DTV, media player, PDA ; Bus interface: USB at HS (480 Mbit/s), FS (12 Mbit/s) and LS (1.5 Mbit/s) data rates ; Downstream ports: 3 ; Features: memory mapped CPU I/F to any 32-bit or16 bit I/F; Integrated patent-pending Transaction Translator supports single EHCI for HS, FS and LS transfers ; Operating/supply voltage (MAX.-Vcc,Vp,VDD): core 1.8 V; dual supply 3.0 V to 3.6 V, digital I/O I/F 1.65 V to 3.6 V V DVD 光电二极管电视
文件：	总111页 (文件大小：486K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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