J112 [NXP]

N-channel silicon field-effect transistors; N-沟道硅音响场效晶体管
J112
型号: J112
厂家: NXP    NXP
描述:

N-channel silicon field-effect transistors
N-沟道硅音响场效晶体管

晶体 晶体管
文件: 总6页 (文件大小:39K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DISCRETE SEMICONDUCTORS  
DATA SHEET  
J111; J112; J113  
N-channel silicon field-effect  
transistors  
July 1993  
Product specification  
File under Discrete Semiconductors, SC07  
Philips Semiconductors  
Product specification  
N-channel silicon field-effect transistors  
J111; J112; J113  
DESCRIPTION  
Symmetrical silicon n-channel  
junction FETs in plastic TO-92  
envelopes. They are intended for  
applications such as analog switches,  
choppers, commutators etc.  
FEATURES  
1
handbook, halfpage  
2
3
d
High speed switching  
g
s
Interchangeability of drain and  
MAM042  
source connections  
Low RDS on at zero gate voltage  
PINNING  
1 = gate  
Fig.1 Simplified outline and symbol, TO-92.  
2 = source  
3 = drain  
Note: Drain and source are  
interchangeable.  
QUICK REFERENCE DATA  
J111  
J112  
J113  
Drain-source voltage  
Drain current  
±VDS  
max.  
min.  
max.  
40  
40  
40  
V
VDS = 15 V; VGS = 0  
Total power dissipation  
up to Tamb = 50 °C  
IDSS  
20  
5
2
mA  
mW  
Ptot  
400  
400  
400  
Gate-source cut-off voltage  
min.  
max.  
3
10  
1
5
0.5  
3
V
V
VDS = 5 V; ID = 1 µA  
VGS off  
Drain-source on-state resistance  
VDS = 0.1 V; VGS = 0  
RDS on  
max.  
30  
50  
100  
July 1993  
2
Philips Semiconductors  
Product specification  
N-channel silicon field-effect transistors  
J111; J112; J113  
RATINGS  
Limiting values in accordance with the Absolute Maximum System (IEC 134)  
Drain-source voltage  
Gate-source voltage  
Gate-drain voltage  
±VDS  
VGSO  
VGDO  
IG  
max.  
max.  
max.  
max.  
40 V  
40 V  
40 V  
50 mA  
Gate forward current (DC)  
Total power dissipation  
up to Tamb = 50 °C  
Ptot  
Tstg  
Tj  
max.  
max.  
400 mW  
65 to + 150 °C  
150 °C  
Storage temperature range  
Junction temperature  
THERMAL RESISTANCE  
From junction to ambient in free air  
Rth j-a  
=
250 K/W  
STATIC CHARACTERISTICS  
Tj = 25 °C unless otherwise specified  
J111  
1
J112  
J113  
Gate reverse current  
VGS = 15 V; VDS = 0  
Drain cut-off current  
VDS = 5 V; VGS = 10 V  
Drain saturation current  
IGSS  
IDSX  
IDSS  
max.  
1
1
nA  
nA  
mA  
V
max.  
min.  
min.  
1
1
5
1
2
VDS = 15 V; VGS = 0  
20  
40  
Gate-source breakdown voltage  
IG = 1 µA; VDS = 0  
V(BR)GSS  
VGS off  
RDSon  
40  
40  
Gate-source cut-off voltage  
min.  
3
1
5
0.5  
3
V
V
V
DS = 5 V; ID = 1 µA  
max.  
10  
Drain-source on-state resistance  
DS = 0.1 V; VGS = 0  
V
max.  
30  
50  
100  
July 1993  
3
Philips Semiconductors  
Product specification  
N-channel silicon field-effect transistors  
J111; J112; J113  
DYNAMIC CHARACTERISTICS  
Tj = 25 °C unless otherwise specified  
Input capacitance  
V
DS = 0; VGS = 10 V; f = 1 MHz  
Cis  
Cis  
typ.  
6 pF  
22 pF  
28 pF  
typ.  
VDS = VGS = 0; f = 1 MHz  
max.  
Feedback capacitance  
VDS = 0; VGS = 10 V; f = 1 MHz  
Crs  
typ.  
3 pF  
Switching times  
test conditions  
VDD = 10 V; VGS = 0 to VGSoff  
VGS off = 12 V; RL = 750 for J111  
VGS off = 7 V; RL = 1550 for J112  
VGS off = 5 V; RL = 3150 for J113  
Rise time  
tr  
typ.  
typ.  
typ.  
typ.  
6 ns  
13 ns  
15 ns  
35 ns  
Turn-on time  
ton  
tf  
Fall time  
Turn-off time  
toff  
V
V
= 0 V  
GS  
10%  
90%  
1 µF  
k, halfpage  
50 Ω  
10 µF  
V
i
DD  
10 nF  
R
L
V
GS off  
t
t
off  
on  
SAMPLING  
SCOPE  
50 Ω  
DUT  
t
t
f
r
90%  
10%  
50 Ω  
V
o
MBK289  
MBK288  
Fig.2 Switching times test circuit.  
Fig.3 Input and output waveforms.  
July 1993  
4
Philips Semiconductors  
Product specification  
N-channel silicon field-effect transistors  
J111; J112; J113  
PACKAGE OUTLINE  
Plastic single-ended leaded (through hole) package; 3 leads  
SOT54  
c
E
d
A
L
b
1
2
e
1
e
D
3
b
1
L
1
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
UNIT  
A
b
b
c
D
d
E
e
e
L
L
1
1
1
5.2  
5.0  
0.48  
0.40  
0.66  
0.56  
0.45  
0.40  
4.8  
4.4  
1.7  
1.4  
4.2  
3.6  
14.5  
12.7  
mm  
2.54  
1.27  
2.5  
Note  
1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
EIAJ  
97-02-28  
SOT54  
TO-92  
SC-43  
July 1993  
5
Philips Semiconductors  
Product specification  
N-channel silicon field-effect transistors  
J111; J112; J113  
DEFINITIONS  
Data sheet status  
Objective specification  
Preliminary specification  
Product specification  
Short-form specification  
This data sheet contains target or goal specifications for product development.  
This data sheet contains preliminary data; supplementary data may be published later.  
This data sheet contains final product specifications.  
The data in this specification is extracted from a full data sheet with the same type  
number and title. For detailed information see the relevant data sheet or data handbook.  
Limiting values  
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or  
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation  
of the device at these or at any other conditions above those given in the Characteristics sections of the specification  
is not implied. Exposure to limiting values for extended periods may affect device reliability.  
Application information  
Where application information is given, it is advisory and does not form part of the specification.  
LIFE SUPPORT APPLICATIONS  
These products are not designed for use in life support appliances, devices, or systems where malfunction of these  
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for  
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such  
improper use or sale.  
July 1993  
6

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