K32L2B3X [NXP]
K32 L2B Microcontroller;
| 型号： | K32L2B3X |
| 厂家： | 
NXP |
| 描述： | K32 L2B Microcontroller 微控制器 |
| 文件： | 总112页 (文件大小：1427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
K32L2B3x
Data Sheet: Technical Data
Rev. 3, 09/2020
K32 L2B Microcontroller
K32L2B31Vxx0A
K32L2B21Vxx0A
K32L2B11Vxx0A
48 MHz Arm® Cortex®-M0+ and 64/128/256 KB Flash
The K32 L2B series is optimized for cost-sensitive and battery-
powered applications requiring low-power USB connectivity and
an optional segment LCD (SLCD). The product offers:
• Optional low power segment LCD up to 24x8 or 28x4
• USB FS 2.0 device without requiring an external crystal
• Embedded ROM with boot loader for flexible program
upgrade
32 QFN
5x5 mm P 0.5 mm
48 QFN
7x7 mm P 0.5 mm
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
• Down to 54 uA/MHz in very low power run mode and 1.96
uA in deep sleep mode (RAM + RTC retained)
64 LQFP
10x10 mm P 0.5 mm
64 BGA
5x5 mm P 0.5 mm
Core Processor
Peripherals
• Arm® Cortex®-M0+ core up to 48 MHz
• SLCD supporting up to 24x8 or 28x4 segments
• USB full-speed 2.0 device controller supporting
crystal-less operation
Memories
• 64/128/256 KB program flash memory
• 32 KB SRAM
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
• 16 KB ROM with build-in bootloader
• 32-byte backup register
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1
Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of
additional UART, SPI, I2C, PWM and other serial
modules, etc.
• One 16-bit 461 ksps ADC module with high
accuracy internal voltage reference (Vref) and up to
16 channels
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
• One 12-bit DAC
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin Serial Wire Debug (SWD) programming and
debug interface
• Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller
Clocks
• 48 MHz high accuracy (up to 0.5%) internal reference
clock
• 1.2 V internal voltage reference
• 8 MHz/2 MHz high accuracy (up to 3%) internal
reference clock
• 1 KHz reference clock active under all low-power
modes (except VLLS0)
I/O
• Up to 50 general-purpose input/output pins (GPIO)
and 6 high-drive pad
• 32–40 KHz and 3–32 MHz crystal oscillator
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Operating Characteristics
Timers
• One 6-channel Timer/PWM module
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
Packages
• 64 LQFP 10mm x 10mm, 0.5 mm pitch, 1.6 mm
thickness
• 64 MAPBGA 5mm x 5mm, 0.5 mm pitch, 1.23 mm
thickness
• 48 QFN 7mm x 7mm, 0.5 mm pitch, 0.65 mm thickness
• 32 QFN 5mm x 5mm, 0.5 mm pitch, 0.65 mm thickness
Security and Integrity
• 80-bit unique identification number per chip
• Advanced flash security
Low Power
• Down to 54 μA/MHz in very low power run mode
• Down to 1.96 μA in VLLS3 mode (RAM + RTC
retained)
• Six flexible static modes
Related Resources
Type
Selector
Description
Resource
Selector Guide
The NXP Selector Guide is a web-based tool that features interactive
application wizards and a dynamic product selector.
Guide
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K32L2B3xRM1
This document.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
Chip Errata
The chip mask set Errata provides additional or corrective information for K32L2B_1N71K1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
64-LQFP: 98ASS23234W, 64-
MAPBGA: 98ASA00420D, 32-
QFN: 98ASA00615D, 48-QFN:
98ASA00616D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
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K32 L2B Microcontroller, Rev. 3, 09/2020
NXP Semiconductors
Table of Contents
1
2
Ordering information............................................................4
4.4.7
Human-machine interfaces (HMI)..................42
Overview............................................................................. 4
2.1 System features...........................................................5
4.5 K32 L2B LQFP and MAPBGA pinouts.........................43
4.6 K32 L2B QFN Pinouts..................................................45
4.7 Package dimensions....................................................47
Electrical characteristics......................................................54
5.1 Ratings.........................................................................54
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
Arm Cortex-M0+ core.................................... 5
NVIC.............................................................. 6
AWIC............................................................. 6
Memory..........................................................7
Reset and boot.............................................. 7
Clock options................................................. 9
Security..........................................................12
Power management.......................................12
LLWU.............................................................14
5
5.1.1
5.1.2
5.1.3
5.1.4
Thermal handling ratings............................... 54
Moisture handling ratings...............................55
ESD handling ratings.....................................55
Voltage and current operating ratings............55
5.2 General........................................................................ 56
5.2.1
5.2.2
5.2.3
5.2.4
AC electrical characteristics...........................56
Nonswitching electrical specifications............56
Switching specifications.................................71
Thermal specifications...................................72
2.1.10 Debug controller............................................ 15
2.1.11 COP...............................................................15
2.2 Peripheral features.......................................................16
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
Segment LCD (SLCD)................................... 16
BME...............................................................16
DMA and DMAMUX.......................................16
TPM............................................................... 17
ADC............................................................... 18
VREF............................................................. 19
CMP...............................................................19
DAC............................................................... 20
RTC............................................................... 20
5.3 Peripheral operating requirements and behaviors.......73
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
Core modules................................................ 73
System modules............................................ 75
Clock modules............................................... 75
Memories and memory interfaces................. 78
Security and integrity modules.......................80
Analog............................................................80
5.4 Timers..........................................................................91
5.5 Communication interfaces........................................... 91
2.2.10 PIT................................................................. 20
2.2.11 LPTMR...........................................................21
2.2.12 UART.............................................................21
2.2.13 LPUART.........................................................22
2.2.14 SPI.................................................................23
2.2.15 I2C................................................................. 23
2.2.16 USB............................................................... 24
2.2.17 FlexIO............................................................ 24
2.2.18 Port control and GPIO................................... 25
Memory map....................................................................... 26
Pinouts................................................................................ 27
4.1 K32 L2B Signal Multiplexing and Pin Assignments
(LQFP and MAPBGA)..................................................27
4.2 K32 L2B Signal Multiplexing and Pin Assignments
(QFN)...........................................................................30
4.3 Pin properties...............................................................32
4.4 Module Signal Description Tables............................... 37
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
USB electrical specifications..........................91
USB VREG electrical specifications.............. 92
SPI switching specifications...........................92
I2C................................................................. 97
UART.............................................................98
5.6 Human-machine interfaces (HMI)................................99
5.6.1 LCD electrical characteristics........................ 99
6
Design considerations.........................................................100
6.1 Hardware design considerations..................................100
3
4
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Printed circuit board recommendations......... 100
Power delivery system...................................101
Analog design................................................102
Digital design................................................. 102
Crystal oscillator............................................ 105
6.2 Software considerations...............................................107
Part identification.................................................................107
7.1 Description...................................................................107
7.2 Format..........................................................................108
7.3 Fields........................................................................... 108
7.4 Example.......................................................................108
Small package marking.......................................................109
Package marking information..............................................109
7
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
Core modules................................................ 37
System modules............................................ 37
Clock modules............................................... 38
Analog............................................................38
Timer Modules...............................................39
Communication interfaces............................. 40
8
9
10 Revision History.................................................................. 110
K32 L2B Microcontroller, Rev. 3, 09/2020
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NXP Semiconductors
Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Memory
Package
IO and ADC channel
Serial
Interface
Part number
Flash
(KB)
SRAM
(KB)
Pin
count
Package
GPIOs
GPIOs
ADC
channels
(SE/DP)
SLCD
(INT/HD)1
K32L2B31VLH0A
K32L2B31VMP0A
K32L2B31VFT0A
K32L2B31VFM0A
K32L2B21VLH0A
K32L2B21VMP0A
K32L2B21VFT0A
K32L2B21VFM0A
K32L2B11VLH0A
K32L2B11VMP0A
K32L2B11VFT0A
K32L2B11VFM0A
256
256
256
256
128
128
128
128
64
32
32
32
32
32
32
32
32
32
32
32
32
64
64
48
32
64
64
48
32
64
64
48
32
LQFP
MAPBGA
QFN
50
50
36
23
50
50
36
23
50
50
36
23
31/6
31/6
24/6
19/6
31/6
31/6
24/6
19/6
31/6
31/6
24/6
19/6
16/2
16/2
14/1
7/0
Yes
Yes
—
QFN
—
LQFP
MAPBGA
QFN
16/2
16/2
14/1
7/0
Yes
Yes
—
QFN
—
LQFP
MAPBGA
QFN
16/2
16/2
14/1
7/0
Yes
Yes
—
64
64
64
QFN
—
1. INT: interrupt pin numbers; HD: high drive pin numbers
2 Overview
The following figure shows the system diagram of this device
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NXP Semiconductors
Overview
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
Slave
Master
Cortex M0+
IOPORT
ADC(16-bit 16-ch)
CMP
64/128/256 KB
Flash
M0
FMC
Debug
(SWD)
CM0+ core
1.2V Voltage reference
TPM0(6-channel)
TPM1(2-channel)
TPM2(2-channel)
S0
S1
NVIC
16 KB ROM
LPTMR
PIT
M2
RTC
DMA
MUX
DMA
32 KB RAM
LPUART0
LPUART1
UART2
SPI0
S2
M3
SPI1
BME
USB FS Device Only
I2C0
I2C1
FlexIO
Watchdog(COP)
MCG-Lite
Register File(32 Bytes)
LLWU
RCM
SMC
PMC
HIRC48M
LIRC2M/8M
OSC
SLCD
Figure 1. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
2.1 System features
The following sections describe the high-level system features.
K32 L2B Microcontroller, Rev. 3, 09/2020
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NXP Semiconductors
Overview
2.1.1 Arm Cortex-M0+ core
The enhanced Arm Cortex M0+ is the member of the Cortex-M series of processors
targeting microcontroller cores focused on very cost sensitive, low power applications.
It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC component. It
also has hardware debug functionality including support for simple program trace
capability. The processor supports the ARMv6-M instruction set (Thumb) architecture
including all but three 16-bit Thumb opcodes (52 total) plus seven 32-bit instructions. It
is upward compatible with other Cortex-M profile processors.
2.1.2 NVIC
The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority
levels for interrupts. In the NVIC, each source in the IPR registers contains two bits. It
also differs in number of interrupt sources and supports 32 interrupt vectors.
The Cortex-M family uses a number of methods to improve interrupt latency to up to 15
clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait and
VLPW modes.
2.1.3 AWIC
The asynchronous wake-up interrupt controller (AWIC) is used to detect asynchronous
wake-up events in Stop mode and signal to clock control logic to resume system
clocking. After clock restarts, the NVIC observes the pending interrupt and performs
the normal interrupt or event processing. The AWIC can be used to wake MCU core
from Stop and VLPS modes.
Wake-up sources are listed as below:
Table 2. AWIC stop wake-up sources
Wake-up source
Available system resets
Low-voltage detect
Low-voltage warning
Pin interrupts
ADC
Description
RESET pin when LPO is its clock source
Power management controller—functional in Stop mode
Power management controller—functional in Stop mode
Port control module—any enabled pin interrupt is capable of waking the system
The ADC is functional when using internal clock source or external crystal clock
Interrupt in normal or trigger mode
CMP0
I2Cx
Address match wakeup
Table continues on the next page...
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K32 L2B Microcontroller, Rev. 3, 09/2020
NXP Semiconductors
Overview
Table 2. AWIC stop wake-up sources (continued)
Wake-up source
Description
Any enabled interrupt can be a source as long as the module remains clocked
Active edge on RXD
LPUART0 , LPUART1
UART2
RTC
Alarm or seconds interrupt
NMI
NMI pin
TPMx
LPTMR
SPIx
Any enabled interrupt can be a source as long as the module remains clocked
Any enabled interrupt can be a source as long as the module remains clocked
Slave mode interrupt
FlexIO
Any enabled interrupt can be a source as long as the module remains clocked
2.1.4 Memory
This device has the following features:
• 32 KB of embedded RAM accessible (read/write) at CPU clock speed with 0 wait
states.
• The non-volatile memory is divided into two arrays
• Up to 256 KB of embedded program memory
• 16 KB ROM (built-in bootloader to support UART, I2C, USB, and SPI
interfaces)
The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program
flash is 1 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
The security circuitry prevents unauthorized access to RAM or flash contents
from debug port.
• System register file
This device contains a 32-byte register file that is powered in all power modes.
Also, it retains contents during low power modes and is reset only during a
power-on reset.
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NXP Semiconductors
Overview
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device.
NOTE
In the following table, Y means the specific module, except
for the registers, bits or conditions mentioned in the footnote,
is reset by the corresponding Reset source. N means the
specific module is not reset by the corresponding Reset
source.
Table 3. Reset source
Reset
Descriptions
Modules
sources
PMC
SIM
SMC RCM LLWU Reset pin RTC LPTMR Others
is
negated
POR reset
Power-on reset (POR)
Y
Y1
N
Y
Y
Y2
Y
Y
N
Y
Y
Y
Y
Y
N
Y
Y
Y3
Y
N
N
Y
Y
N
Y
Y
Y
System resets Low-voltage detect (LVD)
Low leakage wakeup
(LLWU) reset
External pin reset
(RESET)
Y1
Y1
Y2
Y2
Y4
Y4
Y
Y
Y
Y
Y
N
N
N
N
Y
Y
Computer operating
properly (COP) watchdog
reset
Y5
Stop mode acknowledge
error (SACKERR)
Y1
Y2
Y4
Y5
Y
Y
N
N
Y
Software reset (SW)
Y1
Y1
Y1
Y1
Y2
Y2
Y2
Y2
Y4
Y4
Y4
Y4
Y5
Y5
Y5
Y5
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Lockup reset (LOCKUP)
MDM DAP system reset
Debug reset
Debug reset
1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
2. Except SIM_SOPT1
3. Only if RESET is used to wake from VLLS mode.
4. Except SMC_PMCTRL, SMC_STOPCTRL, SMC_PMSTAT
5. Except RCM_RPFC, RCM_RPFW, RCM_FM
The CM0+ core adds support for a programmable Vector Table Offset Register
(VTOR) to relocate the exception vector table after reset. This device supports booting
from:
• internal flash
• ROM
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Overview
The Flash Option (FOPT) register in the Flash Memory module (FTFA_FOPT) allows
the user to customize the operation of the MCU at boot time. The register contains
read-only bits that are loaded from the NVM's option byte in the flash configuration
field. Below is boot flow chart for this device.
POR or Reset
N
RCM[FORCEROM] =00
Y
N
FOPT[BOOTPIN_OPT]=0
Y
N
BOOTCFG0 pin=0
Y
N
FOPT[BOOTSRC
_SEL]=10/11
Y
Boot from ROM
Boot from Flash
Figure 2. Boot flow chart
The blank chip is default to boot from ROM and remaps the vector table to ROM base
address, otherwise, it remaps to flash address.
2.1.6 Clock options
This chip provides a wide range of sources to generate the internal clocks. These
sources include internal resistor capacitor (IRC) oscillators, external oscillators,
external clock sources, and ceramic resonators. These sources can be configured to
provide the required performance and optimize the power consumption.
The IRC oscillators include the high-speed internal resister capacitor (HIRC)
oscillator, the low-speed internal resister capacitor (LIRC) oscillator, and the low
power oscillator (LPO).
The HIRC oscillator generates a 48 MHz clock and synchronizes with the USB clock
in full speed mode to achieve the required accuracy.
The LIRC oscillator generates an 8 MHz or 2 MHz clock, and default to 8 MHz
system clock on reset. The LIRC oscillator cannot be used in any VLLS modes.
The LPO generates a 1 kHz clock and cannot be used in VLLS0 mode.
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NXP Semiconductors
Overview
The system oscillator supports low frequency crystals (32 kHz to 40 kHz), high
frequency crystals (3 MHz to 32 MHz), and ceramic resonators (3 MHz to 32 MHz). An
external clock source, DC to 48 MHz, can be used as the system clock through the
EXTAL0 pin. The external oscillator also supports a low speed external clock (32.768
kHz) on the RTC_CLKIN pin for use with the RTC.
For more details on the clock operations and configurations, see Reference Manual.
The following figure is a high level block diagram of the clock generation.
Multipurpose Clock
Generator Lite
System
Integration
IRC_TRIMs
MCGPCLK
MCGIRCLK
HIRC48M
USB
USB_EN
CG
LIRC_DIV2
LIRC
8MHz
8MHz/
2MHz
IRC
MCGOUTCLK
FCRDIV
OUTDIV1
OUTDIV4
CG
CG
Core/Platform/System clock
Bus/Flash clock
2MHz
IRCS
CLKS
System oscillator
EREFS0
OSCCLK
CG
EXTAL0
XTAL_CLK
OSC
OSCERCLK
ERCLK32K
OSC32KCLK
logic
XTAL0
RTC_CKLIN
OS32KSEL
RTCCLKOUTSEL
LPO
PMC logic
PMC
RTC
RTC_CLKOUT
1Hz
Counter logic
CG — Clock gate
Figure 3. Clock block diagram
In order to provide flexibility, many peripherals can select from multiple clock sources
for operation. This enables the peripheral to select a clock that will always be available
during operation in various operational modes.
The following table summarizes the clocks associated with each module.
Table 4. Module clocks
Module
Bus interface clock
Core modules
Table continues on the next page...
Internal clocks
I/O interface clocks
10
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Overview
Table 4. Module clocks (continued)
Module
Arm Cortex-M0+ core
NVIC
Bus interface clock
Platform clock
Internal clocks
I/O interface clocks
Core clock
—
—
Platform clock
—
—
DAP
Platform clock
SWD_CLK
System modules
DMA
DMA Mux
System clock
Bus clock
—
—
—
—
—
—
—
—
—
—
—
Port control
Bus clock
—
Crossbar Switch
Peripheral bridges
LLWU, PMC, SIM, RCM
Mode controller
MCM
Platform clock
System clock
Bus clock
—
Bus clock
LPO
—
Bus clock
Platform clock
Bus clock
—
COP watchdog
LPO, Bus Clock, MCGIRCLK,
OSCERCLK
Clocks
MCG_Lite
OSC
Bus clock
Bus clock
MCGOUTCLK, MCGPCLK,
MCGIRCLK, OSCERCLK,
ERCLK32K
—
—
OSCERCLK
Memory and memory interfaces
Flash Controller
Flash memory
Platform clock
Flash clock
Flash clock
—
—
—
Analog
ADC
CMP
Bus clock
Bus clock
Bus clock
OSCERCLK
—
—
—
—
—
Internal Voltage Reference
(VREF)
Timers
TPM
PIT
Bus clock
Bus clock
Bus clock
TPM clock
—
TPM_CLKIN0, TPM_CLKIN1
—
—
LPTMR
LPO, OSCERCLK,
MCGPCLK, ERCLK32K
RTC
Bus clock
ERCLK32K
RTC_CLKOUT, RTC_CLKIN
Communication interfaces
USB FS (Device Only)
System clock
USB FS clock
—
SPI0
SPI1
I2C0
I2C1
Bus clock
—
—
—
—
SPI0_SCK
SPI1_SCK
I2C0_SCL
I2C1_SCL
System clock
System Clock
System Clock
Table continues on the next page...
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Overview
Table 4. Module clocks (continued)
Module
Bus interface clock
Internal clocks
LPUART0 clock
LPUART1 clock
—
I/O interface clocks
LPUART0, LPUART1
Bus clock
—
UART2
FlexIO
Bus clock
Bus clock
—
—
FlexIO clock
Human-machine interfaces
Platform clock
GPIO
—
—
2.1.7 Security
Security state can be enabled via programming flash configuration field (0x40e). After
enabling device security, the SWD port cannot access the memory resources of the
MCU, and ROM boot loader is also limited to access flash and not allowed to read out
flash information via ROM boot loader commands.
Access interface
Secure state
Unsecure operation
SWD port
Cannot access memory source by SWD The debugger can write to the Flash
interface
Mass Erase in Progress field of the
MDM-AP Control register to trigger a
mass erase (Erase All Blocks)
command
ROM boot loader Interface
(UART/I2C/SPI/USB)
Limit access to the flash, cannot read
out flash content
Send “FlashEraseAllUnsecureh"
command or attempt to unlock flash
security using the backdoor key
This device features 80-bit unique identification number, which is programmed in
factory and loaded to SIM register after power-on reset.
2.1.8 Power management
The Power Management Controller (PMC) expands upon Arm’s operational modes of
Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can
be used to optimize current consumption for a wide range of applications. The WFI or
WFE instruction invokes a Wait or a Stop mode, depending on the current
configuration. For more information on Arm’s operational modes, See the Arm®
Cortex User Guide.
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Overview
The PMC provides Run (Run), and Very Low Power Run (VLPR) configurations in
Arm’s Run operation mode. In these modes, the MCU core is active and can access all
peripherals. The difference between the modes is the maximum clock frequency of the
system and therefore the power consumption. The configuration that matches the
power versus performance requirements of the application can be selected.
The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in
Arm’s Sleep operation mode. In these modes, even though the MCU core is inactive,
all of the peripherals can be enabled and operate as programmed. The difference
between the modes is the maximum clock frequency of the system and therefore the
power consumption.
The PMC provides Stop (Stop), Very Low Power Stop (VLPS), Low Leakage Stop
(LLS), and Very Low Leakage Stop (VLLS) configurations in Arm’s Deep Sleep
operational mode. In these modes, the MCU core and most of the peripherals are
disabled. Depending on the requirements of the application, different portions of the
analog, logic, and memory can be retained or disabled to conserve power.
The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up
Interrupt Controller (AWIC), and the Low Leakage Wake-Up Controller (LLWU) are
used to wake up the MCU from low power states. The NVIC is used to wake up the
MCU core from WAIT and VLPW modes. The AWIC is used to wake up the MCU
core from STOP and VLPS modes. The LLWU is used to wake up the MCU core
from LLS and VLLSx modes.
For additional information regarding operational modes, power management, the
NVIC, AWIC, or the LLWU, please refer to the Reference Manual.
The following table provides information about the state of the peripherals in the
various operational modes and the modules that can wake MCU from low power
modes.
Table 6. Peripherals states in different operational modes
Core mode
Device mode
Descriptions
Run mode
Run
In Run mode, all device modules are operational.
Very Low Power Run
In VLPR mode, all device modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled.
Sleep mode
Wait
In Wait mode, all peripheral modules are operational. The MCU core is
placed into Sleep mode.
Very Low Power Wait
In VLPW mode, all peripheral modules are operational at a reduced
frequency except the Low Voltage Detect (LVD) monitor, which is disabled.
The MCU core is placed into Sleep mode.
Table continues on the next page...
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Table 6. Peripherals states in different operational modes (continued)
Core mode
Deep sleep
Device mode
Descriptions
Stop
In Stop mode, most peripheral clocks are disabled and placed in a static
state. Stop mode retains all registers and SRAMs while maintaining Low
Voltage Detection protection. In Stop mode, the ADC, CMP, LPTMR, RTC,
and pin interrupts are operational. The NVIC is disabled, but the AWIC can
be used to wake up from an interrupt.
Very Low Power Stop
Low Leakage Stop
In VLPS mode, the contents of the SRAM are retained. The CMP (low
speed), ADC, OSC, RTC, LPTMR, TPM, FlexIO, LPUART, USB, and DMA
are operational, LVD and NVIC are disabled, AWIC is used to wake up from
interrupt.
In LLS mode, the contents of the SRAM and the 32-byte system register file
are retained. The CMP (low speed), LLWU, LPTMR, and RTC are
operational. The ADC, DMA, FlexIO, I2C, LPUART, MCG-Lite, NVIC, PIT,
SPI, TPM, UART, USB, and COP are static, but retain their programming.
The GPIO, and VREF are static, retain their programming, and continue to
drive their previous values.
Very Low Leakage Stop In VLLS modes, most peripherals are powered off and will resume operation
from their reset state when the device wakes up. The LLWU, LPTMR, and
RTC are operational in all VLLS modes.
In VLLS3, the contents of the SRAM and the 32-byte system register file are
retained. The CMP (low speed), and PMC are operational. The GPIO, and
VREF are not operational but continue driving.
In VLLS1, the contents of the 32-byte system register file are retained. The
CMP (low speed), and PMC are operational. The GPIO, and VREF are not
operational but continue driving.
In VLLS0, the contents of the 32-byte system register file are retained. The
PMC is operational. The GPIO is not operational but continues driving. The
POR detection circuit can be enabled or disabled.
2.1.9 LLWU
The LLWU module is used to wake MCU from low leakage power mode (LLS and
VLLSx) and functional only on entry into a low-leakage power mode. After recovery
from LLS, the LLWU is immediately disabled. After recovery from VLLSx, the LLWU
continues to detect wake-up events until the user has acknowledged the wake-up event.
This device uses 8 external wakeup pin inputs and 4 internal modules as wakeup
sources to the LLWU module.
The following is internal peripheral and external pin inputs as wakeup sources to the
LLWU module.
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Table 7. Wakeup source
LLWU pin
LLWU_P5
Module source or pin name
PTB0
PTC1
LLWU_P6
LLWU_P7
PTC3
LLWU_P8
PTC4
LLWU_P9
PTC5
LLWU_P10
LLWU_P14
LLWU_P15
LLWU_M0IF
LLWU_M1IF
LLWU_M2IF
LLWU_M3IF
LLWU_M4IF
LLWU_M5IF
LLWU_M6IF
LLWU_M7IF
PTC6
PTD4
PTD6
LPTMR0
CMP0
Reserved
Reserved
Reserved
RTC alarm
Reserved
RTC seconds
2.1.10 Debug controller
This device supports standard Arm 2-pin SWD debug port. It provides register and
memory accessibility from the external debugger interface, basic run/halt control plus
2 breakpoints and 2 watchpoints.
It also supports trace function with the Micro Trace Buffer (MTB), which provides a
simple execution trace capability for the Cortex-M0+ processor.
2.1.11 COP
The COP monitors internal system operation and forces a reset in case of failure. It
can run from bus clock, LPO, 8/2 MHz internal oscillator or external crystal oscillator.
Optional window mode can detect deviations in program flow or system frequency.
The COP has the following features:
• Support multiple clock input, 1 kHz clock(LPO), bus clock, 8/2 MHz internal
reference clock, external crystal oscillator
• Can work in Stop/VLPS and Debug mode
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• Configurable for short and long timeout values, the longest timeout is up to 262
seconds
• Support window mode
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip.
2.2.1 Segment LCD (SLCD)
The SLCD module is a CMOS charge pump voltage inverter that is designed for low-
voltage and low-power operation. SLCD is designed to generate the appropriate
waveforms to drive multiplexed numeric, alphanumeric, or custom segment LCD
panels. SLCD also has several timing and control settings that can be software
configured depending on the application's requirements. Timing and control consists of
registers and control logic for:
• LCD frame frequency
• Duty cycle selection
• Front plane/back plane selection and enabling
• Blink modes and frequency
• Operation in low-power modes
2.2.2 BME
The Bit Manipulation Engine (BME) provides hardware support for atomic read-
modify-write memory operations to the peripheral address space in Cortex-M0+ based
microcontrollers. It reduces up to 30% of the code size and up to 9% of the cycles for
bit-oriented operations to peripheral registers.
The BME supports unsigned bit field extract, load-and-set 1-bit, load-and-clear 1-bit,
bit field insert, logical AND/OR/XOR operations with byte, halfword or word-sized
data type.
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2.2.3 DMA and DMAMUX
The DMA controller module enables fast transfers of data, which provides an efficient
way to move blocks of data with minimal processor interaction. The DMA controller
in this device implements four channels which can be routed from up to 63 DMA
request sources through DMA MUX module. Some of the peripheral request sources
have asynchronous DMA capability which can be used to wake MCU from Stop
mode. The peripherals which have such capability include . The DMA channel 0 and
1 can be periodically triggered by PIT via DMA MUX.
Main features are listed below:
• Dual-address transfers via 32-bit master connection to the system bus and data
transfers in 8-, 16-, or 32-bit blocks
• Supports programmable source and destination address and transfer size, optional
modulo addressing from 16 bytes to 256 KB
• Automatic updates of source and destination addresses
• Auto-alignment feature for source or destination accesses allows block transfers
to occur at the optimal size based on the address, byte count,and programmed
size, which significantly improves the speed of block transfer
• Automatic single or double channel linking allows the current DMA channel to
automatically trigger a DMA request to the linked channels without CPU
intervention
For more information on asynchronous DMA, see AN4631.
2.2.4 TPM
This device contains three low power TPM modules (TPM). All TPM modules are
functional in Stop/VLPS mode if the clock source is enabled.
The TPM features include:
• TPM clock mode is selectable from external clock input, internal clock source,
external crystal input clock, MCGIRCLK clock or clocking from MCGFLLCLK
and MCGPLLCLK/2
• Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128
• TPM includes a 16-bit counter
• Includes 6 channels that can be configured for input capture, output compare,
edge-aligned PWM mode, or center-aligned PWM mode
• Support the generation of an interrupt and/or DMA request per channel or counter
overflow
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• Support selectable trigger input to optionally reset or cause the counter to start or
stop incrementing
• Support the generation of hardware triggers when the counter overflows and per
channel
2.2.5 ADC
This device contains one ADC module. This ADC module supports hardware triggers
from TPM, LPTMR, PIT, RTC, external trigger pin and CMP output. It supports
wakeup of MCU in low power mode when using internal clock source or external
crystal clock.
ADC module has the following features:
• Linear successive approximation algorithm with up to 16-bit resolution
• Up to four pairs of differential and 17 single-ended external analog inputs
• Support selectable 16-bit, 13-bit, 11-bit, and 9-bit differential output mode, or 16-
bit, 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Selectable clock source up to four
• Operation in low-power modes for lower noise
• Asynchronous clock source for lower noise operation with option to output the
clock
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function up to 32x
• Selectable voltage reference: external or alternate
• Self-calibration mode
2.2.5.1 Temperature sensor
This device integrates one temperature sensor internally connected to the input channel
of AD26, see for details of the linearity factor.
The sensor provides good linearity, but it has to be calibrated to gain good accuracy, see
also AN3031. We recommend to use internal reference voltage as ADC reference with
long sample time.
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2.2.6 VREF
The Voltage Reference (VREF) can supply an accurate voltage output (1.2V typically)
trimmed in 0.5 mV steps. It can be used in applications to provide a reference voltage
to external devices or used internally as a reference to analog peripherals such as the
ADC or CMP.
The VREF supports the following programmable buffer modes:
• Bandgap on only, used for stabilization and startup
• High power buffer mode
• Low-power buffer mode
• Buffer disabled
The VREF voltage output signal, bonded on VREFH for 48 QFN, 64 LQFP and 64
MAPBGA packages and on PTE30 for 32 QFN packages, can be used by both
internal and external peripherals in low and high power buffer mode. A 100 nF
capacitor must always be connected between this pin and VSSA if the VREF is used.
This capacitor must be as close to VREF_OUT pin as possible.
2.2.7 CMP
The device contains one high-speed comparator and two 8-input multiplexers for both
the inverting and non-inverting inputs of the comparator. Each CMP input channel
connects to both muxes.
The CMP includes one 6-bit DAC, which provides a selectable voltage reference for
various user application cases. Besides, the CMP also has several module-to-module
interconnects in order to facilitate ADC triggering, TPM triggering, and interfaces.
The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of
the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, digitally filtered
• External hysteresis can be used at the same time that the output filter is used for
internal functions
• Two software selectable performance levels: shorter propagation delay at the
expense of higher power and Low power with longer propagation delay
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• DMA transfer support
• Functional in all modes of operation except in VLLS0 mode
• The filter functions are not available in Stop, VLPS, LLS, or VLLSx modes
• Integrated 6-bit DAC with selectable supply reference source and can be power
down to conserve power
• Two 8-to-1 channel mux
2.2.8 DAC
The 12-bit Digital-to-Analog Converter (DAC) is a low-power, general-purpose DAC.
The output of the DAC can be placed on an external pin or set as one of the inputs to
the analog comparator, op-amps, or ADC.
The features of the DAC module include:
• On-chip programmable reference generator output. The voltage output range is
from 1⁄4096 Vin to Vin, and the step is 1⁄4096 Vin, where Vin is the input voltage.
• Vin can be selected from two reference sources.
• Static operation in Normal Stop mode.
• 2-word data buffer supported with multiple operation modes.
• DMA support.
2.2.9 RTC
The RTC is an always powered-on block that remains active in all low power modes.
The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an
external crystal using the oscillator or clock directly from RTC_CLKIN pin.
RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all
RTC registers.
The RTC module has the following features
• 32-bit seconds counter with roll-over protection and 32-bit alarm
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
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2.2.10 PIT
The Periodic Interrupt Timer (PIT) is used to generate periodic interrupt to the CPU. It
has two independent channels and each channel has a 32-bit counter. Both channels
can be chained together to form a 64-bit counter.
Channel 0 can be used to periodically trigger DMA channel 0, and channel 1 can be
used to periodically trigger DMA channel 1. Either channel can be programmed as an
ADC trigger source, or TPM trigger source. Channel 0 can be programmed to trigger
DAC.
The PIT module has the following features:
• Each 32-bit timers is able to generate DMA trigger
• Each 32-bit timers is able to generate timeout interrupts
• Two timers can be cascaded to form a 64-bit timer
• Each timer can be programmed as ADC/TPM trigger source
• Timer 0 is able to trigger DAC
2.2.11 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with
optional prescaler, or as a pulse counter with optional glitch filter, across all power
modes, including the low-leakage modes. It can also continue operating through most
system reset events, allowing it to be used as a time of day counter.
The LPTMR module has the following features:
• 16-bit time counter or pulse counter with compare
• Optional interrupt can generate asynchronous wakeup from any low-power
mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
2.2.12 UART
This device contains a basic universal asynchronous receiver/transmitter (UART)
module with DMA function supported. Generally, this module is used in RS-232,
RS-485, and other communications. It also supports LIN slave operation and
ISO7816.
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The UART module has the following features:
• Full-duplex operation
• 13-bit baud rate selection with /32 fractional divide, based on the module clock
frequency
• Programmable 8-bit or 9-bit data format
• Programmable transmitter output polarity
• Programmable receive input polarity
• Up to 14-bit break character transmission.
• 11-bit break character detection option
• Two receiver wakeup methods with idle line or address mark wakeup
• Address match feature in the receiver to reduce address mark wakeup ISR overhead
• Ability to select MSB or LSB to be the first bit on wire
• Support for ISO 7816 protocol to interface with SIM cards and smart cards
• Receiver framing error detection
• Hardware parity generation and checking
• 1/16 bit-time noise detection
• DMA interface
2.2.13 LPUART
This product contains two Low-Power UART modules, both of their clock sources are
selectable from IRC48M, IRC8M/2M or external crystal clock, and can work in Stop
and VLPS modes. They also support 4x to 32x data oversampling rate to meet different
applications.
The LPUART module has the following features:
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4x to 32x
• Transmit and receive baud rate can operate asynchronous to the bus clock and can
be configured independently of the bus clock frequency, support operation in Stop
mode
• Interrupt, DMA or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
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• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
2.2.14 SPI
This device contains two SPI modules. SPI modules support 8-bit and 16-bit modes.
FIFO function is available only on SPI1 module.
The SPI modules have the following features:
• Full-duplex or single-wire bidirectional mode
• Programmable transmit bit rate
• Double-buffered transmit and receive data register
• Serial clock phase and polarity options
• Slave select output
• Mode fault error flag with CPU interrupt capability
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Programmable 8- or 16-bit data transmission length
• Receive data buffer hardware match feature
• 64-bit FIFO mode for high speed/large amounts of data transfers
• Support DMA
2.2.15 I2C
This device contains two I2C modules, which support up to 1 Mbits/s by dual buffer
features, and address match to wake MCU from the low power mode.
I2C modules support DMA transfer, and the interrupt condition can trigger DMA
request when DMA function is enabled.
The I2C modules have the following features:
• Support for system management bus (SMBus) specification, version 2
• Software programmable for one of 64 different serial clock frequencies
• Software-selectable acknowledge bit
• Arbitration-lost interrupt with automatic mode switching from master to slave
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• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated-START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Programmable input glitch filter
• Low power mode wakeup on slave address match
• Range slave address support
• DMA support
• Double buffering support to achieve higher baud rate
2.2.16 USB
This device contains one USB module which implements a USB2.0 full-speed
compliant peripheral and interfaces to the on-chip USBFS transceiver. It implements
keep-alive feature to avoid re-enumerating when exiting from low power modes and
enables HIRC48M to allow crystal-less USB operation.
The USBFS has the following features:
• USB 1.1 and 2.0 compliant full-speed device controller
• 16 bidirectional end points
• DMA or FIFO data stream interfaces
• Low-power consumption
• HIRC48 with clock-recovery is supported to eliminate the 48 MHz crystal. It is
used for USB device-only implementation.
• USB keeps alive in low power mode down to VLPS and is able to wake MCU from
low power mode
2.2.17 FlexIO
The FlexIO is a highly configurable module providing a wide range of protocols
including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform
generation. The module supports programmable baud rates independent of bus clock
frequency, with automatic start/stop bit generation.
The FlexIO module has the following features:
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• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using
remains enabled
• Four 32-bit double buffered shift registers with transmit, receive, and data match
modes, and continuous data transfer
• The timing of the shifter's shift, load and store events are controlled by the highly
flexible 16-bit timer assigned to the shifter
• Two or more shifters can be concatenated to support large data transfer sizes
• Each 16-bit timers operates independently, supports for reset, enable and disable
on a variety of internal or external trigger conditions with programmable trigger
polarity
• Flexible pin configuration supporting output disabled, open drain, bidirectional
output data and output mode
• Supports interrupt, DMA or polled transmit/receive operation
2.2.18 Port control and GPIO
The Port Control and Interrupt (PORT) module provides support for port control,
digital filtering, and external interrupt functions. The GPIO data direction and output
data registers control the direction and output data of each pin when the pin is
configured for the GPIO function. The GPIO input data register displays the logic
value on each pin when the pin is configured for any digital function, provided the
corresponding Port Control and Interrupt module for that pin is enabled.
The PORT module has the following features:
• all PIN support interrupt enable
• Configurable edge (rising, falling, or both) or level sensitive interrupt type
• Support DMA request
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable fast and slow slew rates on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
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Memory map
• Port Data Direction register
• GPIO support single-cycle access via fast GPIO.
3 Memory map
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. The following figure shows the system memory and
peripheral locations
0x4000_0000
0x4000_8000
0x4000_F000
0x4002_0000
0x4002_1000
0x4003_7000
0x4003_8000
0x4003_9000
0x4003_A000
0x4003_B000
0x4003_D000
0x4003_F000
0x4004_0000
Reserved
DMA controller
GPIO Controller (alias to 0x400F_F000)
Flash memory
DMA Channel Multiplexer
PIT
0x0000_0000
Flash
ROM
LPTPM0
LPTPM1
LPTPM2
ADC0
0x0000_0000
0x07FF_FFFF
0x1C00_0000
Code space
Boot ROM
0x07FF_FFFF
0x1C00_0000
RTC
DAC
0x1C00_3FFF
0x1C00_4000
0x1FFF_E000
LPTMR
System register file
SIM low power logic
SIM
0x4004_1000
0x4004_7000
0x1FFF_E000
0x2000_0000
Data Space
Reserved
SRAM_L
SRAM_U
0x4004_8000
0x4004_9000
0x4004_A000
0x4004_B000
0x4004_C000
0x4004_D000
0x4005_3000
0x4005_4000
0x4005_5000
0x4005_F000
0x4006_4000
0x4006_5000
0x4006_6000
0x4006_7000
0x4006_C000
0x4007_2000
0x4007_3000
0x4007_4000
0x4007_6000
0x4007_7000
PORTA
PORTB
PORTC
PORTD
PORTE
SLCD
0x2000_5FFF
0x4000_0000
0x2000_5FFF
0x4000_0000
0x4007_FFFF
Public
peripheral
AIPS
peripherals
0x400F_F000
LPUART0
LPUART1
FlexIO
Reserved
0x4400_0000
0x6000_0000
0x400F_F000
0x400F_FFFF
BME
GPIO
Reserved
0xE000_0000
MCG Lite
OSC
Private
peripheral
Reserved
MTB
0xE010_0000
I2C0
I2C1
MTBDWT
UART2
USB
ROM Table
Others
CMP
MCM
VREF
SPI0
Reserved
IOPORT
0xFFFF_FFFF
SPI1
0x4007_C000
0x4007_D000
0x4007_E000
0x4007_F000
0x400F_F000
LLWU
PMC
SMC
RCM
GPIO
Figure 4. Memory map
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Pinouts
4 Pinouts
4.1 K32 L2B Signal Multiplexing and Pin Assignments (LQFP
and MAPBGA)
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
VREFH can act as VREF_OUT when VREFV1 module is
enabled.
NOTE
When FTFA_FOPT[RESET_PIN_CONFIG]=0, the PTA20
pin acts as RESET_B function only during the POR. After
POR, this pin cannot be used as the RESET function. Then,
writing to PORTA_PCR20[MUX]=0x1, the PTA20 pin will
act as GPIO function (with setting value of ALT1). When
FTFA_FOPT[RESET_PIN_CONFIG]=1, the PTA20 pin
acts as RESET_B and cannot switch to GPIO function
regardless of PORTA_PCR20[MUX]'s setting value.
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP
BGA
A1
1
PTE0
LCD_P48
LCD_P48
PTE0/
CLKOUT32K
SPI1_MISO
SPI1_MOSI
LPUART1_TX
LPUART1_RX
RTC_CLKOUT CMP0_OUT
SPI1_MISO
I2C1_SDA
I2C1_SCL
LCD_P48
LCD_P49
B1
—
2
3
4
5
6
7
8
9
PTE1
LCD_P49
VDD
LCD_P49
VDD
PTE1
VDD
C4
E1
D1
E2
D2
G1
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE20
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
LCD_P59/
ADC0_DP0/
ADC0_SE0
LCD_P59/
ADC0_DP0/
ADC0_SE0
PTE20
TPM1_CH0
LPUART0_TX
FXIO0_D4
LCD_P59
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64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP
BGA
F1
10
PTE21
LCD_P60/
LCD_P60/
PTE21
TPM1_CH1
LPUART0_RX
FXIO0_D5
LCD_P60
ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
G2
F2
11
12
PTE22
PTE23
ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
PTE22
PTE23
TPM2_CH0
TPM2_CH1
UART2_TX
UART2_RX
FXIO0_D6
FXIO0_D7
ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
F4
G4
G3
F3
H1
13
14
15
16
17
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
PTE29
CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29
PTE30
TPM0_CH2
TPM0_CH3
TPM_CLKIN0
TPM_CLKIN1
H2
18
PTE30
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
LPUART1_TX
LPTMR0_
ALT1
H3
H4
H5
D3
D4
E5
D5
G5
F5
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
PTE31
PTE24
PTE25
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA12
PTA13
VDD
DISABLED
DISABLED
DISABLED
SWD_CLK
DISABLED
DISABLED
SWD_DIO
NMI_b
PTE31
PTE24
PTE25
PTA0
TPM0_CH4
TPM0_CH0
TPM0_CH1
TPM0_CH5
I2C0_SCL
I2C0_SDA
SWD_CLK
PTA1
LPUART0_RX TPM2_CH0
PTA2
LPUART0_TX
I2C1_SCL
TPM2_CH1
TPM0_CH0
TPM0_CH1
TPM0_CH2
TPM1_CH0
TPM1_CH1
PTA3
SWD_DIO
NMI_b
PTA4
I2C1_SDA
DISABLED
DISABLED
DISABLED
VDD
PTA5
USB_CLKIN
H6
G6
G7
H7
H8
G8
PTA12
PTA13
VDD
VSS
VSS
VSS
PTA18
PTA19
EXTAL0
EXTAL0
XTAL0
PTA18
PTA19
LPUART1_RX TPM_CLKIN0
XTAL0
LPUART1_TX
TPM_CLKIN1
LPTMR0_
ALT1
F8
F7
34
35
PTA20
RESET_b
PTB0/
LLWU_P5
LCD_P0/
ADC0_SE8
LCD_P0/
ADC0_SE8
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
SPI1_MOSI
TPM1_CH0
TPM1_CH1
TPM2_CH0
TPM2_CH1
LCD_P0
LCD_P1
LCD_P2
LCD_P3
LCD_P12
F6
E7
E8
E6
36
37
38
39
PTB1
PTB2
PTB3
PTB16
LCD_P1/
ADC0_SE9
LCD_P1/
ADC0_SE9
PTB1
PTB2
PTB3
PTB16
LCD_P2/
ADC0_SE12
LCD_P2/
ADC0_SE12
LCD_P3/
ADC0_SE13
LCD_P3/
ADC0_SE13
LCD_P12
LCD_P12
LPUART0_RX TPM_CLKIN0
SPI1_MISO
28
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQFP
BGA
D7
D6
C7
D8
40
41
42
43
PTB17
LCD_P13
LCD_P14
LCD_P15
LCD_P13
LCD_P14
LCD_P15
PTB17
SPI1_MISO
LPUART0_TX
TPM2_CH0
TPM2_CH1
EXTRG_IN
TPM_CLKIN1
SPI1_MOSI
LCD_P13
PTB18
PTB19
PTC0
PTB18
PTB19
PTC0
LCD_P14
LCD_P15
LCD_P20
LCD_P20/
ADC0_SE14
LCD_P20/
ADC0_SE14
audioUSB_
SOF_OUT
CMP0_OUT
C6
44
PTC1/
LCD_P21/
LCD_P21/
PTC1/
I2C1_SCL
TPM0_CH0
LCD_P21
LLWU_P6/
RTC_CLKIN
ADC0_SE15
ADC0_SE15
LLWU_P6/
RTC_CLKIN
B7
C8
45
46
PTC2
LCD_P22/
ADC0_SE11
LCD_P22/
ADC0_SE11
PTC2
I2C1_SDA
SPI1_SCK
TPM0_CH1
LCD_P22
LCD_P23
PTC3/
LCD_P23
LCD_P23
PTC3/
LPUART1_RX TPM0_CH2
CLKOUT
LLWU_P7
LLWU_P7
E3
E4
C5
A6
47
—
48
49
VSS
VDD
VLL3
VLL2
VSS
VDD
VLL3
VSS
VDD
VLL3
VLL2/
LCD_P4
VLL2/
LCD_P4
PTC20
PTC21
PTC22
PTC23
LCD_P4
LCD_P5
LCD_P6
LCD_P39
LCD_P24
LCD_P25
LCD_P26
LCD_P27
B5
B4
A5
B8
A8
A7
B6
50
51
52
53
54
55
56
VLL1
VLL1/
LCD_P5
VLL1/
LCD_P5
VCAP2
VCAP1
VCAP2/
LCD_P6
VCAP2/
LCD_P6
VCAP1/
LCD_P39
VCAP1/
LCD_P39
PTC4/
LLWU_P8
LCD_P24
LCD_P24
PTC4/
LLWU_P8
SPI0_SS
LPUART1_TX
TPM0_CH3
PTC5/
LLWU_P9
LCD_P25
LCD_P25
PTC5/
LLWU_P9
SPI0_SCK
SPI0_MOSI
SPI0_MISO
LPTMR0_
ALT2
CMP0_OUT
PTC6/
LLWU_P10
LCD_P26/
CMP0_IN0
LCD_P26/
CMP0_IN0
PTC6/
LLWU_P10
EXTRG_IN
SPI0_MISO
SPI0_MOSI
PTC7
LCD_P27/
CMP0_IN1
LCD_P27/
CMP0_IN1
PTC7
audioUSB_
SOF_OUT
C3
A4
57
58
PTD0
PTD1
LCD_P40
LCD_P40
PTD0
PTD1
SPI0_SS
TPM0_CH0
TPM0_CH1
FXIO0_D0
FXIO0_D1
LCD_P40
LCD_P41
LCD_P41/
LCD_P41/
SPI0_SCK
ADC0_SE5b
ADC0_SE5b
C2
B3
A3
59
60
61
PTD2
PTD3
LCD_P42
LCD_P43
LCD_P44
LCD_P42
LCD_P43
LCD_P44
PTD2
PTD3
SPI0_MOSI
SPI0_MISO
SPI1_SS
UART2_RX
UART2_TX
UART2_RX
TPM0_CH2
TPM0_CH3
TPM0_CH4
SPI0_MISO
SPI0_MOSI
FXIO0_D2
FXIO0_D3
FXIO0_D4
LCD_P42
LCD_P43
LCD_P44
PTD4/
PTD4/
LLWU_P14
LLWU_P14
C1
B2
A2
62
63
64
PTD5
LCD_P45/
ADC0_SE6b
LCD_P45/
ADC0_SE6b
PTD5
SPI1_SCK
SPI1_MOSI
SPI1_MISO
UART2_TX
TPM0_CH5
FXIO0_D5
FXIO0_D6
FXIO0_D7
LCD_P45
LCD_P46
LCD_P47
PTD6/
LLWU_P15
LCD_P46/
ADC0_SE7b
LCD_P46/
ADC0_SE7b
PTD6/
LLWU_P15
LPUART0_RX
LPUART0_TX
SPI1_MISO
SPI1_MOSI
PTD7
LCD_P47
LCD_P47
PTD7
K32 L2B Microcontroller, Rev. 3, 09/2020
29
NXP Semiconductors
Pinouts
4.2 K32 L2B Signal Multiplexing and Pin Assignments (QFN)
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
When FTFA_FOPT[RESET_PIN_CONFIG]=0, the PTA20
pin acts as RESET_B function only during the POR. After
POR, this pin cannot be used as the RESET function. Then,
writing to PORTA_PCR20[MUX]=0x1, the PTA20 pin will
act as GPIO function (with setting value of ALT1). When
FTFA_FOPT[RESET_PIN_CONFIG]=1, the PTA20 pin acts
as RESET_B and cannot switch to GPIO function regardless
of PORTA_PCR20[MUX]'s setting value.
32
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QFN
QFN
—
—
1
7
VDD
VDD
VDD
PTE20
ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
PTE20
TPM1_CH0
TPM1_CH1
LPUART0_TX
LPUART0_RX
FXIO0_D4
FXIO0_D5
—
8
PTE21
ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
PTE21
—
—
—
10
11
13
VREFH
VREFL
PTE29
VREFH
VREFL
VREFH
VREFL
CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29
TPM0_CH2
TPM_CLKIN0
—
—
—
—
—
—
—
15
16
29
30
31
32
33
PTE24
PTE25
PTB2
DISABLED
DISABLED
ADC0_SE12
ADC0_SE13
DISABLED
DISABLED
ADC0_SE14
PTE24
PTE25
PTB2
TPM0_CH0
TPM0_CH1
TPM2_CH0
TPM2_CH1
LPUART0_RX
LPUART0_TX
EXTRG_IN
I2C0_SCL
I2C0_SDA
ADC0_SE12
ADC0_SE13
I2C0_SCL
I2C0_SDA
SPI1_MOSI
SPI1_MISO
PTB3
PTB3
PTB16
PTB17
PTC0
PTB16
PTB17
PTC0
TPM_CLKIN0
TPM_CLKIN1
SPI1_MISO
SPI1_MOSI
CMP0_OUT
ADC0_SE14
ADC0_SE5b
audioUSB_
SOF_OUT
—
—
—
—
1
41
42
43
44
—
PTD0
PTD1
PTD2
PTD3
PTE0
DISABLED
ADC0_SE5b
DISABLED
DISABLED
DISABLED
PTD0
PTD1
PTD2
PTD3
SPI0_SS
TPM0_CH0
TPM0_CH1
TPM0_CH2
TPM0_CH3
FXIO0_D0
FXIO0_D1
FXIO0_D2
FXIO0_D3
I2C1_SDA
SPI0_SCK
SPI0_MOSI
SPI0_MISO
SPI1_MISO
UART2_RX
UART2_TX
LPUART1_TX
SPI0_MISO
SPI0_MOSI
PTE0/
RTC_CLKOUT CMP0_OUT
CLKOUT32K
2
2
VSS
VSS
VSS
30
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
32
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QFN
QFN
3
4
5
6
7
8
9
3
4
USB0_DP
USB0_DP
USB0_DM
VOUT33
VREGIN
VDDA
USB0_DP
USB0_DM
VOUT33
VREGIN
VDDA
USB0_DM
VOUT33
VREGIN
VDDA
5
6
9
12
14
VSSA
VSSA
VSSA
PTE30
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
PTE30
TPM0_CH3
TPM_CLKIN1
LPUART1_TX
LPTMR0_
ALT1
10
11
12
13
14
15
16
17
18
17
18
19
20
21
22
23
24
25
PTA0
PTA1
PTA2
PTA3
PTA4
VDD
SWD_CLK
DISABLED
DISABLED
SWD_DIO
NMI_b
PTA0
PTA1
PTA2
PTA3
PTA4
TPM0_CH5
TPM2_CH0
TPM2_CH1
TPM0_CH0
TPM0_CH1
SWD_CLK
LPUART0_RX
LPUART0_TX
I2C1_SCL
SWD_DIO
NMI_b
I2C1_SDA
VDD
VDD
VSS
VSS
VSS
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
LPUART1_RX
LPUART1_TX
TPM_CLKIN0
TPM_CLKIN1
LPTMR0_
ALT1
19
20
26
27
PTA20
RESET_b
PTB0/
LLWU_P5
ADC0_SE8
ADC0_SE8
PTB0/
LLWU_P5
I2C0_SCL
TPM1_CH0
TPM1_CH1
21
22
28
34
PTB1
ADC0_SE9
ADC0_SE9
PTB1
I2C0_SDA
I2C1_SCL
PTC1/
ADC0_SE15
ADC0_SE15
PTC1/
TPM0_CH0
LLWU_P6/
RTC_CLKIN
LLWU_P6/
RTC_CLKIN
23
24
35
36
PTC2
ADC0_SE11
DISABLED
ADC0_SE11
PTC2
I2C1_SDA
SPI1_SCK
TPM0_CH1
TPM0_CH2
PTC3/
LLWU_P7
PTC3/
LLWU_P7
LPUART1_RX
LPUART1_TX
CLKOUT
25
26
27
28
29
37
38
39
40
45
PTC4/
LLWU_P8
DISABLED
DISABLED
CMP0_IN0
CMP0_IN1
DISABLED
PTC4/
LLWU_P8
SPI0_SS
TPM0_CH3
PTC5/
LLWU_P9
PTC5/
LLWU_P9
SPI0_SCK
SPI0_MOSI
SPI0_MISO
SPI1_SS
LPTMR0_
ALT2
CMP0_OUT
FXIO0_D4
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
EXTRG_IN
SPI0_MISO
SPI0_MOSI
PTC7
PTC7
audioUSB_
SOF_OUT
PTD4/
LLWU_P14
PTD4/
LLWU_P14
UART2_RX
TPM0_CH4
TPM0_CH5
30
31
46
47
PTD5
ADC0_SE6b
ADC0_SE7b
ADC0_SE6b
ADC0_SE7b
PTD5
SPI1_SCK
UART2_TX
FXIO0_D5
FXIO0_D6
PTD6/
LLWU_P15
PTD6/
LLWU_P15
SPI1_MOSI
LPUART0_RX
SPI1_MISO
SPI1_MOSI
32
48
PTD7
DISABLED
PTD7
SPI1_MISO
LPUART0_TX
FXIO0_D7
K32 L2B Microcontroller, Rev. 3, 09/2020
31
NXP Semiconductors
Pinouts
4.3 Pin properties
The following table lists the pin properties of 64 LQFP/MAPBGA package.
1
2
A1
B1
—
PTE0
PTE1
ND
ND
—
Hi-Z
Hi-Z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PD
—
—
SS
SS
—
N
N
N
N
N
N
3
VDD
—
—
—
—
—
—
N
—
—
—
—
—
—
N
—
—
—
—
—
—
N
4
C4
E1
D1
E2
D2
G1
F1
G2
F2
F4
G4
G3
F3
H1
H2
H3
H4
H5
D3
D4
E5
VSS
—
—
—
5
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE20
PTE21
PTE22
PTE23
VDDA
—
—
—
6
—
—
—
7
—
—
—
8
—
—
—
9
ND
ND
ND
ND
—
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
SS
SS
SS
SS
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
N
N
N
N
N
N
N
N
N
—
—
—
—
N
—
—
—
—
N
—
—
—
—
N
VREFH
VREFL
VSSA
—
—
—
—
—
—
—
—
—
PTE29
PTE30
PTE31
PTE24
PTE25
PTA0
ND
ND
ND
ND
ND
ND
ND
ND
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
L
SS
SS
SS
SS
SS
SS
SS
SS
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
PTA1
Hi-Z
Hi-Z
N
N
Y
PTA2
N
N
Y
Table continues on the next page...
32
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Pinouts
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
D5
G5
F5
H6
G6
G7
H7
H8
G8
F8
F7
F6
E7
E8
E6
D7
D6
C7
D8
C6
PTA3
PTA4
ND
ND
ND
ND
ND
—
H
PU
PU
—
—
—
—
—
—
—
PU
—
—
—
—
—
—
—
—
—
—
FS
SS
SS
SS
SS
—
N
N
N
N
N
—
—
N
N
Y
N
N
N
N
N
—
—
N
N
Y
Y
Y
Y
Y
Y
—
—
Y
Y
Y
N
N
N
N
N
N
N
N
Y
Y
H
PTA5
Hi-Z
Hi-Z
Hi-Z
—
PTA12
PTA13
VDD
VSS
—
—
—
PTA18
PTA19
PTA20
PTB0/LLWU_P5
PTB1
ND
ND
ND
HD
HD
ND
ND
ND
ND
ND
ND
ND
ND
Hi-Z
Hi-Z
H
SS
SS
SS
SS
SS
SS
SS
FS
FS
SS
SS
SS
SS
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
PTB2
PTB3
PTB16
PTB17
PTB18
PTB19
PTC0
PTC1/LLWU_P6/
RTC_CLKIN
45
46
47
—
48
49
50
51
B7
C8
E3
E4
C5
A6
B5
B4
PTC2
PTC3/LLWU_P7
VSS
ND
HD
—
Hi-Z
Hi-Z
—
—
—
—
—
—
—
—
—
SS
FS
—
—
—
—
—
—
N
N
Y
N
N
Y
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD
—
—
VLL3
—
—
VLL2
—
—
VLL1
—
—
VCAP2
—
—
Table continues on the next page...
K32 L2B Microcontroller, Rev. 3, 09/2020
33
NXP Semiconductors
Pinouts
52
53
54
55
56
57
58
59
60
61
62
63
64
A5
B8
A8
A7
B6
C3
A4
C2
B3
A3
C1
B2
A2
VCAP1
PTC4/LLWU_P8
PTC5/LLWU_P9
PTC6/LLWU_P10
PTC7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
N
N
N
N
N
N
N
N
N
N
N
N
—
N
N
N
N
N
N
N
N
N
N
N
N
—
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
HD
ND
ND
ND
ND
ND
ND
ND
ND
ND
HD
HD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
FS
FS
FS
FS
SS
SS
SS
SS
FS
FS
FS
FS
PTD0
PTD1
PTD2
PTD3
PTD4/LLWU_P14
PTD5
PTD6/LLWU_P15
PTD7
The following table lists the pin properties of 32/48 QFN package.
—
1
VDD
—
—
—
—
—
—
—
Table continues on the next page...
34
NXP Semiconductors
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Pinouts
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
7
PTE20
PTE21
VREFH
VREFL
PTE29
PTE24
PTE25
PTB2
ND
ND
—
Hi-Z
Hi-Z
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PD
—
—
PU
SS
SS
—
N
N
N
N
N
N
—
—
N
N
N
N
S
8
10
11
13
15
16
29
30
31
32
33
41
42
43
44
—
2
—
—
N
—
—
N
—
—
—
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
ND
—
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
SS
SS
SS
SS
SS
FS
FS
SS
SS
SS
SS
SS
SS
—
N
N
N
N
N
N
PTB3
N
N
PTB16
PTB17
PTC0
N
N
N
N
Y
N
N
N
N
PTD0
N
N
Y
PTD1
N
N
Y
PTD2
N
N
Y
PTD3
N
N
Y
PTE0
N
N
N
—
—
—
—
—
—
—
N
Y
2
VSS
—
—
—
—
—
—
—
N
—
—
—
—
—
—
—
N
3
3
USB0_DP
USB0_DM
VOUT33
VREGIN
VDDA
VSSA
—
—
—
4
4
—
—
—
5
5
—
—
—
6
6
—
—
—
7
9
—
—
—
8
12
14
17
18
19
20
—
—
—
9
PTE30
PTA0
ND
ND
ND
ND
ND
Hi-Z
L
SS
SS
SS
SS
FS
10
11
12
13
N
N
PTA1
Hi-Z
Hi-Z
H
N
N
Y
PTA2
N
N
Y
PTA3
N
N
Y
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Pinouts
14
15
16
17
18
19
20
21
22
21
22
23
24
25
26
27
28
34
PTA4
VDD
ND
—
H
PU
—
—
—
—
PU
—
—
—
SS
—
N
—
—
N
N
Y
N
—
—
N
N
Y
Y
—
—
Y
—
VSS
—
—
—
PTA18
ND
ND
ND
HD
HD
ND
Hi-Z
Hi-Z
H
SS
SS
SS
SS
SS
SS
PTA19
Y
PTA20
Y
PTB0/LLWU_P5
PTB1
Hi-Z
Hi-Z
Hi-Z
N
N
N
N
N
N
N
N
Y
PTC1/LLWU_P6/
RTC_CLKIN
23
24
25
26
27
28
29
30
31
32
35
36
37
38
39
40
45
46
47
48
PTC2
ND
HD
HD
ND
ND
ND
ND
ND
HD
HD
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
—
—
—
—
—
—
—
—
—
—
SS
FS
FS
FS
FS
FS
FS
FS
FS
FS
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
PTC3/LLWU_P7
PTC4/LLWU_P8
PTC5/LLWU_P9
PTC6/LLWU_P10
PTC7
PTD4/LLWU_P14
PTD5
PTD6/LLWU_P15
PTD7
Properties
Abbreviation
Descriptions
Normal drive
High drive
Driver strength
ND
HD
Hi-Z
H
Default status after POR
High impendence
High level
L
Low level
Pullup/ pulldown setting
after POR
PD
PU
Pulldown
Pullup
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Pinouts
Properties
Abbreviation
Descriptions
Fast slew rate
Slow slew rate
Disabled
Slew rate after POR
FS
SS
N
Passive Pin Filter after
POR
Y
Enabled
Open drain
N
Disabled1
Enabled2
Y
Pin interrupt
Y
Yes
1. When I2C module is enabled and a pin is functional for I2C, this pin is (pseudo-) open drain enabled. When UART or
LPUART module is enabled and a pin is functional for UART or LPUART, this pin is (pseudo-) open drain
configurable.
2. PTA20 is a true open drain pin that must never be pulled above VDD.
4.4 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used
in the module's chapter. They also briefly describe the signal function and direction.
4.4.1 Core modules
Table 9. SWD signal descriptions
Chip signal name
Module signal
name
Description
I/O
SWD_DIO
SWD_DIO
SWD_CLK
Serial Wire Debug Data Input/Output
Input /
Output
The SWD_DIO pin is used by an external debug tool for
communication and device control. This pin is pulled up
internally.
SWD_CLK
Serial Wire Clock
Input
This pin is the clock for debug logic when in the Serial Wire
Debug mode. This pin is pulled down internally.
4.4.2 System modules
Table 10. System signal descriptions
Chip signal name
Module signal
Description
I/O
name
NMI
—
Non-maskable interrupt
I
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Pinouts
Table 10. System signal descriptions (continued)
Chip signal name
Module signal
name
Description
I/O
NOTE: Driving the NMI signal low forces a non-maskable
interrupt, if the NMI function is selected on the
corresponding pin.
RESET
VDD
—
—
—
Reset bidirectional signal
MCU power
I/O
I
I
VSS
MCU ground
Table 11. LLWU signal descriptions
Chip signal name
Module signal
Description
I/O
name
LLWU_Pn
LLWU_Pn
Wakeup inputs
I
4.4.3 Clock modules
Table 12. OSC signal descriptions
Chip signal name
Module signal
Description
I/O
name
EXTAL
XTAL
EXTAL0
XTAL0
External clock/Oscillator input
Oscillator output
I
O
4.4.4 Analog
This table presents the signal descriptions of the ADC0 module.
Table 13. ADC0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
ADC0_DPn
ADC0_DMn
ADC0_SEn
VREFH
DADP3–DADP0
Differential Analog Channel Inputs
I
I
I
I
I
I
I
DADM3–DADM0 Differential Analog Channel Inputs
ADn
VREFSH
VREFSL
VDDA
Single-Ended Analog Channel Inputs
Voltage Reference Select High
Voltage Reference Select Low
Analog Power Supply
VREFL
VDDA
VSSA
VSSA
Analog Ground
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Pinouts
Table 13. ADC0 signal descriptions (continued)
Chip signal name
Module signal
name
Description
I/O
EXTRG_IN
ADHWT
Hardware trigger
I
This table presents the signal descriptions of the CMP0 module.
Table 14. CMP0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
CMP0_IN[5:0]
CMP0_OUT
IN[5:0]
CMPO
Analog voltage inputs
Comparator output
I
O
Table 15. VREF signal descriptions
Chip signal name
Module signal
Description
I/O
name
VREF_OUT
VREF_OUT
Internally-generated voltage reference output
O
4.4.5 Timer Modules
Table 16. TPM0 signal descriptions
Chip signal name
Module signal
name
Description
I/O
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the
counter clock.
I
TPM0_CH[5:0]
EXTRG_IN
TPM_CHn
TPM channel (n = 5 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
I
ADHWT
Hardware trigger
Table 17. TPM1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the
counter clock.
I
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Pinouts
Table 17. TPM1 signal descriptions (continued)
Chip signal name
Module signal
name
Description
I/O
TPM1_CH[1:0]
TPM_CHn
TPM channel (n = 1 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
EXTRG_IN
ADHWT
Hardware trigger
I
Table 18. TPM2 signal descriptions
Chip signal name
Module signal
Description
I/O
name
TPM_CLKIN[1:0]
TPM_EXTCLK
External clock. TPM external clock can be selected to increment
the TPM counter on every rising edge synchronized to the counter
clock.
I
TPM2_CH[1:0]
EXTRG_IN
TPM_CHn
ADHWT
TPM channel (n = 1 to 0). A TPM channel pin is configured as
output when configured in an output compare or PWM mode and
the TPM counter is enabled, otherwise the TPM channel pin is an
input.
I/O
Hardware trigger
I
Table 19. LPTMR0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPTMR0_ALT[3:1]
LPTMR0_ALTn
Pulse Counter Input pin
I
Table 20. RTC signal descriptions
Chip signal name
Module signal
Description
I/O
name
RTC_CLKOUT1
RTC_CLKOUT
1 Hz square-wave output or OSCERCLK
O
1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL]
4.4.6 Communication interfaces
Table 21. USB FS Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
USB0_DM
USB0_DP
usb_dm
usb_dp
—
USB D- analog data signal on the USB bus.
USB D+ analog data signal on the USB bus.
Alternate USB clock input
I/O
I/O
I
USB_CLKIN
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Pinouts
Table 22. SPI0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
MISO
MOSI
SPSCK
SS
SPI0_MISO
SPI0_MOSI
SPI0_SCLK
SPI0_PCS0
Master Data In, Slave Data Out
Master Data Out, Slave Data In
SPI Serial Clock
I/O
I/O
I/O
I/O
Slave Select
Table 23. SPI1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
MISO
MOSI
SPSCK
SS
SPI1_MISO
SPI1_MOSI
SPI1_SCLK
SPI1_PCS0
Master Data In, Slave Data Out
Master Data Out, Slave Data In
SPI Serial Clock
I/O
I/O
I/O
I/O
Slave Select
Table 24. I2C0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
I2C0_SCL
I2C0_SDA
SCL
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the I2C system.
I/O
I/O
SDA
Table 25. I2C1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
I2C1_SCL
I2C1_SDA
SCL
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the I2C system.
I/O
I/O
SDA
Table 26. LPUART0 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPUART0_TX
LPUART0_RX
TxD
Transmit data
Receive data
I/O
I
RxD
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Pinouts
Table 27. LPUART1 signal descriptions
Chip signal name
Module signal
Description
I/O
name
LPUART1_TX
LPUART1_RX
TxD
Transmit data
Receive data
I/O
I
RxD
Table 28. UART2 signal descriptions
Chip signal name
Module signal
Description
I/O
name
UART2_TX
UART2_RX
TxD
Transmit data
Receive data
O
I
RxD
Table 29. FlexIO signal descriptions
Chip signal name
Module signal name
Description
I/O
FXIO0_Dx
FXIO_Dn (n=0...7)
Bidirectional FlexIO Shifter
and Timer pin inputs/outputs
I/O
I
EXTRG_IN
ADHWT
Hardware trigger
4.4.7 Human-machine interfaces (HMI)
Table 30. GPIO Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
PTA[20:0]
PTB[19:0]
PTD[7:0]
PTE[31:0]
PORTA20–PORTA0 General-purpose input/output
PORTB19–PORTB0 General-purpose input/output
PORTD7–PORTD0 General-purpose input/output
PORTE31–PORTE0 General-purpose input/output
I/O
I/O
I/O
I/O
Table 31. LCD Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
LCD_Pn
LCD_P[63:0] . 64 Configurable front plane/back plane driver that connects directly to
LCD front plane/back the display. LCD_P[63:0] can operate as GPIO pins
plane
O
VLL1, VLL2, VLL3
VLL1, VLL2, VLL3. LCD LCD bias voltages (requires external capacitors when charge
I/O
bias voltages
pump is used).
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Pinouts
Table 31. LCD Signal Descriptions (continued)
Chip signal name
Module signal
name
Description
I/O
Vcap1, Vcap2
Vcap1, Vcap2. LCD Charge pump capacitor pins.
O
charge pump
capacitance.
4.5 K32 L2B LQFP and MAPBGA pinouts
Figure below shows the 64 LQFP pinouts
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43
NXP Semiconductors
Pinouts
PTE0
PTE1
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VLL3
2
VSS
VDD
3
PTC3/LLWU_P7
VSS
4
PTC2
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE20
PTE21
PTE22
PTE23
VDDA
5
PTC1/LLWU_P6/RTC_CLKIN
6
PTC0
7
PTB19
PTB18
PTB17
PTB16
PTB3
8
9
10
11
12
13
14
15
16
PTB2
PTB1
VREFH
VREFL
VSSA
PTB0/LLWU_P5
PTA20
PTA19
Figure 5. 64 LQFP Pinout diagram
Figure below shows the 64 MAPBGA pinouts
44
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NXP Semiconductors
Pinouts
1
2
3
4
5
6
7
8
PTD4/
LLWU_P14
PTC6/
LLWU_P10
PTC5/
LLWU_P9
A
B
C
D
E
F
PTE0
PTD7
PTD1
VCAP1
VLL2
A
B
C
D
E
F
PTD6/
LLWU_P15
PTC4/
LLWU_P8
PTE1
PTD5
PTD3
PTD0
PTA0
VSS
VCAP2
VSS
VLL1
VLL3
PTA3
PTA2
PTA5
PTA4
PTC7
PTC2
PTB19
PTB17
PTB2
PTC1/
LLWU_P6/
RTC_CLKIN
PTC3/
LLWU_P7
PTD2
USB0_DM VREGIN
PTA1
PTB18
PTB16
PTB1
PTC0
PTB3
USB0_DP
PTE21
VOUT33
PTE23
PTE22
VDD
PTB0/
LLWU_P5
VSSA
VREFL
VDDA
VREFH
PTA20
PTA19
G
H
PTE20
PTA13
VDD
G
H
PTE29
1
PTE30
2
PTE31
3
PTE24
4
PTE25
5
PTA12
6
VSS
7
PTA18
8
Figure 6. 64 MAPBGA Pinout diagram
4.6 K32 L2B QFN Pinouts
The figure below shows the 32 QFN pinouts.
K32 L2B Microcontroller, Rev. 3, 09/2020
45
NXP Semiconductors
Pinouts
PTC3/LLWU_P7
PTE0
VSS
24
23
22
21
20
19
1
2
3
4
5
6
7
8
PTC2
PTC1/LLWU_P6/RTC_CLKIN
USB0_DP
USB0_DM
VOUT33
VREGIN
VDDA
PTB1
PTB0/LLWU_P5
PTA20
PTA19
18
17
VSSA
PTA18
Figure 7. 32 QFN Pinout diagram (transparent top view)
The figure below shows the 48 QFN pinouts.
46
K32 L2B Microcontroller, Rev. 3, 09/2020
NXP Semiconductors
Pinouts
PTC3/LLWU_P7
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
1
2
PTC2
PTC1/LLWU_P6/RTC_CLKIN
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE20
3
PTC0
4
PTB17
PTB16
PTB3
5
6
7
PTE21
PTB2
8
VDDA
PTB1
9
VREFH
VREFL
VSSA
PTB0/LLWU_P5
PTA20
10
11
12
PTA19
Figure 8. 48 QFN Pinout diagram (transparent top view)
4.7 Package dimensions
The following figures show the dimensions of the package options for the devices
supported by this document.
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NXP Semiconductors
Pinouts
Figure 9. 64-pin LQFP package dimensions 1
48
K32 L2B Microcontroller, Rev. 3, 09/2020
NXP Semiconductors
Pinouts
8
(0.22)
BASE METAL
0.16
B
B
0.20
0.09
8
0.09
8
60X
0.5
PLATING
0.23
0.17
0.25
8
X
X=A, B OR D
SECTION B-B
DETAIL Y
(0.2)
0° MIN
1.45
1.35
0.05
2X R0.2
0.1
0.25
GAUGE
PLANE
0.15
0.05
(0.5)
0.75
0.45
7°
0°
(1.00)
DETAIL AA
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. DATUMS A, B AND D TO BE DETERMINDE AT DATUM PLANE H.
4. DIMENSIONS TO BE DETERMINED AT SEATING PLANE C.
5. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE UPPER LIMIT
BY MORE THAN 0.08 MM AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN
PROTRUSION AND ADJACENT LEAD SHALL NOT BE LESS THAN 0.07 MM.
6. THIS DIMENSION DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.25 MM PER SIDE. THIS DIMENSION IS MAXIMUM PLASTIC BODY SIZE
DIMENSION INCLUDING MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.1 MM AND 0.25 MM FROM THE LEAD TIP.
Figure 10. 64-pin LQFP package dimensions 2
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49
NXP Semiconductors
Pinouts
5
B
C
64X
0.08 A
A1 INDEX AREA
D
A
5
// 0.2 A
SEATING
PLANE
4
5
4X
0.15
D
TOP VIEW
0.25
7X 0.5
H
G
F
7X 0.5
0.25
E
D
C
B
A
0.25
0.15
0.35
Ø0.25
64X
3
M
A B
A
C
Ø0.15
1.23 MAX
M
Ø0.05
A1 INDEX AREA
VIEW D-D
BOTTOM VIEW
NOTES:
1. ALL DIMENSIONS IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. MAXIMUM SOLDER BALL DIAMETER MEASURED PARALLEL TO DATUM A.
4. DATUM A, THE SEATING PLANE, IS DETERMINED BY THE SPHERICAL CROWNS OF THE
SOLDER BALLS.
5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE
OF PACKAGE.
Figure 11. 64-pin MAPBGA package dimension
50
NXP Semiconductors
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Pinouts
Figure 12. 48-pin QFN package dimension 1
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NXP Semiconductors
Pinouts
45°
0.25
(0.05)
0.95
1.13
DETAIL F
// 0.1 C
48X
0.65
0.50
0.08 C
4
0.05
0.00
(0.2)
C
SEATING PLANE
(0.5)
DETAIL G
VIEW ROTATED 90℃W
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. THIS IS A NON-JEDEC REGISTERED PACKAGE.
4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG.
5. MIN. METAL GAP SHOULD BE 0.2 MM.
Figure 13. 48-pin QFN package dimension 2
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NXP Semiconductors
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Pinouts
Figure 14. 32-pin QFN package dimension 1
K32 L2B Microcontroller, Rev. 3, 09/2020
53
NXP Semiconductors
Electrical characteristics
// 0.1 C
32X
0.65
0.50
0.08 C
0.05
0.00
(0.2)
C
SEATING PLANE
(0.5)
DETAIL G
VIEW ROTATED 90℃W
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
3. THIS IS A NON-JEDEC REGISTERED PACKAGE.
4. COPLANARITY APPLIES TO LEADS AND DIE ATTACH FLAG.
5. MIN. METAL GAP SHOULD BE 0.2 MM.
Figure 15. 32-pin QFN package dimension 2
5 Electrical characteristics
5.1 Ratings
54
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Electrical characteristics
5.1.1 Thermal handling ratings
Table 32. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.1.2 Moisture handling ratings
Table 33. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.1.3 ESD handling ratings
Table 34. ESD handling ratings
Symbol
VHBM
Description
Min.
–2000
–500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.1.4 Voltage and current operating ratings
Table 35. Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IDD
120
mA
Table continues on the next page...
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Electrical characteristics
Table 35. Voltage and current operating ratings (continued)
Symbol
VIO
Description
Min.
–0.3
–25
Max.
VDD + 0.3
25
Unit
V
IO pin input voltage
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
USB_DP input voltage
USB_DM input voltage
USB regulator input
VDD – 0.3
–0.3
VDD + 0.3
3.63
V
V
V
V
VUSB_DP
VUSB_DM
VREGIN
–0.3
3.63
–0.3
6.0
5.2 General
5.2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 16. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
5.2.2 Nonswitching electrical specifications
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Electrical characteristics
5.2.2.1 Voltage and current operating requirements
Table 36. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-3
—
—
V
IO pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
2
VDD voltage required to retain RAM
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD
.
5.2.2.2 LVD and POR operating requirements
Table 37. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
1
VLVW1H
VLVW2H
VLVW3H
2.62
2.72
2.82
2.70
2.80
2.90
2.78
2.88
2.98
V
V
V
• Level 2 falling (LVWV = 01)
Table continues on the next page...
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Electrical characteristics
Table 37. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVW4H
• Level 3 falling (LVWV = 10)
2.92
3.00
3.08
V
• Level 4 falling (LVWV = 11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low-power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
5.2.2.3 Voltage and current operating behaviors
Table 38. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
1
VDD – 0.5
VDD – 0.5
—
—
V
V
VOH
Output high voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
1
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
—
100
mA
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
1
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
—
0.5
0.5
V
V
IOLT
Output low current total for all ports
—
100
mA
Table continues on the next page...
58
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Electrical characteristics
Table 38. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IIN
Input leakage current (per pin) for full temperature
range
—
1
μA
2
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
64
μA
μA
2
2
Input leakage current (total all pins) for full
temperature range
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
1
μA
kΩ
RPU
20
50
3
1. PTB0, PTB1, PTC3, PTC4, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the
associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
5.2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 39. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR After a POR event, amount of time from the
—
—
300
μs
1
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
—
—
—
—
—
—
152
152
93
166
166
104
8
μs
μs
μs
μs
μs
μs
7.5
7.5
7.5
• VLPS → RUN
• STOP → RUN
8
8
1. Normal boot (FTFA_FOPT[LPBOOT]=11)
K32 L2B Microcontroller, Rev. 3, 09/2020
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Electrical characteristics
5.2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while (1) test is executed with flash cache enabled.
Table 40. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
—
—
5.76
6.04
6.40
6.68
mA
mA
mA
• at 25 °C
• at 105 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
3.21
3.49
3.85
4.13
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
2
2
—
—
6.45
6.75
7.09
7.39
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable, 24
MHz core/12 MHz flash, VDD = 3.0 V
—
—
3.95
4.23
4.59
4.87
• at 25 °C
mA
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable 12
MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
2
2
—
—
2.68
2.96
3.32
3.60
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
8.08
8.39
8.72
9.03
mA
• at 105 °C
Table continues on the next page...
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock disable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
3.90
4.21
4.54
4.85
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
2.66
2.94
3.30
3.58
mA
mA
mA
mA
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock disable,
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
2.03
2.31
2.67
2.95
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock enable,
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
5.52
5.83
6.16
6.47
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
5.29
5.56
5.93
6.20
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in SRAM all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
6.91
7.19
7.55
7.91
• at 105 °C
IDD_VLPRCO Very Low Power Run Core Mark in Flash in
Compute Operation mode: Core@4 MHz, Flash
@1 MHz, VDD = 3.0 V
—
—
—
826
405
154
907
486
235
μA
μA
μA
• at 25 °C
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode, 4
MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode, 2
MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
108
39
Max.
Unit
Notes
IDD_VLPR Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
189
μA
IDD_VLPR Very-low-power run mode current— 2 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 125 kHz core / 31.25 kHz flash, VDD
3.0 V
=
—
120
μA
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
disable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
—
249
337
416
330
418
497
μA
μA
μA
IDD_VLPR Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in flash all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD
=
3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
494
166
575
247
μA
μA
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM in all peripheral
clock disable, 2 MHz core / 0.5 MHz flash, VDD
=
3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
disable, 125 kHz core / 31.25 kHz flash, VDD
=
—
50
131
μA
3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral clock
enable, 2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
—
208
1.81
1.22
289
1.89
1.39
μA
mA
mA
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
Table continues on the next page...
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_VLPW Very-low-power wait mode current, core disabled,
4 MHz system/ 1 MHz bus and flash, all
—
172
182
μA
peripheral clocks disabled, VDD = 3.0 V
IDD_VLPW Very-low-power wait mode current, core disabled,
2 MHz system/ 0.5 MHz bus and flash, all
—
—
69
36
76
40
μA
μA
peripheral clocks disabled, VDD = 3.0 V
IDD_VLPW Very-low-power wait mode current, core disabled,
125 kHz system/ 31.25 kHz bus and flash, all
peripheral clocks disabled, VDD = 3.0 V
IDD_PSTOP2 Partial Stop 2, core and system clock disabled, 12
MHz bus and flash, VDD = 3.0 V
—
—
1.81
1.00
2.06
1.25
mA
mA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
—
—
—
—
161.93
181.45
236.29
390.33
171.82
191.96
271.17
465.58
• at 50 °C
• at 85 °C
• at 105 °C
μA
μA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
—
—
—
—
3.31
10.43
34.14
104.38
5.14
17.68
61.06
164.44
• at 50 °C
• at 85 °C
• at 105 °C
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
—
—
—
—
3.21
10.26
33.49
102.92
5.22
17.62
60.19
162.20
• at 50 °C
• at 85 °C
• at 105 °C
μA
μA
IDD_LLS Low-leakage stop mode current, all peripheral
disable, at 3.0 V
—
—
—
—
—
2.06
4.72
3.33
6.85
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
8.13
13.30
24.70
52.43
13.34
41.08
IDD_LLS Low-leakage stop mode current with RTC current,
at 3.0 V
μA
—
2.46
3.73
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Table 40. Power consumption operating behaviors (continued)
Symbol Description
• at 25 °C and below
Min.
Typ.
Max.
Unit
Notes
—
5.12
7.25
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
—
—
8.53
13.74
41.48
11.78
18.91
52.83
IDD_LLS Low-leakage stop mode current with RTC current,
3
μA
μA
μA
μA
at 1.8 V
—
—
—
—
—
2.35
4.91
2.70
6.75
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
8.32
11.78
18.21
51.85
13.44
40.47
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
—
—
—
—
—
1.45
3.37
5.76
9.72
30.41
1.85
4.39
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
8.48
14.30
37.50
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
3
—
—
—
—
—
2.05
3.97
2.45
4.99
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
6.36
9.08
10.32
31.01
14.73
38.10
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
3
—
—
—
—
—
1.96
3.86
2.36
5.67
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
6.23
8.53
10.21
30.25
13.37
37.02
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
—
—
—
0.66
1.78
2.55
0.80
3.87
4.26
• at 25 °C and below
• at 50°C
• at 70°C
μA
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Electrical characteristics
Table 40. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• at 85°C
—
4.83
6.64
• at 105 °C
—
16.42
20.49
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
3
—
—
—
—
—
1.26
2.38
3.15
5.43
17.02
1.40
4.47
4.86
7.24
21.09
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
μA
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
3
—
—
—
—
—
1.16
1.96
2.78
4.85
15.78
1.30
2.28
3.37
6.88
18.81
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
μA
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
—
—
—
—
—
0.35
1.25
2.53
4.40
16.09
0.47
1.44
3.24
5.24
19.29
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
—
—
—
—
—
0.18
1.09
2.25
4.25
15.95
0.28
1.31
2.94
5.10
19.10
• at 25 °C and below
μA
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.10 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
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Table 41. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIRC8MHz
8 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
93
93
93
93
93
93
µA
MCG_MC[LIRC_DIV2]=000b.
IIRC2MHz
2 MHz internal reference clock (IRC)
adder. Measured by entering STOP mode
with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
MCG_MC[LIRC_DIV2]=000b.
29
29
29
29
29
29
µA
µA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
224
230
238
245
253
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
• VLLS1
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
• VLLS3
• LLS
• VLPS
• STOP
nA
ILPTMR
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30
22
30
22
30
22
85
22
100
22
200
22
nA
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare. Includes
6-bit DAC power consumption.
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source waiting for RX
data at 115200 baud rate. Includes
selected clock source power consumption.
• IRC8M (8 MHz internal reference
clock)
114
34
114
34
114
34
114
34
114
34
114
34
µA
• IRC2M (2 MHz internal reference
clock)
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Table 41. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source configured for
output compare generating 100 Hz clock
signal. No load is placed on the I/O
generating the clock signal. Includes
selected clock source and I/O switching
currents.
147
42
147
42
147
42
147
42
147
42
147
42
µA
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx or VLLSx mode.
45
45
45
45
45
45
µA
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
330
330
330
330
330
330
ILCD
LCD peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by means
of the OSC0_CR[EREFSTEN,
4.5
4.5
4.5
4.5
4.5
4.5
µA
EREFSTEN] bits. VIREG disabled, resistor
bias network enabled, 1/8 duty cycle, 8 x
36 configuration for driving 288 Segments,
32 Hz frame rate, no LCD glass
connected. Includes ERCLK32K (32 kHz
external crystal) power consumption.
5.2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
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Figure 17. Run mode supply current vs. core frequency
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Figure 18. VLPR mode current vs. core frequency
5.2.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following NXP applications notes, available on nxp.com for advice and
guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
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Electrical characteristics
• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
5.2.2.7 Capacitance attributes
Table 42. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
5.2.3 Switching specifications
5.2.3.1 Device clock specifications
Table 43. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
System and core clock1
Bus clock1
Flash clock1
—
—
—
20
—
48
24
24
—
24
MHz
MHz
MHz
MHz
MHz
fFLASH
fSYS_USB
fLPTMR
System and core clock when Full Speed USB in operation
LPTMR clock
VLPR and VLPS modes2
System and core clock
Bus clock
fSYS
fBUS
fFLASH
fLPTMR
—
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock3
1
24
16
16
fLPTMR_ERCLK LPTMR external reference clock
fosc_hi_2 Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
fTPM
TPM asynchronous clock
—
—
8
8
MHz
MHz
fLPUART0/1 LPUART0/1 asynchronous clock
1. The maximum value of system clock, core clock, bus clock, and flash clock under normal run mode can be 3% higher
than the specified maximum frequency when IRC 48 MHz is used as the clock source.
2. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
3. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
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5.2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 44. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
16
—
—
ns
ns
2
3
36
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
5.2.4 Thermal specifications
5.2.4.1 Thermal operating requirements
Table 45. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
5.2.4.2 Thermal attributes
Table 46. Thermal attributes
Board type
Symbol
Description
48 QFN 32 QFN
64
64
Unit
°C/W
°C/W
Notes
LQFP MAPBG
A
Single-layer (1S)
Four-layer (2s2p)
RθJA
Thermal resistance, junction
to ambient (natural
convection)
86
29
101
33
70
50.3
1
RθJA
Thermal resistance, junction
to ambient (natural
convection)
51
42.9
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Electrical characteristics
Table 46. Thermal attributes (continued)
Board type
Symbol
Description
48 QFN 32 QFN
64
64
Unit
°C/W
°C/W
Notes
LQFP MAPBG
A
Single-layer (1S)
Four-layer (2s2p)
RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
71
24
84
28
58
41.4
RθJMA Thermal resistance, junction
to ambient (200 ft./min. air
speed)
45
38.0
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction
to board
12
1.7
2
13
1.7
3
33
20
4
39.6
27.3
0.4
°C/W
°C/W
°C/W
2
3
4
Thermal resistance, junction
to case
Thermal characterization
parameter, junction to
package top outside center
(natural convection)
—
ΨJB
Thermal characterization
parameter, junction to
package bottom (natural
convection)
-
-
-
12.6
°C/W
5
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
5. Thermal characterization parameter indicating the temperature difference between package bottom center and the
junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization
parameter is written as Psi-JB.
5.3 Peripheral operating requirements and behaviors
5.3.1 Core modules
5.3.1.1 SWD electricals
Table 47. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
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Table 47. SWD full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 19. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 20. Serial wire data timing
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5.3.2 System modules
There are no specifications necessary for the device's system modules.
5.3.3 Clock modules
5.3.3.1 MCG-Lite specifications
Table 48. IRC48M specification
Symbol
IDD
Description
Supply current
Output frequency
Min.
—
Typ.
400
48
Max.
500
—
Unit
µA
Notes
—
fIRC
—
MHz
—
Δfirc48m_ol_lv Open loop total deviation of IRC48M
frequency at low voltage
1
—
—
0.5
1.5
%firc48m
(VDD=1.71V-1.89V) over temperature
Δfirc48m_ol_hv Open loop total deviation of IRC48M
frequency at high voltage
1
0.5
1.0
%firc48m
(VDD=1.89V-3.6V) over temperature
Tj
Period jitter (RMS)
Startup time
—
—
35
2
150
3
ps
µs
—
—
Tsu
1. The maximum value represents characterized results equivalent to mean plus or minus three times the standard
deviation (mean +/-3sigma).
Table 49. IRC8M/2M specification
Symbol
IDD_2M
Description
Supply current in 2 MHz mode
Supply current in 8 MHz mode
Output frequency
Min.
—
Typ.
14
30
2
Max.
17
Unit
µA
Notes
—
IDD_8M
—
35
µA
—
fIRC_2M
fIRC_8M
fIRC_T_2M
fIRC_T_8M
Tsu_2M
—
—
MHz
MHz
%fIRC
%fIRC
µs
—
Output frequency
—
8
—
—
Output frequency range (trimmed)
Output frequency range (trimmed)
Startup time
—
—
—
—
—
3
—
—
3
—
—
12.5
12.5
—
Tsu_8M
Startup time
—
µs
—
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Electrical characteristics
Figure 21. IRC8M Frequency Drift vs Temperature curve
5.3.3.2 Oscillator electrical specifications
5.3.3.2.1 Oscillator DC electrical specifications
Table 50. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
nA
μA
μA
μA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
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Table 50. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• 24 MHz
—
1.5
—
mA
• 32 MHz
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
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3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
5.3.3.2.2 Oscillator frequency specifications
Table 51. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
48
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
5.3.4 Memories and memory interfaces
5.3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
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5.3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 52. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
thversblk128k Erase Block high-voltage time for 128 KB
—
1
—
113
452
ms
ms
—
52
1
1. Maximum time based on expectations at cycling end-of-life.
5.3.4.1.2 Flash timing specifications — commands
Table 53. Flash command timing specifications
Symbol Description
Read 1s Block execution time
• 128 KB program flash
Min.
Typ.
Max.
Unit
Notes
1
trd1blk128k
—
—
1.7
ms
trd1sec1k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
trdrsrc
tpgm4
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 128 KB program flash
30
1
145
—
2
tersblk128k
—
88
600
ms
tersscr
trd1all
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
—
14
—
114
1.8
ms
ms
μs
2
1
trdonce
—
25
1
tpgmonce Program Once execution time
65
—
μs
—
2
tersall
tvfykey
tersallu
Erase All Blocks execution time
175
—
1300
30
ms
μs
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
1
175
1300
ms
2
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
5.3.4.1.3 Flash high voltage current behaviors
Table 54. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
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Table 54. Flash high voltage current behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
5.3.4.1.4 Reliability specifications
Table 55. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
5.3.6 Analog
5.3.6.1 ADC electrical specifications
Using differential inputs can achieve better system accuracy than using single-end
inputs.
5.3.6.1.1 16-bit ADC operating conditions
Table 56. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
Ground voltage Delta to VSS (VSS – VSSA
)
0
2
ADC reference
voltage high
VDDA
3
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Table 56. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
3
VADIN
Input voltage
• 16-bit differential mode
VREFL
VREFL
—
—
31/32 ×
VREFH
V
—
—
• All other modes
• 16-bit mode
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
4
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
24
MHz
MHz
5
5
6
ADC conversion 16-bit mode
clock frequency
12.0
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
1200
ksps
ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
6
rate
No ADC hardware averaging
461.467
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. VREFH can act as VREF_OUT when VREFV1 module is enabled.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
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SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 22. ADC input impedance equivalency diagram
5.3.6.1.2 16-bit ADC electrical characteristics
Table 57. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-linearity
• 12-bit modes
• <12-bit modes
—
—
1.0
0.5
–2.7 to
+1.9
LSB4
5
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Table 57. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
–0.7 to
+0.5
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN = VDDA
Quantization error
0.5
ENOB Effective number of 16-bit differential mode
6
bits
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
dB
• Avg = 4
Signal-to-noise plus See ENOB
SINAD
6.02 × ENOB + 1.76
distortion
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
dB
dB
—
-94
-85
—
16-bit single-ended mode
• Avg = 32
—
—
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor voltage 25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
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4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 23. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
Averaging of 4 samples
Averaging of 32 samples
11.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 24. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
5.3.6.2 Voltage reference electrical specifications
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Table 58. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
V
Notes
3.6
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Table 59 is tested under the condition of setting VREF_TRM[CHOPEN],
VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1.
Table 59. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range: 0 to 70°C)
—
50
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
1
1
Low-power buffer current
High-power buffer current
Ihp
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
Tchop_osc_st Internal bandgap start-up delay with chop
ms
—
1
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full
voltage range)
—
2
—
mV
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 60. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
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Table 61. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
5.3.6.3 CMP and 6-bit DAC electrical specifications
Table 62. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, high-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
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0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 25. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
5.3.6.4 12-bit DAC electrical characteristics
5.3.6.4.1 12-bit DAC operating requirements
Table 63. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
1.13
—
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREF_OUT
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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5.3.6.4.2 12-bit DAC operating behaviors
Table 64. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
250
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
900
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
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8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 27. Typical INL error vs. digital code
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Electrical characteristics
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 28. Offset at half scale vs. temperature
5.4 Timers
See General switching specifications.
5.5 Communication interfaces
5.5.1 USB electrical specifications
The USB electricals for the USB module conform to the standards documented by the
Universal Serial Bus Implementers Forum. For the most up-to-date standards, visit
usb.org .
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NOTE
The IRC48M do not meet the USB jitter specifications for
certification for Host mode operation.
This device cannot support Host mode operation.
5.5.2 USB VREG electrical specifications
Table 65. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.1
Max.
5.5
Unit
V
Notes
VREGIN Input supply voltage
—
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
125
186
μA
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
Quiescent current — Shutdown mode
—
—
650
—
—
4
nA
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
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5.5.3 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 66. SPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
18
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
15
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 67. SPI master mode timing on slew rate enabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
96
0
—
—
ns
ns
—
—
Table continues on the next page...
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Table 67. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol Description
Min.
—
Max.
52
Unit
ns
Note
—
8
9
tv
Data valid (after SPSCK edge)
tHO
tRI
Data hold time (outputs)
Rise time input
0
—
ns
—
10
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
tFO
Rise time output
Fall time output
—
36
ns
—
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 29. SPI master mode timing (CPHA = 0)
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1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 30. SPI master mode timing (CPHA = 1)
Table 68. SPI slave mode timing on slew rate disabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2.5
3.5
—
—
—
0
—
ns
7
—
ns
8
tperiph
tperiph
31
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
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Electrical characteristics
Table 69. SPI slave mode timing on slew rate enabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
122
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 31. SPI slave mode timing (CPHA = 0)
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Electrical characteristics
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 32. SPI slave mode timing (CPHA = 1)
5.5.4 I2C
5.5.4.1 Inter-Integrated Circuit Interface (I2C) timing
Table 70. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency
fSCL
0
4
100
—
0
4001
kHz
µs
Hold time (repeated) START condition. tHD; STA
After this period, the first clock pulse is
generated.
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
02
2505
—
3.453
—
04
1003, 6
20 +0.1Cb
20 +0.1Cb
0.6
0.92
—
µs
ns
ns
ns
µs
µs
Data set-up time
7
6
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
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Electrical characteristics
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the high
drive pins across the full voltage range and when using the normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
Table 71. I 2C 1Mbit/s timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
0.5
0.26
—
—
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
Set-up time for a repeated START condition
Data hold time for I2C bus devices
Data set-up time
tSU; STA
tHD; DAT
tSU; DAT
tr
0.26
—
0
—
50
—
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
20 +0.1Cb
120
120
—
2
tf
20 +0.1Cb
tSU; STO
tBUF
0.26
0.5
0
Bus free time between STOP and START condition
—
Pulse width of spikes that must be suppressed by
the input filter
tSP
50
1. The maximum SCL clock frequency of 1 Mbit/s can support maximum bus loading when using the high drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 33. Timing definition for devices on the I2C bus
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Electrical characteristics
5.5.5 UART
See General switching specifications.
5.6 Human-machine interfaces (HMI)
5.6.1 LCD electrical characteristics
Table 72. LCD electricals
Symbol Description
fFrame LCD frame frequency
Min.
Typ.
Max.
Unit
Notes
• GCR[FFR]=0
• GCR[FFR]=1
23.3
46.6
—
—
73.1
Hz
Hz
146.2
CLCD
LCD charge pump capacitance — nominal
value
—
100
—
nF
CBYLCD LCD bypass capacitance — nominal value
—
—
100
—
nF
pF
V
1
2
3
CGlass
VIREG
LCD glass capacitance
VIREG
2000
8000
• RVTRIM=0000
• RVTRIM=1000
• RVTRIM=0100
• RVTRIM=1100
• RVTRIM=0010
• RVTRIM=1010
• RVTRIM=0110
• RVTRIM=1110
• RVTRIM=0001
• RVTRIM=1001
• RVTRIM=0101
• RVTRIM=1101
• RVTRIM=0011
• RVTRIM=1011
• RVTRIM=0111
• RVTRIM=1111
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.91
0.92
0.93
0.94
0.96
0.97
0.98
0.99
1.01
1.02
1.03
1.05
1.06
1.07
1.08
1.09
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ΔRTRIM VIREG TRIM resolution
IVIREG VIREG current adder — RVEN = 1
IRBIAS RBIAS current adder
—
—
—
1
3.0
—
% VIREG
µA
Table continues on the next page...
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Design considerations
Symbol Description
Table 72. LCD electricals (continued)
Min.
Typ.
Max.
Unit
Notes
• LADJ = 10 or 11 — High load (LCD glass
—
10
—
µA
capacitance ≤ 8000 pF)
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
—
1
—
µA
RRBIAS RBIAS resistor values
• LADJ = 10 or 11 — High load (LCD glass
capacitance ≤ 8000 pF)
—
—
0.28
2.98
—
—
MΩ
MΩ
• LADJ = 00 or 01 — Low load (LCD glass
capacitance ≤ 2000 pF)
VLL1
VLL2
VLL3
VLL1
VLL2
VLL3
VLL1 voltage
—
—
—
—
—
—
—
—
—
—
—
—
VIREG
2 x VIREG
3 x VIREG
VDDA / 3
VDDA / 1.5
VDDA
V
V
V
V
V
V
4
4
4
5
5
5
VLL2 voltage
VLL3 voltage
VLL1 voltage
VLL2 voltage
VLL3 voltage
1. The actual value used could vary with tolerance.
2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter
within the device's reference manual.
3. VIREG maximum should never be externally driven to any level other than VDD - 0.15 V
4. VLL1, VLL2 and VLL3 are a function of VIREG only when the regulator is enabled (GCR[RVEN]=1) and the charge pump
is enabled (GCR[CPSEL]=1).
5. VLL1, VLL2 and VLL3 are a function of VDDA only under either of the following conditions:
• The charge pump is enabled (GCR[CPSEL]=1), the regulator is disabled (GCR[RVEN]=0), and VLL3 = VDDA
through the internal power switch (GCR[VSUPPLY]=0).
• The resistor bias string is enabled (GCR[CPSEL]=0), the regulator is disabled (GCR[RVEN]=0), and VLL3 is
connected to VDDA externally (GCR[VSUPPLY]=1).
6 Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit.
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Design considerations
6.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital
circuits between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground. Consider to add ferrite bead or
inductor to some sensitive lines.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground
plane directly under LQFP packages; and solder the exposed pad (EP) to ground
directly under QFN packages.
6.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as
sequential segments.
• Always route the power net as star topology, and make each power trace loop as
minimum as possible.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
• Take special care to minimize noise levels on the VREFH/VREFL inputs. An
option is to use the internal reference voltage (output 1.2 V typically) as the ADC
reference.
NOTE
The internally-generated Voltage Reference Output
(VREF_OUT) is bonded to the VREFH pin on some
packages and to PTE30 on other packages. When
VREF_OUT is used, a 0.1 μF capacitor is required as a
filter. Do not connect any other supply voltage to the pin
that has VREF_OUT activated.
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Design considerations
6.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value of R must be RAS max if fast sampling and high resolution are
required. The value of C must be chosen to ensure that the RC time constant is very
small compared to the sample period.
MCU
1
2
Input signal
ADCx
R
C
Figure 34. RC circuit for ADC input
High voltage measurement circuits require voltage division, current limiting, and over-
voltage protection as shown the following figure. The voltage divider formed by R1 –
R4 must yield a voltage less than or equal to VREFH. The current must be limited to
less than the injection current limit. Since the ADC pins do not have diodes to VDD,
external clamp diodes must be included to protect against transient over-voltages.
MCU
R1
R2
R3
VDD
1
1
1
2
2
2
R5
1
2
ADCx
High voltage input
R4
1
2
C
BAT54SW
Figure 35. High voltage measurement with an ADC input
NOTE
For more details of ADC related usage, refer to AN5250:
How to Increase the Analog-to-Digital Converter Accuracy in
an Application.
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Design considerations
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
CAUTION
Do not provide power to I/O pins prior to VDD, especially
the RESET_b pin.
• RESET_b pin
The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An
external RC circuit is recommended to filter noise as shown in the following
figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the
recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable
digital filter to reject spurious noise.
VDD
MCU
10k
RESET_b
RESET_b
0.1uF
Figure 36. Reset circuit
When an external supervisor chip is connected to the RESET_b pin, a series
resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in the following figure. The series resistor value (RS below) must be in
the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength.
Select the open-drain output from the supervisor chip.
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Design considerations
VDD
Supervisor Chip
MCU
10k
1
2
OUT
RESET_b
RS
0.1uF
Figure 37. Reset signal connection to external reset chip
• NMI pin
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low level
on this pin will trigger non-maskable interrupt. When this pin is enabled as the NMI
function, an external pull-up resistor (10 kΩ) as shown in the following figure is
recommended for robustness.
If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
VDD
MCU
10k
NMI_b
Figure 38. NMI pin biasing
• Debug interface
This MCU uses the standard Arm SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required (SWD_DIO
has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ
pull resistors are recommended for system robustness. The RESET_b pin
recommendations mentioned above must also be considered.
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Design considerations
VDD
10k
VDD
J1
SWD_DIO
SWD_CLK
1
3
5
7
9
2
4
6
8
RESET_b
10k
10
0.1uF
HDR_5X2
Figure 39. SWD debug interface
• Low leakage stop mode wakeup
Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the
low leakage stop modes (LLS/VLLSx). See the pinout table for pin selection.
• Unused pin
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital
input path to the MCU.
If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM)
floating.
6.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators.
An external feedback is required when using high gain (HGO=1) mode.
Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786 kHz)
mode. Use the SCxP bits in the OSC0_CR register to adjust the load capacitance for
the crystal. Typically, values of 10pf to 16 pF are sufficient for 32.768 kHz crystals
that have a 12.5 pF CL specification. The internal load capacitor selection must not be
used for high frequency crystals and resonators.
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Design considerations
Table 73. External crystal/resonator connections
Oscillator mode
Low frequency (32.768 kHz), low power
Low frequency (32.768 kHz), high gain
High frequency (3-32 MHz), low power
High frequency (3-32 MHz), high gain
Oscillator mode
Diagram 1
Diagram 2, Diagram 4
Diagram 3
Diagram 4
OSCILLATOR
EXTAL
XTAL
1
2
CRYSTAL
Figure 40. Crystal connection – Diagram 1
OSCILLATOR
EXTAL
XTAL
1
2
RF
RS
1
2
CRYSTAL
Figure 41. Crystal connection – Diagram 2
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 42. Crystal connection – Diagram 3
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Part identification
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
2
RF
RF
RS
RS
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 43. Crystal connection – Diagram 4
6.2 Software considerations
All K32 L-series ultra-low power Microcontrollers (MCUs), optimized for low-
leakage applications, are supported by comprehensive NXP and third-party hardware
and software enablement solutions, which can reduce development costs and time to
market. Featured software and tools are listed below.
Evaluation and Prototyping Hardware
• NXP Freedom Development Platform: http://www.nxp.com/freedom
• Tower System Development Platform: http://www.nxp.com/tower
IDEs for K32 L2B MCUs
• MCUXpresso: https://mcuxpresso.nxp.com
Run-time Software
• K32 L2B SDK: http://mcuxpresso.nxp.com
For all other partner-developed software and tools, visit http://www.nxp.com/partners.
7 Part identification
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Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
B PF S FS SPF T PG FR SR PT
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 74. Part number fields descriptions
Field
Description
Values
B
Brand
• K32
• L2
PF
S
Product Family
Sub-family
• A= Sub-family A
• B= Sub-family B
FS
Flash size
• 1 = 64 KB
• 2 = 128 KB
• 3 = 256 KB
• 4 = 512 KB
SPF
Special Feature
• 0 = Dual core
• 1 = Single core
T
Temperature range (°C)
Package
• V = -40 to 105
PG
• FM = 32 QFN
• FT = 48 QFN
• MP = 64 BGA
• LH = 64 LQFP
FR
SR
Frequency (MHz)
Silicon Revision
• 0 = 0 - 50 MHz
• A = Initial Mask Set
• B = 1st Major Spin
PT
Packaging Type
• R = Std Reel
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Small package marking
7.4 Example
This is an example part number:
K32L2B31VLH0A
8 Small package marking
In order to save space, small package devices use special marking on the chip.
Q FS FF TP
Field
Description
Values
Q
Qualification status
K=M
PK=P
FS
FF
Family
L2B=K32L2B family
6=64 KB
Program flash memory size
7=128 KB
8=256 KB
TP
Temperature range
V=-40 to 105 for all 4 packages
For example:
KL2B6V = K32L2B11VFM0A
9 Package marking information
The K32L2B 64LQFP package has the following top-side marking:
• First line: aaaaaaaa
• Second line: aaaaa
• Third line: mmmmm
• Fourth line: xxxyywwx
The K32L2B 64MAPBGA package has the following top-side marking:
• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx
The K32L2B 48QFN package has the following top-side marking:
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Revision History
• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx
The K32L2B 32QFN package has the following top-side marking:
• First line: aaaaaa
• Second line: mmmmm
• Third line: xxywx
The detailed code format for these identifiers is show in the table below.
Identifier
Description
a
Part number code, refer to the "Part identification" section.
m
y
Mask set
Work year
w
x
Work week
NXP internal use
10 Revision History
The following table provides a revision history for this document.
Table 75. Revision History
Rev. No.
Date
Substantial Changes
3
September
2020
• Updated value of ADC to 461 ksps from 818 in front page of the Data sheet.
• Removed "RESET_b" from ALT7 column and "PTA20" from ALT1 column
corresponding to PTA20 pin in K32 L2B Signal Multiplexing and Pin Assignments
(LQFP and MAPBGA) and K32 L2B Signal Multiplexing and Pin Assignments (QFN).
Also added the following note: When FTFA_FOPT[RESET_PIN_CONFIG]=0, PTA20
pin acts as RESET_B function only during ............of PORTA_PCR20[MUX]'s setting
value.
• Added Package marking information and Small package marking.
• Removed "OTG/On the Go" references.
2
1
December
2019
• Added Related Resources table in front page of the Data sheet.
• Corrected description of PD/PU in Table 8 Pin Properties section.
• Updated values in "Default" column for pins 1, 2, 9, 10, 49-52 in K32 L2B Signal
Multiplexing and Pin Assignments (LQFP and MAPBGA).
• Added EXTRG_IN signal in TPM signal descriptions and Table 29.
September Initial public release.
2019 • Removed support of CRC throughout.
• Replaced name of function pin VREFO with VREF_OUT.
• Changed the high drive pin number to 6 for 48 QFN in Ordering information.
• Updated flash and RAM in Figure 1. System diagram in the Overview section.
Table continues on the next page...
110
NXP Semiconductors
K32 L2B Microcontroller, Rev. 3, 09/2020
Revision History
Table 75. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Added DAC topic to the "Peripheral Features" section.
• Updated memory addresses and peripherals in Memory map.
• Updated 32 QFN and 48 QFN pinouts and diagrams to remove usage of USB_VDD
pin.
• Updated pin names in Pin properties. Split the table into two, each for 64 LQFP/
MAPBGA and 32/48 QFN packages.
• Added thermal attributes for 32 QFN and 48 QFN packages in Thermal attributes.
• Updated part number format and fields in Format and Fields.
0
July 2019
• Initial release (internal).
K32 L2B Microcontroller, Rev. 3, 09/2020
111
NXP Semiconductors
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