KMPC860SRCZQ50D4_技术文档

Freescale Semiconductor, Inc.

10/97

MPC8XXFADS

Design Speciﬁcation—Rev 0.1

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General Information

1 - General Information

1•1

Introduction

This document is an operation guide for the MPC8XXFADS board. It contains operational, functional

and general information about the FADS. The MPC8XXFADS is meant to serve as a platform for s/

w and h/w development around the MPC8XX family processors. Using its on-board resources and its

associated debugger, a developer is able to download his code, run it, set breakpoints, display

memory and registers and connect his own proprietary h/w via the expansion connectors, to be in-

corporated to a desired system with the MPC8XX processor.

A

This board could also be used as a demonstration tool, i.e., application s/w may be burned into its

flash memory and ran in exhibitions etc‘.

1•2

MPC8XX Family Support

The MPC8XXFADS supports the following MPC8XX family members:

❏

MPC801

MPC821

MPC823

MPC850

MPC860

MPC860SAR

MPC860T

1•3

Abbreviations’ List

B

•

FADS - the MPC8XXFADS, the subject of this document.

UPM - User Programmable Machine

GPCM - General Purpose Chip-select Machine

GPL - General Purpose Line (associated with the UPM)

I/R - Infra-Red

BCSR - Board Control & Status Register.

ZIF - Zero Input Force

BGA - Ball Grid Array

SIMM - Single In-line Memory Module

1•4

Related Documentation

•

MPC8XX User’s Manuals.

ADI Board Specification.

A. Either on or off-board.

B. Not to be mistaken for the M683XX Family Ads

MPC8XXFADS Design Specification—Rev 0.1

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SPECIFICATIONS

General Information

1•5

The MPC8XXFADS specifications are given in TABLE 1-1.

TABLE 1-1. MPC8XXFADS Specifications

CHARACTERISTICS

SPECIFICATIONS

Power requirements (no other boards attached)

+5Vdc @ 1.7 A (typical), 3 A (maximum)

+12Vdc - @1A.

Microprocessor

MPC8XX running upto @ 50 MHz

Addressing

Total address range:

4 GigaBytes

Flash Memory

Dynamic RAM

2 MByte, 32 bits wide expandable to 8 MBytes

4 MByte, 32 bits wide EDO SIMM

Support for up to 32 MByte, EDO or FPM SIMM

4 MBytes, organized as 1 Meg X 32 bit.

Synchronous DRAM

Operating temperature

Storage temperature

Relative humidity

0^OC - 30^OC

-25^OC to 85^OC

5% to 90% (non-condensing)

Dimensions:

Length

9.173" (233 mm)

6.3" (160 mm)

Width

Thickness

0.063" (1.6 mm)

MPC8XXFADS Design Specification—Rev 0.1

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MPC8XXFADS Features

General Information

1•6

❏

4 MByte, Unbuffered, Synchronous Dram On-Board.

4 MByte EDO 60nsec delay DRAM SIMM. Support for 4 - 32 MByte FPM or EDO

Dram SIMM, with Automatic Dram SIMM identification. 16 Bit Data-Bus Width Sup-

port.

❏

2 MByte Flash SIMM. Support for upto 8 MByte, 5V or 12V Programmable, with Au-

tomatic Flash SIMM identification.

❏

Memory Disable Option for each local memory map slaves.

Board Control & Status Register - BCSR, Controlling Board’s Operation.

Programmable Hard-Reset Configuration via BCSR.

5V only PCMCIA Socket With Full Buffering, Power Control and Port Disable Option.

Complies with PCMCIA 2.1+ Standard.

❏

Module Enable Indications.

10-Base-T Port On-Board, with Stand-By Mode.

Fast-IrDA (4MBps) Port with Stand-By Mode.

Dual RS232 port with Low-Power Option per each port.

On - Board Debug Port Controller with ADI I/F.

MPC8XXFADS Serving as Debug Station for Target System option.

A

Optional Hard-Reset Configuration Burned in Flash .

External Tools’ Identification Capability, via BCSR.

B

Soft / Hard Reset Push - Button

ABORT Push - Button

C

Single 5V Supply.

Reverse / Over Voltage Protection for Power Inputs.

D

3.3V / 2V MPC Internal Logic Operation , 3.3V MPC I/O Operation.

Power Indications for Each Power Bus.

Software Option Switch provides 16 S/W options via BCSR.

A. Available only if supported also on the MPC8XX.

B. Hard reset is applied by depressing BOTH Soft Reset & ABORT buttons.

C. Unless a 12V supply is required for a PCMCIA card or for a 12V programmable Flash SIMM.

D. Implemented on Daughter Board.

MPC8XXFADS Design Specification—Rev 0.1

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General Information

FIGURE 1-1 MPC8XXFADS Motherboard Block Diagram

SDRAM

4 MBytes

DATA & ADDRESS

BUFFERS

FLASH SIMM.

2 - 8MByte

Reset,

Interrupts

& Clock

DRAM SIMM

4 - 32 Mbyte

Dram Width

& Size Logic

DAUGHTER

BOARD

CONN.

Debug

Port

Connector

DEBUG

PORT

CONTROLLER

(ADI I/F)

EEST

PCMCIA

Buffering

&

Control

ADI PORT

(*)

(*) May be on a separate board.

1•7

MPC8XXFADS Goals

The MPC8XXFADS is meant to become a general platform for s/w and h/w development around the

MPC8XX family. Using its on-board resources and its associated debugger, the developer is able to

load his code, run it, set breakpoints, display memory and registers and connect his own proprietary

h/w via the expansion connectors, to be incorporated to a system with the MPC.

A

This board could also be used as a demonstration tool, i.e., application s/w may be programmed into

its flash memory and ran in exhibitions etc.

A. Either on or off-board.

MPC8XXFADS Design Specification—Rev 0.1

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Hardware Preparation and Installation

2 - Hardware Preparation and Installation

2•1

INTRODUCTION

This chapter provides unpacking instructions, hardware preparation, and installation instructions for

the MPC8XXFADS.

2•2

UNPACKING INSTRUCTIONS

NOTE

If the shipping carton is damaged upon

receipt, request carrier’s agent to be present

during unpacking and inspection of

equipment.

Unpack equipment from shipping carton. Refer to packing list and verify that all items are present.

Save packing material for storing and reshipping of equipment.

CAUTION

AVOID

TOUCHING

AREAS

OF

INTEGRATED

CIRCUITRY;

STATIC

DISCHARGE CAN DAMAGE CIRCUITS.

2•3

HARDWARE PREPARATION

To select the desired configuration and ensure proper operation of the MPC8XXFADS board,

changes of the Dip-Switch settings may be required before installation. The location of the switches,

LEDs, Dip-Switches, and connectors is illustrated in FIGURE 2-1. The board has been factory tested

and is shipped with Dip-Switch settings as described in the following paragraphs. Parameters can be

changed for the following conditions:

•

ADI port address

MPC Clock Source

Power-On Reset Source.

MPC Keep Alive Power Source

MPC Internal Logic Supply Source

Debug Mode Indication Source

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FIGURE 2-1 MPC8XXFADS Top Side Part Location diagram

MPC8XXFADS Design Specification—Rev 0.1

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Hardware Preparation and Installation

2•3•1

ADI Port Address Selection

The MPC8XXFADS can have eight possible slave addresses set for its ADI port, enabling up to eight

MPC8XXFADS boards to be connected to the same ADI board in the host computer. The selection

of the slave address is done by setting switches 1, 2 & 3 in the Dip-Switch - DS2. Switch 1 stands for

the most-significant bit of the address and switch 3 stands for the least-significant bit. If the switch is

in the ’ON’ state, it stands for logical ’1’. In FIGURE 2-2 DS1 is shown to be configured to address ’0’.

FIGURE 2-2 Configuration Dip-Switch - DS2

O

ADR2

1

2

3

4

ADR2

ADR1

ADR0

ADR1

ADR0

3 - 5 MHz Generator via EXTCLK

32.678 KHz Crystal Resonator

DS2

Table 2-1 describes the switch settings for each slave address:

Table 2-1 ADI Address Selection

ADDRESS

Switch 1

Switch 2

Switch 3

0

1

2

3

4

5

6

7

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

OFF

ON

2•3•2

Clock Source Selection

Switch #4 on DS2 selects the clock source for the MPC. When it is in the ’ON’ position while the FADS

A

is powered-up, the on-board 32.768 KHz crystal resonator becomes the clock source and the PLL

multiplication factor becomes 1:513. When switch #4 is in the ’OFF’ position while the FADS is

B

powered-up, the on-board 4 MHz clock generator^Abecomes the clock source while the PLL

multiplication factor becomes 1:5.

2•3•3

Power-On Reset Source Selection

As there are differences between MPC revisions regarding the functionality of the Power-On Reset

logic, it is therefore necessary to select different sources for Power-ON reset generation.

The above selection is done on the Daughter Board and therefore, documented in the specific

A. Located on the Daughter-Board

B. A 5MHz clock generator is packed as well.

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Daughter Board user’s manual.

2•3•4

VDDL Source Selection

This selection is done on the Daughter Board and therefore, documented in the specific Daughter

Board user’s manual.

2•3•5

Keep Alive Power Source Selection

This selection is done on the Daughter Board and therefore, documented in the specific Daughter

Board user’s manual.

2•3•6

Debug Mode Indication Source Selection

Jumper J1 selects between VFLS(0:1) signals and FRZ signal of the MPC as an indication for debug

mode state. Since with the MPC8XXs, each of these signals has alternate function, it may be neces-

sary to switch between the two sources, in favor of alternate function being used.

When a jumper is positioned between pins 1 and 2 of J1 - VFLS(0:1) are selected towards the debug-

port controller. When a jumper is placed between positions 2 - 3 of J1(2) - FRZ signal is selected.

FIGURE 2-3

J1

1

VFLS(0:1) Selected

FRZ Selected

2•4

INSTALLATION INSTRUCTIONS

When the MPC8XXFADS has been configured as desired by the user, it can be installed according

to the required working environment as follows:

•

Host Controlled Operation

Debug Port Controller for Target System

Stand-Alone

•

2•4•1

Host Controlled Operation

In this configuration the MPC8XXFADS is controlled by a host computer via the ADI through the

debug port. This configuration allows for extensive debugging using on-host debugger.

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Hardware Preparation and Installation

FIGURE 2-4 Host Controlled Operation Scheme

Host

Computer

ADI

37 Wire

P1

Flat Cable

P1

5V Power Supply

P6

2•4•2

Debug Port Controller For Target System

This configuration resembles the previous, but here the local MPC is removed from its socket while

the FADS is connected via a 10 lead Flat-Cable between P5 and a matching connector on a target

system.

WARNNING

When connecting the FADS to a target system via

P5 and a 10 lead flat-cable, the MPC MUST be RE-

MOVED from its SOCKET. Otherwise, PERMANENT

DAMAGE might be inflicted to either the Local MPC

or to the Target MPC.

With this mode of operation, all on-board modules are disabled and can not be accessed in anyway,

A

except for the debug port controller. Also, all indications except for 5V power, 3.3V-Power and RUN

are darkened.

All debugger commands and debugging features are available in this mode, including s/w download,

breakpoints, etc‘... The target system may be reset or interrupted by the debug port or reset by the

FADS’s RESET switches. It is the responsibility of the target system designer, to provide Power-On-

Reset and HARD-Reset configurations, while SOFT-Reset configuration is provided by the debug-

port controller. See also 4•12•1 "MPC8XXFADS As Debug Port Controller For Target System" on

page 58.

A. On Daughter Board.

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FIGURE 2-5 Debug Port Controller For Target System Operation Scheme

Target System

Host

Computer

10 Wire

37 Wire

ADI

Flat Cable

P5

Flat Cable

P1

5V Power Supply

P6

MPC Removed From Socket

2•4•3

Stand Alone Operation

In this mode, the FADS is not controlled by the host via the ADI/Debug port. It may connect to host

via one of its other ports, e.g., RS232 port, I/R port, Ethernet port, etc‘. Operating in this mode

requires an application program to be programmed into the board‘s Flash memory (while with the host

controlled operation, no memory is required at all).

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Hardware Preparation and Installation

FIGURE 2-6 Stand Alone Configuration

Host

Computer

P1

5V Power Supply

P6

2•4•4

+5V Power Supply Connection

The MPC8XXFADS requires +5 Vdc @ 5 A max, power supply for operation. Connect the +5V power

supply to connector P6 as shown below:

FIGURE 2-7 P6: +5V Power Connector

+5V

1

2

3

GND

P6 is a 3 terminal block power connector with power plug. The plug is designed to accept 14 to 22

AWG wires. It is recommended to use 14 to 18 AWG wires. To provide solid ground, two Gnd

terminals are supplied. It is recommended to connect both Gnd wires to the common of the power

supply, while VCC is connected with a single wire.

NOTE

Since hardware applications may be connected to the

MPC8XXFADS via the Daughter-Boards’ expansion

connectors PX1, PX2 PX3, PX4 or FADS’s P8, the

additional power consumption should be taken into

consideration when a power supply is connected to the

MPC8XXFADS.

2•4•5

P7: +12V Power Supply Connection

The MPC8XXFADS requires +12 Vdc @ 1 A max, power supply for the PCMCIA channel Flash

programming capability or for 12V programmable Flash SIMM. The MPC8XXFADS can work properly

without the +12V power supply, if there is no need to program either a 12V programmable PCMCIA

flash card or a 12V programmable Flash SIMM.

Connect the +12V power supply to connector P7 as shown below:

MPC8XXFADS Design Specification—Rev 0.1

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FIGURE 2-8 P7: +12V Power Connector

+12V

GND

1

2

P7 is a 2 terminal block power connector with power plug. The plug is designed to accept 14 to 22

AWG wires. It is recommended to use 14 to 18 AWG wires.

2•4•6

ADI Installation

For ADI installation on various host computers, refer to APPENDIX C - "ADI Installation" on page 155.

2•4•7

Host computer to MPC8XXFADS Connection

The MPC8XXFADS ADI interface connector, P1, is a 37 pin, male, D type connector. The connection

between the MPC8XXFADS and the host computer is by a 37 line flat cable, supplied with the ADI

board. FIGURE 2-9 below shows the pin configuration of the connector.

FIGURE 2-9 P1 - ADI Port Connector

1

2

3

4

5

6

7

8

N.C

D_C~

Gnd

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

HST_ACK

ADS_SRESET

ADS_HRESET

ADS_SEL2

ADS_SEL1

ADS_SEL0

HOST_REQ

ADS_REQ

ADS_ACK

N.C.

Gnd

(+ 12 v) N.C.

HOST_VCC

9

10

11

12

13

14

15

16

HOST_ENABLE~

Gnd

N.C.

PD1

PD3

PD5

PD7

Gnd

PD0

PD2

PD4

PD6

17

18

19

NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the MPC8XXFADS.

2•4•8

Terminal to MPC8XXFADS RS-232 Connection

A serial (RS232) terminal or any other RS232 equipment, may be connected to the RS-232

connectors PA2 and PB2. The RS-232 connectors is a 9 pin, female, Stacked D-type connector as

shown in FIGURE 2-10.

The connectors are arranged in a manner that allows for 1:1 connection with the serial port of an IBM-

A

AT or compatibles, i.e. via a flat cable.

A. IBM-AT is a trademark of International Business Machines Inc.

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FIGURE 2-10 PA2, PB2 - RS-232 Serial Port Connectors

CD

TX

1

2

6

DSR

7 RTS

8

9

RX

3

4

5

CTS

N.C.

DTR

GND

NOTE: The RTS line (pin 7) is not connected on the MPC8XXFADS.

2•4•9

Memory Installation

The MPC8XXFADS is supplied with two types of memory SIMM:

•

Dynamic Memory SIMM

Flash Memory SIMM.

To avoid shipment damage, these memories are packed aside rather than being installed in their

sockets. Therefore, they should be installed on site. To install a memory SIMM, it should be taken out

of its package, put diagonally in its socket (no error can be made here, since the Flash socket has 80

contacts, while the DRAM socket has 72) and then twisted to a vertical position until the metal lock

clips are locked. See FIGURE 2-11 "Memory SIMM Installation" below.

CAUTION

The memory SIMMs have alignment nibble near

their # 1 pin. It is important to align the memory cor-

rectly before it is twisted, otherwise damage might

be inflicted to both the memory SIMM and its sock-

et.

FIGURE 2-11 Memory SIMM Installation

(1)

(2)

Memory

SIMM

Metal Lock Clip

SIMM Socket

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3 - OPERATING INSTRUCTIONS

3•1

INTRODUCTION

This chapter provides necessary information to use the MPC8XXFADS in host-controlled and stand-

alone configurations. This includes controls and indicators, memory map details, and software

initialization of the board.

3•2

CONTROLS AND INDICATORS

The MPC8XXFADS has the following switches and indicators.

3•2•1

ABORT Switch SW1

The ABORT switch is normally used to abort program execution, this by issuing a level 0 interrupt to

the

MPC. If the FADS is in stand alone mode, it is the responsibility of the user to provide means of

handling

the interrupt, since there is no resident debugger with the MPC8XXFADS. The ABORT switch signal

is

debounced, and can not be disabled by software.

3•2•2

SOFT RESET Switch SW2

The SOFT RESET switch SW2 performs Soft reset to the MPC internal modules, maintaining MPC’s

configuration (clocks & chip-selects) Dram and SDram contents. The switch signal is debounced, and

it is not possible to disable it by software. At the end of the Soft Reset Sequence, the Soft Reset

Configuration is sampled and becomes valid.

3•2•3

HARD RESET - Switches SW1 & SW2

When BOTH switches - SW1 and SW2 are depressed simultaneously, HARD reset is generated to

the MPC. When the MPC is HARD reset, all its configuration is lost, including data stored in the DRAM

or SDRAM and the MPC has to be re-initialized. At the end of the Hard Reset sequence, the Hard

Reset Configuration stored in BCSR0 becomes valid.

3•2•4

DS1 - Software Options Switch

DS1 is a 4-switches Dip-Switch. This switch is connected over EXTOLI(0:3) lines which are available

at BCSR, S/W options may be manually selected, according to DS1 state.

FIGURE 3-1 DS1 - Description

1

2

3

4

EXTOLI0 Driven to ’0’

EXTOLI0 Pulled to ’1’

EXTOLI1 Pulled to ’1’

EXTOLI1 Driven to ’0’

EXTOLI2 Driven to ’0’

EXTOLI2 Pulled to ’1’

EXTOLI3 Pulled to ’1’

EXTOLI3 Driven to ’0’

DS1

3•2•5

GND Bridges

There are 3 GND bridges on the MPC8XXFADS. They are meant to assist general measurements

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and logic-analyzer connection.

Warning

When connecting to a GND bridge, use only INSU-

LATED GND clips. Failure in doing so, might result

in permanent damage to the MPC8XXFADS.

3•2•6

ETH ON - LD1

When the yellow ETH ON led is lit, it indicates that the ethernet port transceiver - the MC68160 EEST,

is active. When it is dark, it indicates that the EEST is in power down mode, enabling the use of its

associated SCC pins off-board via the expansion connectors.

3•2•7

IRD ON - LD2

When the yellow IRD ON led is lit, it indicates that the Infra-Red transceiver - the TFDS6000, is active

and enables communication via that medium. When it is dark, the I/R transceiver is in shutdown

mode, enabling the use of its associated SCC pins off-board via the expansion connectors.

3•2•8

RS232 Port 1 ON - LD3

When the yellow RS232 Port 1 ON led is lit, it designates, that the RS232 transceiver connected to

PA2, is active and communication via that medium is allowed. When darkened, it designates that the

transceiver is in shutdown mode, so its associated MPC pins may be used off-board via the expan-

sion connectors.

3•2•9

RS232 Port 2 ON - LD4

When the yellow RS232 Port 2 ON led is lit, it designates that the RS232 transceiver connected to

PB2,

is active and communication via that medium is allowed. When darkened, it designates, that the

transceiver is in shutdown mode, so its associated MPC pins may be used off-board via the expan-

sion connectors.

3•2•10 Ethernet RX Indicator - LD5

The green Ethernet Receive LED indicator blinks whenever the EEST is receiving data from one of

the Ethernet port.

3•2•11 Ethernet TX Indicator - LD6

The green Ethernet Receive LED indicator blinks whenever the EEST is transmitting data via the

Ethernet port.

3•2•12 Ethernet JABB Indicator - LD7

The red Ethernet TP Jabber LED indicator - JABB, lights whenever a jabber condition is detected on

the TP ethernet port.

3•2•13 Ethernet CLSN Indicator LD8

The red Ethernet Collision LED indicator CLSN, blinks whenever a collision condition is detected on

the ethernet port, i.e., simultaneous receive and transmit.

3•2•14 Ethernet PLR Indicator - LD9

The red Ethernet TP Polarity LED indicator - PLR, lights whenever the wires connected to the receiver

input of the ethernet port are reversed. The LED is lit by the EEST, and remains on while the EEST

has automatically corrected for the reversed wires.

3•2•15 Ethernet LIL Indicator - LD10

The yellow Ethernet Twisted Pair Link Integrity LED indicator - LIL, lights to indicate good link integrity

on the TP port. The LED is off when the link integrity fails.

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3•2•16 5V Indicator - LD11

The yellow 5V led, indicates the presence of the +5V supply at P6.

3•2•17 RUN Indicator - LD12

When the green RUN led - LD12 is lit, it indicates that the MPC is not in debug mode, i.e., VFLS0 &

VFLS1 == 0 (or FRZ == 0, which ever selected by J1).

3•2•18 AUXILARY Indicator LD13

This indication has no dedicated function over the FADS. It is meant to provide some visibility for

program behavior. It is controlled by the Signal Lamp bit in BCSR4.

3•2•19 FLASH ON - LD14

When the yellow FLASH ON led is lit, it indicates that the FLASH SIMM is enabled in the BCSR1

register. I.e., any access done to the CS0~ address space will hit the flash memory. When it is dark,

the flash is disabled and CS0~ may be used off-board via the expansion connectors.

3•2•20 DRAM ON - LD15

When the yellow DRAM ON led is lit, it indicates the DRAM SIMM is enabled in BCSR1. Therefore,

any access made to CS2~ (or CS3~) will hit on the DRAM. When it is dark, it indicates that either the

DRAM is disabled in BCSR1, enabling the use of CS2~ and CS3~ off-board via the expansion

connectors.

3•2•21 SDRAM ON - LD16

When the yellow SDRAM ON led is lit, it indicates the SDRAM is enabled in BCSR1. Therefore, any

access made to CS4~ (will hit on the SDRAM. When it is dark, it indicates that either the SDRAM is

disabled in BCSR1, enabling the use of CS4~ off-board via the expansion connectors.

3•2•22 PCMCIA ON - LD17

When the yellow PCMCIA ON led is lit, it indicates the following:

1) Address & strobe buffers are driven towards the PCMCIA card

A

B

2) Data buffers are driven to / from the PCMCIA card whenever CE1A~ or CE2A~ signals

are asserted.

3) Card status lines are driven towards the MPC from the PCMCIA card.

When it is dark, it indicates that all the above buffers are tri-stated and the pins associated with

C

PCMCIA channel A , may be used off-board via the expansion connectors.

3•3

MEMORY MAP

All accesses to MPC8XXFADS’s memories are controlled by the MPC’s memory controller.

Therefore, the memory map is reprogrammable to the desire of the user. After Hard Reset is

performed by the debug station, the debugger checks to see the size, delay and type of the DRAM

and FLASH SIMMs mounted on board and initializes the chip-selects accordingly. The DRAM,

A. Connected to CE1B~ for MPC823FADSDB.

B. Connected to CE2B~ for MPC823FADSDB.

C. Or B for MPC823FADSDB.

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SDRAM and the FLASH memory respond to all types of memory access i.e., user / supervisory,

program / data and DMA.

TABLE 3-1. MPC8XXADS Main Memory Map

Port

Size

ADDESS RANGE

Memory Type

DRAM SIMM

Device Type

a

00000000 - 003FFFFF

00400000 - 007FFFFF

00800000 - 00FFFFFF

01000000 - 01FFFFFF

02000000 - 020FFFFF

02100000 - 02103FFF

02100000 - 02103FE3

2100004 - 02103FE7

2100008 - 02103FEB

210000C - 02103FEF

2100010 - 02103FF3

02104000 - 021FFFFF

02200000 - 02207FFF

MB321Bx 08 MB322Bx 08

MC324Cx 00

MB328Cx 00

32

Empty Space

b

c

BCSR(0:4)

32

BCSR0

BCSR1

BCSR2

BCSR3

BCSR4

Empty Space

MPC Internal

32

d

MAP

02208000 - 027FFFFF

02800000 - 029FFFFF

02A00000 - 02BFFFFF

02C00000 - 02FFFFFF

03000000 - 033FFFFF

03400000 - FFFFFFFF

a. x [B,T]

Empty Space

Flash SIMM

MCM29F020 MCM29F040

MCM29F080

32

SM732A1000A SM732A2000

SDRAM

Empty Space

b. The device appears repeatedly in multiples of its size. E.g., BCSR0 appears at memory locations

2100000, 2100020, 2100040..., while BCSR1 appears at 2100004, 2100024, 2100044... and so on.

c. Only upper 16 bit (D0-D15) are in fact used.

d. Refer to the relevant MPC User’s Manual for complete description of the MPC internal memory map.

3•4

Programming The MPC Registers

The MPC provides the following functions on the MPC8XXFADS:

1) DRAM Controller

2) SDRAM Controller

3) Chip Select generator.

4) UART for terminal or host computer connection.

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5) Ethernet controller.

6) Infra-Red Port Controller

7) General Purpose I/O signals.

The internal registers of the MPC must be programmed after Hard reset as described in the following

paragraphs. The addresses and programming values are in hexadecimal base.

For better understanding the of the following initializations refer to the MPC821 or to the MPC860

User’s Manual for more information.

TABLE 3-2. SIU REGISTERS’ PROGRAMMING

Register

SIUMCR

Init Value[hex]

01032440

Description

Internal arbitration, External master arbitration priority - 0, External arbitration

priority - 0, PCMCIA channel II pins - PCMCIA, Debug Port on JTAG port pins,

FRZ/IRQ6~ - FRZ, debug register - locked, No parity for non-CS regions, DP(0:3)/

IRQ(3:6)~ pins - DP(0:3), reservation disabled, SPKROUT - Tri-stated, BS_A(0:3)~

and WE(0:3)~ are driven just on their dedicated pins, GPL_B5~ enabled, GPL_A/

B(2:3)~ function as GPLs.

SYPCR

FFFFFF88

Software watchdog timer count - FFFF, Bus-monitor timing FF, Bus-monitor -

Enabled, S/W watch-dog - Freeze, S/W watch-dog - disabled, S/W watch-dog (if

enabled) causes NMI, S/W (if enabled) not prescaled.

TBSCR

RTCSC

PISCR

00C2

0082

No interrupt level, reference match indications cleared, interrupts disabled, no

freeze, time-base disabled.

Interrupt request level - 0, 32768 Hz source, second interrupt disabled, Alarm

interrupt disabled, Real-time clock - FREEZE, Real-time clock enabled.

No level for interrupt request, Periodic interrupt disabled, clear status, interrupt

disabled, FREEZE, periodic timer disabled.

3•4•1

Memory Controller Registers Programming

The memory controller on the MPC8XXFADS is initialized to 50 MHz operation. I.e., registers’ pro-

gramming is based on 50 MHZ timing calculation except for refresh timer which is initialized to

16.67Mhz, the lowest frequency at which the FADS may wake up. Since the FADS may be made to

A

wake-up at 25MHz as well, the initializations are not efficient, since there are too many wait-states

inserted. Therefore, additional set of initialization is provided to support efficient 25MHz operation.

The reason for initializing the FADS for 50Mhz is to allow proper (although not efficient) FADS oper-

ation through all available FADS clock frequencies.

A. The only parameter which is initialized to the start-up frequency, is the refresh rate, which would have been

inadequate if initialized to 50Mhz while board is running at a lower frequency. Therefore, for best bus band-

width availability, refresh rate should be adapted to the current system clock frequency.

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Warning

Due to availability problems with few of the sup-

ported memory components, the below initializa-

tions were not tested with all parts. Therefore, the

below initializations are liable to CHANGE,

throughout the testing period.

TABLE 3-3. Memory Controller Initializations For 50Mhz

Register

BR0

Device Type

Init Value [hex]

SIMMs 02200001

Description

All

Flash

Base at 2200000, 32 bit port size, no parity, GPCM

supported.

OR0

MCM29F020-90

FFE00D34

FFC00D34

FF800D34

FFE00D44

FFC00D44

FF800D44

2MByte block size, all types access, CS early negate,

6 w.s., Timing relax

MCM29F040-90

SM732A1000A-9

4MByte block size, all types access, CS early negate,

6 w.s., Timing relax

MCM29F080-90

SM732A2000-9

8MByte block size, all types access, CS early negate,

6 w.s., Timing relax

MCM29F020-12

2MByte block size, all types access, CS early negate,

8 w.s., Timing relax

MCM29F040-12

SM732A1000A-12

4MByte block size, all types access, CS early negate,

8 w.s., Timing relax

MCM29F080-12

SM732A2000-12

8MByte block size, all types access, CS early negate,

8 w.s., Timing relax

BR1

OR1

BCSR

02100001

FFFF8110

Base at 2100000, 32 bit port size, no parity, GPCM

32 KByte block size, all types access, CS early

negate, 1 w.s.

BR2

OR2

All

Dram

SIMMs 00000081

Base at 0, 32 bit port size, no parity, UPMA

Supported

MCM36100/200-60/70

FFC00800

FF000800

4MByte block size, all types access, initial address

multiplexing according to AMA.

MCM36400/800-60/70

MT8/16D432/832X-6/7

16MByte block size, all types access, initial address

multiplexing according to AMA.

BR3

OR3

MCM36200-60/70

00400081

01000081

Base at 400000, 32 bit port size, no parity, UPMA

Base at 1000000, 32 bit port size, no parity, UPMA

MCM36800-60/70

MT16D832X-6/7

MCM36200-60/70

FFC00800

FF000800

4MByte block size, all types access, initial address

multiplexing according to AMA

MCM36800-60/70

MT16D832X-6/7

16MByte block size, all types access, initial address

multiplexing according to AMA.

BR4

OR4

MB811171622A-100

030000C1

FFC00A00

Base at 3000000, on UPM B

4 MByte block size, all types access, initial address

multiplexing according to AMB.

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TABLE 3-3. Memory Controller Initializations For 50Mhz

Register

MPTPR

Device Type

Init Value [hex]

SIMMs 0400

Description

Divide by 16 (decimal)

All

Dram

Supported

a

b

a

b

c

MAMR

MB321BT08TASN60

40A21114

60A21114

refresh clock divided by 40 or 60 or C0 , periodic

timer enabled, type 2 address multiplexing scheme, 1

cycle disable timer, GPL4 disabled for data sampling

edge ﬂexibility, 1 loop read, 1 loop write, 4 beats

refresh burst.

c

C0A21114

a

b

c

MB322BT08TASN60

MB324CT00TBSN60

MB328CT00TBSN60

MB811171622A-100

20A21114

30A21114

60A21114

refresh clock divided by 20 or 30 or 60 , periodic

timer

b

c

enabled, type 2 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

a

b

a

b

c

40B21114

60B21114

refresh clock divided by 40 or 60 or C0 , periodic

timer

c

C0B21114

enabled, type 3 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

a

b

c

20B21114

30B21114

60B21114

refresh clock divided by 20 or 30 or 60 , periodic

timer

b

c

enabled, type 3 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

c

MBMR

D0802114

refresh clock divided by D0 or 80, periodic timer

enabled, type 0 address multiplexing scheme, 1 cycle

disable timer, GPL4enabled, 1 loop read, 1 loop write,

4 beats refresh burst.

d

80802114

a. Assuming 16.67 MHz BRGCLK.

b. Assuming 25MHz BRGCLK

c. For 50MHz BRGCLK

d. Assuming 32MHz BRGCLK.

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TABLE 3-4. UPMA Initializations for 60nsec DRAMs @ 50MHz

Cycle Type

Single Read

0

Burst Read

8

Single Write

Burst Write

20

Refresh

Exception

Offset in UPM

18

30

3C

Contents

@ Offset +

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

8FFFEC24

0FFFEC04

0CFFEC04

00FFEC04

00FFEC00

37FFEC47

X

8FFFEC24

0FFFEC04

08FFEC04

00FFEC0C

03FFEC00

00FFEC44

00FFCC08

0CFFCC44

00FFEC0C

03FFEC00

00FFEC44

00FFCC00

3FFFC847

X

8FAFCC24

0FAFCC04

0CAFCC00

03AFCC4C

0CAFCC00

03AFCC4C

0CAFCC00

03AFCC4C

0CAFCC00

33BFCC4F

X

C0FFCC84

33FFCC07

0FAFCC04

00FFCC04

X

0CAFCC00

07FFCC04

11BFCC47

3FFFCC06

X

FFFFCC85

FFFFCC05

X

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TABLE 3-5. UPMA Initializations for 60nsec EDO DRAMs @ 50MHz

Cycle Type

Single Read

0

Burst Read

8

Single Write

Burst Write

20

Refresh

Exception

Offset in UPM

18

30

3C

Contents

@ Offset +

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

8FFBEC24

0FF3EC04

0CF3EC04

00F3EC04

00F3EC00

37F7EC47

X

8FFFEC24

0FFBEC04

0CF3EC04

00F3EC0C

0CF3EC00

00F3EC4C

0CF3EC00

00F3EC4C

0CF3EC00

00F3EC44

03F3EC00

3FF7EC47

X

8FFFCC24

0FEFCC04

0CAFCC00

03AFCC4C

0CAFCC00

03AFCC4C

0CAFCC00

03AFCC4C

0CAFCC00

33BFCC4F

X

C0FFCC84

33FFCC07

0FEFCC04

00FFCC04

X

0CAFCC00

07FFCC04

11BFCC47

3FFFCC06

X

FFFFCC85

FFFFCC05

X

TABLE 3-6. Memory Controller Initializations For 20Mhz

Register

BR0

Device Type

Init Value [hex]

SIMMs 02200001

Description

Base at 2200000, 32 bit port size, no parity, GPCM

All

Flash

supported.

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TABLE 3-6. Memory Controller Initializations For 20Mhz

Register

OR0

Device Type

Init Value [hex]

FFE00D20

Description

MCM29F020-90

2MByte block size, all types access, CS early negate,

2 w.s.

MCM29F040-90

SM732A1000A-9

FFC00D20

FF800920

FFE00D30

FFC00D30

FF800930

4MByte block size, all types access, CS early negate,

2 w.s.

MCM29F080-90

SM732A2000-9

8MByte block size, all types access, CS early negate,

2 w.s., Timing relax

MCM29F020-12

2MByte block size, all types access, CS early negate,

3 w.s.

MCM29F040-12

SM732A1000A-12

4MByte block size, all types access, CS early negate,

3 w.s.

MCM29F080-12

SM732A2000-12

8MByte block size, all types access, CS early negate,

3 w.s.

BR1

OR1

BCSR

02100001

FFFF8110

Base at 2100000, 32 bit port size, no parity, GPCM

32 KByte block size, all types access, CS early

negate, 1 w.s.

BR2

OR2

All

Dram

SIMMs 00000081

Base at 0, 32 bit port size, no parity, UPMA

Supported

MB321/2BT08TASN60

FFC00800

FF000800

4MByte block size, all types access, initial address

multiplexing according to AMA.

MB324/8CT00TBSN60

16MByte block size, all types access, initial address

multiplexing according to AMA.

a

BR3

MB322BT08TASN60

MB328CT00TBSN60

MB322BT08TASN60

00400081

01000081

FFC00800

Base at 400000, 32 bit port size, no parity, UPMA

Base at 1000000, 32 bit port size, no parity, UPMA

OR3

4MByte block size, all types access, initial address

multiplexing according to AMA

MB328CT00TBSN60

MB811171622A-100

FF000800

16MByte block size, all types access, initial address

multiplexing according to AMA.

BR4

OR4

030000C1

FFC00A00

Base at 3000000, on UPM B.

4MByte block size, all types access, initial address

multiplexing according to AMB

MPTPR

All

Dram

SIMMs 0400

Divide by 16 (decimal)

Supported

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TABLE 3-6. Memory Controller Initializations For 20Mhz

Register

MAMR

Device Type

Init Value [hex]

60A21114

Description

MB321BT08TASN60

refresh clock divided by 60, periodic timer enabled,

type 2 address multiplexing scheme, 1 cycle disable

timer, GPL4 disabled for data sampling edge ﬂexibility,

1 loop read, 1 loop write, 4 beats refresh burst.

MB322BT08TASN60

MB324CT00TBSN60

MB328CT00TBSN60

MB811171622A-100

30A21114

60B21114

30B21114

refresh clock divided by 30, periodic timer

enabled, type 2 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

refresh clock divided by 60, periodic timer

enabled, type 3 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

refresh clock divided by 30, periodic timer

enabled, type 3 address multiplexing scheme, 1 cycle

disable timer, GPL4 disabled for data sampling edge

ﬂexibility, 1 loop read, 1 loop write, 4 beats refresh

burst.

b

MBMR

42802114

refresh clock divided by 42, periodic timer enabled,

type 0 address multiplexing scheme, 1 cycle

disable timer, GPL4 enabled, 1 loop read, 1 loop write,

4 beats refresh burst.

a. BR3 is not initialized for MB321xx or MB324xx EDO DRAM SIMMs.

b. Assuming 16.67MHz BRGCLK

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TABLE 3-7. UPMA Initializations for 60nsec EDO DRAMs @ 20MHz

Cycle Type

Single Read

Burst Read

Single Write

Burst Write

Refresh

Exception

Offset in UPM

0

8

18

20

30

3C

Contents

@ Offset +

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

8FFFCC04

8FEFCC00

80FFCC84

33FFCC07

08FFCC00

08FFCC08

39BFCC47

09AFCC48

17FFCC04

X

33FFCC47

08FFCC08

X

09AFCC48

FFFFCC86

X

08FFCC08

09AFCC48

FFFFCC05

08FFCC00

39BFCC47

X

3FFFCC47

X

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TABLE 3-8. UPMB Initializations for MB811171622A-100 upto 32MHz

Cycle Type

Single Read

Burst Read

Single Write

Burst Write

Refresh

Exception

Offset In UPM

0

8

18

20

30

3C

Contents

@ Offset +

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0126CC04

0FB98C00

1FF74C47

X

0026FC04

0E26BC04

0E26BC00

1FF5FC84

7FFFFC07

10ADFC00

01B93C00

10AD7C00

FFFFFC04

X

F0AFFC00

1FF77C47

F0AFFC00

FFFFFC84

F1AFFC00

X

F0AFFC00

FFFFFC07

X

EFBBBC00

E1BBBC04

X

a

1FE77C34

1FF77C47

EFAABC34

1FA57C35

X

a. MRS initialization. Uses Free space.

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TABLE 3-9. UPMB Initializations for MB811171622A-100, 32+MHz - 50MHz

Cycle Type

Single Read

0

Burst Read

Single Write

Burst Write

Refresh

Exception

Offset In UPM

8

18

20

30

3C

Contents

@ Offset +

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

1F07FC04

EEAEFC04

11ADFC04

EFBBBC00

1FF77C47

1F07FC04

1F27FC04

1F07FC04

1FF5FC84

7FFFFC07

EEAEFC04

EEAEBC00

FFFFFC04

X

10ADFC04

01B93C04

10AD7C00

FFFFFC04

F0AFFC00

1FF77C47

F0AFFC00

FFFFFC04

F0AFFC00

X

F0AFFC00

FFFFFC84

a

1FF77C34

F1AFFC00

E1BBBC04

FFFFFC07

EFEABC34

1FB57C35

EFBBBC00

1FF77C47

X

1FF77C47

X

a. MRS initialization, Uses free space.

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Functional Description

4 - Functional Description

In this chapter the various modules combining the MPC8XXFADS are described to their design

details.

4•1

Reset & Reset - Configuration

There are several reset sources on the FADS:

A

1) Keep Alive Power-On Reset

2) Regular Power On Reset

3) Manual Soft-Reset

4) Manual Hard-Reset

5) MPC Internal Sources. (See the appropriate Spec or U/M)

4•1•1

Keep Alive Power-On Reset

The Keep Alive Power - On Reset logic resides on the daughter board this since the Keep Alive power

bus is on that board and it also allows the use of the daughter board connected directly to a user’s

application.

4•1•2

Regular Power - On Reset

The regular power on reset operates in the same manner as the keep alive power-on reset, using a

similar device - the Seiko - S-8052ANY-NH-X with detection voltage of 2.595V to 2.805V. The refer-

B

ence voltage of this device is the MAIN VDDH bus of the MPC while the reset line asserted , is the

HRESET* line.

When HRESET~ is asserted to the MPC, Hard-Reset configuration is made available to the MPC, via

BCSR0. See 4•1•6•2 "Hard Reset Configuration" on page 29 and TABLE 4-9. "BCSR0 Description"

on page 46.

4•1•3

Manual Soft Reset

To support application development not around the debug port and resident debuggers, a soft reset

push-button is provided. (SW2) Depressing that button, asserts the SRESET* pin of the MPC, gen-

erating a SOFT RESET sequence.

When the SRESET~ line is asserted to the MPC, the Soft-Reset configuration is made available to

the MPC, by the debug-port controller. See 4•1•6•3 "Soft Reset Configuration" on page 29.

4•1•4

Manual Hard Reset

To support application development not around the debug port, a Hard-Reset push-button is provid-

C

ed . When the Soft Reset push-button (SW2) is depressed in conjunction with the ABORT push-

button (SW1), the HRESET* line is asserted, generating a HARD RESET sequence. The button

sharing is for economy and board space saving and does not effect in any way, functionality.

4•1•5

MPC Internal Sources

Since the HRESET* and SRESET* lines of the MPC are open-drain and the on-board reset logic

drives these lines with open-drain gates, the correct operation of the internal reset sources of the

MPC is facilitated. As a rule, an internal reset source asserts HRESET* and / or SRESET* for a

minimum time of 512 system clocks. It is beyond the scope of this document to describe these

D

sources, however Debug-Port Soft / Hard Resets which are part of the development system , are

A. In fact generated on the daughter board.

B. Again not directly.

C. It is not a dedicated button.

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Functional Description

regarded as such.

4•1•6

Reset Configuration

During reset the MPC device samples the state of some external pins to determine its operation

modes and pin configuration. There are 3 kinds of reset levels to the MPC each level having its own

configuration sampled:

1) Power - On Reset configuration

2) Hard Reset configuration

3) Soft Reset Configuration.

4•1•6•1 Power - On Reset Configuration

Just before PORESET* is negated by the external logic, the power-on reset configuration which

include the MODCK(1:2) pins is sampled. These pins determine the clock operation mode of the

MPC. Two clock modes are supported on the MPC8XXFADS:

1) 1:5 PLL operation via on-board clock generator.

A

In this mode MODCK(1:2) are driven with ’11’ during power on reset.

2) 1:513 PLL operation via on-board clock generator.

In this mode MODCK(1:2) are driven with ’00’. during power-on reset.

4•1•6•2 Hard Reset Configuration

During HARD reset sequence, when RSTCONF* pin is asserted, the MPC data bus state is sampled

to acquire the MPC’s hard reset configuration. The reset configuration word is driven by BCSR0 reg-

ister, defaults of which are set during power-on reset. The BCSR0 drives half of the configuration

word, i.e., data bits D(0:15) in which the reserved bits are designated RSRVxx. If the hard-reset con-

B

figuration is to be changed , BCSR0 may be written with new values, which become valid after HARD

reset is applied to the MPC.

On the FADS, the RSTCONF* line is always driven during HARD reset, i.e., no use is possible with

the MPC’s internal HARD reset configuration defaults.

The system parameters to which BCSR0 defaults during power-on reset and are driven at hard-reset,

are listed below:

1) Arbitration: internal arbitration is selected.

2) Interrupt Prefix: The internal default is interrupt prefix at 0xFFF00000. It is overridden to

provide interrupt prefix at address 0, which is located within the DRAM.

3) Boot Disable: Boot is enabled.

4) Boot Port Size: 32 bit boot port size is selected.

5) Initial Internal Space Base: Immediately after HARD reset, the internal space is located at

$FF000000.

C

6) Debug pins configuration: PCMCIA port B pins become PCMCIA port B pins.

7) Debug port pins configuration. Debug port pins are on the JTAG port.

8) External Bus Division Factor: 1:1 internal to external clocks’ frequencies ratio is selected.

4•1•6•3 Soft Reset Configuration

The rising edge of SRESET* is used to configure the development port. Before the negation of

D

SRESET*, DSCK is sampled to determine for debug-mode enable / disable. After SRESET* is

D. And therefore mentioned.

A. The MODCK lines are in fact driven longer - by HRESET~ line.

B. With respect the FADS’s power-on defaults.

C. Where they exist.

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Functional Description

negated, if debug mode was enabled, DSCK is sampled again for debug-mode entry / non-entry.

DSDI is used to determine the debug port clock mode and is sampled after the negation of SRESET*.

The Soft Reset configuration is provided by the debug-port controller via the ADI I/F. Option is given

to enter debug mode directly or only after exception.

4•2

Local Interrupter

The only external interrupt which is applied to the MPC via its interrupt controller is the ABORT (NMI),

which is generated by a push-button. When this button is depressed, the NMI input to the MPC is

asserted. The purpose of this type of interrupt, is to support the use of resident debuggers if any is

made available to the FADS. All other interrupts to the MPC, are generated internally by the MPC’s

peripherals and by the debug port.

To support external (off-board) generation of an NMI, the IRQ0* line which is routed as an NMI input,

is driven by an open-drain gate. This allows for external h/w to also drive this line. If an external h/w

indeed does so, it is compulsory that IRQ0* is driven by an open-drain (or open-collector) gate.

4•3

Clock Generator^A

There are 2 ways to clock the MPC on the MPC8XXFADS:

B

1) 3 - 5MHz Clock generator connected to CLK4IN input. 1:5 PLL mode.

2) 32.768 KHz crystal resonator^Bvia EXTAL-XTAL pair of the MPC, 1:513 initial PLL multi-

plication factor.

The selection between the above modes is done using Dip-switch (DS2 / 4) with dual functionality: it

is responsible to the combination driven to the MODCK lines during power-on reset and to the con-

nection of the appropriate capacitor between MPC’s XFC and VDDSYN lines to match the PLL’s mul-

tiplication factor. When 1:5 mode is selected, a capacitor of 5nF is connected, while when 1:513 mode

is selected a 0.68µF capacitor is connected parallel to it via a TMOS gate. The capacitors’ values are

calculated to support a wider range of multiplication factors as possible.

When mode (2) above is selected, the output of the clock generator is gated from EXTCLK input and

driven to ’0’ constantly so that a jitter-free system clock is generated.

On-board logic is clocked by the MPC’s CLKOUT coming from the Daughter board. This clock is mul-

tiplexed with the debug port’s clock generator, so that on-board logic is always clocked, even when

C

the MPC is removed from its socket .

4•4

Buffering

As the FADS meant to serve also as a hardware development platform, it is necessary to buffer the

MPC from the local bus, so the MPC’s capacitive drive capability is not wasted internally and remains

available for user’s off-board applications via the expansion connectors.

D

Buffers are provided for address and strobe lines while transceivers are provided for data. Since the

E

capacitive load over dram’s address lines might exceed 200 pF, the dram address lines are sepa-

rately buffered. Use is done with 74LCX buffers which are 3.3V operated and are 5V tolerant. This

D. DSCK is configured at hard-reset to reside on the JTAG port.

A. Although this module resides on the DAUGHTER boards, it is described here, as it is common to all

MPC8XX supported.

B. Located On the Daughter Board.

C. When the FADS serves a debug station for target system.

D. If necessary.

E. Depended on dram SIMM’s internal structure.

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Functional Description

type of buffers reduces noise on board due to reduced transitions’ amplitude.

To further reduce noise and reflections, series resistors are placed over dram’s address and strobe

lines.

A B

The data transceivers open only if there is an access to a valid

board address or during Hard -

C

Reset configuration . That way data conflicts are avoided in case an off-board memory is read,

provided that it is not mapped to an address valid on board. It is the users’ responsibility to avoid such

errors.

4•5

Chip - Select Generator

D

The memory controller of the MPC is used as a chip-select generator to access on-board memories,

saving board’s area reducing cost, power consumption and increasing flexibility. To enhance off-

board application development, memory modules (including the BCSRx) may be disabled via

E

BCSR1 in favor of an external memory connected via the expansion connectors. That way, a CS

line may be used off-board via the expansion connectors, while its associated local memory is dis-

abled.

When a CS region is disabled via BCSR1, the local data transceivers do not open during access to

F

that region, avoiding possible contention over data lines.

The MPC’s chip-selects assignment to the various memories / registers on the FADS are as shown

in TABLE 4-1. "MPC8XXFADS Chip Selects’ Assignment" below:

TABLE 4-1. MPC8XXFADS Chip Selects’ Assignment

Chip Select:

CS0*

Assignment

Flash Memory

CS1*

BCSR

CS2*

DRAM Bank 1

DRAM Bank 2

SDRAM

a

CS3*

CS4*

CS(5-7)*

Unused, user available

a. If exists.

4•6

DRAM

The MPC8XXFADS is provided with 4 MBytes of 60nsec delay EDO Dram SIMM. Support is given

to any 5V powered FPM / EDO Dram SIMM configured as 1M X32 upto 2 X 4M X 32, with 60 nsec

or 70nsec delay.

All dram configurations are supported via the Board Control & Status Register (BCSR), i.e., DRAM

size (4M to 32M) and delay (60 / 70 nsec) are read from BCSR2 and the associated registers (includ-

A. An address which covered in a Chip-Select region.

B. Except for SDRAM, which is Unbuffered.

C. To allow a configuration word stored in Flash memory become active.

D. And off-board. See further.

E. After the BCSR is removed from the local memory map, there is no way to access it but to re-apply power to

the FADS.

F. During read cycles.

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Functional Description

ing the UPM) are programmed accordingly.

Dram timing control is performed by UPMA of the MPC via CS2 (and CS3 for a dual-bank SIMM) re-

A

gion(s), i.e., RAS and CAS signals’ generation, during normal access as well as during refresh

B

cycles and the necessary address multiplexing are performed using UPMA. CS2* and CS3* signals

are buffered from the DRAM and each is split to 2 to overcome the capacitive load over the Dram

SIMM RAS lines.

The DRAM module may enabled / disabled at any time by writing the DRAMEN~ bit in BCSR1. See

TABLE 4-10. "BCSR1 Description" on page 48.

4•6•1

DRAM 16 Bit Operation

To enhance evaluation capabilities, support is given to Dram with 16-bit and 32-bit data bus width.

That way users can tailor dram configuration, to get best fit to their application requirements. When

the DRAM is in 16 bit mode, half of it can not be used, i.e., the memory portion that is connected to

data lines D(16:31).

To configure the DRAM for 16 bit data bus width operation, the following steps should be taken:

1) Set the Dram_Half_Word bit in BCSR1 to Half-Word. See TABLE 4-10. "BCSR1 Descrip-

tion" on page 48

2) The Port Size bits of BR2~ (and of BR3~ for a 2-bank DRAM simm) should be set to 16 bits.

3) The AM bits in OR2 register should be set to 1/2 of the nominal single-bank DRAM simm

volume or to 1/4 of the nominal dual-bank DRAM simm volume.

If a Dual-Bank DRAM simm is being used:

4) The Base-Address bits in BR3 register should be set to DRAM_BASE + 1/4

Nominal_Volume, that is, if a contiguous block of DRAM is desired.

5) The AM bits of OR3 register, should be set to 1/4 Nominal_Volume.

If the above is executed out of running code, than this code should not reside on the DRAM while

executing, otherwise, erratic behavior is likely to be demonstrated, resulting in a system crash.

4•6•2

DRAM Performance Figures

The projected performance figures for the dram are shown in TABLE 4-2. "Regular DRAM Perfor-

A. Normal i.e.: Single Read, Single Write, Burst Read & Burst Write.

B. Taking into account support for narrower bus widths.

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Functional Description

mance Figures" on page 33 and in TABLE 4-3. "EDO DRAM Performance Figures" on page 33.

TABLE 4-2. Regular DRAM Performance Figures

Number of System Clock Cycles

System Clock Frequency [MHz]

DRAM Delay [nsec]

50

25

60

70

60

70

Single Read

Single Write

6

4

6

4

3

4

3

Burst Read

6,2,3,2

4,2,2,2

6,3,2,3

4,2,2,2

3,2,2,2

3,1,2,2

4,2,2,2

3,2,2,2

Burst Write

a b

Refresh

21

25

13

a. Four-beat refresh burst.

b. Not including arbitration overhead.

TABLE 4-3. EDO DRAM Performance Figures

Number of System Clock Cycles

System Clock Frequency [MHz]

DRAM Delay [nsec]

Single Read

50

25

60

70

60

70

6

4

6

4

3

2

4

Single Write

3

Burst Read

6,2,2,2

4,2,2,2

6,3,2,2

4,2,2,2

3,1,1,1

2,1,1,1

4,1,2,2

3,2,2,2

Burst Write

a b

Refresh

21

25

13

a. Four-beat refresh burst.

b. Not including arbitration overhead.

4•6•3

Refresh Control

The refresh to the dram is a CAS before RAS refresh, which is controlled by UPMA as well. The

refresh logic is clocked by the MPC’s BRG clock which is not influenced by the MPC’s low-power

divider.

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Functional Description

FIGURE 4-1 Refresh Scheme

BRG Clock

PTP

UPMB

PTB

DRAM BANKS

As seen in FIGURE 4-1 "Refresh Scheme" above, the BRG clock is twice divided: once by the PTP

(Periodic Timer Prescaler) and again by another prescaler - the PTA, dedicated for each UPM. If

there are more than one dram banks, than refresh cycles are performed for consecutive banks, there-

fore, refresh should be made faster. The formula for calculation of the PTA is given below:

Refresh_Period X Number_Of_Beats_Per_Refresh_Cycle

PTA =

Number_Of_Rows_To_Refresh X T_BRG X MPTPR X Number_Of_Banks

Where:

•

PTA - Periodic Timer A filed in MAMR. The value of the 2’nd divider.

Refresh_Period is the time (usually in msec) required to refresh a dram bank

Number_Of_Beats_Per_Refresh_Cycle: using the UPM looping capability, it is possible to

perform more than one refresh cycle per refresh burst (in fact upto 16).

•

Number_Of_Rows_To_Refresh: the number of rows in a dram bank

T_BRG: the cycle time of the BRG clock

MPTPR: the value of the periodic timer prescaler (2 to 64)

Number_Of_Banks: number of dram banks to refresh.

If we take for example a MCM36200 SIMM which has the following data:

•

Refresh_Period == 16 msec

Number_Of_Beats_Per_Refresh_Cycle: on the FADS it is 4.

Number_Of_Rows_To_Refresh == 1024

T_BRG == 20 nsec (system clock @ 50 Mhz)

MPTPR arbitrarily chosen to be 16

Number_Of_Banks == 2 for that SIMM

If we assign the figures to the PTA formula we get the value of PTA should be 97 decimal or 61 hex.

4•6•4

Variable Bus-Width Control

Since a port’s width determines its address lines’ connection scheme, i.e., the number of address

lines required for byte-selection varies (1 for 16-bit port and 2 for 32-bit port) according to the port’s

width, it is necessary to change address connections to a memory port if its width is to be changed.

E.g.: if a certain memory is initially configured as a 32-bit port, the list significant address line which

is connected to that memory’s A0 line should be the MPC’s A29. Now, if that port is to be reconfigured

as a 16-bit port, the LS address line becomes A30.

A

If a linear address scheme is to be maintained, all address lines connected to that memory are to

A. Consequent addresses lead to adjacent memory cells

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Functional Description

be shifted one bit, this obviously involves extensive multiplexing (passive or active). If linear address-

ing scheme is not a must, than only minimal multiplexing is required to support variable port width.

In TABLE 4-4. "DRAM ADDRESS CONNECTIONS" below, the FADS’s dram address connection

scheme is presented:

TABLE 4-4. DRAM ADDRESS CONNECTIONS

Width

32 - Bit

Depth

16 - Bit

Depth

Dram ADD

4 M

1 M

4 M

1 M

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA19

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA20

BA30

BA29

BA28

BA27

BA26

BA25

BA24

BA23

BA22

BA21

BA30

As can seen from the table above, most of the address lines remain fixed while only 2 lines (the

shaded cells) need switching. The switching scheme is shown in FIGURE 4-2 "DRAM Address Lines’

Switching Scheme" on page 35. The switches on that figure are implemented by active multiplexers

controlled by the BCSR1/Dram_Half_Word* bit.

FIGURE 4-2 DRAM Address Lines’ Switching Scheme

DRAM

BA(21:29)

A(0:8)

BA20

A9

BA30

BA19

A10

BA30

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Flash Memory SIMM

Functional Description

4•7

The MPC8XXFADS is provided with 2Mbyte of 90 nsec flash memory SIMM - the MCM29020 by Mo-

torola. Support is given also to 4MBytes MCM29F040, 8 MBytes MCM29F080, 4 MBytes SM73218

and to 8 MBytes SM73228 by Smart Technology. The Motorola SIMMs are internally composed of 1,

2 or 4 banks of 4 Am29F040 compatible devices, while the Smart SIMMs are arranged as 1 or 2

banks of four 28F008 devices by Intel. The flash SIMM resides on an 80 pin SIMM socket.

To minimize use of MPC’s chip-select lines, only one chip-select line (CS0~) is used to select the

flash as a whole, while distributing chip-select lines among the internal banks is done via on-board

programmable logic, according to the Presence-Detect lines of the Flash SIMM inserted to the FADS.

FIGURE 4-3 Flash Memory SIMM Architecture

Flash Presence-Detect Lines

ADD

M29F040 or

1M X 8

M29F040 or

1M X8

M29F040 or

1M X 8

M29F040 or

1M X 8

F_CS1~

F_CS2~

M29F040 or

1M X 8

M29F040 or

1M X 8

M29F040 or

1M X 8

M29F040 or

1M X 8

FADS’s

Logic

CS0~

M29F040

F_CS3~

F_CS4~

DATA

MCM29F020

SM73218

MCM29F040

SM73228

MCM29F080

The access time of the Flash memory provided with the FADS is 90 nsec, however, 120 nsec devices

may be used as well. Reading the delay section of the Flash SIMM Presence-Detect lines, the

debugger establishes (via OR0) the correct number of wait-states (considering 50MHz system clock

frequency).

The Motorola SIMMs are built of AMD’s Am29F0X0 devices which are 5V programmable, i.e., there

A

is no need for external programming voltage and the flash may be written almost as a regular

memory.

The SMART parts however, require 12V ± 0.5% programming voltage to be applied for programming.

If on-boards programming of such device is required, a 12V supply needs to be connected to the

B

FADS (P7). Otherwise, for normal Flash operation, 12V supply is not required.

The control over the flash is done using the GPCM and a dedicated CS0~ region, controlling the

whole bank. During hard - reset initializations, the debugger reads the Flash Presence-Detect lines

via BCSR2 and decides how to program BR0 & OR0 registers, within which the size and the delay of

the region are determined.

A. A manufacturer specific dedicated programming algorithm should be implemented during flash program-

ming.

B. I.e., Read-Only.

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Functional Description

The performance of the flash memory is shown in TABLE 4-5. "Flash Memory Performance Figures"

below:

TABLE 4-5. Flash Memory Performance Figures

Number of System Clock Cycles

System Clock Frequency [MHz]

Flash Delay [nsec]

50

25

90

8

120

10

90

4

120

5

a

Read / Write Access [Clocks]

a. The figures in the table refer to the actual write access. The write operation continues internally

and the device has to be polled for operation completion.

The Flash module may disabled / enabled at any time by writing ’1’ / ’0’ the FlashEn~ bit in BCSR1.

4•8

Synchronous Dram

To enhance performance, especially in higher operation frequencies - 4 MBytes of SDRAM is

provided on board. The SDRAM is unbuffered from the MPC bus and is configured as 2 X 512K X

32. Use is done with two MB811171622A-100 chips by Fujitsu or compatibles.

To enhance performance, the SDRAM is unbuffered from the MPC, saving the delay associated with

address and data buffers. Since only 2 memory chips are involved, it does not adversely effect overall

system performance. The SDRAM does not reside on a SIMM but is soldered directly to the FADS

pcb. The SDRAM may be enabled / disabled at any time by writing 1 / 0 to the SDRAMEN bit in

BCSR1. See TABLE 4-10. "BCSR1 Description" on page 48.

The SDRAM’s timing is controlled by UPMB via its assigned CS (See TABLE 4-1. "MPC8XXFADS

Chip Selects’ Assignment" on page 31) line. Unlike a regular dram the synchronous dram has a CS

input in addition to the RAS and CAS signals.

The sdram connection scheme is shown in FIGURE 4-4 "SDRAM Connection Scheme" on page 38.

The SDRAM’s performance figures, are shown in TABLE 4-6. "Estimated SDRAM Performance Fig-

ures":

TABLE 4-6. Estimated SDRAM Performance Figures

Number of System Clock Cycles

System Clock Frequency [MHz]

50

25

Single Read

Single Write

Burst Read

Burst Write

Refresh

5

3

a

3+1

2 + 1

5,1,1,1

3,1,1,1

a

3,1,1,1 + 1

2,1,1,1 + 1

b

21

13

a. One additional cycle for RAS precharge

b. 4-beat Refresh Burst, not including arbitration overhead.

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Functional Description

FIGURE 4-4 SDRAM Connection Scheme

CS4

CS

GPL1

RAS

GPL2

GPL3

A10

CAS

W

CAS

W

A11

GPL0 (A11)

A10

A(20:21)

A(22:29)

SDRAMEN

SYSCLK

BS0_B

A(9:8)

A(7:0)

CKE

A(9:8)

A(7:0)

CKE

CLK

DQMU

DQML

DQMU

DQML

BS1_B

DQ(15:0)

D(0:15)

BS2_B

BS3_B

D(16:31)

4•8•1

SDRAM Programming

After power-up, the sdram needs to be initialized by means of programming, to establish its mode of

operation. Sdram is programmed by issuing a Mode Register Set command. During that command

data is passed to the Mode Register through the sdram’s address lines. This command is fully sup-

ported by the UPM by means of a dedicated Memory Address Register and a UPM command run

option.

Mode Register programming values are shown in TABLE 4-7. "SDRAM’s Mode Register Program-

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ming" below:

TABLE 4-7. SDRAM’s Mode Register Programming

Value @ Frequency

SDRAM Option

Burst Length

50MHz

25MHz

4

Sequential

2

4

Sequential

1

Burst Type

CAS Latency

Write Burst Length

Burst

4•8•1•1 SDRAM Initializing Procedure

After Power-up the SDRAM needs to be initialized in a certain manner, described below:

1) UPMB should be programmed with values described in TABLE 3-8. "UPMB Initializations

for MB811171622A-100 upto 32MHz" on page 26 or in TABLE 3-9. "UPMB Initializations

for MB811171622A-100, 32+MHz - 50MHz" on page 27.

2) Memory controller’s MPTPR, MBMR, OR4 and BR4 registers should be programmed ac-

cording to TABLE 3-6. "Memory Controller Initializations For 20Mhz" on page 22 or TABLE

3-3. "Memory Controller Initializations For 50Mhz" on page 19.

3) MAR should be set with proper value (0x48 for upto 32MHz or 0x88 for 32 - 50 MHz)

4) MCR should be written with 0x80808105 to run the MRS command programmed in loca-

tions 5 - 8 of UPMB.

5) MBMR’s TLFB field should be changed to 8, to constitute 8-beat refresh Bursts.

6) MCR should be written with 0x80808130 to run the refresh sequence (8 refresh cycles are

performed now)

7) MBMR’s TLFB field should be restored to 4, to provide 4-beat refresh Bursts for normal op-

eration. The SDRAM is initialized and ready for operation.

4•8•2

SDRAM Refresh

The SDRAM is refreshed using its auto-refresh mode. I.e., using UMPB’s periodic timer, a burst of

four auto-refresh commands is issued to the SDRAM every 62.4 µsec, so that all 2048 SDRAM rows

are refreshed within specified 32.8 msec.

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Communication Ports

Functional Description

4•9

Since the FADS platform is meant to serve all the MPC8XX family, it only contains modules that are

common to all family members. The various communication ports for the present and future family

members are shown in TABLE 4-8. "MPC8XX Family Comm. Ports" below:

TABLE 4-8. MPC8XX Family Comm. Ports

Family Member - MPC

Comm.

Port

801

823

821

860

860SAR

860T

SCC1

Uart, IrDA USB

✓ +Enet

SCC2

Uart, IrDA ✓ +Enet,

✓ +IrDA

✓ +Enet,

Fast IrDA

IrDA

SCC3

SCC4

SMC1

SMC2

✓ +Enet

✓ Uart

✓ +Enet

✓ Uart

✓ +Enet

✓ Uart

✓ TDM

Only

a

SPI

✓

2

I C^a

Fast Enet

Utopia

✓

a. This is an interchip protocol and therefore will not be supported for evaluation.

A

As can be seen from the above table the Ethernet, I/R and Uart (RS232) support are common to all

family members. Therefore, the FADS is equipped with 2 port of RS232, each with independent

enable via BCSR and an IRDA transceiver, supporting Fast IRDA.

4•9•1

Ethernet Port

An Ethernet port with T.P. (10-Base-T) I/F is provided on the MPC8XXFADS. The comm. port over

B

which this port resides, is determined according to the MPC type . Use is done with the MC68160

EEST 10-base-T transceiver, used also with the MPC8XXFADS.

To allow alternative use of the Ethernet’s SCC pins, they appear at the expansion connectors over

the daughter-board and over the Comm. Ports expansion connector (P8) of the this board, while the

Ethernet transceiver may be Disabled / Enabled at any time by writing ’1’ / ’0’ to the EthEn~ bit in

BCSR1.

4•9•2

Infra-Red Port

An infra-Red communication port is provided with the FADS - the Temic’s TFDS 6000 integrated

transceiver, which incorporates both the receiver and transmitter optical devices with the translating

logic and supports Fast IrDA (upto 4 Mbps). The comm. port over which this port resides, is deter-

A. Except for the MPC801 which does not have Ethernet support.

B. I.e., routing is done on the daughter board.

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Functional Description

mined according to the MPC type^B.

To allow alternative use of the I/R’s SCC or its pins, the infra-red transceiver may be disabled /

enabled at any time, by writing ’1’ / ’0’ to the IrdEn~ bit in BCSR1, while all pins appear on the

daughter-board expansion connector, as well as on P8 of this board.

4•9•2•1 Infra-Red Port Rate Range Selection

The TFDS6000 has 2 bit-rate ranges:

1) 9600 Bps to 1.2 MBps

2) 1.2 MBps to 4 MBps.

Selection between the 2 ranges is determined by the state of the transceiver’s TX input on the falling

edge of IrdEn~.

When TX input is LOW at least 200 nsec before the falling edge of IrdEn~, then, the LOWER range

is selected. If TX is HIGH for that period of time, then, the HIGHER range is selected.

4•9•3

RS232 Ports

To assist user’s applications and to provided convenient communication channels with both a

terminal and a host computer, two identical RS232 ports are provided on the FADS. The MPC’s com-

munication ports to which these RS232 ports is routed, is established according to the type of MPC

residing on the daughter board. Use is done with MC145707 transceivers which generates RS232

levels internally using a single 5V supply and are equipped with OE and shutdown mode. When the

RS232EN1 or RS232EN2 bits in BCSR1 are asserted (low), the associated transceiver is enabled.

When negated, the associated transceiver enters standby mode, in which the receiver outputs are tri-

stated, enabling use of the associated port’s pins, off-board via the expansion connectors.

Use is done with 9 pins, female D-Type stacked connector, configured to be directly (via a flat cable)

connected to a standard IBM-PC like RS232 connector.

FIGURE 4-5 RS232 Serial Ports’ Connector

DCD

1

6

DSR

TX

2

3

4

5

7 RTS

8

9

TX

CTS

N.C.

DTR

GND

4•9•3•1 RS-232 Ports’ Signal Description

In the list below, the directions ’I’, ’O’, and ’I/O’ are relative to the FADS board. (I.e. ’I’ means input to

the FADS)

•

CD ( O ) - Data Carrier Detect. This line is always asserted by the FADS.

TX ( O ) - Transmit Data.

RX ( I ) - Receive Data.

DTR ( I ) - Data Terminal Ready. This signal may be used by the software on the FADS to

detect if a terminal is connected to the FADS board.

A

•

DSR ( O ) - Data Set Ready. This line is always asserted by the FADS.

RTS ( I ) - Request To Send. This line is not connected in the FADS.

CTS ( O ) - Clear To Send. This line is always asserted by the FADS.

A. Since there are only 3 RS232 transmitters in the device, DSR is connected to CD.

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PCMCIA Port^A

Functional Description

4•10

To enhance PCMCIA i/f development, a dedicated PCMCIA port is provided on the FADS. Support

is given to 5V only PC-Cards, PCMCIA standard 2.1+ compliant. All the necessary control signals are

generated by the MPC itself. To protect MPC signals from external hazards, and to provide sufficient

drive capability, a set of buffers and latches is provided over PC-Card’s address, data & strobe lines.

To conform with the design spirit of the FADS, i.e., making as much as possible MPC resources avail-

able for external application development, input buffers are provided for input control signals, con-

trolled by the PCC_EN~ bit in BCSR1, so the PCMCIA port may be Disabled / Enabled at any time,

by writing ’1’ / ’0’ to that bit. When the PCMCIA channel is disabled, its associated pins are available

for off-board use via the expansion connectors.

A loudspeaker is provided on board and connected to SPKROUT line of the MPC. The speaker is

buffered from the MPC and low-pass filtered. When the PCC_EN~ bit in BCSR1 is negated (high) the

speaker buffer is tri-stated so the SPKROUT signal of the MPC may be used for alternate function.

B

Since it is not desirable to apply control signals to unpowered PC-Card, the strobe / data signal

buffers / transceivers are tri-stated and may be driven only when the PC-Card is powered.

The block diagram of the PCMCIA port is shown in FIGURE 4-6 "PCMCIA Port Configuration" on

page 43.

A. As the MPC801 does not have a PCMCIA port, this port is not operational with an MPC801 daughter board.

B. This since the PC-Card might have protection diodes on its inputs, which will force down input signals re-

gardless of their driven level.

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Functional Description

FIGURE 4-6 PCMCIA Port Configuration

PCMCIA SOCKET

PCCVCC

1

Power Logic

PCMCIA POWER CONTROL

PCCVPP

1

From BCSR

LTC1315

or equiv.

1

5V 12V

D[8:15]

Data_A[15:8]

8

D[0:7]

Data_A[7:0]

8

OE

From BCSR

PCMCIA_EN

1

R/W

CE1

1

CE1_A(B)

CE2_A(B)

1

CE2

1

WE/PGM

1

OE

1

2

IORD,IOWR

RESET_A(B)

IORD,IOWR

2

1

RESET

1

buffer

with OE

1

POE_A(B)

MPC8XX

On Daughter - Board

Transparent latch

with OE

A[6:31]

REG

Address_A[25:0]

REG

26

1

26

1

ALE_A(B)

VDD

1

2

OE

WAIT_A(B), IOIS16_A(B)

2

RDY/BSY_A(B), BVD(1:2)_A(B)

VDD

3

5

3

VDD

CD(1:2)_A(B),VS(1:2)_A(B)

4

SPKROUT

1

LPF

4•10•1 PCMCIA Power Control

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Functional Description

A

To support hot-insertion the socket’s power is controlled via a dedicated PCMCIA power controller

the LTC1315 made by LINEAR TECHNOLOGY. This device, controlled by BCSR1, switches 12V

VPP for card programming and controls gates of external MOSFET transistors, through which the PC

Card VCC is switched.

When a card is inserted while the channel is enabled via BCSR1, i.e., both of the CD(1:2)* (Card

Detect) lines are asserted (low), the status of the voltage select lines VS(1:2)* should be read to de-

termine the PC Card’s operation voltage level according to which, PCCVCC(0:1) bits in BCSR1

should be set, to drive the correct VCC (5V) to the PC-Card.

When a card is being removed from the socket while the channel is enabled via BCSR1, the negation

of CD1~ and CD2~ may be sensed by the MPC and power supply to the card may be cut.

WARNNING

Any application S/W handling the PCMCIA channel

must check the Voltage-Sense lines before Power

is applied to the PC-Card. Otherwise, if 5V power is

applied to a 3.3V-Only card, permanent damage will

be inflicted to the PC-Card.

4•11

Board Control & Status Register - BCSR

Most of the hardware options on the MPC8XXFADS are controlled or monitored by the BCSR, which

B

is a 32 bit wide read / write register file. The BCSR is accessed via the MPC’s CS1 region and in

fact includes 5 registers: BCSR0 to BCSR4. Since the minimum block size for a CS region is

32KBytes, BCSR0 - BCSR4 are multiply duplicated within that region. See also TABLE 3-1.

"MPC8XXADS Main Memory Map" on page 17.

The following functions are controlled / monitored by the BCSR:

1) MPC’s Hard Reset Configuration.

2) Flash Module Enable / Disable

3) Dram Module Enable / Disable

4) Dram port width - 32 bit / 16 bit.

5) SDRAM Module Enable / Disable.

6) Ethernet port Enable / Disable.

7) Infra-Red port Enable / Disable.

8) RS232 port 1 Enable / Disable.

9) RS232 port 2 Enable / Disable.

10) BCSR Enable / Disable.

C

11) Hard Reset Configuration Source - BCSR0 / Flash Memory

12) PCMCIA control which include:

•

Channel Enable / Disable.

PC Card VCC appliance.

PC Card VPP appliance.

D

E

F

13) USB Port Enable or Utopia Port Enable or 100-Base-T Port Enable

A. I.e., card insertion when the FADS is powered

B. In fact only the upper 16 bits - D(0:15) are used, but the BCSR is mapped as a 32 bit wide register and should

be accessed as such.

C. Provided that support is provided also within the MPC.

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Functional Description

14) USB Power Control.

15) Video Port Enable

16) Video Port Clock Select

17) Ethernet Port Control.

18) Dram Type / Size and Delay Identification.

19) Flash Size / Delay Identification.

20) External (off-board) tools identification or S/W option selection switch - DS1 status.

21) Daughter Board ID.

22) Mother Board Revision code

23) Daughter Board Revision code

Since all of the FADS’s modules are controlled by the BCSR and since they may be disabled in favor

of external hardware, the enable signals for these modules are presented at both the daughter board

connector and at the expansion connector over the daughter board, so that off- board hardware may

be mutually exclusive enabled with on-board modules.

4•11•1 BCSR Disable Protection Logic

The BCSR itself may be disabled in favor of off-board logic. To avoid accidental disable of the BCSR,

an event from which only power re-appliance recovers, protection logic is provided:

The BCSR_EN~ bit resides on BCSR1. This bit wakes-up active (low) during power-up and may not

A

be changed unless BCSR_EN_PROTECT~ bit in BCSR3 is written with ’1’ previously.

After the BCSR_EN_PROTECT~ is written with ’1’ to unprotect the BCSR_EN~ bit there is only one

shot at disabling the BCSR, since, immediately after any write to BCSR1, BCSR_EN_PROTECT~ is

re-activated and BCSR_EN~ is re-protected and the disabling procedure has to be repeated if

desired.

4•11•2 BCSR0 - Hard Reset Configuration Register

B

BCSR0 is located at offset 0 on BCSR space. It may be read or written at any time . BCSR0 gets its

C

defaults upon MAIN Power-On reset. During Hard-Reset data contained in BCSR0 is driven on the

data bus to provide the Hard-Reset configuration for the MPC, this, if the

Flash_Configuration_Enable~ bit in BCSR1 is not active. BCSR0 may be written at any time to

change the Hard-Reset configuration of the MPC. The new values become valid when the next Hard-

Reset is issued to the MPC regardless of the Hard-Reset source. The description of BCSR0 bits is

D. For the MPC823 daughter board

E. For the MPC860SAR daughter board

F. For the MPC860T daughter board

A. It may be written but will not be influenced.

B. Provided that BCSR is not disabled.

C. I.e., when VDDH to the MPC is powered.

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Functional Description

shown in TABLE 4-9. "BCSR0 Description" on page 46.

TABLE 4-9. BCSR0 Description

PON

DEF.

0

BIT

MNEMONIC

FUNCTION

ATT

0

1

ERB

External Arbitration. When ’0’ during Hard-Reset, Arbitration is performed

internally. When ’1’ during Hard-Reset, Arbitration is performed externally.

R,W

IP

Interrupt Preﬁx. When ’0’ during Hard-Reset, Interrupt preﬁx set to

0xFFF00000, if ’1’ Interrupt Preﬁx set to 0.

0

a

2

3

Reserved

BDIS

Implemented

0

R,W

Boot Disable. When ’0’ during Hard-Reset, CS0~ region is enabled for boot.

When ’1’, CS0~ region is disabled for boot.

4 - 5

BPS(0:1)

Boot Port Size. Determines the port size for CS0~ at boot. ’00’ - 32 bit, ’01’ - ’00’

8 bit, ’10’ - 16 bit, ’11’ - reserved.

R,W

a

6

Reserved

ISB(0:1)

Implemented

0

R,W

7 - 8

Initial Space Base. Value during Hard-Reset determines the initial base ’10’

address of the internal MPC memory map. When ’00’ - initial space at 0,

when ’01’ - initial space at 0x00F00000, when ’10’ - initial space at

0xFF000000, when ’11’ - initial space at 0xFFF00000.

9 - 10

11-12

DBGC(0:1)

DBPC(0:1)

Debug Pins Conﬁguration. Value during Hard-Reset determines the ’11’

function of the PCMCIA channel II pins. When ’00’ - these pins function as

PCMCIA channel II pins, when ’01’ - they serve as Watch-Points,’10’ -

Reserved, when ’11’ - they become show-cycle attribute pins, e.g., VFLS,

VF...

R,W

Debug Port Pins Conﬁguration. Value during Hard-Reset determines the ’00’

location of the debug port pins. When ’00’ - debug port pins are on the JTAG

port, when ’01’ - debug port non-existent, ’10’ - Reserved, when ’11’ debug

port is on PCMCIA channel II pins.

R,W

b

13 - 14 EBDF(0:1)

External Bus Division Factor. Value during Hard Reset determines the ’00’

factor upon which the CLKOUT of the MPC external bus, is divided with

respect to its internal MPC clock. When ’00’ - CLKOUT is GCLK2 divided by

1, when ’01’, CLKOUT is GCLK2 divided by 2.

a

15

Reserved

Implemented .

’0’

-

R,W

-

16 - 31 Reserved

Un-Implemented

a. May be read and written as any other fields and are presented at their associated data pins during Hard-Reset.

b. Applicable for MPC’s revision A or above. Otherwise have no influence.

4•11•3 BCSR1 - Board Control Register 1

The BCSR1 serves as a control register on the FADS. It is accessed at offset 4 from BCSR base

A

address. It may be read or written at any time . BCSR1 gets its defaults upon Power-On reset. Most

of BCSR1 pins are available at the daughter board connectors and on the expansion connectors

A. Provided that BCSR is not disabled.

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Functional Description

residing over the daughter boards, providing visibility towards daughter boards’ and external logic.

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Functional Description

BCSR1 fields are described in TABLE 4-10. "BCSR1 Description" on page 48.

a

TABLE 4-10. BCSR1 Description

PON

DEF

0

BIT

MNEMONIC

FLASH_EN

Function

ATT.

R,W

0

1

Flash Enable. When this bit is active (low), the Flash memory module is

enabled on the local memory map. When in-active, the Flash memory is

removed from the local memory map and CS0~, to which the Flash memory

is connected may be used off-board via the expansion connectors.

DRAM_EN

Dram Enable. When this bit is active (low), the DRAM module is enabled

0

R,W

on the local memory map. When in-active, the DRAM is removed from the

b

local memory map and CS2~ and CS3~ , to which the DRAM is connected

may be used off-board via the expansion connectors.

2

3

ETHEN

IRDEN

Ethernet Port Enable. When asserted (low) the EEST connected to SCC1

is enabled. When negated (high) that EEST is in standby mode, while all its

system i/f signals are tri-stated.

1

R,W

Infra-Red Port Enable. When asserted (low), the Infra-Red transceiver,

connected to SCC2 is enabled. When negated, the Infra-Red transceiver is

put in shutdown mode. And SCC2 pins are available for off-board use via

the expansion connectors.

4

5

FLASH_CFG_EN

Flash Conﬁguration Enable. When this bit is asserted (low): (A) - the

Hard-Reset conﬁguration held in BCSR0 is NOT driven on the data bus

during Hard-Reset and (B) - conﬁguration data held at the 1’st word of the

1

0

R,W

R

c

ﬂash memory is driven to the data bus during Hard-Reset.

CNT_REG_EN_P

ROTECT

Control Register Enable Protect. When this bit is active (low) the

BCSR_EN bit in that register can not be written. When in-active, BCSR_EN

may be written to remove the BCSR from the memory map. After any write

d

to BCSR1 this bit becomes active again. This bit is a read-only bit on that

register.

6

BCSR_EN

BCSR Enable. When this bit is active (low) the Board Control & Status

Register is enabled on the local memory map. When inactive, the BCSR

may not be read or written and its associated CS1~ is available for off-board

use via the expansion connectors.

0

R,W

This bit may be written with ’1’ only if CNT_REG_EN_PROTECT bit is

negated (1).

When the BCSR is disabled it still continues to conﬁgure the board

according the last data held in it even during Hard-Reset.

7

8

9

RS232EN_1

PCCEN

RS232 port 1 Enable. When asserted (low) the RS232 transceiver for port

1, is enabled. When negated, the RS232 transceiver for port 1, is in standby

mode and the relevant MPC communication port pins are available for off-

board use via the expansion connectors.

1

0

R,W

PC Card Enable. When asserted (low), the on-board PCMCIA channel is

enabled, i.e., address and strobe buffers are enabled to / from the card.

When negated, all buffers to / from the PCMCIA channel are disabled

allowing off-board use of its associated lines.

PCCVCC0

Pc Card VCC Select 0. These signal in conjunction with PCCVCC1

determine the voltage applied to the PCMCIA card’s VCC. Possible values

are 0 / 3.3 / 5 V. For the encoding of these lines and their associated

voltages see TABLE 4-11. "PCCVCC(0:1) Encoding" on page 49.

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Functional Description

a

TABLE 4-10. BCSR1 Description

PON

ATT.

DEF

BIT

MNEMONIC

Function

10 - 11 PCCVPP(0:1)

PC Card VPP. These signals determine the voltage applied to the PCMCIA

card’s VPP. Possible values are 0 / 5 / 12 V. For the encoding of these lines

and their associated voltages see TABLE 4-12. "PCCVPP(0:1)

Encoding" on page 49.

’11’

R,W

12

13

Dram_Half_Word

RS232EN_2

Dram Half Word. When this bit is active (low) and the steps listed in 4•6•1

"DRAM 16 Bit Operation" on page 32, are taken, the DRAM becomes

16 bit wide. When inactive the DRAM is 32 bit wide.

1

R,W

RS232 port 2 Enable. When asserted (low) the RS232 transceiver for port

2, is enabled. When negated, the RS232 transceiver for port 2, is in standby

mode and the relevant MPC communication port pins are available for off-

board use via the expansion connectors.

14

15

SDRAMEN

PCCVCC1

SDRAM Enable. When this bit is active (high), the SDRAM module is

enabled on the local memory map. When in-active, the DRAM is place in

low-power mode, in fact removed from the local memory map, allowing its

associated CS line, to be used off-board via the expansion connectors.

1

0

-

R,W

-

Pc Card VCC Select 1. These signal in conjunction with PCCVCC0

determine the voltage applied to the PCMCIA card’s VCC. Possible values

are 0 / 3.3 / 5 V. For the encoding of these lines and their associated

voltages see TABLE 4-11. "PCCVCC(0:1) Encoding" on page 49.

16 - 31 Reserved

Un-implemented

a. Shaded areas are additions with respect to the MPC8XXFADS.

b. In case a Single Bank DRAM SIMM is used CS3~ is free as well.

c. Provided that this option is supported by the MPC by driving address lines low and asserting

CS0~ during Hard-Reset.

d. It is written in BCSR3.

TABLE 4-11. PCCVCC(0:1) Encoding

PC-Card VCC

PCCVCC(0:1)

[V]

00

01

10

11

0

5

3.3

0

TABLE 4-12. PCCVPP(0:1) Encoding

PC Card VPP

PCCVPP(0:1)

[V]

00

0

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TABLE 4-12. PCCVPP(0:1) Encoding

PC Card VPP

PCCVPP(0:1)

[V]

01

10

11

5

a

12

Hi-Z

a. Provided that a 12V

power supply is applied.

4•11•4 BCSR2 - Board Control / Status Register - 2

BCSR2 is a status register which is accessed at offset 8 from the BCSR base address. Its a read only

A

register which may be read at any time . BCSR2’s various fields are described in TABLE 4-13.

A. Provided that BCSR is not disabled.

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Functional Description

"BCSR2 Description" on page 51.

a

TABLE 4-13. BCSR2 Description

PON

ATT.

DEF

BIT

MNEMONIC

Function

0 - 3

FLASH_PD(4:1)

Flash Presence Detect(4:1). These lines are connected to the Flash SIMM

presence detect lines which encode the type of Flash SIMM mounted on the

Flash SIMM socket. There are additional 3 presence detect lines which

encode the SIMM’s delay but appear in BCSR3. For the encoding of

FLASH_PD(4:1) see TABLE 4-14. "Flash Presence Detect (4:1)

Encoding" on page 51.

-

R

4

Reserved

Un-implemented

-

5 - 8

DRAM_PD(4:1)

Dram Presence Detect. These lines are connected to the DRAM SIMM

presence detect lines which encode the size and the delay of the DRAM

SIMM mounted on the DRAM SIMM socket. For the encoding of

DRAM_PD(4:1) see TABLE 4-15. "DRAM Presence Detect (2:1)

Encoding" on page 52 and TABLE 4-16. "DRAM Presence Detect

(4:3) Encoding" on page 52.

R

9 - 12

EXTTOLI(0:3)

External Tools Identiﬁcation. These lines, which are available at the

expansion connectors over the daughter board, are intended to serve as

tools’ identiﬁer or as S/W option selection. On board s/w may check these

lines to detect The presence of various tools (h/w expansions) at the

expansion connectors or the state of a dedicated 4 switches dip-switch

which resides over the same lines or a combination of both. Half of the

available combinations is reserved while the other half is available to users’

applications. For the external tools’ codes and their associated

combinations see TABLE 4-17. "EXTOOLI(0:3) Assignment" on page

52.

-

R

13 - 15 DBREVN(0:2)

13 - 31 Reserved

Daughter Board Revision Number (0:2). This ﬁeld represents the revision

code, hard-assigned to each daughter board. This is a production revision

which may be identical for different types of daughter boards. See TABLE

4-18. "MPC8XXFADS Daughter Boards’ Revision Encoding" on

page 53, for revisions’ encoding.

-

R

-

Un-implemented.

a. Shaded areas are additions with respect to the MPC812/860ADS.

TABLE 4-14. Flash Presence Detect (4:1) Encoding

FLASH_PD(4:1)

FLASH TYPE / SIZE

0 - 3

Reserved

SM732A2000 / SM73228 - 8 Mbyte SIMM, by SMART Modular Technologies.

4

5

SM732A1000A

Technologies.

/ SM73218 - 4 Mbyte SIMM, by SMART Modular

6

MCM29080 - 8 MByte SIMM, by Motorola

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TABLE 4-14. Flash Presence Detect (4:1) Encoding

FLASH_PD(4:1)

FLASH TYPE / SIZE

MCM29040 - 4 MByte SIMM, by Motorola

7

8

MCM29020 - 2 MByte SIMM, by Motorola

Reserved

9 - F

TABLE 4-15. DRAM Presence Detect (2:1) Encoding

DRAM_PD(2:1)

DRAM TYPE / SIZE

00

01

10

11

MCM36100 by Motorola or MT8D132X by Micron- 4 MByte SIMM

MCM36800 by Motorola or MT16D832X by Micron - 32 MByte SIMM

MCM36400 by Motorola or MT8D432X by Micron - 16 MByte SIMM

MCM36200 by Motorola or MT16D832X by Micron - 8 MByte SIMM

TABLE 4-16. DRAM Presence Detect (4:3) Encoding

DRAM_PD(4:3)

DRAM DELAY

Reserved

00

01

10

11

Reserved

70 nsec

60 nsec

TABLE 4-17. EXTOOLI(0:3) Assignment

EXTTOOLI(0:3)

External Tool

0000-0111

1000-1110

1111

Reserved

User Available

Non Existent

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WARNING

Since EXTOLI(0:3) lines may be DRIVEN LOW (’0’)

by the dip-switch, OFF-BOARD tools should NEV-

ER DRIVE them HIGH. Failure in doing so, might re-

sult in PERMANENT DAMAGE to the FADS and / or

to OFF-BOARD logic.

TABLE 4-18. MPC8XXFADS Daughter Boards’ Revision Encoding

Revision Number (0:3)

[Hex]

MPC8XXFADS

Daughter Board Revision

0

1

ENG (Engineering)

PILOT

2 - 7

Reserved

4•11•5 BCSR3 - Board Control / Status Register 3

BCSR3 is an additional control / status register which may be accessed at offset 0xC from BCSR

base address. BCSR3 gets its defaults during Power-On reset and may be read or written at any time.

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Functional Description

The description of BCSR3 is shown in TABLE 4-19. "BCSR3 Description" on page 54.

TABLE 4-19. BCSR3 Description

PON

DEF

BIT

MNEMONIC

Function

ATT.

0 - 1

2 - 7

Reserved

Implemented

’00’

-

R

DBID(0:5)

Daughter Board ID. This ﬁeld holds a code for the daughter board ID. Each

Daughter board carries a unique ID code. For the speciﬁc daughter boards’

codes see TABLE 4-20. "Daughter Boards’ ID Codes" on page 54.

a

5

CNT_REG_EN_P

ROTECT

Control Register Enable Protect. When this bit is active (low) the

BCSR_EN bit in that register can not be written. When in-active, BCSR_EN

may be written to remove the BCSR from the memory map. After any write

to BCSR1 this bit becomes active again. This bit is a write-only bit on that

register.

0

W

6 - 7

8

Reserved

BREVN0

Un-Implemented

-

Board Revision Number 0. This is the MS bit of the Board Revision

Number. See TABLE 4-18. "MPC8XXFADS Daughter Boards’

Revision Encoding" on page 53, for the interpretation of the Board

Revision Number.

R

9 - 11

FLASH_PD(7:5)

Flash Presence Detect(7:5). These lines are connected to the Flash SIMM

presence detect lines which encode the Delay of Flash SIMM mounted on

the Flash SIMM socket - U15. There are additional 4 presence detect lines

which encode the SIMM’s Type but appear in BCSR2. For the encoding of

FLASH_PD(7:5) see TABLE 4-22. "FLASH Presence Detect (7:5)

Encoding" on page 55.

-

12

13

BREVN1

Reserved

Board Revision Number 1. Second bit of the Board Revision Number. See

TABLE 4-18. "MPC8XXFADS Daughter Boards’ Revision Encoding"

on page 53, for the interpretation of the Board Revision Number.

-

R

Implemented

’0’

-

R

14 - 15 BREVN(2:3)

Board Revision Number (2:3). The 2 LS bits of the Board Revision

Number. See TABLE 4-18. "MPC8XXFADS Daughter Boards’

Revision Encoding" on page 53, for the interpretation of the Board

Revision Number.

a. This is a WRITE ONLY bit so it does not conflict with the DBID filed which is READ ONLY.

TABLE 4-20. Daughter Boards’ ID Codes

DBID(0:5)

[HEX}

MPC8XX On

D/B

a

0

1

Reserved .

b

MPC813

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Functional Description

TABLE 4-20. Daughter Boards’ ID Codes

DBID(0:5)

[HEX}

MPC8XX On

D/B

2

3

MPC821

MPC823

Reserved

MPC801

4 - 1F

20

b

21

MPC850

22

MPC860

b

23

MPC860SAR

b

24

MPC860T

25 - 3F

Reserved

a. To distinguish between

MPC8XXFADS

and

b. Future 8XX Members

TABLE 4-21. MPC8XXFADS Revision Number Conversion Table

Revision Number (0:3)

MPC8XXFADS Revision

[Hex]

0

1

ENG (Engineering)

PILOT

2 - F

Reserved

TABLE 4-22. FLASH Presence Detect (7:5) Encoding

FLASH_PD(7:5)

Flash Delay [nsec]

Not Supported

000

001

150

010

120

011

90

100 - 111

Not Supported

4•11•6 BCSR4 - Board Control / Status Register 4

The BCSR4 serves as a control register on the FADS. It is accessed at offset 10H from BCSR base

A

address. It may be read or written at any time . BCSR4 gets its defaults upon Power-On reset. Most

of BCSR4 pins are available at the daughter board connectors and on the expansion connectors

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Functional Description

residing over the daughter boards, providing visibility towards daughter boards’ and external logic.

BCSR4 fields are described in TABLE 4-23. "BCSR4 Description" on page 56.

a

TABLE 4-23. BCSR4 Description

PON

BIT

MNEMONIC

Function

ATT.

R,W

DEF

0

1

2

3

4

ETHLOOP

Ethernet port Diagnostic Loop-Back. When active (high), the MC68160

EEST is conﬁgured into diagnostic Loop-Back mode, where the transmit

output is internally fed back into the receive section.

TFPLDL~

Twisted Pair Full-Duplex. When active (low), the MC68160 EEST is put

into full-duplex mode, where, simultaneous receive and transmit are

enabled.

1

R,W

TPSQEL~

Twisted Pair Signal Quality Error Test Enable. When active (low), a

simulated collision state is generated within the EEST, so the collision

detection circuitry within the EEST may be tested.

SIGNAL_LAMP

Signal Lamp. When this signal is active (low), a dedicated LED illuminates.

When in-active, this led is darkened. This led is used for S/W signalling to

user.

b

USB_EN

/

USB port Enable or Utopia Port Enable or Fast Ethernet Port Enable.

When this signal is active (low) it enables the USB port transceiver in case

an MPC823 daughter board is attached to the FADS or it enables the

Utopia port in case an MPC860SAR daughter board is attached to the

FADS or it enables the Fast Ethernet Port (100-Base-T) if an MPC860T

daughter board is connected.

c

UTOPIA_EN

FETH_EN

d

This signal has no function with the MPC801, MPC821 and MPC860

daughter boards.

5

6

USB_SPEED

USB_VCC0

USB Port Speed. When this signal is active (high) the USB transceiver of

the MPC823 daughter board is in full-speed mode. When inactive, the USB

transceiver is in low-speed mode.

This signal has no function with any daughter board other the MPC823 or

MPC850 daughter boards.

1

R,W

USB Port VCC EN. When this signal is active (low), 5V power is enabled to

the USB port. When inactive, power to the USB port is disconnected.

This signal has no function with any daughter board other the MPC823 or

MPC850 daughter boards.

7

8

Reserved.

Implemented.

0

1

R,W

VIDEO_ON

Video Port Enable. When this signal is active (low), the Video-On Led on

the MPC823FADSDB is lit. When inactive, the led is darkened. This is

merely an indication that should be set by application S/W to indicate

2

activity of the Video Port, after it has been enabled via the I C port.

This signal has no function with any daughter board other the MPC823

daughter board.

A. Provided that BCSR is not disabled.

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Functional Description

a

TABLE 4-23. BCSR4 Description

PON

ATT.

DEF

BIT

MNEMONIC

Function

9

VDO_EXT_CLK_

EN

Video Port Clock Enable. When this signal is active (high), it enables an

on-board 27MHz clock generator as a source for both the video encoder

and the video port controller of the MPC823.

1

R,W

The system programmer should avoid asserting this signal, until it is

assured that the MPC823 is set to accept external video clock. Failure in

doing so might result in permanent damage to the MPC823 and / or the on-

board 27 MHz clock generator.

This signal has no function with any daughter board other the MPC823

daughter board.

e

10

VIDEO_RST

Video Port Reset. when this active (low) signal is being asserted, the

1

R,W

Video Encoder, located on the MPC823FADSDB, is being reset. For further

informations see 2•4 "VIDEO Support" on page

MPC823FADSDB spec.

This signal has no function with any daughter board other the MPC823

daughter board

4 of the

11

12

MODEM_EN

DATA_VOICE

Modem Enable for MPC823. When this signal is active (low) while an

MPC823FADSDB is connected to the FADS, it is possible to operate the

MPC821 Modem Tool. This signal has no function with any other daughter

board.

Modem Tool Function Select. Effective only with MPC823AFDSDB. When

This signal is high, the DATA function of the modem tool is selected. When

low, the VOICE function of the modem tool is selected.

1

-

R,W

-

13 - 31 Reserved

Un-implemented

a. Shaded areas are additions with respect to the MPC8XXFADS.

b. MPC823 Daughter Board function.

c. MPC860SAR Daughter Board function.

d. MPC860T Daughter Board function.

e. I.e., on the negative edge.

4•12

Debug Port Controller

A

The debug port of the MPC8XXFADS is implemented on-board, connected to the MPC via the JTAG

B

port. Since the location of the debug port is determined via the Hard-Reset configuration, It is impor-

tant that the relevant configuration bits (see 4•1•6 "Reset Configuration" on page 29) are not changed,

if working with the local debug port is desired.

The debug port controller is interfaced to host computer via Motorola’s ADI port, which is an 8-bit wide

parallel port. Since the debug port is serial, conversion is done by hardware between the parallel and

serial protocols.

The MPC’s debug port is configured at SOFT-Reset to "Asynchronous Clock Mode" i.e., the debug

port generates the debug clock - DSCK, which is asynchronous with the MPC system clock.

The debug port controller block diagram is shown in FIGURE 4-7 "Debug Port Controller Block

Diagram" on page 58.

A. The debug port location is determined by the HARD - Reset configuration.

B. In terms of MPC pins.

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Functional Description

FIGURE 4-7 Debug Port Controller Block Diagram

ADI Port Connector

Debug Port Conn.

Daughter Board Connector

ADI Address

Selection

HRESET*

SRESET*

ADI - Handshake Logic

& Port Control

VFLS0

1

0

1

0

VFLS1

FRZ

1

0

S

CHINS*

Data Register

DSDI

Control / Status Register

DSCK

DSDO

Parallel <--> Serial

Converter

’1’

’0’

J1

To allow for an external debug port controller to be incorporated with the FADS and to allow target

system debug by the FADS, a standard 10 pin, debug port connector is provided and the local debug

A

port controller may be disabled by removing the ADI bundle from the its connector.

When the ADI’s 37 lead cable is disconnected from either the ADI connector or from the FADS’s 37

pin connector, the debug port controller is disabled allowing either the connection of an external

debug port controller, or independent s/w run, i.e., the MPC boots from the flash memory to run user’s

application without debug port controller intervention. This feature becomes especially handy regard-

ing demo’s.

B

In this state, VFLS(0:1) or FRZ signals are routed to the debug port connector, so that, the external

debug port controller has run mode status information.

The ADI I/F supports upto 8 boards connected on the same bundle. Address selection is done by DS2

/ 1,2,3. See 2•3•1 "ADI Port Address Selection" on page 7.

The debug port I/F has two registers: a control / status register and a data register. The control / status

register hold I/F related control / status functions, while the data register serves as the parallel side

of the Transmit / Receive shift register.

The control / status register is accessed when D_C~ bit is low while the data register is accessed

when D_C~ is driven high by the host via the ADI port.

4•12•1 MPC8XXFADS As Debug Port Controller For Target System

The FADS may be used as a debug port controller for a target system, provided that the target system

A. I.e., debug port controller outputs are tri-stated, allowing debug port to be driven by an external debug-tool.

B. Depended on H/W settings.

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Functional Description

has a 10 pin header connector matching the one on the FADS.

In this mode of operation, the on-board debug port controller, is connected to the target system’s

debug-port connector (see 4•12•1•1 "Debug Port Connection - Target System Requirements"

below). Since DSDO signal is driven by the MPC, it is a must, to remove the local MPC from its

socket, to avoid contention over this line.

When either the local MPC is removed from its socket or the daughter board is removed from the

FADS, all FADS’s modules are inaccessible, except for the debug-port controller. All module-enable

indications are darkened, regardless of their associated enable bits in the BCSR. Pull-up resistors are

connected to Chip-Select lines, so they do not float when the MPC is removed from its socket,

avoiding possible contention over data-bus lines.

4•12•1•1 Debug Port Connection - Target System Requirements

In order for a target system may be connected to the FADS, as a debug port controller, few measures

need to be taken on the target system:

1) A 10-pin header connector should be made available, with electrical connections matching

FIGURE 4-8 "Standard Debug Port Connector" on page 61.

A

2) Pull-down resistors, of app. 1KΩ should be connected over DSDI and DSCK^Asignals.

B

These resistors are to provide normal operation, when a debug-port controller, is not con-

nected to the target system

3) The debug-port should be enabled and routed to the desired pins. See the DBGC and

DBPC fields within the HARD-RESET configuration word.

4•12•2 Debug Port Control / Status Register

The control / status register is an 8 bit register (bit 7 stands for MSB). For the description of the ADI

A. Remember that the location of DSDI and DSCK is determined by the HARD-Reset configuration.

B. Normal - i.e., boot via CS0~.

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Functional Description

control status register see TABLE 4-24. "Debug Port Control / Status Register" on page 60.

TABLE 4-24. Debug Port Control / Status Register

I/F

Res

et

BIT

MNEMONIC

Function

ATT.

DEF

7

6

MpcRst

Mpc Reset. When this status only bit indicates when active (high) that

either a SOFT or a HARD reset is driven by the MPC.

-

R

TxError

Transmit Error. When this status only bit is active (high) it indicates that

the last transmission towards the MPC, was cut by an internal MPC8XX

reset source. This bit is updated for each byte sent.

-

5

InDebug

In Debug Mode. When this status only bit is active (high) it indicates that

R

a

the MPC is in debug mode .

4 - 3

DebugClockFreq

Debug Clock Frequency Select. This ﬁeld controls a frequency divider ’00’

which divides DSCK. For the division factors and associated DSCK

frequencies see TABLE 4-25. "DSCK Frequency Select" below.

R/W

2

1

StatusRequest

DiagLoopBack

Status Request. When the host writes this bit active (low), the I/F will issue

a status read request to the host by asserting ADS_REQ line to the host.

When the host writes the control register with this bit negated, no status

read request is issued.

0

R/W

Upon I/F reset this bit wakes-up active.

Diagnostic Loopback Mode. When this control bit is active (low) the I/F is

placed in Diagnostic Loopback Mode. I.e., DSDI is connected internally to

DSDO, DSDI is tri-stated, and each data byte sent to the I/F data register, is

sampled back into the receive shift register. This mode allows for complete

ADI I/F test, upto transmit and receive shift registers.

0

Upon I/F reset this bit wakes-up active.

0

DebugEntry

Debug Mode Entry. When this bit is active (low), the MPC will enter debug

mode instantly after SOFT reset. When inactive, the MPC will start

executing normally and will enter debug mode only after exception.

Upon I/F reset this bit wakes-up active.

0

R/W

a. Provided that the PCMCIA channel II pins are configured as debug pins - i.e, VFLS(0:1) signals are available. If

not, the debug port can not be operated correctly.

TABLE 4-25. DSCK Frequency Select

DSCK

DebugClockFreq

Frequency

[MHz]

00

01

10

11

10

5

2.5

1.25

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FIGURE 4-8 Standard Debug Port Connector

1

3

5

2

SRESET

DSCK

VFLS0

GND

4

6

GND

VFLS1

DSDI

8

7

HRESET

VDD

10

9

DSDO

4•12•3 Standard MPCXXX Debug Port Connector Pin Description

The pins on the standard debug port connector are the maximal group needed to support debug port

controllers for both the MPC5XX and MPC8XX families. Some of the pins are redundant for the

MPC8XX family but are necessary for the MPC5XX family.

4•12•3•1 VFLS(0:1)

These pins indicate to the debug port controller whether or not the MPC is in debug mode. When both

VFLS(0:1) are at ’1’, the MPC is in debug mode. These lines may serve alternate functions with the

A

MPC, in which case FRZ needs to selected, on either the FADS or target system .

4•12•3•2 HRESET*

This is the Hard-Reset bidirectional signal of the MPC. When this signal is asserted (low) the MPC

enters hard reset sequence which include hard reset configuration. This signal is made redundant

with the MPC8XX debug port controller since there is a hard-reset command integrated within the

debug port protocol. However, the local debug port controller uses this signal for compatibility with

MPC5XX existing boards and s/w.

4•12•3•3 SRESET*

This is the Soft-Reset bidirectional signal of the MPC8XX. On the MPC5XX it is an output. The debug

B

port configuration is sampled and determined on the rising-edge of SRESET* (for both processor

families). On the MPC8XX it is a bidirectional signal which may be driven externally to generate soft

reset sequence. This signal is in fact redundant regarding the MPC8XX debug port controller since

there is a soft-reset command integrated within the debug port protocol. However, the local debug

port controller uses this signal for compatibility with MPC5XX existing boards and s/w.

4•12•3•4 DSDI - Debug-port Serial Data In

Via the DSDI signal, the debug port controller sends its data to the MPC. The DSDI serves also a role

during soft-reset configuration. (See 4•1•6•3 "Soft Reset Configuration" on page 29).

4•12•3•5 DSCK - Debug-port Serial Clock

During asynchronous clock mode, the serial data is clocked into the MPC according to the DSCK

C

clock. The DSCK serves also a role during soft-reset configuration. (See 4•1•6•3 "Soft Reset Config-

uration" on page 29).

4•12•3•6 DSDO - Debug-port Serial Data Out

DSDO is clocked out by the MPC according to the debug port clock, in parallel with the DSDI being

D

clocked in. The DSDO serves also as "READY" signal for the debug port controller to indicate that

the debug port is ready to receive controller’s command (or data).

A. If a target system needs to use VFLS(0:1) alternate function, then, FRZ line should be connected to both

VFLS(0:1) pins on the debug port connector.

B. In fact that configuration is divided into 2 parts, the first is sampled 3 system clock cycles prior to the rising

edge of SRESET* and the second is sampled 8 clocks after that edge.

C. I.e., DSDI must meat setup / hold time to / from rising edge of the DSCK.

D. I.e., full-duplex communication.

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Functional Description

4•13

Power

There are 4 power buses with the MPC8XXs:

1) I/O

2) Internal Logic

3) Keep Alive

4) PLL

and there are 3 power buses on the MPC8XXFADS:

1) 5V bus

2) 3.3V bus

3) 12V bus

FIGURE 4-1 MPC8XXFADS Power Scheme

FADS Logic & Peripherals

3.3V

2V

PCMCIA

Buffers

VDDSYN

K.A.

VDDL

VDDH

5V

VCC

VPP

PCMCIA

Power

Control

MPC8XX

VKA

12V

DAUGHTER BOARD

MOTHER BOARD

To support off-board application development, the power buses are connected to the expansion con-

nectors, so that external logic may be powered directly from the board. The maximum current allowed

to be drawn from the board on each bus is shown in TABLE 4-26. "Off-board Application Maximum

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Functional Description

Current Consumption" below.

TABLE 4-26. Off-board Application Maximum Current Consumption

Power BUS

Current

5V

3.3V

2V

2A

0.5A

12V

100 mA.

To protect on board devices against supply spikes, decoupling capacitors (typically 0.1µF) are

provided between the devices’ power leads and GND, located as close as possible to the power

leads.

4•13•1 5V Bus

Some of the FADS peripherals reside on the 5V bus. Since the MPC is 5V friendly, it may operate

with 5V levels on its lines with no damage. The 5V bus is connected to an external power connector

via a fuse (5A).

To protect against reverse-voltage or over-voltage being applied to the 5V inputs a set of high-current

diodes and zener diode is connected between the 5V bus GND. When either over or reverse voltage

is applied to the FADS, the protection logic will blow the fuse, while limiting the momentary effects on

board.

4•13•2 3.3V Bus

A

The MPC itself as well as the SDRAM, the address and data buffers are powered by the 3.3 bus,

which is produced from the 5V bus using a special low-voltage drop, linear voltage regulator made

by Micrel, the MIC29500-3.3BT which is capable of driving upto 5A, facilitating operation of external

logic as well.

4•13•3 12V Bus

The sole purpose of the 12V bus is to supply VPP (programming voltage) for the PCMCIA card and

B

for the Flash SIMM . It is connected to a dedicated input connector via a fuse (1A) and protected from

over / reverse voltage application.

If the 12V supply is not required for either the PC-Card and for the flash SIMM, the 12V input to the

FADS may be omitted.

A. At full speed. When lower performance is needed the internal logic may be powered from the 2V bus.

B. If necessary.

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Support Information

5 - Support Information

In this chapter all information needed for support, maintenance and connectivity to the

MPC8XXFADS is provided.

5•1

Interconnect Signals

The MPC8XXFADS interconnects with external devices via the following set of connectors:

1) P1 - ADI Port connector

2) PA2 - RS232 port 1

3) PB2 - RS232 port 2

4) P3 - Ethernet port

5) P4 - PCMCIA port

6) P5 - External Debug port controller input / output

7) P6 - 5V Power In

8) P7 - 12V Power In

9) P8 - Serial Ports’ Expansion connector

10) PD1, PD2, PD3 & PD4 - Daughter-Board Connectors

5•1•1

P1 ADI - Port Connector

o

The ADI port connector - P1, is a 37-pin, Male, 90 , D-Type connector, signals of which are described

in TABLE 5-1 "P1 - ADI Port Interconnect Signals" below:

TABLE 5-1 P1 - ADI Port Interconnect Signals

Pin No.

Signal Name

Description

1

2

Not connected with this application

D_C~

Data / Control selection. When ’1’, the debug port controller’s data register is accessed,

when ’0’ the debug port controller’s control register is accessed.

3

4

HST_ACK

Host Acknowledge input signal from the host.

ADS_SRESET

When asserted (’1’) and the FADS is selected by the host, generates Soft Reset to the

MPC.

5

ADS_HRESET

When asserted (’1’) and the FADS is selected by the host, generates Hard Reset

to the MPC.

6

ADS_SEL2

ADS_SEL1

ADS_SEL0

HOST_REQ

ADS_REQ

ADS_ACK

ADI I/F address line 2 (MSB).

7

ADI I/F address line 1.

8

ADI I/F address line 0 (LSB).

9

HOST Request input signal from the host

ADS Request output signal from the MPC8XXFADS to the host

ADS Acknowledge output signal from the MPC8XXFADS to the host

Not connected with this application

Bit 1 of the ADI port data bus

10

11

12

13

14

15

16

17

18

19

PD1

PD3

PD5

PD7

Bit 3 of the ADI port data bus

Bit 5 of the ADI port data bus

Bit 7 of the ADI port data bus

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TABLE 5-1 P1 - ADI Port Interconnect Signals

Pin No.

Signal Name

GND

Description

20 - 25

26

Ground.

Not connected with this application

27 - 29

HOST_VCC

HOST VCC input from the host. Used to qualify FADS selection by the host. When host

is off, the debug port controller is disabled.

30

HOST_ENABLE~

HOST Enable input signal from the host. (Active low). Indicates that the host computer

is connected to FADS. Used, in conjunction with HOST_VCC and ADS_SEL(2:0) to

qualify FADS selection by the host.

31 - 33

34

GND

PD0

PD2

PD4

PD6

Ground.

Bit 0 of the ADI port data bus

Bit 2 of the ADI port data bus

Bit 4 of the ADI port data bus

Bit 6 of the ADI port data bus

35

36

37

5•1•2

PA2, PB2 - RS232 Ports’ Connectors

The RS232 ports’ connectors - PA2 and PB2 are 9 pin, 90^o, female D-Type Stacked connectors,

signals of which are presented in TABLE 5-2. "PA2, PB2 Interconnect Signals" below

TABLE 5-2. PA2, PB2 Interconnect Signals

Pin No.

Signal Name

Description

1

2

3

4

5

6

7

8

9

CD

TX

Carrier Detect output from the MPC8XXFADS.

Transmit Data output from the MPC8XXFADS.

Receive Data input to the MPC8XXFADS.

Data Terminal Ready input to the MPC8XXFADS.

Ground signal of the MPC8XXFADS.

RX

DTR

GND

DSR

RTS (N.C.)

CTS

Data Set Ready output from the MPC8XXFADS.

Request To Send. This line is not connected in the MPC8XXFADS.

Clear To Send output from the MPC8XXFADS.

Not connected

-

5•1•3

P3 - Ethernet Port Connector

The Ethernet connector on the MPC8XXFADS - P3, is a Twisted-Pair (10-Base-T) compatible con-

o

nector. Use is done with 90 , 8-pin, RJ45 connector, signals of which are described in TABLE 5-3.

"P3 - Ethernet Port Interconnect Signals" below.

TABLE 5-3. P3 - Ethernet Port Interconnect Signals

Pin No.

Signal Name

Description

1

2

TPTX

TPTX~

Twisted-Pair Transmit Data positive output from the MPC8XXFADS.

Twisted-Pair Transmit Data negative output from the MPC8XXFADS.

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TABLE 5-3. P3 - Ethernet Port Interconnect Signals

Pin No.

Signal Name

Description

3

4

5

6

7

8

TPRX

Twisted-Pair Receive Data positive input to the MPC8XXFADS.

-

Not connected

-

Not connected

TPRX~

Twisted-Pair Receive Data negative input to the MPC8XXFADS.

-

Not connected

5•1•4

PCMCIA Port Connector

The PCMCIA port connector - P4, is a 68 - pin, Male, 90⁰, PC Card type, signals of which are present-

ed in TABLE 5-4. "P4 - PCMCIA Connector Interconnect Signals" below

TABLE 5-4. P4 - PCMCIA Connector Interconnect Signals

Pin No.

Signal Name

GND

Attribute

Description

1

2

3

4

5

6

7

Ground.

PCCD3

PCCD4

PCCD5

PCCD6

PCCD7

BCE1A~

I/O

O

PCMCIA Data line 3.

PCMCIA Data line 4.

PCMCIA Data line 5.

PCMCIA Data line 6.

PCMCIA Data line 7.

PCMCIA Chip Enable 1. Active-low. Enables EVEN numbered

address bytes.

8

9

PCCA10

OE~

O

PCMCIA Address line 10.

PCMCIA Output Enable signal. Active-low. Enables data outputs

from PC-Card during memory read cycles.

10

11

12

13

14

15

PCCA11

PCCA9

O

PCMCIA Address line 11.

PCMCIA Address line 9.

PCMCIA Address line 8.

PCMCIA Address line 13.

PCMCIA Address line 14.

PCCA8

PCCA13

PCCA14

WE~/PGM~

PCMCIA Memory Write Strobe. Active-low. Strobes data to PC-

Card during memory write cycles.

16

17

RDY

I

+Ready/-Busy signal from PC-Card. Allows PC-Card to stall

access from the host, in case a previous access’s processing is

not completed.

PCCVCC

O

5V VCC for the PC-Card. Switched by the MPC8XXFADS, via

BCSR1.

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TABLE 5-4. P4 - PCMCIA Connector Interconnect Signals

Pin No.

18

Signal Name

PCCVPP

Attribute

O

Description

12V/5V VPP for the PC-Card programming. 12V available only

if12V is applied to P8. Controlled by the MPC8XXFADS, via

BCSR1.

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

PCCA16

PCCA15

PCCA12

PCCA7

PCCA6

PCCA5

PCCA4

PCCA3

PCCA2

PCCA1

PCCA0

PCCD0

PCCD1

PCCD2

WP

O

PCMCIA Address line 16.

PCMCIA Address line 15.

PCMCIA Address line 12.

PCMCIA Address line 7.

PCMCIA Address line 6.

PCMCIA Address line 5.

PCMCIA Address line 4.

PCMCIA Address line 3.

PCMCIA Address line 2.

PCMCIA Address line 1.

PCMCIA Address line 0.

PCMCIA Data line 0.

O

I/O

I

PCMCIA Data line 1.

PCMCIA Data line 2.

Write Protect indication from the PC-Card.

Ground

GND

Ground

CD1~

I

Card Detect 1~. Active-low. Indicates in conjunction with CD2~

that a PC-Card is placed correctly in socket.

37

38

39

40

41

42

PCCD11

PCCD12

PCCD13

PCCD14

PCCD15

BCE2A~

I/O

O

PCMCIA Data line 11.

PCMCIA Data line 12.

PCMCIA Data line 13.

PCMCIA Data line 14.

PCMCIA Data line 15.

PCMCIA Chip Enable 2. Active-low. Enables ODD numbered

address bytes.

43

44

45

46

VS1

I

Voltage Sense 1 from PC-Card. Indicates in conjunction with VS2

the operation voltage for the PC-Card.

IORD~

IOWR~

PCCA17

O

I/O Read. Active-low. Drives data bus during I/O-Cards’ read

cycles.

I/O Write. Active-low. Strobes data to the PC-Card during I/O-

Card write cycles.

PCMCIA Address line 17.

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TABLE 5-4. P4 - PCMCIA Connector Interconnect Signals

Pin No.

Signal Name

PCCA18

Attribute

Description

47

48

49

50

51

O

PCMCIA Address line 18.

PCMCIA Address line 19.

PCMCIA Address line 20.

PCMCIA Address line 21.

PCCA19

PCCA20

PCCA21

PCCVCC

5V VCC for the PC-Card. Switched by the MPC8XXFADS, via

BCSR1.

52

PCCVPP

O

12V/5V VPP for the PC-Card programming. 12V available only

if12V is applied to P8. Controlled by the MPC8XXFADS, via

BCSR1.

53

54

55

56

57

PCCA22

PCCA23

PCCA24

PCCA25

VS2

O

I

PCMCIA Address line 22.

PCMCIA Address line 23.

PCMCIA Address line 24.

PCMCIA Address line 25.

Voltage Sense 2 from PC-Card. Indicates in conjunction with VS1

the operation voltage for the PC-Card.

58

59

60

RESET

O

I

Reset signal for PC-Card.

WAITA~

INPACK~

Cycle Wait from PC-Card. Active-low.

I

Input Port Acknowledge. Active-low. Indicates that the Pc-Card

can respond to I/O access for a certain address.

61

62

63

PCREG~

BVD2

O

I

Attribute Memory or I/O Space - Select. Active-low. Used to select

either attribute (card-conﬁguration) memory or I/O space.

Battery Voltage Detect 2. Used in conjunction with BVD1 to

indicate the condition of the PC-Card’s battery.

BVD1

I

Battery Voltage Detect 1. Used in conjunction with BVD2 to

indicate the condition of the PC-Card’s battery.

64

65

66

67

PCCD8

PCCD9

PCCD10

CD2~

I/O

I

PCMCIA Data line 8.

PCMCIA Data line 9.

PCMCIA Data line 10.

Card Detect 2~. Active-low. Indicates in conjunction with CD1~

that a PC-Card is placed correctly in socket.

68

GND

Ground.

5•1•5

P5 - External Debug Port Controller Input Interconnect.

The debug port connector - P5, is a 10 pin, Male, header connector, signals of which are described

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in TABLE 5-5. "P5 - Interconnect Signals" below

TABLE 5-5. P5 - Interconnect Signals

Pin No.

1

Signal Name

VFLS0

Attribute

O

Description

Visible history FLushes Status 0. Indicates in conjunction with

VFLS1, the number of instructions ﬂushed from the core’s history

buffer. Indicates also whether the MPC is in debug mode. If not

using the debug port, may be conﬁgured for alternate function.

When the FADS is disconnected from the ADI bundle, it may be

FRZ signal, depended on J1’s position.

2

3

4

SRESET~

GND

I/O

Soft Reset line of the MPC. Active-low, Open-Drain.

Ground.

DSCK

Debug Serial Clock. Over the rising edge of which serial date is

sampled by the MPC from DSDI signal. Over the falling edge of

which DSDI is driven towards the MPC and DSDO is driven by

the MPC. Conﬁgured on the MPC’s JTAG port.

When the debug-port controller is on the local MPC or when the

FADS is a debug-port controller for a target system - OUTPUT,

when the FADI bundle is disconnected from the FADS - INPUT.

5

6

GND

Ground

VFLS1

O

See VFLS0. When the FADS is disconnected from the ADI

bundle, it may be FRZ signal, depended on J1’s position.

7

8

HRESET~

DSDI

I/O

Hard Reset line of the MPC. Active-low, Open-Drain

Debug Serial Data In of the debug port. Conﬁgured on the MPC’s

JTAG port.

When the debug-port controller is on the local MPC or when the

FADS is a debug-port controller for a target system - OUTPUT,

when the ADI bundle is disconnected from the FADS - INPUT.

9

V3.3

O

3.3V Power indication. This line is merely for indication. No

signiﬁcant power may be drawn from this line.

10

DSDO

I/O

Debug Serial Data Output from the MPC. Conﬁgured on the

MPC’s JTAG port.

When the debug-port controller is on the local MPC or when the

ADI bundle is disconnected from the FADS - OUTPUT, when the

FADS is a debug-port controller for a target system - INPUT.

5•1•6

P6 - 5V Power Connector

The 5V power connector - P6, is a 3-lead, two-part terminal block. The male part is soldered to the

pcb, while the receptacle is connected to the power supply. That way fast connection / disconnection

of power is facilitated and physical efforts are avoided on the solders, which therefore maintain solid

connection over time.

TABLE 5-6. P6 - Interconnect Signals

Number

Signal Name

Description

5V input from external power supply.

1

2

5V

GND

GND line from external power supply.

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TABLE 5-6. P6 - Interconnect Signals

Number

Signal Name

GND

Description

3

GND line from external power supply.

5•1•7

P7 - 12V Power Connector

The 12V power connector - P7, is a two-lead, 2 part, terminal block connector, identical in type to the

5V connector. P7 supplies, when necessary, programming voltage to the Flash SIMM and / or to the

TABLE 5-7. P7 - Interconnect Signals

Number

Signal Name

Description

1

2

12V

GND

12V input from external power supply.

GND line from external power supply.

PCMCIA slot.

5•1•8

P8 - Serial Ports’ Expansion Connector

A

P8 is the serial ports expansion connector. Its is compatible with the QUADS board and with the

previous MPC8XXFADS.

P8 is a 96 pin, Female, DIN 41612 connector.

Since the pinout of P8 is specific to the Daughter-Board connected to the FADS, it is described in

each Daughter-Board User’s manual.

5•1•9

PD1, PD2, PD3 & PD4 - Daughter Boards’ Connectors Interconnect Signals

To be described in the next edition of this document.

5•2

MPC8XXFADS Part List

In this section the MPC8XXFADS’s bill of material is listed according to their reference designation.

To be added in the next edition of this document.

A. True for the MPC860, but true upto an extent for other derivatives.

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APPENDIX A - Programmable Logic Equations

The MPC8XXFADS has 3 programmable logic devices on it. Use is done with MACH220-12 by AMD.

These device support the following function on the FADS:

1) U7 - Debug Port Controller

2) U10 - auxiliary board control functions, e.g,. buffers control, local interrupter, reset logic,

etc’.

3) U11 - the BCSR.

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U2 - Debug Port Controller

Support Information

A•1

"******************************************************************************

"* MPC8XX FADS Debug Port Controller.

*

"* Mach controller for an interface between Sun ADI port at one side, to

"* debug port at the other.

"******************************************************************************

"* In this file (8):

"* - Added support for VFLS / FRZ switching, for both normal operation and

"*

external debug station connected to the FADS.

Support includes:

- separating vfls between MPC and debug port.

- Selection between frz / vfls (default) is done by VflsFrz~ input pin.

- Selection between on-board / off-board vfls/frz is done by ChinS~ coming

from the expansion connectors.

- VFLS(0:1) are driven towards the debug-port connector when board is not

selected, i.e., either ADI is disconnected or addresses don't match.

"******************************************************************************

"* In this file (7):

"* - BundleDelay field in the control register is changed to debug port

"*

clock frquency select according to the following values:

0 - divide by 8 (1.25 Mhz)

1 - divide by 4 (2.5 Mhz)

2 - divide by 2 (5 Mhz)

3 - divide by 1 (10 Mhz) default.

"* - Added clock divider for 2 , 4, 8 output of which is routed externaly

"* to the i/f clock input.

"******************************************************************************

"* In this file (6):

"* - RUN siganl polarity was changed to active-high, this, to support

"*

other changes for revision PILOT of the fads.

"******************************************************************************

"* In this file (5) added:

"* - protection against spikes on the reset lines, so that the interface

"*

"* - D_C~ signal was synchronized to avoid accidental write to control

"* during data write.

"* - DSDI is given value (H) prior to negation of SRESET* to comply with 5XX

"* family

will not be reset by an accidental spike.

"******************************************************************************

"* In this file (4) the polarity of address selection lines is reversed so

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"* that ON the switch represent address line at high and vice-versa

"******************************************************************************

"* In this file (3) the IClk is not reseted at all so it can be used to

"* sync MPC8XX reset signals inside.

"* Added consideration for reset generated by the MPC8XX:

"* - when MPC8XX is reset (i.e., its hard | soft reset signals are asserted,

"*

it is not allowed for the host to initiate data trnasfer towards the MPC8XX.

It can however, access the control / status register to either change

parameters and / or check for status.

"* - The status of reset signals is added to the status register, so it can

"* be polled by the host.

"******************************************************************************

module dbg_prt8

title 'MPC8XXFADS Debug Port Controller’

"******************************************************************************

"* Device declaration.

*

"******************************************************************************

U02 device 'mach220a';

"******************************************************************************

"* #######

"* #

*

#

##### ###### #####

#

##

#

####

*

"* #

#

##

# #

#

"* #####

"* #

##

#####

#

####

#

#####

# # ######

#

"* #

#

##

#

"* #######

#

######

#

######

####

"******************************************************************************

"* Pins declaration.

*

"******************************************************************************

"ADI Port pins.

HstReq

AdsAck

PIN 20 ;

"Host to ADS, write pulse. (IN)

PIN 31 ISTYPE 'reg, buffer'; "ADS to host, write ack.

"(OUT,3s)

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AdsReq

PIN 2 ISTYPE 'reg, buffer';

"signal. (OUT,3s)

"ADS to host, write

HstAck

PIN 54;

PIN 50;

PIN 17;

PIN 3;

"Host to ADS, write ack.

(IN)

"Host to ADS, Hard reset. (IN)

"Host to ADS, Soft reset. (IN)

AdsHardReset

AdsSoftReset

HstEn~

"Host connected to ADS.

(IN)

HostVcc

PIN 49;

PIN 51;

"Host to ADS, host is on. (IN)

"Host to ADS, select data

D_C~

"or control access.

(IN)

AdsSel0

AdsSel1

AdsSel2

PIN 22;

PIN 21;

PIN 9; "Host to ADS, card addr.

(IN)

AdsAddr0

AdsAddr1

AdsAddr2

PIN 7;

PIN 6;

PIN 5; "ADS board address switch. (IN)

AdsSelect~

NODE ISTYPE 'com, buffer'; "ADS selection indicator. (OUT)

"******************************************************************************

"* MPC pins. Including debug port.

"******************************************************************************

*

PdaHardReset~

PdaSoftReset~

VFLS0

PIN 40;

PIN 65;

PIN 10 ;

PIN 11 ;

PIN 24;

"Pda's hard reset input. (I/O. o.d.)

"Pda's soft reset output. (I/O. o.d.)

VFLS1

"Debug/Trap mode, report. (IN)

Freeze

"Alternative debug mode report (IN)

DSCK

PIN 48 istype 'com'; "Pda's debug port clock. (Out)

PIN 47 istype 'com'; "Pda's debug serial data in (Out)

PIN 4; " MPC8XX's debug serial data output (In)

DSDI

DSDO

"******************************************************************************

"* Dedicated Debug Port pins.

"******************************************************************************

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VflsP0

PIN 38 istype 'com';

PIN 37 istype 'com';

VflsP1

VflsFrz~

PIN 13;

" selectes between VFLS/FRZ from MPC

"******************************************************************************

"* Mach to ADI data bus.

*

"******************************************************************************

PD7,

PD6,

PD5,

PD4,

PD3,

PD2,

PD1,

PD0 PIN 66,60,67,59,58,57,56,55; "ADI data bus.(I/O)

"******************************************************************************

"* Clock gen pins.

*

"******************************************************************************

DbgClk

PIN 16;

"Debug Clock input source. (IN)

DbgClkOut

PIN 33 istype 'com' ; " to be connected to IClk. (out)

Clk2

PIN 14 istype 'reg, buffer'; "IClk divided by 2 (Out)

" (Out for testing, may be node)

IClk

PIN 15;

" Connected to Clkout externally (In)

"******************************************************************************

"* Misc.

"******************************************************************************

Run

PIN 23 istype 'com';

PIN 12;

"external indication

ChinS~

" active (L) when chips is In socket

"******************************************************************************

"*

###

#

*

#

##### ###### #####

#

##

#

####

*

#

##

# #

#

##

# #

#

#####

#

####

#

# #

##

#

#####

# # ######

##

#

MPC8XXFADS Design Specification—Rev 0.1

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"*

###

#

######

#

######

####

*

"******************************************************************************

"* Clock genrator Internals:

"******************************************************************************

DbgClkDivBy2

DbgClkDivBy4

DbgClkDivBy8

NODE istype 'reg, buffer';

NODE istype 'reg, buffer'; " counter (divider) signals.

Cstr0

Cstr1

NODE istype 'reg, buffer';

NODE istype 'reg, buffer'; " Clock Safe Transition Register

"******************************************************************************

"* Reset active. (Active when at least one of the reset sources is active)

"******************************************************************************

*

PrimReset

NODE istype 'com';

" Primary Reset. Host initiated

" delayed Reset

D_PrimReset

DD_PrimReset

" double delayed primary reset.

Reset

NODE istype 'com';

" Interface reset.

PdaRst

NODE istype 'reg, buffer'; " MPC8XX continued / initiated.

" part of the status register.

"******************************************************************************

"* ADS_ACK, ADS_REQ auxiliary internal control signals

*

"******************************************************************************

S_HstReqNODE istype 'reg'; "sync. host req.

DS_HstReqNODE istype 'reg'; " double sync. host req.

S_D_C~NODE istype 'reg, buffer'; " synchronized data/ control selection

S_HstAckNODE istype 'reg, buffer'; " sync host ack

DS_HstAckNODE istype 'reg, buffer'; " double sync host ack

BundleDelay1,

BundleDelay0NODE istype 'reg, buffer'; "delay counter for bundle

" delay compensation

BndTmrExpNODE istype 'com';" terminal count for bundle

" delay timer.

PDOeNODE istype 'com';

"Mach to ADI data OE.

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PdaHardResetEnNODE istype 'com';

PdaSoftResetEnNODE istype 'com';

" enables hard reset buffer.

" enables soft reset buffer.

"******************************************************************************

"* Tx Shift Register

*

"******************************************************************************

TxReg7,

TxReg6,

TxReg5,

TxReg4,

TxReg3,

TxReg2,

TxReg1,

TxReg0NODE istype 'reg, buffer'; " Transmit latch and

" shift register

"******************************************************************************

"* Tx Control Logic

*

"******************************************************************************

TxWordLen3,

TxWordLen2,

TxWordLen1,

TxWordLen0NODE istype 'reg, buffer'; " Counter, counts (on fast clock,

" to gain 1/2 clock resolution)

" transmission length

TxWordEndNODE istype 'com'; " Terminal count, sets transmission

" length.

TxEnNODE istype 'reg, buffer'; " Transmit Enable.

TxClkSnsNODE istype 'reg, buffer'; " transmit clock polarity

"******************************************************************************

"* Rx Shift Register

*

"******************************************************************************

RxReg0NODE istype 'reg, buffer'; " receive shift register

" and latch

"******************************************************************************

"* Rx Control Logic

"******************************************************************************

DsdiEnNODE istype 'reg'; " enables dsdi towards

*

"******************************************************************************

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"* ADI control & status register bits.

*

"******************************************************************************

StatusRequest~

DebugEntry~

DiagLoopBack~

DbgClkDivSel0

DbgClkDivSel1

InDebugMode

TxError

NODE istype 'reg, buffer';

"Status request

"Debug enable after reset (L)

NODE istype 'reg, buffer'; "diagnostic loopback mode (L)

NODE istype 'reg, buffer';

" DbgClk division select

" sync. VFLSs, became pin

" tx interrupted by MPC8XX

" internal reset.

"******************************************************************************

"* #####

*

"* #

#

####

#

####

#####

##

#

#####

#

##

# #

#

##

# #

#

####

#

# #

##

#

######

# #

##

#

"* #####

"*

####

#

####

#

"* ######

"* #

#

######

#

####

#

##

#####

#

#####

#

#####

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"* #

#

###### #####

*

#

"* ######

"*

######

####

######

#

"*

##

#####

#

####

#

##

# #

#

"* ######

# #

##

#

"*

#

####

#

"******************************************************************************

H, L, X, Z = 1, 0, .X., .Z.;

C, D, U

= .C., .D., .U.;

"******************************************************************************

"* Since all state machines operate at interface clock (IClk) there is no

"* need to have DbgClk driven during simulation (it will double the number

"* of vectors required). Therefore, an alternative clock generator was built

"* with which the 1/2 clock is the 1'st in the chain.

"* This alternative clock is compiled in if the SIMULATION variable is defined.

"* If not the original clock generator design is compiled, however simulation

"* will not pass then.

"******************************************************************************

"* SIMULATION = 1;

"******************************************************************************

"* Signal groups

"******************************************************************************

AdsSel

= [AdsSel2,AdsSel1,AdsSel0];

AdsAddr

= [!AdsAddr2,!AdsAddr1,!AdsAddr0];

AdsRst

Rst

= [AdsHardReset, AdsSoftReset];

= [PdaHardReset~, PdaSoftReset~];

ClkOut

= [Clk2];

DbgClkDiv

DbgClkDivSel

Cstr

= [DbgClkDivBy8, DbgClkDivBy4, DbgClkDivBy2];

= [DbgClkDivSel1, DbgClkDivSel0];

= [Cstr1, Cstr0];

PD

= [PD7,PD6,PD5,PD4,PD3,PD2,PD1,PD0];

= [VFLS0, VFLS1];

VFLS

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VflsP

= [VflsP0,VflsP1];

BndDly

= [BundleDelay1, BundleDelay0]; "bundle delay

"compensation timer

TxReg

= [TxReg7..TxReg0];

RxReg

= [TxReg6,TxReg5,TxReg4,TxReg3,TxReg2,TxReg1,TxReg0,RxReg0];

= [DbgClkDivSel1, DbgClkDivSel0, StatusRequest~,

DiagLoopBack~,DebugEntry~];

AdiCtrlReg

AdiStatReg

= [PdaRst, TxError, InDebugMode, DbgClkDivSel1, DbgClkDivSel0,

StatusRequest~, DiagLoopBack~, DebugEntry~];

TxWordLen

PortEn

= [TxWordLen3, TxWordLen2, TxWordLen1, TxWordLen0];

= [AdsSel2,AdsSel1,AdsSel0,!AdsAddr2,!AdsAddr1,!AdsAddr0,

HostVcc,HstEn~];

"******************************************************************************

"* Select Logic definitions

"******************************************************************************

HOST_VCC_ACTIVE = 1;

HOST_EN~_ACTIVE = 0;

HOST_IS_ON = ((HstEn~==HOST_EN~_ACTIVE) & (HostVcc==HOST_VCC_ACTIVE));

HOST_IS_OFF = !HOST_IS_ON;

BOARD_IS_SELECTED = 0;

ADS_IS_SELECTED = (AdsSelect~.fb==BOARD_IS_SELECTED) ;

"Data_Cntrl~ line levels.

DATA

= 1;

CONTROL = !DATA;

"******************************************************************************

"* Reset Logic definitions

"******************************************************************************

ADS_HARD_RESET_ACTIVE

ADS_SOFT_RESET_ACTIVE

= 1;

"******************************************************************************

"* Clock Logic definitions

"******************************************************************************

SELECT_CHANGE_ALLOWED = (DbgClkDiv.fb == 0);

DEBUG_CLOCK_DIV_BY_1 = (Cstr.fb == 0);

DEBUG_CLOCK_DIV_BY_2 = (Cstr.fb == 1);

DEBUG_CLOCK_DIV_BY_4 = (Cstr.fb == 2);

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DEBUG_CLOCK_DIV_BY_8 = (Cstr.fb == 3);

"******************************************************************************

"* AdsAck Logic definitions

"******************************************************************************

BUNDLE_DELAY = 2;

HOST_REQ_ACTIVE

ADS_ACK_ACTIVE

= 1;

"The other state is - !ADS_ACK_ACTIVE

HOST_ACK_ACTIVE = 1;

HOST_WRITE_ADI

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(DS_HstReq.fb ==HOST_REQ_ACTIVE) &

(AdsAck==!ADS_ACK_ACTIVE) &

(HstAck==!HOST_ACK_ACTIVE) );

HOST_WRITE_ADI_CONTROL

HOST_WRITE_ADI_DATA

HOST_WRITE_COMPLETE

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(DS_HstReq.fb ==HOST_REQ_ACTIVE) &

(AdsAck==!ADS_ACK_ACTIVE) &

(D_C~==CONTROL) &

(S_D_C~.fb == CONTROL) &

(HstAck==!HOST_ACK_ACTIVE) );

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(DS_HstReq.fb==HOST_REQ_ACTIVE) &

(AdsAck==!ADS_ACK_ACTIVE) &

(D_C~==DATA) &

(S_D_C~.fb ==DATA) &

(HstAck==!HOST_ACK_ACTIVE) );

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(DS_HstReq.fb==!HOST_REQ_ACTIVE) &

(AdsAck==!ADS_ACK_ACTIVE) );

"******************************************************************************

"* Control & Status register definitions

"******************************************************************************

STATUS_REQUEST= 0;

DEBUG_ENTRY= 0;

DIAG_LOOP_BACK= 0;

IN_DEBUG_MODE

= 1;

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TX_DONE_OK= 0;

TX_INTERRUPTED = !TX_DONE_OK;

FRZ_SELECTED

= 0;

IS_STATUS_REQUEST = (StatusRequest~.fb == STATUS_REQUEST);

DEBUG_MODE_ENTRY = (DebugEntry~.fb == DEBUG_ENTRY);

IN_DIAG_LOOP_BACK = (DiagLoopBack~.fb == DIAG_LOOP_BACK);

IS_IN_DEBUG_MODE = (InDebugMode.fb == IN_DEBUG_MODE);

FRZ_IS_SELECTED

= (VflsFrz~ == FRZ_SELECTED);

"******************************************************************************

"* DSDI_ENABLE Logic definitions

"******************************************************************************

DSDI_ENABLED = 1;

DSDI_DISABLED = 0;

STATE_DSDI_ENABLED = (DsdiEn.fb == DSDI_ENABLED);

"******************************************************************************

"* Tx enable state machine

"******************************************************************************

TX_ENABLED = 1;

TX_DISABLED = 0;

STATE_TX_ENABLED = (TxEn.fb == TX_ENABLED);

STATE_TX_DISABLED = (TxEn.fb == TX_DISABLED);

TX_WORD_LENGTH = 14; " In 1/2 IClk clocks

"******************************************************************************

"* TxClkSns state machine

"******************************************************************************

TX_ON_RISING = 0;

TX_ON_FALLING = 1;

STATE_TX_ON_RISING = (TxClkSns.fb == TX_ON_RISING);

STATE_TX_ON_FALLING = (TxClkSns.fb == TX_ON_FALLING);

"******************************************************************************

"* AdsReq machine definitions.

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"******************************************************************************

ADS_REQ_ACTIVE = 1;

"The other state is - !ADS_REQ_ACTIVE

HOST_READ_ADI

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(DS_HstAck.fb==HOST_ACK_ACTIVE) &

(AdsReq==ADS_REQ_ACTIVE) &

(HstReq==!HOST_REQ_ACTIVE) );

HOST_READ_ADI_DATA

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(DS_HstAck.fb==HOST_ACK_ACTIVE) &

(HstReq==!HOST_REQ_ACTIVE) &

(AdsReq==ADS_REQ_ACTIVE) &

(D_C~==DATA) );

HOST_READ_ADI_CONTROL

ADS_SEND_STATUS

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(DS_HstAck.fb==HOST_ACK_ACTIVE) &

(HstReq==!HOST_REQ_ACTIVE) &

(AdsReq==ADS_REQ_ACTIVE) &

(D_C~==CONTROL) );

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(DS_HstReq.fb == !HOST_REQ_ACTIVE) &

(D_C~==CONTROL) &

(AdsAck==ADS_ACK_ACTIVE) &

IS_STATUS_REQUEST );

"******************************************************************************

"* ADI Data Bus definitions

"******************************************************************************

DATA_BUFFERS_ENABLE

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(HstAck==HOST_ACK_ACTIVE) &

(HstReq==!HOST_REQ_ACTIVE) );

STATUS_WORD_ON_ADI_BUS

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(HstAck==HOST_ACK_ACTIVE) &

(HstReq==!HOST_REQ_ACTIVE) &

(D_C~==CONTROL) );

READ_DATA_WORD_ON_ADI_BUS

= ( (AdsSelect~.fb==BOARD_IS_SELECTED) &

(HstAck==HOST_ACK_ACTIVE) &

(HstReq==!HOST_REQ_ACTIVE) &

(D_C~== DATA) );

"******************************************************************************

"* Vfls / Frz select definitions

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"******************************************************************************

CHIP_IN_SOCKET = 0;

CHIP_IS_IN_SOCKET = (ChinS~ == CHIP_IN_SOCKET);

"******************************************************************************

"* Equations, state diagrams.

*

"******************************************************************************

"*

*

"* #######

"* #

####

#

##

#####

#

####

#

####

"* #

#

##

# #

#

"* #####

"* #

#

####

# #

#

######

# #

##

#

"* #

#

"* #######

"*

### #

####

#

####

"******************************************************************************

"* AdsSelect.

*

"* ADS selection indicator. At low state, when host accesses the ADS.

"******************************************************************************

equations

!AdsSelect~ = HOST_IS_ON & (AdsSel==AdsAddr); "AdsAddr is already inverted

"******************************************************************************

"* Internal Logic Reset.

"******************************************************************************

equations

PrimReset = HOST_IS_OFF #

"internal logic reset

( (AdsHardReset == ADS_HARD_RESET_ACTIVE) &

(AdsSoftReset ==ADS_SOFT_RESET_ACTIVE) &

ADS_IS_SELECTED );

D_PrimReset = PrimReset.fb;

DD_PrimReset = D_PrimReset.fb;

Reset = PrimReset.fb & D_PrimReset.fb & DD_PrimReset.fb;" spike filter

"******************************************************************************

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"* Reset MPC8XX. (Connected to MPC8XX hard and reset inputs) Asynchronous.

*

"******************************************************************************

equations

!PdaHardReset~ = H;

PdaHardReset~.oe = PdaHardResetEn; "open-drain

PdaHardResetEn = ADS_IS_SELECTED &

(AdsHardReset==ADS_HARD_RESET_ACTIVE);

!PdaSoftReset~ = H;

PdaSoftReset~.oe = PdaSoftResetEn; "needs to be open-drain

PdaSoftResetEn = ADS_IS_SELECTED &

(AdsSoftReset==ADS_SOFT_RESET_ACTIVE );

"******************************************************************************

"* Clock generator.

"* All i/f logic works on IClk, which is driven externally by the output

"* of DbgClk divider.

"* The debug clock divider is a 3 bit free-running counter, outputs of which

"* control a 4:1 mux, output of which drives IClk (externally).

"* Since mux control may change on the fly, a protection logic by means of

"* 2 bit register is provided, so that mux control is allowed to change

"* only when all divider outputs are high which assures a falling edge prior

"* to a rising edge.

"* Clk2 is infact the source for DSCK and is available outside for debug

"* purpose.

"******************************************************************************

equations

DbgClkDiv.clk = DbgClk;

DbgClkDiv := DbgClkDiv.fb + 1; " free running counter.

"******************************************************************************

"* Clock Safe Transition Register. (CSTR)

"* The goal of this register is to provide safe clock transitions, i.e., that

"* a trasition will not cause races over the clockout. E.g., in a transition

"* between divide by 1 and divide by any bigger order, a possible race may

"* occur since the divided outputs are delayed with respect to DbgClk.

"* Therefore, a safe transition may be performed only when all clocks are LOW.

"******************************************************************************

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equations

Cstr.clk = DbgClk;

"* Cstr.ar = Reset;

when (SELECT_CHANGE_ALLOWED) then

Cstr := DbgClkDivSel.fb;

else

Cstr := Cstr.fb;

"******************************************************************************

"* Clock selector.

"* Controlled by the CSTR.

"******************************************************************************

equations

DbgClkOut.oe = 1;

when (DEBUG_CLOCK_DIV_BY_1) then

DbgClkOut = DbgClk;

else when (DEBUG_CLOCK_DIV_BY_2) then

DbgClkOut = DbgClkDivBy2.fb;

else when (DEBUG_CLOCK_DIV_BY_4) then

DbgClkOut = DbgClkDivBy4.fb;

else when (DEBUG_CLOCK_DIV_BY_8) then

DbgClkOut = DbgClkDivBy8.fb;

"******************************************************************************

"* Clk2.

"* IClk divided by 2 .

"******************************************************************************

equations

Clk2.clk = IClk;

ClkOut.oe = 3;

ClkOut.ar = Reset;

Clk2 := !Clk2 & HOST_IS_ON;

"divide by 2

"******************************************************************************

"* Bundle delay timer. This timer ensures data validity in the following casses:

"* 1) Host write to adi. In that case AdsAck is ASSERTED only after that timer

"*

expired.

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"* 2) Host read from adi. In that case AdsReq is NEGATED after that timer

"*

expired, ensuring enough time for data propgation over the bundle.

"* The timer is async reset when both soft and hard reset is applied to the i/f.

"* The timer is sync. reset a clock after it expires.

"* Count starts when either HstReq or HstAck are detected asserted

"* (after proper synchronization)

"* The value upon which the terminal count is assereted, is in the control

"* register. When the interface is reset by the host, this value defaults

"* to its upper bound. Using the diagnostic loop-back mode this value

"* may be re-established for optimal performance. (by means of test & error)

"******************************************************************************

equations

BndDly.ar = Reset;

BndDly.clk = IClk;

when ( ( (HOST_WRITE_ADI_CONTROL # HOST_READ_ADI_CONTROL ) #

(HOST_WRITE_ADI_DATA # HOST_READ_ADI_DATA) & !PdaRst.fb)

& !BndTmrExp.fb) then

BndDly := BndDly.fb +1;

else

BndDly := 0;

BndTmrExp = (BndDly.fb == BUNDLE_DELAY) & !AdsAck ; "delay field

"active low.

"******************************************************************************

"* AdsAck.

"* Host write to ads ack. This state machine generates an automatic ADS_ACK,

"* during a host to ADS write.

"* When the host access the ADS data / control register, an automatic

"* acknowledge is generated, after data has been latched into either the

"* tx shift register or the control register.

"* Acknowledge is released when the host removes its write control line.

"* (HstReq)

"*

"* The machine steps through these states :

"* 0 - !ADS_ACK_ACTIVE

"* 1 - ADS_ACK_ACTIVE

"******************************************************************************

equations

AdsAck.clk = IClk;

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AdsAck.ar

AdsAck.oe

= Reset;

= ADS_IS_SELECTED;

S_HstReq.clk = IClk;

DS_HstReq.clk = IClk;

S_HstReq := HstReq;

DS_HstReq := S_HstReq.fb & HstReq;"double synced

S_D_C~.clk = IClk;" synchronizing D_C~ selector

S_D_C~ := D_C~;

state_diagram AdsAck

state !ADS_ACK_ACTIVE:

if ( (HOST_WRITE_ADI_CONTROL #

(HOST_WRITE_ADI_DATA & !PdaRst.fb) ) & BndTmrExp.fb) then

ADS_ACK_ACTIVE

else

!ADS_ACK_ACTIVE;

state ADS_ACK_ACTIVE:

if ( DS_HstReq.fb==!HOST_REQ_ACTIVE ) then

!ADS_ACK_ACTIVE

else

ADS_ACK_ACTIVE;

"******************************************************************************

"* Transmit Enable logic.

"* Enables transmit of serial data over DSDI and generation of serial

"* clock over DSCK.

"* Transmission begins immediately after data written by the host is latched

"* into the transmit shift register and ends after 7 shifts were made to the

"* tx shift register.

"* Termination is done using a 4 bit counter TxWordLength which has a terminal

"* count (and reset) TxWordEnd.

"******************************************************************************

equations

TxEn.ar = Reset;

TxEn.clk = IClk;" to provide 1/2 clock resolution

state_diagram TxEn

state TX_DISABLED:

if(HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then

TX_ENABLED

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else

TX_DISABLED;

state TX_ENABLED:

if(TxWordEnd # PdaRst.fb) then

TX_DISABLED

else

TX_ENABLED;

"******************************************************************************

"* Transmit Length Counter. This counter determines the length of transmission

"* towards the MPC. The fast clock is used here to allow 1/2 clock resolution

"* with the negation of TxEn, which enables DSCK outside.

"******************************************************************************

equations

TxWordLen.ar = Reset;

TxWordLen.clk = IClk;

TxWordEnd = (TxWordLen.fb == TX_WORD_LENGTH);

when ( STATE_TX_ENABLED & !TxWordEnd & !PdaRst.fb) then

TxWordLen.d = TxWordLen.fb + 1;

else

TxWordLen.d = 0;

"******************************************************************************

"* TxClkSns - Transmit Clock Sense.

"* Since Host req is synced acc to IClk and may be detected active when Clk2 is

"* either '1' or '0', DSCK and the clock according to which DSDI is sent and

"* DSDO is sampled should be changed.

"* When TxClkSns is '0' - DSCK will be !Clk2 while transmit will be done

"*

"* When TxClkSns is '1' - DSCK will be Clk2 while transmit will be done

"* according to !Clk2~ and recieve by Clk2.

according to Clk2 and recieve by !Clk2.

"******************************************************************************

equations

TxClkSns.clk = IClk;

TxClkSns.ar = Reset;

state_diagram TxClkSns

state TX_ON_RISING:

if (HOST_WRITE_ADI_DATA & BndTmrExp.fb & Clk2) then

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TX_ON_FALLING

else

TX_ON_RISING;

state TX_ON_FALLING:

if (HOST_WRITE_ADI_DATA & BndTmrExp.fb & !Clk2) then

TX_ON_RISING

else

TX_ON_FALLING;

"******************************************************************************

"* Tx shift Register.

"* 8 bits shift register which either shifts data out (MSB first) or holds

"* its data. The edge (in Clk2 terms) upon which the above actions are taken,

"* is determined by TxClkSns. The Tx shift register operates according to IClk.

"* The Tx shift register is 1'st written by the host (data cycle) and along

"* with write being acknowledged to the host data is shifted out via DSDI.

"*

"* In order of saving logic, the Tx shift register is shared with the Receive

"* shift register, this, due to the fact that when a bit is shifted out a FF

"* becomes available. Since the Tx shift register is shifted MSB first, its

"* LSB FFs are grdualy becoming available for received data.

"* To provide a 1/2 DSCK hold time for DSDI, a single FF receive SR is used

"* which is the source for the Tx shift register. (if 0 hold is required

"* for DSDI this FF may be ommited)

"******************************************************************************

equations

TxReg.clk = IClk;

TxReg.ar = Reset;

when ( HOST_WRITE_ADI_DATA & BndTmrExp.fb & !STATE_TX_ENABLED) then

[TxReg7..TxReg1] := [PD7..PD1].pin;

" latching ADI data

else when (STATE_TX_ENABLED & STATE_TX_ON_RISING & !Clk2 #

STATE_TX_ENABLED & STATE_TX_ON_FALLING & Clk2) then

[TxReg7..TxReg1] := [TxReg6..TxReg0].fb; " shifting out MSB 1'st.

else

[TxReg7..TxReg1] := [TxReg7..TxReg1].fb; " Holding value.

when ( HOST_WRITE_ADI_DATA & BndTmrExp.fb & !STATE_TX_ENABLED) then

TxReg0 := PD0.pin;

else when (STATE_TX_ENABLED & STATE_TX_ON_RISING & !Clk2 #

STATE_TX_ENABLED & STATE_TX_ON_FALLING & Clk2) then

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TxReg0 := RxReg0.fb;

else

TxReg0 := TxReg0.fb;

"******************************************************************************

"* Receive Shift Register.

"* A single stage shift register used as a source for the Tx shift register.

"* In normal mode the input for the Rx shift register is the MPC8XX's DSDO, while

"* in diagnostic loopback mode, data is taken directly from the Tx shift

"* serial output.

"*

"* The output of the Rx shift register is fed to the input of the Tx shift

"* register. When transmission (and reception) is done the received data

"* word is compossed of the Rx shift register (LSB) concatenated with the

"* 7 LSBs of the Tx shift register.

"*

"* The edge (in Clk2 terms) upon which data is shifted in is determined by

"* TxClkSns as with the Tx shift register but on opposite edges, i.e.,

"* data is shifted Out from the Tx shift register on the Falling edge of

"* DSCK while is shifted In to the Rx shift register on the Rising edge

"* DSCK. (DSCK terms are constant in that regard).

"******************************************************************************

equations

RxReg0.clk = IClk;

RxReg0.ar = Reset;

when ( STATE_TX_ENABLED & STATE_TX_ON_RISING & Clk2 #

STATE_TX_ENABLED & STATE_TX_ON_FALLING & !Clk2) & (!IN_DIAG_LOOP_BACK) then

RxReg0.d = DSDO;

"shift in ext data

else when ( STATE_TX_ENABLED & STATE_TX_ON_RISING & Clk2 #

STATE_TX_ENABLED & STATE_TX_ON_FALLING & !Clk2) & IN_DIAG_LOOP_BACK then

RxReg0.d = TxReg7.fb;" shift in from transmit reg

else

RxReg0.d = RxReg0.fb;" hold value

"******************************************************************************

"* AdsReq.

"* Host from ads, read acknowledge. This state machine generates an automatic

"* ADS read request from the host when either a byte of data is received in the

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"* Rx shift register or the status request bit in the control register is

"* active during a previous host write to the control register.

"* When the host detectes AdsReq asserted, it assertes HstAck in return. HstAck

"* double synchronized from the ADI port and delayed using the bundle delay

"* compensation timer to negate AdsReq. When the host detects AdsReq negated

"* it knows that data is valid to be read. After the host reads the data it

"* negates HstAck.

"* The machine steps through these states :

"* 0 - !ADS_REQ_ACTIVE

"* 1 - ADS_REQ_ACTIVE

"******************************************************************************

equations

AdsReq.clk = IClk;

AdsReq.ar

AdsReq.oe

= Reset;

= ADS_IS_SELECTED;

S_HstAck.clk = IClk;

DS_HstAck.clk = IClk;

S_HstAck := HstAck;

DS_HstAck := HstAck & S_HstAck;"double synced

state_diagram AdsReq

state !ADS_REQ_ACTIVE:

if ( TxEn.fb & TxWordEnd

#" end of data shift to MPC8XX

ADS_SEND_STATUS) then" end of control write and status required

ADS_REQ_ACTIVE

else

!ADS_REQ_ACTIVE;

state ADS_REQ_ACTIVE:

if ( HOST_READ_ADI & BndTmrExp.fb ) then

!ADS_REQ_ACTIVE

else

ADS_REQ_ACTIVE;

"******************************************************************************

"* ADI control register.

"* The ADI control register is written upon host to ADI write with a

"* D_C~ line is in control mode. It also may be read when StatusRequest~ bit

"* is active.

"*

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"* Control register bits description:

"*

"* DebugEntry~: (Bit 0). When this bit is active (L), the MPC8XX will enter debug

"* mode immediately after reset, i.e., DSCK will be held high

"* after the rising edge of SRESET*. When negated, DSCK will be

"* held low after the rising edge of SRESET so the MPC8XX will start

"* running instantly.

"* DiagLoopBack~: (Bit 1). When active (L), the interface is in Diagnostic

"* Loopback mode. I.e., the source for the Rx shift register is

"* the output of the Tx shift register. During that mode, DSCK

"* and DSDI are tri-stated, so no arbitrary data is sent to the

"* debug port. When inactive, the interface is in normal mode,

"* i.e., DSCK and DSDI are driven and the source of the Rx shift

"* register is DSDO.

"* StatusRequest~: (Bit 2). When active (L) any write to the control register

"* will be followed by a status read cycle initiated by the

"* debug port controller, i.e., AdsReq will be asserted after

"* the write cycle ends. When inactive, a write to the control

"* register will not be followed by a read from status register.

"* DbgClkDivSel(1:0) : (Bits 4,3). This field selects the division of the

"*

DbgClk input. Division factors are set as follows:

"* 0 - by 1

"* 1 - by 2

"* 2 - by 4

"* 3 - by 8

"*

"* Important!!! All bits wake up active (L) after reset.

"*

"******************************************************************************

equations

AdiCtrlReg.clk = IClk;

AdiCtrlReg.ar = Reset;"All active low.

when ( HOST_WRITE_ADI_CONTROL & BndTmrExp.fb) then

AdiCtrlReg.d = [PD4.pin, PD3.pin, PD2.pin, PD1.pin, PD0.pin];

else

AdiCtrlReg.d = AdiCtrlReg.fb;

"******************************************************************************

"* ADI Data Bus.

"* The Adi data bus is driven towards the host when the host reads the i/f.

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"* When D_C~ line is high (data) the Rx shift register contents is driven. If

"* D_C~ is low (control) the status register contents is driven.

"* The status register contains all control register's bits (4:0) with the

"* addition of the following:

"*

"* InDebugMode: (Bit 5). When this bit is active (H), the mpc is in debug mode,

"* i.e., either Freeze or VFLS(0:1) lines are driven high.

"*

When mpc is not in socket, VflsP(0:1) coming from the debug port

are selected.

"* TxError: (Bit 6). When this bit is active (H), it signals that the MPC8XX was

"* reset (internally) during data transmission. (i.e., data received

"* during that trnasmission is corrupted). This bit is reset (L) when

"* either happens: (1) - The interface is reset by the host (both

"*AdsHardReset and AdsSoftReset are asserted (H) by the host

"* while the board is selected). (2) - The host writes the interface with

"* D_C~ signal low (control) and with data bit 6 high. (3) - a new data

"* word is written to the Tx shift register. (I.e., error is not kept

"*indefinitely).

"* PdaRst: (Bit 7). When this bit is active (H), it means that either SRESET*

"*or HRESET* or both are driven by the MPC8XX. The host have to wait until

"* this bit negates so that data may be wrriten to the debug port.

"******************************************************************************

equations

PDOe = DATA_BUFFERS_ENABLE ;

PD.oe = PDOe;

when ( READ_DATA_WORD_ON_ADI_BUS) then

PD = RxReg.fb;

elsewhen ( STATUS_WORD_ON_ADI_BUS ) then

PD = [PdaRst.fb, TxError.fb, InDebugMode.fb, DbgClkDivSel1.fb, DbgClkDivSel0.fb,

StatusRequest~.fb, DiagLoopBack~.fb, DebugEntry~.fb ];

"******************************************************************************

"* Reset Status

"******************************************************************************

PdaRst.clk = IClk;

PdaRst := (!PdaHardReset~ # !PdaSoftReset~) &

(AdsSelect~.fb==BOARD_IS_SELECTED);

" synchronized inside.

"******************************************************************************

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"* In debug Mode

"******************************************************************************

InDebugMode.clk = IClk;

when (FRZ_IS_SELECTED & CHIP_IS_IN_SOCKET) then

InDebugMode := Freeze;

else when (!FRZ_IS_SELECTED & CHIP_IS_IN_SOCKET) then

InDebugMode := (VFLS0 & VFLS1);

else when (!CHIP_IN_SOCKET) then

InDebugMode := (VflsP0.pin & VflsP1.pin);

"******************************************************************************

"* TxError.

"* This bit of the status register is set ('1') when the MPC8XX internally resets

"* during data transmission over the debug port.

"* When this bit is writen '1' by the adi port (control) the status bit is

"* cleared. Writing '0' has no influence on that bit.

"******************************************************************************

equations

TxError.clk = IClk;

TxError.ar = Reset;

state_diagram TxError

state TX_DONE_OK:

if(STATE_TX_ENABLED & PdaRst.fb) then

TX_INTERRUPTED

else

TX_DONE_OK;

state TX_INTERRUPTED:

if (HOST_WRITE_ADI_CONTROL & BndTmrExp.fb & PD6.pin

# HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then

TX_DONE_OK

else

TX_INTERRUPTED;

"******************************************************************************

"* DSCK.

"* MPC8XX debug port, gated serial clock.

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"******************************************************************************

equations

DSCK.oe = ADS_IS_SELECTED;

when ( ADS_IS_SELECTED & !PdaSoftReset~ ) then

DSCK = H;"debug mode enable

else when ( ADS_IS_SELECTED & !TxEn.fb & PdaSoftReset~ ) then

DSCK = !DebugEntry~.fb;"debug mode direct entry

else when (ADS_IS_SELECTED & TxEn.fb & STATE_TX_ON_RISING) then

DSCK = !Clk2;"debug port clock

else when (ADS_IS_SELECTED & TxEn.fb & STATE_TX_ON_FALLING) then

DSCK = Clk2;"debug port inverted clock

else when (!ADS_IS_SELECTED) then

DSCK = H;"default value, infact X

"******************************************************************************

"* DSDI.

"* Debug Port Serial Data in. (from MPC8XX).

"* To provide better hold time for DSDI from the last rising edge of DSCK,

"* a dedicated enable for DSDI is provided - DSDI_ENABLE.

"******************************************************************************

equations

DsdiEn.ar = Reset;

DsdiEn.clk = IClk;

state_diagram DsdiEn

state DSDI_DISABLED:

if(HOST_WRITE_ADI_DATA & BndTmrExp.fb & !PdaRst.fb) then

DSDI_ENABLED

else

DSDI_DISABLED;

state DSDI_ENABLED:

if(STATE_TX_DISABLED # PdaRst.fb) then

DSDI_DISABLED

else

DSDI_ENABLED;

equations

DSDI.oe = ADS_IS_SELECTED & !IN_DIAG_LOOP_BACK; "avoid junk driven on DSDI input

"during diagnostic loop back mode.

when (ADS_IS_SELECTED & !PdaSoftReset~) then

DSDI = H;

else when (ADS_IS_SELECTED & !STATE_DSDI_ENABLED & PdaSoftReset~ ) then

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DSDI = L;

else when (ADS_IS_SELECTED & STATE_DSDI_ENABLED) then

DSDI = TxReg7.fb;

else

DSDI = L;

"******************************************************************************

"* Debug Port VFLS pins.

"******************************************************************************

equations

VflsP.oe = !ADS_IS_SELECTED;

when (!FRZ_IS_SELECTED) then

VflsP = [VFLS0,VFLS1];

else when (FRZ_IS_SELECTED) then

VflsP = [Freeze,Freeze];

"******************************************************************************

"* Run Led

"******************************************************************************

Run.oe = H;

!Run = IS_IN_DEBUG_MODE;"when 1 lits a led.

end dbg_prt7

MPC8XXFADS Design Specification—Rev 0.1

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U11 - Board Control & Status Register

Support Information

A•2

"******************************************************************************

"* In this file (6):

"* - Added board revision # at BCSR3: 0 ENG

"*

1 - PILOT.

"* - Flash Presence detect lines - added FlashPD(7:5).

"* - Changed polarity of Power-On Reset (now active high)

"* - DramEn becomes active-low to enhance debug-station support changes.

"******************************************************************************

"* In this file (7):

"* - Board revisiob code @ BCSR3 is changed to 2 - Rev A.

"******************************************************************************

"* In this file (8):

"* - Board revisiob code @ BCSR3 is changed to 3 - Rev B.

"* - Added RS232En2~ for 2'nd RS232 port.

"******************************************************************************

"* In this file (9):

"* - All status bits (except CntRegEnProtect~) are removed for external buffers.

"* - Added address line A27

"* - Added BCSR2CS~ and BCSR3CS~ for external status registers.

"* - Added controls on bcsr1:

"*

- SdramEn~

- PccVcc1~

"* - Added BCSR4 with following controls:

"*

- UsbUtpFethEn~ (bit 0) enables Usb or Utopia or Fast Ethernet ports

- UsbSpeed (bit 1) Usb speed control ('1'- full speed)

- UsbVcc0(bit 2) enables VCC for Usb channel

- UsbVcc1 (bit 3) reserved for possible 3.3V usb power

- VideoOn~(bit 4) enables video transceiver

- VideoExtClkEn (bit 5) enables ext 27Mhz clock for video encoder

- VideoRst~(bit 6) resets the video encoder.

- SignaLamp(bit 7) used for s/w signaling to user.

"******************************************************************************

"* In this file (10):

"* - Added ethernet transceiver control signals to BCSR4:

"*

- EthLoop

- TPFFLDL~

- TPSQEL~

(bit 8) sets the transceiver to internal loopback (H)

(bit 9) sets the trans. to full-duplex mode. (L)

(bit 10) allows for testing the colission ciruitry

of the 68160.

- ModemEne~

(bit 11) enables the modem tool with the MPC823FADSDB

(bit 12) selects between modem / audio function for

- Modem_Audio~

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Support Information

"*

modem tool with MPC823 daughter board.

"******************************************************************************

module bcsr10

title 'MPC8XXFADS Board Control and Status Register'

"******************************************************************************

"* Device declaration.

*

"******************************************************************************

U11 device 'mach220a';

"******************************************************************************

"* #######

"* #

*

#

##### ###### #####

#

##

#

####

*

"* #

#

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# #

#

"* #####

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"* #

#

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######

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####

"******************************************************************************

"* Pins declaration.

*

"******************************************************************************

"* System i/f pins

"******************************************************************************

SYSCLKPIN 15;

RGPORInPIN 54;

ResetConf~PIN 45;

BrdContRegCs~PIN 49;

TA~ PIN 16;

R_W~PIN 50;

A27 PIN 17;

A28 PIN 20;

A29 PIN 51;

D0 PIN 10;

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D1 PIN 11;

D2 PIN 12;

D3 PIN 13;

D4 PIN 33;

D5 PIN 14;

D6 PIN 25;

D7 PIN 24;

D8 PIN 23;

D9 PIN 22;

D10 PIN 21;

D11 PIN 29;

D12 PIN 30;

D13 PIN 31;

D14 PIN 32;

D15 PIN 9;

"******************************************************************************

"* Board Control Pins. Read/Write.

"******************************************************************************

FlashEn~PIN 62 istype 'reg,buffer';

DramEn~PIN 7 istype 'reg,buffer';

EthEn~PIN 6 istype 'reg,buffer';

InfRedEn~PIN 41 istype 'reg,buffer';

" flash enable.

" dram enable

" ethernet port enable

" infra-red port enable

FlashCfgEn~PIN 37 istype 'reg,buffer';

CntRegEn~PIN 36 istype 'reg,buffer';

RS232En1~PIN 63 istype 'reg,buffer';

" flash configuration enable

" control register access enable

" RS232 port 1 enable

PccEn~PIN 40 istype 'reg,buffer';

PccVcc0PIN 65 istype 'reg,buffer';

PccVpp0PIN 59 istype 'reg,buffer';

PccVpp1PIN 66 istype 'reg,buffer';

HalfWord~PIN 58 istype 'reg,buffer';

RS232En2~PIN 64 istype 'reg,buffer';

SdramEn~PIN 56 istype 'reg,buffer';

PccVcc1PIN 57 istype 'reg,buffer';

" PCMCIA port enable

" PCMCIA operation voltage select 0

" PCMCIA programming voltage select

" 32/16 bit dram operation select

" RS232 port 2 enable

" sdram enable

" PCMCIA operation voltage select 1

EthLoop

TPFLDL~

TPSQEL~

PIN 60 istype 'reg,buffer';

PIN 43 istype 'reg,buffer';

PIN 44 istype 'reg,buffer';

" 68160 internal loop back

" 68160 full-duplex

" 68160 colission circuitry test.

" status lamp for misc s/w visual signaling

" Usb or Utopia or Fast ethernet port enable

SignaLamp~PIN 4 istype 'reg,buffer';

UsbUtpFethEn~ PIN 67 istype 'reg,buffer';

UsbSpeedPIN 46 istype 'reg,buffer';

UsbVcc0PIN 3 istype 'reg,buffer';

" Usb speed control

" Usb VCC select 0 line

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UsbVcc1PIN 2 istype 'reg,buffer';

VideoOn~PIN 39 istype 'reg,buffer';

" Usb VCC select 1 line

" Video encoder enable

VideoExtClkEn PIN 38 istype 'reg,buffer'; " Enable external clock gen for video encoder

VideoRst~PIN 5 istype 'reg,buffer'; " Video Encoder reset

PIN 28 istype 'reg,buffer'; " modem tool enable for MPC823FADSDB

PIN 55 istype 'reg,buffer';

ModemEn~

Modem_Audio~

" Modem / Audio functions select

" for modem tool with MPC823 d/b.

"******************************************************************************

"* Board Status Pins. Read only.

"******************************************************************************

"* removed to external buffers

"******************************************************************************

"* Board Status Registers Chip-Selects

"******************************************************************************

Bcsr2Cs~PIN 47 istype 'com';

Bcsr3Cs~PIN 48 istype 'com';

"******************************************************************************

"* Auxiliary Pins.

"******************************************************************************

"*

###

#

*

#

##### ###### #####

#

##

#

####

*

#

##

# #

#

##

# #

#

#####

#

####

#

# #

##

#

#####

# # ######

#

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####

"******************************************************************************

"* System Hard Reset Configuration.

"******************************************************************************

ERBNODE istype 'reg,buffer';

IP~NODE istype 'reg,buffer';

BDISNODE istype 'reg,buffer';

RSV2NODE istype 'reg,buffer';

BPS0,

" External Arbitration

" Interrupt Prefix in MSR

" Boot Disable

" reserved config bit 2

BPS1NODE istype 'reg,buffer';

RSV6NODE istype 'reg,buffer';

ISB0,

" Boot Port Size

" reserved config bit 6

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ISB1NODE istype 'reg,buffer';

DBGC0,

" Internal Space Base

DBGC1NODE istype 'reg,buffer';

DBPC0,

" Debug pins Config.

DBPC1NODE istype 'reg,buffer';

" Debug Port pins Config

" reserved config bit 13

" reserved config bit 14

" reserved config bit 15

RSV13

RSV14

RSV15

NODE istype 'reg,buffer';

DataOeNODE istype 'com';" data bus output enable on read.

"******************************************************************************

"* Control Register Enable Protection.

"******************************************************************************

CntRegEnProtect~NODE istype 'reg,buffer';

"******************************************************************************

"* Control Register Write (space saving) Mach 10 required for 52Mhz

"******************************************************************************

Bcsr0Write~ NODE istype 'com';

Bcsr1Write~ NODE istype 'com';

Bcsr4Write~ NODE istype 'com';

"******************************************************************************

"* #####

*

"* #

#

####

#

####

#####

##

#

#####

#

##

# #

#

##

# #

#

####

#

# #

##

#

######

# #

##

#

"* #####

"*

####

#

####

#

MPC8XXFADS Design Specification—Rev 0.1

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Support Information

"* ######

*

"* #

#

######

####

#

##

#####

#

#####

#

#####

#

###### #####

#

"* ######

"*

######

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"*

##

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"*

#

####

#

"******************************************************************************

H, L, X, Z = 1, 0, .X., .Z.;

C, D, U

= .C., .D., .U.;

"******************************************************************************

"* SIMULATION = 1;

"* SLOW_PLL_LOCK = 1;

"* DRAM_8_BIT_OPERATION = 1;

"******************************************************************************

"* Signal groups

"******************************************************************************

Add = [A27,A29];

Data = [D0..D15];

ConfigReg = [ERB,IP~,RSV2,BDIS,

BPS0,BPS1,RSV6,ISB0,

ISB1,DBGC0,DBGC1,DBPC0,

DBPC1,RSV13,RSV14,RSV15];

BPS = [BPS0,BPS1];" boot port size

ISB = [ISB0,ISB1];" Initial Internal Space Base

DBGC = [DBGC0,DBGC1];" Debug Pins Configuration

DBPC = [DBPC0,DBPC1];" Debug port location

ContReg = [FlashEn~,

DramEn~,EthEn~,InfRedEn~,FlashCfgEn~,

CntRegEnProtect~,CntRegEn~,RS232En1~,PccEn~,

PccVcc0,PccVpp0,PccVpp1,HalfWord~,

RS232En2~,SdramEn~,PccVcc1,EthLoop,

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TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~,

UsbSpeed,UsbVcc0,UsbVcc1,VideoOn~,

VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~];

ReadBcsr1 = [FlashEn~,DramEn~,EthEn~,InfRedEn~,

FlashCfgEn~,CntRegEnProtect~.fb,CntRegEn~,RS232En1~,

PccEn~,PccVcc0,PccVpp0,PccVpp1,

HalfWord~,RS232En2~,SdramEn~,PccVcc1];

ReadBcsr4 = [EthLoop,

TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~,

UsbSpeed,UsbVcc0, UsbVcc1 ,VideoOn~,

VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~];

DrivenContReg = [FlashEn~,DramEn~,EthEn~,InfRedEn~,

FlashCfgEn~,CntRegEn~,RS232En1~,PccEn~,

PccVcc0,PccVpp0,PccVpp1,HalfWord~,

RS232En2~,SdramEn~,PccVcc1,EthLoop,

TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~,

UsbSpeed,UsbVcc0,UsbVcc1,VideoOn~,

VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~];

PccVcc = [PccVcc0,PccVcc1];

PccVpp = [PccVpp0,PccVpp1];

WideContReg = [FlashEn~,

DramEn~,EthEn~,InfRedEn~,FlashCfgEn~,

CntRegEnProtect~,CntRegEn~,RS232En1~,PccEn~,

PccVcc0,PccVpp0,PccVpp1,HalfWord~,

RS232En2~,SdramEn~,PccVcc1,EthLoop,

TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~,

UsbSpeed,UsbVcc0,UsbVcc1,VideoOn~,

VideoExtClkEn,VideoRst~,ModemEn~,Modem_Audio~];

Bcsr2_3Cs~ = [Bcsr2Cs~,Bcsr3Cs~];

"******************************************************************************

"* Power On Reset definitions

"******************************************************************************

FLASH_CFG_ENABLE = 0;

K_A_PON_RESET_ACTIVE = 1;

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RESET_CONFIG_ACTIVE = 0;

"**** changed due to long lock delay of the pda *** 17,7,95 ******************

@ifndef SLOW_PLL_LOCK {

KA_PON_RESET = (RGPORIn == K_A_PON_RESET_ACTIVE);

}

@ifdef SLOW_PLL_LOCK {

PON_DEFAULT_ACTIVE = 0;

KA_PON_RESET = (PonDefault~ == PON_DEFAULT_ACTIVE);

}

"*********** end of change ***************

RESET_CONFIG_DRIVEN = ((ResetConf~ == RESET_CONFIG_ACTIVE) &

(FlashCfgEn~ != FLASH_CFG_ENABLE));

"******************************************************************************

"* Register Access definitions

"******************************************************************************

CONFIG_REG_ADD = 0;

CONTROL_REG_1_ADD = 1;

STATUS_REG2_ADD = 2;

STATUS_REG3_ADD = 3;

CONTROL_REG_4_ADD = 4;

" MPC_WRITE_BCSR_0 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & !A29 & !CntRegEn~);

" MPC_WRITE_BCSR_1 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & A29 & !CntRegEn~);

MPC_WRITE_BCSR_3 = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & A28 & A29 & !CntRegEn~);

"MPC_WRITE_BCSR_4 = (!BrdContRegCs~ & !TA~ & !R_W~ & A27 & !A28 & !A29 & !CntRegEn~);

BCSR_WRITE_ACTIVE = 0;

MPC_WRITE_BCSR_0 = (Bcsr0Write~.fb == BCSR_WRITE_ACTIVE);

MPC_WRITE_BCSR_1 = (Bcsr1Write~.fb == BCSR_WRITE_ACTIVE);

MPC_WRITE_BCSR_4 = (Bcsr4Write~.fb == BCSR_WRITE_ACTIVE);

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MPC_READ = (!BrdContRegCs~ & R_W~ & !CntRegEn~);

MPC_READ_BCSR_0 = (!BrdContRegCs~ & R_W~ & !A27 & !A28 & !A29 & !CntRegEn~);

MPC_READ_BCSR_1 = (!BrdContRegCs~ & R_W~ & !A27 & !A28 & A29 & !CntRegEn~);

MPC_READ_BCSR_2 = (!BrdContRegCs~ & R_W~ & !A27 & A28 & !A29 & !CntRegEn~);

MPC_READ_BCSR_3 = (!BrdContRegCs~ & R_W~ & !A27 & A28 & A29 & !CntRegEn~);

MPC_READ_BCSR_4 = (!BrdContRegCs~ & R_W~ & A27 & !A28 & !A29 & !CntRegEn~);

"******************************************************************************

"* BCSR 0 definitions

"******************************************************************************

INTERNAL_ARBITRATION = 0;

EXTERNAL_ARBITRATION = !INTERNAL_ARBITRATION;

IP_AT_0xFFF00000 = 0;"active low

IP_AT_0x00000000 = !IP_AT_0xFFF00000;

RSV2_ACTIVE = 1;

BOOT_DISABLE = 1;

BOOT_ENABLE = !BOOT_DISABLE;

BOOT_PORT_32 = 0;

BOOT_PORT_8 = 1;

BOOT_PORT_16 = 2;

BOOT_PORT_RESERVED = 3;

RSV6_ACTIVE = 1;

INT_SPACE_BASE_0x00000000 = 0;

INT_SPACE_BASE_0x00F00000 = 1;

INT_SPACE_BASE_0xFF000000 = 2;

INT_SPACE_BASE_0xFFF00000 = 3;

DEBUG_PINS_PCMCIA_2 = 0;

DEBUG_PINS_WATCH_POINTS = 1;

DEBUG_PINS_RESREVED = 2;

DEBUG_PINS_FOR_SHOW = 3;

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DEBUG_PORT_ON_JTAG = 0;

DEBUG_PORT_NON_EXISTANT = 1;

DEBUG_PORT_RESERVED = 2;

DEBUG_PORT_ON_DEBUG_PINS = 3;

RSV13_ACTIVE = 1;

RSV14_ACTIVE = 1;

RSV15_ACTIVE = 1;

"***********************************************

"******* Power On Defaults Assignments *********

"***********************************************

ERB_PON_DEFAULT = INTERNAL_ARBITRATION;

IP~_PON_DEFAULT = IP_AT_0x00000000;

RSV2_PON_DEFAULT = !RSV2_ACTIVE;

BDIS_PON_DEFAULT = BOOT_ENABLE;

BPS_PON_DEFAULT = BOOT_PORT_32;

RSV6_PON_DEFAULT = !RSV6_ACTIVE;

ISB_PON_DEFAULT = INT_SPACE_BASE_0xFF000000;

DBGC_PON_DEFAULT = DEBUG_PINS_PCMCIA_2;

DBPC_PON_DEFAULT = DEBUG_PORT_ON_JTAG;

RSV13_PON_DEFAULT = !RSV13_ACTIVE;

RSV14_PON_DEFAULT = !RSV14_ACTIVE;

RSV15_PON_DEFAULT = !RSV15_ACTIVE;

"*******************************************

"******* Data Bits Assignments *************

"*******************************************

ERB_DATA_BIT = [D0];

IP~_DATA_BIT = [D1];

RSV2_DATA_BIT = [D2];

BDIS_DATA_BIT = [D3];

BPS_DATA_BIT = [D4,D5];

RSV6_DATA_BIT = [D6];

ISB_DATA_BIT = [D7,D8];

DBGC_DATA_BIT = [D9,D10];

DBPC_DATA_BIT = [D11,D12];

RSV13_DATA_BIT = [D13];

RSV14_DATA_BIT = [D14];

RSV15_DATA_BIT = [D15];

"******************************************************************************

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"******************************************************************************

"* BCSR 1 definitions.

"******************************************************************************

HALF_WORD = 0;

ETH_ENABLED = 0;

DRAM_ENABLED = 0;

CONT_REG_ENABLE = 0;

RS232_1_ENABLE = 0;

RS232_2_ENABLE = 0;

PCC_ENABLE = 0;

PCC_VCC_CONT_0 = 0;

PCC_VCC_CONT_1 = 1;

PCC_VPP0 = 1;

PCC_VPP1 = 1;

FLASH_ENABLED = 0;

INF_RED_ENABLE = 0;

"* FLASH_CFG_ENABLE = 0; needed to be defined ealier

DRAM_5V = 0;

DRAM_3V = !DRAM_5V;

CNT_REG_EN_PROTECT = 0; " inadvertant write protect

SDRAM_ENABLED = 1;

"***********************************************

"******* Power On Defaults Assignments *********

"***********************************************

FLASH_ENABLE_PON_DEFAULT = FLASH_ENABLED;

FLASH_CFG_ENABLE_PON_DEFAULT = !FLASH_CFG_ENABLE;

DRAM_ENABLE_PON_DEFAULT = DRAM_ENABLED;

ETH_ENABLE_PON_DEFAULT = !ETH_ENABLED;

CONT_REG_ENABLE_PON_DEFAULT = CONT_REG_ENABLE;

RS232_1_ENABLE_PON_DEFAULT = !RS232_1_ENABLE;

RS232_2_ENABLE_PON_DEFAULT = !RS232_2_ENABLE;

PCC_ENABLE_PON_DEFAULT = !PCC_ENABLE;

PCC_VCC_0_PON_DEFAULT = PCC_VCC_CONT_0;

PCC_VCC_1_PON_DEFAULT = PCC_VCC_CONT_0;

PCC_VPP0_PON_DEFAULT = PCC_VPP0;

PCC_VPP1_PON_DEFAULT = PCC_VPP1;

" T.S. as default

INF_RED_ENABLE_PON_DEFAULT = !INF_RED_ENABLE;

HALF_WORD_PON_DEFAULT = !HALF_WORD;

SDRAM_ENABLE_PON_DEFAULT = SDRAM_ENABLED;

CNT_REG_EN_PROTECT_PON_DEFAULT = CNT_REG_EN_PROTECT;

"*******************************************

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"******* Data Bits Assignments *************

"*******************************************

FLASH_ENABLE_DATA_BIT = [D0];

DRAM_ENABLE_DATA_BIT = [D1];

ETH_ENABLE_DATA_BIT = [D2];

INF_RED_ENABLE_DATA_BIT = [D3];

FLASH_CFG_ENABLE_DATA_BIT = [D4];

CNT_REG_EN_PROTECT_DATA_BIT = [D5];

CONT_REG_ENABLE_DATA_BIT = [D6];

RS232_1_ENABLE_DATA_BIT = [D7];

PCC_ENABLE_DATA_BIT = [D8];

PCC_VCC_0_DATA_BIT = [D9];

PCC_VPP0_DATA_BIT = [D10];

PCC_VPP1_DATA_BIT = [D11];

HALF_WORD_DATA_BIT = [D12];

RS232_2_ENABLE_DATA_BIT = [D13];

SDRAM_ENABLE_DATA_BIT = [D14];

PCC_VCC_1_DATA_BIT = [D15];

"******************************************************************************

"* BCSR 4 definitions.

"******************************************************************************

ETH_LOOP = 1;

ETH_FULL_DUP = 0;

ETH_CLSN_TEST = 0;

SIGNAL_LAMP_ON = 0;

USB_UTP_FETH_ENABLED = 0;

USB_FULL_SPEED = 1;

USB_VCC_CONT_0 = 0;

VIDEO_ENABLED = 0;

VIDEO_EXT_CLK_ENABLED = 1;

VIDEO_RESET_ACTIVE = 0;

MODEM_ENABLED_FOR_823 = 0;

MODEM = 1;

"***********************************************

"******* Power On Defaults Assignments *********

"***********************************************

ETH_LOOP_PON_DEFAULT = !ETH_LOOP;

ETH_FULL_DUP_PON_DEFAULT = !ETH_FULL_DUP;

ETH_CLSN_TEST_PON_DEFAULT = !ETH_CLSN_TEST;

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SIGNAL_LAMP_PON_DEFAULT = !SIGNAL_LAMP_ON;

USB_UTP_FETH_EN_PON_DEFAULT = !USB_UTP_FETH_ENABLED;

USB_SPEED_PON_DEFAULT = USB_FULL_SPEED;

USB_VCC_0_CONT_PON_DEFAULT = !USB_VCC_CONT_0;

USB_VCC_1_CONT_PON_DEFAULT = !USB_VCC_CONT_0;

VIDEO_ENABLE_PON_DEFAULT = !VIDEO_ENABLED;

VIDEO_EXT_CLK_EN_PON_DEFAULT = !VIDEO_EXT_CLK_ENABLED;

VIDEO_RESET_PON_DEFAULT = !VIDEO_RESET_ACTIVE;

MODEM_ENABLE_PON_DEFAULT = !MODEM_ENABLED_FOR_823;

MODEM_FUNC_SEL_PON_DEFAULT = MODEM;

"*******************************************

"******* Data Bits Assignments *************

"*******************************************

ETH_LOOP_DATA_BIT = [D0];

ETH_FULL_DUP_DATA_BIT = [D1];

ETH_CLSN_TEST_DATA_BIT = [D2];

SIGNAL_LAMP_DATA_BIT = [D3];

USB_UTP_FETH_EN_DATA_BIT = [D4];

USB_SPEED_DATA_BIT = [D5];

USB_VCC_0_DATA_BIT = [D6];

USB_VCC_1_DATA_BIT = [D7];

VIDEO_ENABLE_DATA_BIT = [D8];

VIDEO_EXT_CLK_EN_DATA_BIT = [D9];

VIDEO_RESET_DATA_BIT = [D10];

MODEM_ENABLE_DATA_BIT = [D11];

MODEM_FUNC_SEL_DATA_BIT = [D12];

"******************************************************************************

"* Equations, state diagrams.

*

"******************************************************************************

"*

*

"* #######

"* #

####

#

##

#####

#

####

#

####

"* #

#

##

# #

#

"* #####

"* #

#

####

# #

#

######

# #

##

#

"* #

#

"* #######

"*

### #

####

#

####

"******************************************************************************

"* Configuration Register.

"* Gets its default pon reset values which are driven to the data bus when

"* during hard reset configuration.

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"* If other values are required, this register may be written with new values

"* to become active for the next hard reset.

"* The state machines are built in a way that its power on value is changed in

"* one place - the declarations area.

"******************************************************************************

equations

@ifdef SLOW_PLL_LOCK {

!PonDefault~ = !ResetConf~ #

RGPORIn;

}

!Bcsr0Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & !A29 & !CntRegEn~);

!Bcsr1Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & !A27 & !A28 & A29 & !CntRegEn~);

!Bcsr4Write~ = (!BrdContRegCs~ & !TA~ & !R_W~ & A27 & !A28 & !A29 & !CntRegEn~);

ConfigReg.clk = SYSCLK;

state_diagram ERB

state INTERNAL_ARBITRATION:

if (MPC_WRITE_BCSR_0 &

(ERB_DATA_BIT.pin == EXTERNAL_ARBITRATION) &

(!KA_PON_RESET # (ERB_PON_DEFAULT != INTERNAL_ARBITRATION)) #

(KA_PON_RESET & (ERB_PON_DEFAULT == EXTERNAL_ARBITRATION)) ) then

EXTERNAL_ARBITRATION

else

INTERNAL_ARBITRATION;

state EXTERNAL_ARBITRATION:

if (MPC_WRITE_BCSR_0 &

(ERB_DATA_BIT.pin == INTERNAL_ARBITRATION) &

(!KA_PON_RESET # (ERB_PON_DEFAULT != EXTERNAL_ARBITRATION)) #

(KA_PON_RESET & (ERB_PON_DEFAULT == INTERNAL_ARBITRATION)) ) then

INTERNAL_ARBITRATION

else

EXTERNAL_ARBITRATION;

"******************************************************************************

state_diagram IP~

state IP_AT_0xFFF00000:

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if (MPC_WRITE_BCSR_0 &

(IP~_DATA_BIT.pin == IP_AT_0x00000000) &

(!KA_PON_RESET # (IP~_PON_DEFAULT != IP_AT_0xFFF00000)) #

(KA_PON_RESET & (IP~_PON_DEFAULT == IP_AT_0x00000000)) ) then

IP_AT_0x00000000

else

IP_AT_0xFFF00000;

state IP_AT_0x00000000:

if (MPC_WRITE_BCSR_0 &

(IP~_DATA_BIT.pin == IP_AT_0xFFF00000) &

(!KA_PON_RESET # (IP~_PON_DEFAULT != IP_AT_0x00000000)) #

(KA_PON_RESET & (IP~_PON_DEFAULT == IP_AT_0xFFF00000)) ) then

IP_AT_0xFFF00000

else

IP_AT_0x00000000;

"******************************************************************************

state_diagram RSV2

state !RSV2_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV2_DATA_BIT.pin == RSV2_ACTIVE) &

(!KA_PON_RESET # (RSV2_PON_DEFAULT != !RSV2_ACTIVE)) #

(KA_PON_RESET & (RSV2_PON_DEFAULT == RSV2_ACTIVE)) ) then

RSV2_ACTIVE

else

!RSV2_ACTIVE;

state RSV2_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV2_DATA_BIT.pin == !RSV2_ACTIVE) &

(!KA_PON_RESET # (RSV2_PON_DEFAULT != RSV2_ACTIVE)) #

(KA_PON_RESET & (RSV2_PON_DEFAULT == !RSV2_ACTIVE)) ) then

!RSV2_ACTIVE

else

RSV2_ACTIVE;

"******************************************************************************

state_diagram BDIS

state BOOT_ENABLE:

if (MPC_WRITE_BCSR_0 &

(BDIS_DATA_BIT.pin == BOOT_DISABLE) &

(!KA_PON_RESET # (BDIS_PON_DEFAULT != BOOT_ENABLE)) #

(KA_PON_RESET & (BDIS_PON_DEFAULT == BOOT_DISABLE)) ) then

BOOT_DISABLE

else

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BOOT_ENABLE;

state BOOT_DISABLE:

if (MPC_WRITE_BCSR_0 &

(BDIS_DATA_BIT.pin == BOOT_ENABLE) &

(!KA_PON_RESET # (BDIS_PON_DEFAULT != BOOT_DISABLE)) #

(KA_PON_RESET & (BDIS_PON_DEFAULT == BOOT_ENABLE)) ) then

BOOT_ENABLE

else

BOOT_DISABLE;

"******************************************************************************

state_diagram BPS

state BOOT_PORT_32:

if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_8) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_32)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_8)) ) then

BOOT_PORT_8

else if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_16) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_32)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_16)) ) then

BOOT_PORT_16

else if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_RESERVED) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_32)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_RESERVED)) ) then

BOOT_PORT_RESERVED

else

BOOT_PORT_32;

state BOOT_PORT_8:

if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_32) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_8)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_32)) ) then

BOOT_PORT_32

else if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_16) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_8)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_16)) ) then

BOOT_PORT_16

else if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_RESERVED) &

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(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_8)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_RESERVED)) ) then

BOOT_PORT_RESERVED

else

BOOT_PORT_8;

state BOOT_PORT_16:

if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_32) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_16)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_32)) ) then

BOOT_PORT_32

else if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_8) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_16)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_8)) ) then

BOOT_PORT_8

else if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_RESERVED) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_16)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_RESERVED)) ) then

BOOT_PORT_RESERVED

else

BOOT_PORT_16;

state BOOT_PORT_RESERVED:

if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_32) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_RESERVED)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_32)) ) then

BOOT_PORT_32

else if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_16) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_RESERVED)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_16)) ) then

BOOT_PORT_16

else if (MPC_WRITE_BCSR_0 &

(BPS_DATA_BIT.pin == BOOT_PORT_8) &

(!KA_PON_RESET # (BPS_PON_DEFAULT != BOOT_PORT_RESERVED)) #

(KA_PON_RESET & (BPS_PON_DEFAULT == BOOT_PORT_8)) ) then

BOOT_PORT_8

else

BOOT_PORT_RESERVED;

"******************************************************************************

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state_diagram RSV6

state !RSV6_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV6_DATA_BIT.pin == RSV6_ACTIVE) &

(!KA_PON_RESET # (RSV6_PON_DEFAULT != !RSV6_ACTIVE)) #

(KA_PON_RESET & (RSV6_PON_DEFAULT == RSV6_ACTIVE)) ) then

RSV6_ACTIVE

else

!RSV6_ACTIVE;

state RSV2_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV6_DATA_BIT.pin == !RSV6_ACTIVE) &

(!KA_PON_RESET # (RSV6_PON_DEFAULT != RSV6_ACTIVE)) #

(KA_PON_RESET & (RSV6_PON_DEFAULT == !RSV6_ACTIVE)) ) then

!RSV6_ACTIVE

else

RSV6_ACTIVE;

"******************************************************************************

state_diagram ISB

state INT_SPACE_BASE_0x00000000:

if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00F00000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00000000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00F00000)) ) then

INT_SPACE_BASE_0x00F00000

else if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFF000000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00000000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFF000000)) ) then

INT_SPACE_BASE_0xFF000000

else if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFFF00000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00000000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFFF00000)) ) then

INT_SPACE_BASE_0xFFF00000

else

INT_SPACE_BASE_0x00000000;

state INT_SPACE_BASE_0x00F00000:

if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00000000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00F00000)) #

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(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00000000)) ) then

INT_SPACE_BASE_0x00000000

else if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFF000000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00F00000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFF000000)) ) then

INT_SPACE_BASE_0xFF000000

else if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFFF00000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0x00F00000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFFF00000)) ) then

INT_SPACE_BASE_0xFFF00000

else

INT_SPACE_BASE_0x00F00000;

state INT_SPACE_BASE_0xFF000000:

if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00000000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFF000000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00000000)) ) then

INT_SPACE_BASE_0x00000000

else if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00F00000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFF000000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00F00000)) ) then

INT_SPACE_BASE_0x00F00000

else if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFFF00000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFF000000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFFF00000)) ) then

INT_SPACE_BASE_0xFFF00000

else

INT_SPACE_BASE_0xFF000000;

state INT_SPACE_BASE_0xFFF00000:

if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00000000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFFF00000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00000000)) ) then

INT_SPACE_BASE_0x00000000

else if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0x00F00000) &

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(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFFF00000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0x00F00000)) ) then

INT_SPACE_BASE_0x00F00000

else if (MPC_WRITE_BCSR_0 &

(ISB_DATA_BIT.pin == INT_SPACE_BASE_0xFF000000) &

(!KA_PON_RESET # (ISB_PON_DEFAULT != INT_SPACE_BASE_0xFFF00000)) #

(KA_PON_RESET & (ISB_PON_DEFAULT == INT_SPACE_BASE_0xFF000000)) ) then

INT_SPACE_BASE_0xFF000000

else

INT_SPACE_BASE_0xFFF00000;

"******************************************************************************

state_diagram DBGC

state DEBUG_PINS_PCMCIA_2:

if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_WATCH_POINTS) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_PCMCIA_2)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_WATCH_POINTS)) ) then

DEBUG_PINS_WATCH_POINTS

else if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_RESREVED) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_PCMCIA_2)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_RESREVED)) ) then

DEBUG_PINS_RESREVED

else if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_FOR_SHOW) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_PCMCIA_2)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_FOR_SHOW)) ) then

DEBUG_PINS_FOR_SHOW

else

DEBUG_PINS_PCMCIA_2;

state DEBUG_PINS_WATCH_POINTS:

if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_PCMCIA_2) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_WATCH_POINTS)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_PCMCIA_2)) ) then

DEBUG_PINS_PCMCIA_2

else if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_RESREVED) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_WATCH_POINTS)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_RESREVED)) ) then

DEBUG_PINS_RESREVED

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else if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_FOR_SHOW) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_WATCH_POINTS)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_FOR_SHOW)) ) then

DEBUG_PINS_FOR_SHOW

else

DEBUG_PINS_WATCH_POINTS;

state DEBUG_PINS_RESREVED:

if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_PCMCIA_2) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_RESREVED)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_PCMCIA_2)) ) then

DEBUG_PINS_PCMCIA_2

else if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_WATCH_POINTS) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_RESREVED)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_WATCH_POINTS)) ) then

DEBUG_PINS_WATCH_POINTS

else if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_FOR_SHOW) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_RESREVED)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_FOR_SHOW)) ) then

DEBUG_PINS_FOR_SHOW

else

DEBUG_PINS_RESREVED;

state DEBUG_PINS_FOR_SHOW:

if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_PCMCIA_2) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_FOR_SHOW)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_PCMCIA_2)) ) then

DEBUG_PINS_PCMCIA_2

else if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_WATCH_POINTS) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_FOR_SHOW)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_WATCH_POINTS)) ) then

DEBUG_PINS_WATCH_POINTS

else if (MPC_WRITE_BCSR_0 &

(DBGC_DATA_BIT.pin == DEBUG_PINS_RESREVED) &

(!KA_PON_RESET # (DBGC_PON_DEFAULT != DEBUG_PINS_FOR_SHOW)) #

(KA_PON_RESET & (DBGC_PON_DEFAULT == DEBUG_PINS_RESREVED)) ) then

DEBUG_PINS_RESREVED

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else

DEBUG_PINS_FOR_SHOW;

"******************************************************************************

state_diagram DBPC

state DEBUG_PORT_ON_JTAG:

if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_NON_EXISTANT) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_JTAG)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_NON_EXISTANT)) ) then

DEBUG_PORT_NON_EXISTANT

else if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_RESERVED) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_JTAG)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_RESERVED)) ) then

DEBUG_PORT_RESERVED

else if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_ON_DEBUG_PINS) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_JTAG)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_DEBUG_PINS)) ) then

DEBUG_PORT_ON_DEBUG_PINS

else

DEBUG_PORT_ON_JTAG;

state DEBUG_PORT_NON_EXISTANT:

if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_ON_JTAG) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_NON_EXISTANT)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_JTAG)) ) then

DEBUG_PORT_ON_JTAG

else if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_RESERVED) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_NON_EXISTANT)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_RESERVED)) ) then

DEBUG_PORT_RESERVED

else if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_ON_DEBUG_PINS) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_NON_EXISTANT)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_DEBUG_PINS)) ) then

DEBUG_PORT_ON_DEBUG_PINS

else

DEBUG_PORT_NON_EXISTANT;

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state DEBUG_PORT_RESERVED:

if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_ON_JTAG) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_RESERVED)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_JTAG)) ) then

DEBUG_PORT_ON_JTAG

else if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_NON_EXISTANT) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_RESERVED)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_NON_EXISTANT)) ) then

DEBUG_PORT_NON_EXISTANT

else if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_ON_DEBUG_PINS) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_RESERVED)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_DEBUG_PINS)) ) then

DEBUG_PORT_ON_DEBUG_PINS

else

DEBUG_PORT_RESERVED;

state DEBUG_PORT_ON_DEBUG_PINS:

if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_ON_JTAG) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_DEBUG_PINS)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_ON_JTAG)) ) then

DEBUG_PORT_ON_JTAG

else if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_NON_EXISTANT) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_DEBUG_PINS)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_NON_EXISTANT)) ) then

DEBUG_PORT_NON_EXISTANT

else if (MPC_WRITE_BCSR_0 &

(DBPC_DATA_BIT.pin == DEBUG_PORT_RESERVED) &

(!KA_PON_RESET # (DBPC_PON_DEFAULT != DEBUG_PORT_ON_DEBUG_PINS)) #

(KA_PON_RESET & (DBPC_PON_DEFAULT == DEBUG_PORT_RESERVED)) ) then

DEBUG_PORT_RESERVED

else

DEBUG_PORT_ON_DEBUG_PINS;

"******************************************************************************

state_diagram RSV13

state !RSV13_ACTIVE:

if (MPC_WRITE_BCSR_0 &

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(RSV13_DATA_BIT.pin == RSV13_ACTIVE) &

(!KA_PON_RESET # (RSV13_PON_DEFAULT != !RSV13_ACTIVE)) #

(KA_PON_RESET & (RSV13_PON_DEFAULT == RSV13_ACTIVE)) ) then

RSV13_ACTIVE

else

!RSV13_ACTIVE;

state RSV13_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV13_DATA_BIT.pin == !RSV13_ACTIVE) &

(!KA_PON_RESET # (RSV13_PON_DEFAULT != RSV13_ACTIVE)) #

(KA_PON_RESET & (RSV13_PON_DEFAULT == !RSV13_ACTIVE)) ) then

!RSV13_ACTIVE

else

RSV13_ACTIVE;

"******************************************************************************

state_diagram RSV14

state !RSV14_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV14_DATA_BIT.pin == RSV14_ACTIVE) &

(!KA_PON_RESET # (RSV14_PON_DEFAULT != !RSV14_ACTIVE)) #

(KA_PON_RESET & (RSV14_PON_DEFAULT == RSV14_ACTIVE)) ) then

RSV14_ACTIVE

else

!RSV14_ACTIVE;

state RSV14_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV14_DATA_BIT.pin == !RSV14_ACTIVE) &

(!KA_PON_RESET # (RSV14_PON_DEFAULT != RSV14_ACTIVE)) #

(KA_PON_RESET & (RSV14_PON_DEFAULT == !RSV14_ACTIVE)) ) then

!RSV14_ACTIVE

else

RSV14_ACTIVE;

"******************************************************************************

state_diagram RSV15

state !RSV15_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV15_DATA_BIT.pin == RSV15_ACTIVE) &

(!KA_PON_RESET # (RSV15_PON_DEFAULT != !RSV15_ACTIVE)) #

(KA_PON_RESET & (RSV15_PON_DEFAULT == RSV15_ACTIVE)) ) then

RSV15_ACTIVE

else

!RSV15_ACTIVE;

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state RSV15_ACTIVE:

if (MPC_WRITE_BCSR_0 &

(RSV15_DATA_BIT.pin == !RSV15_ACTIVE) &

(!KA_PON_RESET # (RSV15_PON_DEFAULT != RSV15_ACTIVE)) #

(KA_PON_RESET & (RSV15_PON_DEFAULT == !RSV15_ACTIVE)) ) then

!RSV15_ACTIVE

else

RSV15_ACTIVE;

"******************************************************************************

"* BCSR 1

"******************************************************************************

equations

WideContReg.clk = SYSCLK;

DrivenContReg.oe = ^hfffffff;

state_diagram FlashEn~

state FLASH_ENABLED:

if (MPC_WRITE_BCSR_1 &

(FLASH_ENABLE_DATA_BIT.pin == !FLASH_ENABLED) &

(!KA_PON_RESET # (FLASH_ENABLE_PON_DEFAULT != FLASH_ENABLED)) #

(KA_PON_RESET & (FLASH_ENABLE_PON_DEFAULT == !FLASH_ENABLED)) ) then

!FLASH_ENABLED

else

FLASH_ENABLED;

state !FLASH_ENABLED:

if (MPC_WRITE_BCSR_1 &

(FLASH_ENABLE_DATA_BIT.pin == FLASH_ENABLED) &

(!KA_PON_RESET # (FLASH_ENABLE_PON_DEFAULT != !FLASH_ENABLED)) #

(KA_PON_RESET & (FLASH_ENABLE_PON_DEFAULT == FLASH_ENABLED)) ) then

FLASH_ENABLED

else

!FLASH_ENABLED;

"******************************************************************************

state_diagram DramEn~

state DRAM_ENABLED:

if (MPC_WRITE_BCSR_1 &

(DRAM_ENABLE_DATA_BIT.pin == !DRAM_ENABLED) &

(!KA_PON_RESET # (DRAM_ENABLE_PON_DEFAULT != DRAM_ENABLED)) #

(KA_PON_RESET & (DRAM_ENABLE_PON_DEFAULT == !DRAM_ENABLED)) ) then

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!DRAM_ENABLED

else

DRAM_ENABLED;

state !DRAM_ENABLED:

if (MPC_WRITE_BCSR_1 &

(DRAM_ENABLE_DATA_BIT.pin == DRAM_ENABLED) &

(!KA_PON_RESET # (DRAM_ENABLE_PON_DEFAULT != !DRAM_ENABLED)) #

(KA_PON_RESET & (DRAM_ENABLE_PON_DEFAULT == DRAM_ENABLED)) ) then

DRAM_ENABLED

else

!DRAM_ENABLED;

"******************************************************************************

state_diagram EthEn~

state ETH_ENABLED:

if (MPC_WRITE_BCSR_1 &

(ETH_ENABLE_DATA_BIT.pin == !ETH_ENABLED) &

(!KA_PON_RESET # (ETH_ENABLE_PON_DEFAULT != ETH_ENABLED)) #

(KA_PON_RESET & (ETH_ENABLE_PON_DEFAULT == !ETH_ENABLED)) ) then

!ETH_ENABLED

else

ETH_ENABLED;

state !ETH_ENABLED:

if (MPC_WRITE_BCSR_1 &

(ETH_ENABLE_DATA_BIT.pin == ETH_ENABLED) &

(!KA_PON_RESET # (ETH_ENABLE_PON_DEFAULT != !ETH_ENABLED)) #

(KA_PON_RESET & (ETH_ENABLE_PON_DEFAULT == ETH_ENABLED)) ) then

ETH_ENABLED

else

!ETH_ENABLED;

"******************************************************************************

state_diagram InfRedEn~

state INF_RED_ENABLE:

if (MPC_WRITE_BCSR_1 &

(INF_RED_ENABLE_DATA_BIT.pin == !INF_RED_ENABLE) &

(!KA_PON_RESET # (INF_RED_ENABLE_PON_DEFAULT != INF_RED_ENABLE)) #

(KA_PON_RESET & (INF_RED_ENABLE_PON_DEFAULT == !INF_RED_ENABLE)) ) then

!INF_RED_ENABLE

else

INF_RED_ENABLE;

state !INF_RED_ENABLE:

if (MPC_WRITE_BCSR_1 &

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(INF_RED_ENABLE_DATA_BIT.pin == INF_RED_ENABLE) &

(!KA_PON_RESET # (INF_RED_ENABLE_PON_DEFAULT != !INF_RED_ENABLE)) #

(KA_PON_RESET & (INF_RED_ENABLE_PON_DEFAULT == INF_RED_ENABLE)) ) then

INF_RED_ENABLE

else

!INF_RED_ENABLE;

"******************************************************************************

state_diagram FlashCfgEn~

state FLASH_CFG_ENABLE:

if (MPC_WRITE_BCSR_1 &

(FLASH_CFG_ENABLE_DATA_BIT.pin == !FLASH_CFG_ENABLE) &

(!KA_PON_RESET # (FLASH_CFG_ENABLE_PON_DEFAULT != FLASH_CFG_ENABLE)) #

(KA_PON_RESET & (FLASH_CFG_ENABLE_PON_DEFAULT == !FLASH_CFG_ENABLE)) )then

!FLASH_CFG_ENABLE

else

FLASH_CFG_ENABLE;

state !FLASH_CFG_ENABLE:

if (MPC_WRITE_BCSR_1 &

(FLASH_CFG_ENABLE_DATA_BIT.pin == FLASH_CFG_ENABLE) &

(!KA_PON_RESET # (FLASH_CFG_ENABLE_PON_DEFAULT != !FLASH_CFG_ENABLE)) #

(KA_PON_RESET & (FLASH_CFG_ENABLE_PON_DEFAULT == FLASH_CFG_ENABLE)) ) then

FLASH_CFG_ENABLE

else

!FLASH_CFG_ENABLE;

"******************************************************************************

"* To avoid in advertant write to the Control Register Enable bit, which might

"* result in a need to re-power the board - protection logic is provided.

"* In order of writing the Control Register Enable this bit in the status register

"* must be negated. After any write to the control register, this bit asserts

"* again (to protected mode)

"******************************************************************************

equations

CntRegEnProtect~.clk = SYSCLK;

state_diagram CntRegEnProtect~

state CNT_REG_EN_PROTECT:

if (MPC_WRITE_BCSR_3 &

(CNT_REG_EN_PROTECT_DATA_BIT.pin == !CNT_REG_EN_PROTECT) &

(!KA_PON_RESET # (CNT_REG_EN_PROTECT_PON_DEFAULT != CNT_REG_EN_PROTECT)) #

(KA_PON_RESET & (CNT_REG_EN_PROTECT_PON_DEFAULT == !CNT_REG_EN_PROTECT)) then

!CNT_REG_EN_PROTECT

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else

CNT_REG_EN_PROTECT;

state !CNT_REG_EN_PROTECT:

if (MPC_WRITE_BCSR_3 &

(CNT_REG_EN_PROTECT_DATA_BIT.pin == CNT_REG_EN_PROTECT) &

(!KA_PON_RESET # (CNT_REG_EN_PROTECT_PON_DEFAULT != !CNT_REG_EN_PROTECT)) #

(KA_PON_RESET & (CNT_REG_EN_PROTECT_PON_DEFAULT == CNT_REG_EN_PROTECT)) #

MPC_WRITE_BCSR_1) then " any write to control reg 1

CNT_REG_EN_PROTECT

else

!CNT_REG_EN_PROTECT;

"******************************************************************************

"* protected by CntRegEnProtect~ to prevent from inadvertant write

"******************************************************************************

state_diagram CntRegEn~

state CONT_REG_ENABLE:

if (MPC_WRITE_BCSR_1 & (CntRegEnProtect~.fb != CNT_REG_EN_PROTECT) &

(CONT_REG_ENABLE_DATA_BIT.pin == !CONT_REG_ENABLE) &

(!KA_PON_RESET # (CONT_REG_ENABLE_PON_DEFAULT != CONT_REG_ENABLE)) #

(KA_PON_RESET & (CONT_REG_ENABLE_PON_DEFAULT == !CONT_REG_ENABLE)) ) then

!CONT_REG_ENABLE

else

CONT_REG_ENABLE;

state !CONT_REG_ENABLE:" in fact not applicable

if (MPC_WRITE_BCSR_1 &

(CONT_REG_ENABLE_DATA_BIT.pin == CONT_REG_ENABLE) &

(!KA_PON_RESET # (CONT_REG_ENABLE_PON_DEFAULT != !CONT_REG_ENABLE)) #

(KA_PON_RESET & (CONT_REG_ENABLE_PON_DEFAULT == CONT_REG_ENABLE)) ) then

CONT_REG_ENABLE

else

!CONT_REG_ENABLE;

"******************************************************************************

state_diagram RS232En1~

state RS232_1_ENABLE:

if (MPC_WRITE_BCSR_1 &

(RS232_1_ENABLE_DATA_BIT.pin == !RS232_1_ENABLE) &

(!KA_PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != RS232_1_ENABLE)) #

(KA_PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == !RS232_1_ENABLE)) ) then

!RS232_1_ENABLE

else

RS232_1_ENABLE;

state !RS232_1_ENABLE:

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if (MPC_WRITE_BCSR_1 &

(RS232_1_ENABLE_DATA_BIT.pin == RS232_1_ENABLE) &

(!KA_PON_RESET # (RS232_1_ENABLE_PON_DEFAULT != !RS232_1_ENABLE)) #

(KA_PON_RESET & (RS232_1_ENABLE_PON_DEFAULT == RS232_1_ENABLE)) ) then

RS232_1_ENABLE

else

!RS232_1_ENABLE;

"******************************************************************************

state_diagram PccEn~

state PCC_ENABLE:

if (MPC_WRITE_BCSR_1 &

(PCC_ENABLE_DATA_BIT.pin == !PCC_ENABLE) &

(!KA_PON_RESET # (PCC_ENABLE_PON_DEFAULT != PCC_ENABLE)) #

(KA_PON_RESET & (PCC_ENABLE_PON_DEFAULT == !PCC_ENABLE)) ) then

!PCC_ENABLE

else

PCC_ENABLE;

state !PCC_ENABLE:

if (MPC_WRITE_BCSR_1 &

(PCC_ENABLE_DATA_BIT.pin == PCC_ENABLE) &

(!KA_PON_RESET # (PCC_ENABLE_PON_DEFAULT != !PCC_ENABLE)) #

(KA_PON_RESET & (PCC_ENABLE_PON_DEFAULT == PCC_ENABLE)) ) then

PCC_ENABLE

else

!PCC_ENABLE;

"******************************************************************************

state_diagram PccVcc0

state PCC_VCC_CONT_0:

if (MPC_WRITE_BCSR_1 &

(PCC_VCC_0_DATA_BIT.pin == !PCC_VCC_CONT_0) &

(!KA_PON_RESET # (PCC_VCC_0_PON_DEFAULT != PCC_VCC_CONT_0)) #

(KA_PON_RESET & (PCC_VCC_0_PON_DEFAULT == !PCC_VCC_CONT_0)) ) then

!PCC_VCC_CONT_0

else

PCC_VCC_CONT_0;

state !PCC_VCC_CONT_0:

if (MPC_WRITE_BCSR_1 &

(PCC_VCC_0_DATA_BIT.pin == PCC_VCC_CONT_0) &

(!KA_PON_RESET # (PCC_VCC_0_PON_DEFAULT != !PCC_VCC_CONT_0)) #

(KA_PON_RESET & (PCC_VCC_0_PON_DEFAULT == PCC_VCC_CONT_0)) ) then

PCC_VCC_CONT_0

else

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!PCC_VCC_CONT_0;

"******************************************************************************

state_diagram PccVpp0

state PCC_VPP0:

if (MPC_WRITE_BCSR_1 &

(PCC_VPP0_DATA_BIT.pin == !PCC_VPP0) &

(!KA_PON_RESET # (PCC_VPP0_PON_DEFAULT != PCC_VPP0)) #

(KA_PON_RESET & (PCC_VPP0_PON_DEFAULT == !PCC_VPP0)) ) then

!PCC_VPP0

else

PCC_VPP0;

state !PCC_VPP0:

if (MPC_WRITE_BCSR_1 &

(PCC_VPP0_DATA_BIT.pin == PCC_VPP0) &

(!KA_PON_RESET # (PCC_VPP0_PON_DEFAULT != !PCC_VPP0)) #

(KA_PON_RESET & (PCC_VPP0_PON_DEFAULT == PCC_VPP0)) ) then

PCC_VPP0

else

!PCC_VPP0;

"******************************************************************************

state_diagram PccVpp1

state PCC_VPP1:

if (MPC_WRITE_BCSR_1 &

(PCC_VPP1_DATA_BIT.pin == !PCC_VPP1) &

(!KA_PON_RESET # (PCC_VPP1_PON_DEFAULT != PCC_VPP1)) #

(KA_PON_RESET & (PCC_VPP1_PON_DEFAULT == !PCC_VPP1)) ) then

!PCC_VPP1

else

PCC_VPP1;

state !PCC_VPP1:

if (MPC_WRITE_BCSR_1 &

(PCC_VPP1_DATA_BIT.pin == PCC_VPP1) &

(!KA_PON_RESET # (PCC_VPP1_PON_DEFAULT != !PCC_VPP1)) #

(KA_PON_RESET & (PCC_VPP1_PON_DEFAULT == PCC_VPP1)) ) then

PCC_VPP1

else

!PCC_VPP1;

"******************************************************************************

state_diagram HalfWord~

state HALF_WORD:

if (MPC_WRITE_BCSR_1 &

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(HALF_WORD_DATA_BIT.pin == !HALF_WORD) &

(!KA_PON_RESET # (HALF_WORD_PON_DEFAULT != HALF_WORD)) #

(KA_PON_RESET & (HALF_WORD_PON_DEFAULT == !HALF_WORD)) ) then

!HALF_WORD

else

HALF_WORD;

state !HALF_WORD:

if (MPC_WRITE_BCSR_1 &

(HALF_WORD_DATA_BIT.pin == HALF_WORD) &

(!KA_PON_RESET # (HALF_WORD_PON_DEFAULT != !HALF_WORD)) #

(KA_PON_RESET & (HALF_WORD_PON_DEFAULT == HALF_WORD)) ) then

HALF_WORD

else

!HALF_WORD;

"******************************************************************************

state_diagram RS232En2~

state RS232_2_ENABLE:

if (MPC_WRITE_BCSR_1 &

(RS232_2_ENABLE_DATA_BIT.pin == !RS232_2_ENABLE) &

(!KA_PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != RS232_2_ENABLE)) #

(KA_PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == !RS232_2_ENABLE)) ) then

!RS232_2_ENABLE

else

RS232_2_ENABLE;

state !RS232_2_ENABLE:

if (MPC_WRITE_BCSR_1 &

(RS232_2_ENABLE_DATA_BIT.pin == RS232_2_ENABLE) &

(!KA_PON_RESET # (RS232_2_ENABLE_PON_DEFAULT != !RS232_2_ENABLE)) #

(KA_PON_RESET & (RS232_2_ENABLE_PON_DEFAULT == RS232_2_ENABLE)) ) then

RS232_2_ENABLE

else

!RS232_2_ENABLE;

"******************************************************************************

state_diagram PccVcc1

state PCC_VCC_CONT_0:

if (MPC_WRITE_BCSR_1 &

(PCC_VCC_1_DATA_BIT.pin == !PCC_VCC_CONT_0) &

(!KA_PON_RESET # (PCC_VCC_1_PON_DEFAULT != PCC_VCC_CONT_0)) #

(KA_PON_RESET & (PCC_VCC_1_PON_DEFAULT == !PCC_VCC_CONT_0)) ) then

!PCC_VCC_CONT_0

else

PCC_VCC_CONT_0;

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state !PCC_VCC_CONT_0:

if (MPC_WRITE_BCSR_1 &

(PCC_VCC_1_DATA_BIT.pin == PCC_VCC_CONT_0) &

(!KA_PON_RESET # (PCC_VCC_1_PON_DEFAULT != !PCC_VCC_CONT_0)) #

(KA_PON_RESET & (PCC_VCC_1_PON_DEFAULT == PCC_VCC_CONT_0)) ) then

PCC_VCC_CONT_0

else

!PCC_VCC_CONT_0;

"******************************************************************************

state_diagram SdramEn~

state SDRAM_ENABLED:

if (MPC_WRITE_BCSR_1 &

(SDRAM_ENABLE_DATA_BIT.pin == !SDRAM_ENABLED) &

(!KA_PON_RESET # (SDRAM_ENABLE_PON_DEFAULT != SDRAM_ENABLED)) #

(KA_PON_RESET & (SDRAM_ENABLE_PON_DEFAULT == !SDRAM_ENABLED)) ) then

!SDRAM_ENABLED

else

SDRAM_ENABLED;

state !SDRAM_ENABLED:

if (MPC_WRITE_BCSR_1 &

(SDRAM_ENABLE_DATA_BIT.pin == SDRAM_ENABLED) &

(!KA_PON_RESET # (SDRAM_ENABLE_PON_DEFAULT != !SDRAM_ENABLED)) #

(KA_PON_RESET & (SDRAM_ENABLE_PON_DEFAULT == SDRAM_ENABLED)) ) then

SDRAM_ENABLED

else

!SDRAM_ENABLED;

"******************************************************************************

"* BCSR4 State Machines

"******************************************************************************

state_diagram UsbUtpFethEn~

state USB_UTP_FETH_ENABLED:

if (MPC_WRITE_BCSR_4 &

(USB_UTP_FETH_EN_DATA_BIT.pin == !USB_UTP_FETH_ENABLED) &

(!KA_PON_RESET # (USB_UTP_FETH_EN_PON_DEFAULT != USB_UTP_FETH_ENABLED)) #

(KA_PON_RESET & (USB_UTP_FETH_EN_PON_DEFAULT == !USB_UTP_FETH_ENABLED)) ) then

!USB_UTP_FETH_ENABLED

else

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USB_UTP_FETH_ENABLED;

state !USB_UTP_FETH_ENABLED:

if (MPC_WRITE_BCSR_4 &

(USB_UTP_FETH_EN_DATA_BIT.pin == USB_UTP_FETH_ENABLED) &

(!KA_PON_RESET # (USB_UTP_FETH_EN_PON_DEFAULT != !USB_UTP_FETH_ENABLED)) #

(KA_PON_RESET & (USB_UTP_FETH_EN_PON_DEFAULT == USB_UTP_FETH_ENABLED)) )then

USB_UTP_FETH_ENABLED

else

!USB_UTP_FETH_ENABLED;

"******************************************************************************

state_diagram UsbSpeed

state USB_FULL_SPEED:

if (MPC_WRITE_BCSR_4 &

(USB_SPEED_DATA_BIT.pin == !USB_FULL_SPEED) &

(!KA_PON_RESET # (USB_SPEED_PON_DEFAULT != USB_FULL_SPEED)) #

(KA_PON_RESET & (USB_SPEED_PON_DEFAULT == !USB_FULL_SPEED)) ) then

!USB_FULL_SPEED

else

USB_FULL_SPEED;

state !USB_FULL_SPEED:

if (MPC_WRITE_BCSR_4 &

(USB_SPEED_DATA_BIT.pin == USB_FULL_SPEED) &

(!KA_PON_RESET # (USB_SPEED_PON_DEFAULT != !USB_FULL_SPEED)) #

(KA_PON_RESET & (USB_SPEED_PON_DEFAULT == USB_FULL_SPEED)) ) then

USB_FULL_SPEED

else

!USB_FULL_SPEED;

"******************************************************************************

state_diagram UsbVcc0

state USB_VCC_CONT_0:

if (MPC_WRITE_BCSR_4 &

(USB_VCC_0_DATA_BIT.pin == !USB_VCC_CONT_0) &

(!KA_PON_RESET # (USB_VCC_0_CONT_PON_DEFAULT != USB_VCC_CONT_0)) #

(KA_PON_RESET & (USB_VCC_0_CONT_PON_DEFAULT == !USB_VCC_CONT_0)) ) then

!USB_VCC_CONT_0

else

USB_VCC_CONT_0;

state !USB_VCC_CONT_0:

if (MPC_WRITE_BCSR_4 &

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(PCC_VCC_0_DATA_BIT.pin == PCC_VCC_CONT_0) &

(!KA_PON_RESET # (USB_VCC_0_CONT_PON_DEFAULT != !USB_VCC_CONT_0)) #

(KA_PON_RESET & (USB_VCC_0_CONT_PON_DEFAULT == USB_VCC_CONT_0)) ) then

USB_VCC_CONT_0

else

!USB_VCC_CONT_0;

"******************************************************************************

state_diagram UsbVcc1

state USB_VCC_CONT_0:

if (MPC_WRITE_BCSR_4 &

(USB_VCC_1_DATA_BIT.pin == !USB_VCC_CONT_0) &

(!KA_PON_RESET # (USB_VCC_1_CONT_PON_DEFAULT != USB_VCC_CONT_0)) #

(KA_PON_RESET & (USB_VCC_1_CONT_PON_DEFAULT == !USB_VCC_CONT_0)) ) then

!USB_VCC_CONT_0

else

USB_VCC_CONT_0;

state !USB_VCC_CONT_0:

if (MPC_WRITE_BCSR_4 &

(PCC_VCC_1_DATA_BIT.pin == PCC_VCC_CONT_0) &

(!KA_PON_RESET # (USB_VCC_1_CONT_PON_DEFAULT != !USB_VCC_CONT_0)) #

(KA_PON_RESET & (USB_VCC_1_CONT_PON_DEFAULT == USB_VCC_CONT_0)) ) then

USB_VCC_CONT_0

else

!USB_VCC_CONT_0;

"******************************************************************************

state_diagram VideoOn~

state VIDEO_ENABLED:

if (MPC_WRITE_BCSR_4 &

(VIDEO_ENABLE_DATA_BIT.pin == !VIDEO_ENABLED) &

(!KA_PON_RESET # (VIDEO_ENABLE_PON_DEFAULT != VIDEO_ENABLED)) #

(KA_PON_RESET & (VIDEO_ENABLE_PON_DEFAULT == !VIDEO_ENABLED)) ) then

!VIDEO_ENABLED

else

VIDEO_ENABLED;

state !VIDEO_ENABLED:

if (MPC_WRITE_BCSR_4 &

(VIDEO_ENABLE_DATA_BIT.pin == VIDEO_ENABLED) &

(!KA_PON_RESET # (VIDEO_ENABLE_PON_DEFAULT != !VIDEO_ENABLED)) #

(KA_PON_RESET & (VIDEO_ENABLE_PON_DEFAULT == VIDEO_ENABLED)) ) then

VIDEO_ENABLED

else

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!VIDEO_ENABLED;

"******************************************************************************

state_diagram VideoExtClkEn

state VIDEO_EXT_CLK_ENABLED:

if (MPC_WRITE_BCSR_4 &

(VIDEO_EXT_CLK_EN_DATA_BIT.pin == !VIDEO_EXT_CLK_ENABLED) &

(!KA_PON_RESET # (VIDEO_EXT_CLK_EN_PON_DEFAULT != VIDEO_EXT_CLK_ENABLED)#

(KA_PON_RESET & (VIDEO_EXT_CLK_EN_PON_DEFAULT ==!VIDEO_EXT_CLK_ENABLED)))then

!VIDEO_EXT_CLK_ENABLED

else

VIDEO_EXT_CLK_ENABLED;

state !VIDEO_EXT_CLK_ENABLED:

if (MPC_WRITE_BCSR_4 &

(VIDEO_EXT_CLK_EN_DATA_BIT.pin == VIDEO_EXT_CLK_ENABLED) &

(!KA_PON_RESET # (VIDEO_EXT_CLK_EN_PON_DEFAULT != !VIDEO_EXT_CLK_ENABLED)) #

(KA_PON_RESET & (VIDEO_EXT_CLK_EN_PON_DEFAULT == VIDEO_EXT_CLK_ENABLED)) ) then

VIDEO_EXT_CLK_ENABLED

else

!VIDEO_EXT_CLK_ENABLED;

"******************************************************************************

state_diagram VideoRst~

state VIDEO_RESET_ACTIVE:

if (MPC_WRITE_BCSR_4 &

(VIDEO_RESET_DATA_BIT.pin == !VIDEO_RESET_ACTIVE) &

(!KA_PON_RESET # (VIDEO_RESET_PON_DEFAULT != VIDEO_RESET_ACTIVE)) #

(KA_PON_RESET & (VIDEO_RESET_PON_DEFAULT == !VIDEO_RESET_ACTIVE)) ) then

!VIDEO_RESET_ACTIVE

else

VIDEO_RESET_ACTIVE;

state !VIDEO_RESET_ACTIVE:

if (MPC_WRITE_BCSR_4 &

(VIDEO_RESET_DATA_BIT.pin == VIDEO_RESET_ACTIVE) &

(!KA_PON_RESET # (VIDEO_RESET_PON_DEFAULT != !VIDEO_RESET_ACTIVE)) #

(KA_PON_RESET & (VIDEO_RESET_PON_DEFAULT == VIDEO_RESET_ACTIVE)) ) then

VIDEO_RESET_ACTIVE

else

!VIDEO_RESET_ACTIVE;

"******************************************************************************

state_diagram SignaLamp~

state SIGNAL_LAMP_ON:

if (MPC_WRITE_BCSR_4 &

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(SIGNAL_LAMP_DATA_BIT.pin == !SIGNAL_LAMP_ON) &

(!KA_PON_RESET # (SIGNAL_LAMP_PON_DEFAULT != SIGNAL_LAMP_ON)) #

(KA_PON_RESET & (SIGNAL_LAMP_PON_DEFAULT == !SIGNAL_LAMP_ON)) ) then

!SIGNAL_LAMP_ON

else

SIGNAL_LAMP_ON;

state !SIGNAL_LAMP_ON:

if (MPC_WRITE_BCSR_4 &

(SIGNAL_LAMP_DATA_BIT.pin == SIGNAL_LAMP_ON) &

(!KA_PON_RESET # (SIGNAL_LAMP_PON_DEFAULT != !SIGNAL_LAMP_ON)) #

(KA_PON_RESET & (SIGNAL_LAMP_PON_DEFAULT == SIGNAL_LAMP_ON)) ) then

SIGNAL_LAMP_ON

else

!SIGNAL_LAMP_ON;

"******************************************************************************

state_diagram EthLoop

state ETH_LOOP:

if (MPC_WRITE_BCSR_4 &

(ETH_LOOP_DATA_BIT.pin == !ETH_LOOP) &

(!KA_PON_RESET # (ETH_LOOP_PON_DEFAULT != ETH_LOOP)) #

(KA_PON_RESET & (ETH_LOOP_PON_DEFAULT == !ETH_LOOP)) ) then

!ETH_LOOP

else

ETH_LOOP;

state !ETH_LOOP:

if (MPC_WRITE_BCSR_4 &

(ETH_LOOP_DATA_BIT.pin == ETH_LOOP) &

(!KA_PON_RESET # (ETH_LOOP_PON_DEFAULT != !ETH_LOOP)) #

(KA_PON_RESET & (ETH_LOOP_PON_DEFAULT == ETH_LOOP)) ) then

ETH_LOOP

else

!ETH_LOOP;

"******************************************************************************

state_diagram TPFLDL~

state ETH_FULL_DUP:

if (MPC_WRITE_BCSR_4 &

(ETH_FULL_DUP_DATA_BIT.pin == !ETH_FULL_DUP) &

(!KA_PON_RESET # (ETH_FULL_DUP_PON_DEFAULT != ETH_FULL_DUP)) #

(KA_PON_RESET & (ETH_FULL_DUP_PON_DEFAULT == !ETH_FULL_DUP)) ) then

!ETH_FULL_DUP

else

ETH_FULL_DUP;

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state !ETH_FULL_DUP:

if (MPC_WRITE_BCSR_4 &

(ETH_FULL_DUP_DATA_BIT.pin == ETH_FULL_DUP) &

(!KA_PON_RESET # (ETH_FULL_DUP_PON_DEFAULT != !ETH_FULL_DUP)) #

(KA_PON_RESET & (ETH_FULL_DUP_PON_DEFAULT == ETH_FULL_DUP)) ) then

ETH_FULL_DUP

else

!ETH_FULL_DUP;

"******************************************************************************

state_diagram TPSQEL~

state ETH_CLSN_TEST:

if (MPC_WRITE_BCSR_4 &

(ETH_CLSN_TEST_DATA_BIT.pin == !ETH_CLSN_TEST) &

(!KA_PON_RESET # (ETH_CLSN_TEST_PON_DEFAULT != ETH_CLSN_TEST)) #

(KA_PON_RESET & (ETH_CLSN_TEST_PON_DEFAULT == !ETH_CLSN_TEST)) ) then

!ETH_CLSN_TEST

else

ETH_CLSN_TEST;

state !ETH_CLSN_TEST:

if (MPC_WRITE_BCSR_4 &

(ETH_CLSN_TEST_DATA_BIT.pin == ETH_CLSN_TEST) &

(!KA_PON_RESET # (ETH_CLSN_TEST_PON_DEFAULT != !ETH_CLSN_TEST)) #

(KA_PON_RESET & (ETH_CLSN_TEST_PON_DEFAULT == ETH_CLSN_TEST)) ) then

ETH_CLSN_TEST

else

!ETH_CLSN_TEST;

"******************************************************************************

state_diagram ModemEn~

state MODEM_ENABLED_FOR_823:

if (MPC_WRITE_BCSR_4 &

(MODEM_ENABLE_DATA_BIT.pin == !MODEM_ENABLED_FOR_823) &

(!KA_PON_RESET # (MODEM_ENABLE_PON_DEFAULT != MODEM_ENABLED_FOR_823)) #

(KA_PON_RESET & (MODEM_ENABLE_PON_DEFAULT == !MODEM_ENABLED_FOR_823)) ) then

!MODEM_ENABLED_FOR_823

else

MODEM_ENABLED_FOR_823;

state !MODEM_ENABLED_FOR_823:

if (MPC_WRITE_BCSR_4 &

(MODEM_ENABLE_DATA_BIT.pin == MODEM_ENABLED_FOR_823) &

(!KA_PON_RESET # (MODEM_ENABLE_PON_DEFAULT != !MODEM_ENABLED_FOR_823)) #

(KA_PON_RESET & (MODEM_ENABLE_PON_DEFAULT == MODEM_ENABLED_FOR_823)) ) then

MODEM_ENABLED_FOR_823

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else

!MODEM_ENABLED_FOR_823;

"******************************************************************************

state_diagram Modem_Audio~

state MODEM:

if (MPC_WRITE_BCSR_4 &

(MODEM_FUNC_SEL_DATA_BIT.pin == !MODEM) &

(!KA_PON_RESET # (MODEM_FUNC_SEL_PON_DEFAULT != MODEM)) #

(KA_PON_RESET & (MODEM_FUNC_SEL_PON_DEFAULT == !MODEM)) ) then

!MODEM

else

MODEM;

state !MODEM:

if (MPC_WRITE_BCSR_4 &

(MODEM_FUNC_SEL_DATA_BIT.pin == MODEM) &

(!KA_PON_RESET # (MODEM_FUNC_SEL_PON_DEFAULT != !MODEM)) #

(KA_PON_RESET & (MODEM_FUNC_SEL_PON_DEFAULT == MODEM)) ) then

MODEM

else

!MODEM;

"******************************************************************************

" External Read Registers' Chip-Selects

"******************************************************************************

equations

Bcsr2_3Cs~.oe = 3;

!Bcsr2Cs~ = MPC_READ_BCSR_2;

!Bcsr3Cs~ = MPC_READ_BCSR_3;

"******************************************************************************

"* Read Registers.

"* All registers have read capabilty.

"******************************************************************************

equations

DataOe = MPC_READ_BCSR_0 #

MPC_READ_BCSR_1 #

MPC_READ_BCSR_4 #

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RESET_CONFIG_DRIVEN;

Data.oe = DataOe;

" Data.oe = ^hffff;

when (MPC_READ_BCSR_0 #

RESET_CONFIG_DRIVEN) then

Data = [ERB.fb,IP~.fb,RSV2.fb,BDIS.fb,BPS0.fb,BPS1.fb,RSV6.fb,

ISB0.fb,ISB1.fb,DBGC0.fb,DBGC1.fb,DBPC0.fb,DBPC1.fb,

RSV13.fb,RSV14.fb,RSV15.fb];

else when (MPC_READ_BCSR_1) then

Data = ReadBcsr1;

else when (MPC_READ_BCSR_4) then

"

Data = [UsbUtpFethEn~,UsbSpeed,UsbVcc0, UsbVcc1, VideoOn~,VideoExtClkEn,

VideoRst~,SignaLamp~,EthLoop,TPFLDL~,TPSQEL~,Modem_Audio~,0,0,0,0];

Data = [EthLoop,TPFLDL~,TPSQEL~,SignaLamp~,UsbUtpFethEn~,Usb

Speed,UsbVcc0,

UsbVcc1, VideoOn~,VideoExtClkEn,VideoRst~,Mode-

mEn~,Modem_Audio~,0,0,0];

end bcsr10

"******************************************************************************

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U22 - Auxiliary Board Control

Support Information

A•3

"******************************************************************************

"* In this file (5):

"* 1) The use of BCLOSE~ is removed. This due to the assignment

"*

BCLOSE~ to GPL4A. In order of using of GPL4A bit in the upm to determine

data sampling edge, GPL4A may not be used as a GPL. Therefore DramBankXCs~

must envelope the cycle so that data buffers remain open throughout the

cycle.

"* 2) Removed CS support for flash configuration. I.e., FlashCs1~ will not be

"*

asserted during hard reset. Flash configuration will be supported on

silicon next revisions.

data buffers will still open for flash configuration when hard reset

asserted and flash configuration option bit, asserted.

"* 3) Since Bclose~ is no longer available, the data buffers will open

"*

asynchronously. I.e., driven directly by the various chip-selects.

to provide data hold (0) on write cycles to flash, CSNT bit in the OR

should be programmed active, while ACS == 00.

"******************************************************************************

"* In This file (6), A12 and A11 are removed from the flash selection equation

"* since they can select only a 1/2 Mbyte of flash rather then 2Mbyte selection

"* needed. Therefore, only one bank of 2 Mbyte flash may be used (MCM29F020).

"* The rest of the CS are driven high constantly.

"******************************************************************************

"* In this file (7):

"* - Pon Reset Out is removed. Pon Reset is driven directly to MPC.

"* - Modck0 becomes Modck2

"* - A9 and A10 replace A11 and A12 in flash bank selection

"* - Optional BufClose~ is removed.

"* - DramEn becomes active-low to support debug-station support changes.

"* - Added F_PD(1:3) to support SMART Flash SIMMs.

"* - Support for 32KHz crystal - renewed.

"******************************************************************************

"* In this file (8):

"* - Added protection against data contention for write cycles after

"*

Flash read cycle. This is achieved using a state-machine which identifies

end of flash read and a chain of internal gates serving as a delay line.

This kind of solution guaranties a fixed delay over the data buffer enable

signal, that is, only after a flash read cycle.

"******************************************************************************

"* In this file (9):

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"* - The addressing scheme of the flash is changed so that the bank does

"*

not occupy a space bigger than its real size. I.e. A9 and A10 use

is conditioned with the module type.

"******************************************************************************

" In this file (10):

"* - A bug is fixed in Smart flash memories presence detect encoding:

"*

for SM732A1000A - F_PD == 5 (was 2)

for SM732A2000 - F_PD == 4 (was 3)

"******************************************************************************

"* In this file (11):

"* - KAPORIn (power-on reset input) line is removed. It was unused previously.

"* - Instead of the the above, F_PD4 input is added, so excact identification

"*

"* - Number of delay stages for flash turn-off time protection is decreased

"* This to avoid possible problem in write to 0-w.s. memories.

may be given to any flash memory.

"******************************************************************************

"* In This file (12):

"* - Added ATA support for PCMCIA. I.e., PccEvenEn~ and PccOddEn~ become

"*

identical, enabled by logic OR of CE1~ and CE2~

"******************************************************************************

module brdctl12

title 'MPC821ADS Board Misc. Control Functions.

Originated for MPC821ADS, Yair Liebman - (MSIL) - April 10, 1995'

"******************************************************************************

"* Device declaration.

*

"******************************************************************************

U22 device 'mach220a';

"******************************************************************************

"* #######

"* #

*

#

##### ###### #####

#

##

#

####

*

"* #

#

##

# #

#

"* #####

"* #

##

#####

#

####

#

#####

# # ######

#

"* #

#

##

#

"* #######

#

######

#

######

####

"******************************************************************************

MPC8XXFADS Design Specification—Rev 0.1

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Support Information

"******************************************************************************

"* Pins declaration.

*

"******************************************************************************

"* clock generator

"******************************************************************************

SYSCLKPIN 50;" pda clkout

"******************************************************************************

"* Dram Associated Pins.

"******************************************************************************

A9 PIN 55;

A10 PIN 39;

A19 PIN 38;

A20 PIN 2;

A30 PIN 36;" pda address lines inputs (IN)

R_W~PIN 23;

SizeDetect1PIN 26;

SizeDetect0PIN 20; " dram simm size detect lines (IN)

HalfWord~PIN 51; " dram port width selection from control register:

" '1' - 32 bit

" '0' - 16 bit

DramBank1Cs~PIN 45;" 1'st bank chip-select(IN, L)

DramBank2Cs~PIN 46;" 2'nd bank chip-select (IN, L)

DramEn~PIN 54;" Dram enable from control reg. (IN, H). Active

" high to support power control.

DramAdd10PIN 32 istype 'com';

DramAdd9PIN 33 istype 'com';" dram address lines

Ras1~PIN 28 istype 'com';

Ras1DD~PIN 30 istype 'com';

Ras2~PIN 29 istype 'com';

Ras2DD~PIN 31 istype 'com';" dram RAS lines.

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"******************************************************************************

"* Flash Associated Pins.

"******************************************************************************

F_PD1PIN 7;

F_PD2PIN 65;

F_PD3PIN 41;

F_PD4PIN 25;

FlashCs~ PIN 49;" flash bank chip-select

FlashEn~PIN 15;" flash enable from control reg.

FlashCs1~PIN 12 istype 'com';" Flash bank1 chip-select

FlashCs2~PIN 22 istype 'com';" Flash bank2 chip-select

FlashCs3~PIN 57 istype 'com';" Flash bank3 chip-select

FlashCs4~PIN 24 istype 'com';" Flash bank4 chip-select

FlashOe~PIN 58 istype 'com';" Flash output enable.

"******************************************************************************

"* Control Register pins

"******************************************************************************

ContRegCs~PIN 59;" control register cs from MPC8XX

ContRegEn~PIN 56;" control register enable from control register.

"******************************************************************************

"* Reset & Interrupt Logic Pins.

"******************************************************************************

Rst0

Rst1

PIN 13;

PIN 21;

" connected to N.C. of Reset P.B.

" connected to N.O. of Reset P.B.

!RegPORIn~PIN 9;

" Regular Power On Reset In. (H)

HardReset~PIN 48 istype 'com';

SoftReset~PIN 40 istype 'com';

ResetConfig~PIN 67 istype 'com';

" Actual hard reset output (O.D.)

" Actual soft reset output (O.D.)

" Drives the RSTCONF* signal of the MPC8XX.

DriveConfig~PIN 63 istype 'com';" Drives configuration data to the MPC8XX

Abr0 PIN 10;

Abr1 PIN 11;

" connected to N.C. of Abort P.B.

" connected to N.O. of Abort P.B.

NMIEnNODE istype 'com';

" enables T.S. NMI pin

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NMI~PIN 44 istype 'com';

" Actual NMI pin (O.D.)

"******************************************************************************

"* Power On Reset Configuration Support

"******************************************************************************

ModInPIN 64;" MODCK dip-switch

Modck2PIN 60 istype 'com';" MODCK2 output

Modck1PIN 66 istype 'com';" MODCK1 output

ModckOeNODE istype 'com';" enables MODCKs towards MPC8XX during

" Hard Reset.

"******************************************************************************

"* Data Buffers Enables and Reset configuration support

"******************************************************************************

TA~ PIN 6;

TEA~PIN 47;

" transfer Acknowledge

" Transfer Error Acknowledge.

FlashCfgEn~PIN 17;

" flash configuration enable from control

" register.

PccEn~PIN 4;

" PCMCIA channel enable from control reg.

PccCE1~PIN 16;

PccCE2~PIN 43;

UpperHalfEn~PIN 3 istype 'com,invert';

LowerHalfEn~PIN 5 istype 'com,invert';

" bits 0:15 data buffer enable

" bits 16:31 data buffer enable

PccEvenEn~PIN 14 istype 'com,invert';

PccOddEn~PIN 37 istype 'com,invert';

" pcc upper byte data buffer enable

" pcc lower byte data buffer enable

PccR_W~PIN 62 istype 'com';" pcmcia data buffers direction

"******************************************************************************

"*

###

#

*

#

##### ###### #####

#

##

#

####

*

#

##

# #

#

##

# #

#

#####

#

####

#

# #

##

#

#####

# # ######

#

##

#

###

#

######

#

######

####

MPC8XXFADS Design Specification—Rev 0.1

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"******************************************************************************

"* Reset & Interrupt Logic Pins.

"******************************************************************************

RstDeb1NODE istype 'com';

AbrDeb1NODE istype 'com';

" reset push button debouncer

" abort push button debouncer

HardResetEnNODE istype 'com';

SoftResetEnNODE istype 'com';

" enables T.S. hard reset pin

" enables T.S. soft reset pin

ConfigHold2,

ConfigHold1,

ConfigHold0node istype 'reg,buffer';" supplies data hold time for

" hard reset configuration

ConfigHoldEndnode istype 'com';

"******************************************************************************

"* data buffers enable.

"******************************************************************************

SyncHardReset~NODE istype 'reg,buffer';

" synchronized hard reset

DSyncHardReset~ NODE istype 'reg,buffer';" double synchronized hard reset

SyncTEA~NODE istype 'reg,buffer';

" needed since TEA~ is O.D.

HoldOffConsidered NODE istype 'reg,buffer';" data drive hold-off state

" machine.

D_FlashOe~NODE istype 'com'; " delayed flash output enable

DD_FlashOe~NODE istype 'com';" double delayed flash output

" enable

TD_FlashOe~NODE istype 'com';" triple delayed flash output

" enable

" QD_FlashOe~NODE istype 'com'; quad delayed

" PD_FlashOe~NODE istype 'com'; penta delayed

KeepPinsConnected node istype 'com';

"******************************************************************************

"* #####

*

"* #

#

####

#

####

#####

#

##

#

#####

#

##

#

##

MPC8XXFADS Design Specification—Rev 0.1

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"* #

#

# #

#

# #

##

####

#

# #

#

# #

##

#

*

#

######

#

"* #####

"*

####

#

####

#

"* ######

"* #

#

######

####

#

##

#####

#

#####

#

#####

#

###### #####

#

"* ######

"*

######

####

######

#

"*

##

#####

#

####

#

##

# #

#

"* ######

# #

##

#

"*

#

####

#

"******************************************************************************

H, L, X, Z = 1, 0, .X., .Z.;

C, D, U

= .C., .D., .U.;

"******************************************************************************

"* SLOW_32K_LOCK = 1;

"******************************************************************************

"* Signal groups

"******************************************************************************

PdaAdd = [A9,A10,A19,A20,A30];

DramAdd = [DramAdd10,DramAdd9];

DramCS~ =[DramBank2Cs~,DramBank1Cs~];

RAS = [Ras1~,Ras1DD~,Ras2~,Ras2DD~];

SD = [SizeDetect1,SizeDetect0];

FlashCsOut = [FlashCs4~,FlashCs3~,FlashCs2~,FlashCs1~];

Reset = [HardReset~,SoftReset~];

ResetEn = [HardResetEn,SoftResetEn];

Rst = [Rst1,Rst0];

Abr = [Abr1,Abr0];

Debounce = [RstDeb1,AbrDeb1];

DramCs = [DramBank2Cs~,DramBank1Cs~];

Cs = [ContRegCs~,FlashCs~ ,DramBank1Cs~,DramBank2Cs~];

PccCs = [PccCE1~,PccCE2~];

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LocDataBufEn = [UpperHalfEn~,LowerHalfEn~];

PccDataBufEn = [PccEvenEn~,PccOddEn~];

ModuleEn = [DramEn~,FlashEn~,PccEn~,ContRegEn~];

SyncReset = [SyncHardReset~,DSyncHardReset~];

RstCause = [Rst1,Rst0,Abr1,Abr0,RegPORIn~];

Stp = [TA~];

Modck = [Modck2, Modck1];

ConfigHold =[ConfigHold2, ConfigHold1, ConfigHold0];

F_PD = [F_PD4, F_PD3, F_PD2, F_PD1];

"******************************************************************************

"* Dram Declarations.

"******************************************************************************

DRAM_ENABLE_ACTIVE = 0;

DRAM_ENABLED = (DramEn~ == DRAM_ENABLE_ACTIVE);

SIMM36100 = (SD == 0);

SIMM36200 = (SD == 3);

SIMM36400 = (SD == 2);

SIMM36800 = (SD == 1);

IS_HALF_WORD = (HalfWord~ == 0);

"******************************************************************************

"* Flash Declarations.

"******************************************************************************

FLASH_ENABLE_ACTIVE = 0;

FLASH_ENABLED = (FlashEn~ == FLASH_ENABLE_ACTIVE);

MCM29020 = (F_PD == 8);

MCM29040 = (F_PD == 7);

MCM29080 = (F_PD == 6);

SM732A1000A = (F_PD == 5);

SM732A2000 = (F_PD == 4);

FLASH_BANK1 = ( (MCM29020 # SM732A1000A) #

(MCM29040 & !A10) #

(MCM29080 & !A9 & !A10) #

(SM732A2000 & !A9) );

FLASH_BANK2 = ( (MCM29040 & A10) #

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(MCM29080 & !A9 & A10) #

(SM732A2000 & A9) );

FLASH_BANK3 = (A9 & !A10 & MCM29080);

FLASH_BANK4 = (A9 & A10 & MCM29080);

"******************************************************************************

"* Reset Declarations.

"******************************************************************************

KEEP_ALIVE_PON_RESET_ACTIVE = 0;

REGULAR_PON_RESET_ACTIVE = 0;

HARD_RESET_ACTIVE = 0;

SOFT_RESET_ACTIVE = 0;

HARD_CONFIG_HOLD_VALUE = 4;

DRIVE_MODCK_TO_PDA = (HardReset~ == HARD_RESET_ACTIVE);" have modck stable

" during hard reset.

REGULAR_POWER_ON_RESET = (RegPORIn~ == REGULAR_PON_RESET_ACTIVE);

HARD_RESET_ASSERTED = (SyncHardReset~.fb == HARD_RESET_ACTIVE);

HARD_RESET_NEGATES = ( (SyncHardReset~.fb != HARD_RESET_ACTIVE )

& (DSyncHardReset~.fb == HARD_RESET_ACTIVE));

" detecting hard reset negation

"******************************************************************************

"* data buffers enable.

"******************************************************************************

BUFFER_DISABLED = 1;

BUFFER_ENABLED = !BUFFER_DISABLED;

CONTROL_REG_ENABLE_ACTIVE = 0;

FLASH_CONFIG_ENABLED_ACTIVE = 0;

PCMCIA_ENABLE_ACTIVE = 0;

GPL_ACTIVE = 0;

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TEA_ASSERTS = (!TEA~ & SyncTEA~.fb);" first clock of TEA~ asserted

CONTROL_REG_ENABLED = (ContRegEn~ == CONTROL_REG_ENABLE_ACTIVE);

FLASH_CONFIGURATION_ENABLED = (FlashCfgEn~ == FLASH_CONFIG_ENABLED_ACTIVE);

PCC_ENABLED = (PccEn~ == PCMCIA_ENABLE_ACTIVE);

NO_HOLD_OFF = 0;

HOLD_OFF_CONSIDERED = 1;

STATE_HOLD_OFF_CONSIDERED = (HoldOffConsidered.fb == HOLD_OFF_CONSIDERED);

STATE_NO_HOLD_OFF = (HoldOffConsidered.fb == NO_HOLD_OFF);

END_OF_FLASH_READ = !TA~ & !FlashCs~ & R_W~;" end of flash read cycle.

END_OF_OTHER_CYCLE = (!TA~ & FlashCs~ # " another access or

!TA~ & !FlashCs~ & !R_W~); " flash write

"* HOLD_OFF_PERIOD = (!R_W~ & !PD_FlashOe~.fb);

HOLD_OFF_PERIOD = (!R_W~ & !TD_FlashOe~.fb);

"******************************************************************************

"* Equations, state diagrams.

*

"******************************************************************************

"*

*

"* #######

"* #

####

#

##

#####

#

####

#

####

"* #

#

##

# #

#

"* #####

"* #

#

####

# #

#

######

# #

##

#

"* #

#

"* #######

"*

### #

####

#

####

"******************************************************************************

"* Reset Logic

"******************************************************************************

equations

Reset.oe = ResetEn;

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Reset = 0;" open drain

RstDeb1 = !( Rst1 & (!( RstDeb1.fb & Rst0) ) );

AbrDeb1 = !( Abr1 & (!( AbrDeb1.fb & Abr0) ) );

" Reset push-button debouncer

" Abort push-button debouncer

HardResetEn = RstDeb1.fb & AbrDeb1.fb " both buttons are depressed;

# REGULAR_POWER_ON_RESET;

SoftResetEn = RstDeb1.fb & !AbrDeb1.fb;" only reset button depressed

"******************************************************************************

"* Power On reset configuration

"******************************************************************************

equations

Modck.oe = ModckOe;

ModckOe = DRIVE_MODCK_TO_PDA;

Modck2 = L;

@ifndef SLOW_32K_LOCK {

Modck2 = ModIn;" support for 1:513 (32KHz crystal) or

Modck1 = ModIn;" 1:5 (5MHz clock gen.) via CLK4IN

}

@ifdef SLOW_32K_LOCK {

Modck2 = !ModIn;" support for 1:1 or 1:5 from CLK4IN only

Modck1 = H;" no support for 32K oscillator.

}

"******************************************************************************

"* Hard reset configuration

"******************************************************************************

equations

ResetConfig~.oe = H;

DriveConfig~.oe = H;

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"* Configuration hold counter. Since the rise time of the HARD RESET signal

"* is relatively slow, there is a need to provide a hold time for reset

"* configuration.

ConfigHold.clk = SYSCLK;

when (SyncHardReset~.fb & !ConfigHoldEnd.fb) then ConfigHold := ConfigHold.fb +1;

else when (SyncHardReset~.fb & ConfigHoldEnd.fb) then ConfigHold := ConfigHold.fb;

else when (!SyncHardReset~.fb) then ConfigHold := 0;

ConfigHoldEnd = (ConfigHold.fb == HARD_CONFIG_HOLD_VALUE); " terminal count

!ResetConfig~ = !HardReset~;" drives RSTCONF~ to MPC8XX

!DriveConfig~ = !ConfigHoldEnd.fb; " drives configuration data on the bus.

"******************************************************************************

"* NMI generation

"******************************************************************************

equations

NMI~.oe = NMIEn;

NMI~ = 0;" O.D.

NMIEn = !RstDeb1.fb & AbrDeb1.fb;" only abort button depressed

"******************************************************************************

"* local data buffers enable

"******************************************************************************

equations

SyncHardReset~.clk = SYSCLK;

DSyncHardReset~.clk = SYSCLK;

SyncHardReset~ := HardReset~;

DSyncHardReset~ := SyncHardReset~.fb;

SyncTEA~.clk = SYSCLK;

SyncTEA~ := TEA~;

LocDataBufEn.oe = 3;

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!UpperHalfEn~ = (!DramBank1Cs~ & DRAM_ENABLED #

!DramBank2Cs~ & (SIMM36200 # SIMM36800) & DRAM_ENABLED #

!FlashCs~ & FLASH_ENABLED #

!ContRegCs~ & CONTROL_REG_ENABLED #

!PccCE1~ & PCC_ENABLED #

!PccCE2~ & PCC_ENABLED #

!ConfigHoldEnd.fb)

&

(STATE_HOLD_OFF_CONSIDERED & (!HOLD_OFF_PERIOD) #

STATE_NO_HOLD_OFF);

!LowerHalfEn~ = (!DramBank1Cs~ & DRAM_ENABLED & !IS_HALF_WORD #

!DramBank2Cs~ & (SIMM36200 # SIMM36800) &

!IS_HALF_WORD & DRAM_ENABLED #

!FlashCs~ & FLASH_ENABLED #

!ConfigHoldEnd.fb & FLASH_CONFIGURATION_ENABLED) &

(STATE_HOLD_OFF_CONSIDERED & !HOLD_OFF_PERIOD #

STATE_NO_HOLD_OFF);

"******************************************************************************

"* local data buffers disable (data contention protection)

"******************************************************************************

equations

HoldOffConsidered.clk = SYSCLK;

D_FlashOe~ = FlashOe~;

DD_FlashOe~ = D_FlashOe~.fb;

TD_FlashOe~ = DD_FlashOe~.fb;

"* QD_FlashOe~ = TD_FlashOe~.fb;

"* PD_FlashOe~ = QD_FlashOe~.fb;

@ifdef DEBUG {

equations

HoldOffConsidered := HOLD_OFF_CONSIDERED;

}

@ifndef DEBUG {

state_diagram HoldOffConsidered

state NO_HOLD_OFF:

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if (END_OF_FLASH_READ & DSyncHardReset~.fb) then

HOLD_OFF_CONSIDERED

else

NO_HOLD_OFF;

state HOLD_OFF_CONSIDERED:

if (END_OF_OTHER_CYCLE # !DSyncHardReset~.fb) then

NO_HOLD_OFF

else

HOLD_OFF_CONSIDERED;

}

"******************************************************************************

"* pcc data buffers enable

"******************************************************************************

equations

PccDataBufEn.oe = 3;

!PccEvenEn~ = (!PccCE1~ # !PccCE2~) & PCC_ENABLED & !HARD_RESET_ASSERTED &

(STATE_HOLD_OFF_CONSIDERED & HOLD_OFF_PERIOD #

STATE_NO_HOLD_OFF);

!PccOddEn~ = (!PccCE1~ # !PccCE2~) & PCC_ENABLED & !HARD_RESET_ASSERTED &

(STATE_HOLD_OFF_CONSIDERED & HOLD_OFF_PERIOD #

STATE_NO_HOLD_OFF);

"******************************************************************************

"* pcc data buffers direction

"******************************************************************************

equations

PccR_W~.oe = H;

PccR_W~ = R_W~;

"******************************************************************************

"* Dram Address lines.

"* These lines are conencted to the dram high order address lines A9 and A10

"* (if available). These lines change value according to the dram size and

"* port size.

"* The dram size is encoded from the presence detect lines (see definitions

"* above) and the port size is determined by the control register.

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"******************************************************************************

equations

DramAdd.oe = 3;

when (!IS_HALF_WORD # IS_HALF_WORD & (SIMM36400 # SIMM36800)) then

DramAdd9 = A20;

else

DramAdd9 = A30;

when ( (SIMM36400 # SIMM36800) & !IS_HALF_WORD) then

DramAdd10 = A19;

else when ( (SIMM36400 # SIMM36800) & IS_HALF_WORD) then

DramAdd10 = A30;

else

DramAdd10 = 0;

"******************************************************************************

"* RAS generation.

"* Since the dram simm requires RAS signals to be split due to high capacitive

"* load and to allow 16 bit operation. When working with 16 bit port size,

"* the double drive RAS signals are disabled.

"******************************************************************************

equations

RAS.oe = ^hf;

!Ras1~ = !DramBank1Cs~ & DramBank2Cs~ & DRAM_ENABLED;

!Ras2~ = !DramBank2Cs~ & DramBank1Cs~ & DRAM_ENABLED & (SIMM36200 # SIMM36800);

!Ras1DD~ = !DramBank1Cs~ & DramBank2Cs~ & DRAM_ENABLED;

!Ras2DD~ = !DramBank2Cs~ & DramBank1Cs~ & DRAM_ENABLED & (SIMM36200 # SIMM36800);

"******************************************************************************

"* Flash Chip Select

"******************************************************************************

equations

FlashCsOut.oe = ^hf;

!FlashCs1~ = FLASH_ENABLED & !FlashCs~ & FLASH_BANK1;

!FlashCs2~ = FLASH_ENABLED & !FlashCs~ & FLASH_BANK2 ;

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!FlashCs3~ = FLASH_ENABLED & !FlashCs~ & FLASH_BANK3 ;

!FlashCs4~ = FLASH_ENABLED & !FlashCs~ & FLASH_BANK4 ;

FlashOe~.oe = H;

!FlashOe~ = FLASH_ENABLED & R_W~;

"******************************************************************************

"* Auxiliary functions

"******************************************************************************

equations

KeepPinsConnected = TA~ ;

end brdctl12

"******************************************************************************

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APPENDIX B - ADI I/F

The ADI parallel port supplies parallel link from the MPC8XXFADS to various host computers. This

port is connected via a 37 line cable to a special board called ADI (Application Development Interface)

installed in the host computer. Four versions of the ADI board are available to support connection to

IBM-PC/XT/AT, MAC II, VMEbus computers and SUN-4 SPARC stations. It is possible to connect the

MPC281ADS board to these computers provided that the appropriate software drivers are installed

on them.

Each MPC281ADS can have 8 possible slave addresses set for its ADI port, enabling up to 8

MPC281ADS boards to be connected to the same ADI board.

The ADI port connector is a 37 pin, male, D type connector. The connection between the

MPC281ADS and the host computer is by a 37 line flat cable, supplied with the ADI board. FIGURE

A-1 below shows the pin configuration of the connector.

FIGURE A-1 ADI Port Connector

1

2

3

4

5

6

7

8

N.C.

D_C~

Gnd

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

HST_ACK

ADS_SRESET

ADS_HRESET

ADS_SEL2

ADS_SEL1

ADS_SEL0

HOST_REQ

ADS_REQ

ADS_ACK

N.C.

Gnd

(+ 12 v) N.C.

HOST_VCC

9

10

11

12

13

14

15

16

HOST_ENABLE~

Gnd

N.C.

PD1

PD3

PD5

PD7

Gnd

PD0

PD2

PD4

PD6

17

18

19

NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the MPC281ADS.

B•1

ADI Port Signal Description

The ADI port on the MPC281ADS was slightly modified to generate either hard reset or soft reset.

This feature was added to comply with the MPC’s reset mechanism.

In the list below, the directions ’I’, ’O’, and ’I/O’ are relative to the MPC8XXFADS board. (I.E. ’I’ means

input to the MPC8XXFADS)

NOTE:

Since the ADI was originated for the DSP56001ADS

some of its signals throughout the boards it was used

with, were designated with the prefix "ADS". This

convention is kept with this design also.

•

ADS_SEL(0:2) - ’I’

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These three input lines determine the slave address of the MPC8XXFADS being accessed

by the host computer. Up to 8 boards can be addressed by one ADI board.

•

ADS_SRESET - ’I’

This input line is used to generate Soft Reset for the MPC. When an ads is selected and

this line is asserted by the host computer, Soft Reset will be generated to the MPC along

with the Soft Reset configuration applied during that sequence.

HOST_ENABLE~ - ’I’

This line is always driven low by the ADI board. When an ADI is connected to the

MPC8XXFADS, this signals enabled the operation of the debug port controller. Otherwise

the debug port controller is disabled and its outputs are tri-stated.

ADS_HRESET - ’I’

When a host is connected, this line is used in conjunction with the addressing lines to gen-

erate a Hard Reset to the MPC8XXFADS board. When this signal is driven in conjunction

with the ADS_SRESET signal, the ADI I/F state machines and registers are reset.

•

HOST_REQ -’I’

This signal initiates a host to MPC8XXFADS write cycle.

ADS_ACK - ’O’

This signal is the MPC8XXFADS response to the HOST_REQ signal, indicating that the

board has detected the assertion of HOST_REQ.

•

ADS_REQ - ’O’

This signal initiates an MPC8XXFADS to host write cycle.

HST_ACK - ’I’

This signal serves as the host’s response to the ADS_REQ signal.

HOST_VCC - ’I’ (three lines)

These lines are power lines from the host computer. In the MPC8XXFADS, these lines are

used by the hardware to determine if the host computer is powered on.

•

PD(0:7) - ’I/O’

These eight I/O lines are the parallel data bus. This bus is used to transmit and receive data from the

host computer.

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APPENDIX C - ADI Installation

C•1

INTRODUCTION

This appendix describes the hardware installation of the ADI board into various host computers.

The installation instructions cover the following host computers:

1) IBM-PC/XT/AT

2) SUN - 4 (SBus interface)

C•2

IBM-PC/XT/AT to MPC8XXFADS Interface

The ADI board should be installed in one of the IBM-PC/XT/AT motherboard system expansion slots.

A single ADI can control up to eight MPC8XXFADS boards. The ADI address in the computer is

configured to be at I/O memory addresses 100-102 (hex), but it may be reconfigured for an alternate

address space.

CAUTION

BEFORE REMOVING OR INSTALLING

ANY EQUIPMENT IN THE IBM-PC/XT/AT

COMPUTER, TURN THE POWER OFF

AND REMOVE THE POWER CORD.

C•2•1

ADI Installation in IBM-PC/XT/AT

Refer to the appropriate Installation and Setup manual of the IBM-PC/XT/AT computer for instructions

on removing the computer cover.

The ADI board address block should be configured at a free I/O address space in the computer. The

address must be unique and it must not fall within the address range of another card installed in the

computer.

The ADI board address block can be configured to start at one of the three following addresses:

•

$100 - This address is unassigned in the IBM-PC

$200 - This address is usually used for the game port

$300 - This address is defined as a prototype port

The ADI board is factory configured for address decoding at 100-102 hex in the IBM-PC/XT/AT I/O

address map. These are undefined peripheral addresses.

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FIGURE A-1 Physical Location of jumper JG1 and JG2

JG1 JG2

NOTE: Jumper JG2 should be left unconnected.

The following figure shows the required jumper connection for each address configuration. Address

0 hex is not recommended, and its usage might cause problems.

FIGURE A-2 JG1 Configuration Options

0 hex

100 hex

200 hex

300 hex

To properly install the ADI board, position its front bottom corner in the plastic card guide channel at

the front of the IBM-PC/XT/AT chassis. Keeping the top of the ADI board level and any ribbon cables

out of the way, lower the board until its connectors are aligned with the computer expansion slot

connectors. Using evenly distributed pressure, press the ADI board straight down until it seats in the

expansion slot.

Secure the ADI board to the computer chassis using the bracket retaining screw. Refer to the

computer Installation and Setup manual for instructions on reinstalling the computer cover.

C•3

SUN-4 to MPC8XXFADS Interface

The ADI board should be installed in one of the SBus expansion slots in the Sun-4 SPARCstation

computer. A single ADI can control up to eight MPC8XXFADS boards.

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CAUTION

BEFORE REMOVING OR INSTALLING ANY

EQUIPMENT IN THE SUN-4 COMPUTER,

TURN THE POWER OFF AND REMOVE

THE POWER CORD.

C•3•1

ADI Installation in the SUN-4

There are no jumper options on the ADI board for the Sun-4 computer. The ADI board can be inserted

into any available SBus expansion slot on the motherboard.

Refer to the appropriate Installation and Setup manual for the Sun-4 computer for instructions on

removing the computer cover and installing the board in an expansion slot.

FIGURE A-3 ADI board for SBus

SBus

Connector

ADI

Connector

Following is a summary of the Instructions in the Sun manual:

1. Turn off power to the system, but keep the power cord plugged in. Be sure to save all open files

and then the following steps should shut down your system:

•

hostname% /bin/su

Password: mypasswd

hostname# /usr/etc/halt

wait for the following messages.

Syncing file systems... done

Halted

Program Terminated

Type b(boot), c(continue), n(new command mode)

When these messages appear, you can safely turn off the power to the system unit.

•

2. Open the system unit. Be sure to attach a grounding strap to your wrist and to the metal casing

of the power supply. Follow the instructions supplied with your system to gain access to the

SBus slots.

3. Remove the SBus slot filler panel for the desired slot from the inner surface of the back panel

of the system unit. Note that the ADI board is a slave only board and thus will function in any

available SBus slot.

4. Slide the ADI board at an angle into the back panel of the system unit. Make sure that the

mounting plate on the ADI board hooks into the holes on the back panel of the system unit.

MPC8XXFADS Design Specification—Rev 0.1

For More Information On This Product,

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Support Information

5. Push the ADI board against the back panel and align the connector with its mate and gently

press the corners of the board to seat the connector firmly.

6. Close the system unit.

7. Connect the 37 pin interface flat cable to the ADI board and secure.

8. Turn power on to the system unit and check for proper operation.

MPC8XXFADS Design Specification—Rev 0.1

For More Information On This Product,

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

For More Information On This Product,

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Freescale Semiconductor, Inc.

For More Information On This Product,

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Freescale Semiconductor, Inc.

10/97

MPC860TFADS Daughter Board

Design Speciﬁcation—Rev 0.1

PRELIMINARY

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee

regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or

circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in

different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola

does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components

in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure

of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and

Employer.

are registered trademarks of Motorola, Inc. Mfax is a trademark of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Afﬁrmative Action

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

General Information

1 - General Information

1•1

Introduction

This document is the operation guide for the MPC8XXFADS Daughter Board for the MPC860T-

named the MPC860TFADSDB.

The daughter board holds the evaluated MPC860T along with some necessary logic, which is

required to be in the nearest vicinity of the MPC860T as well as peripherals, that are dedicated to the

MPC860T and are not required for any other member of the MPC8XX family.

A

B

The daughter board has 2 sets of matching connectors - on the print side and on the component

side. Those on the print side, connect to a matching set found on the MPC8XXFADS while those on

the component side, are to serve hardware expansion via a dedicated adaptor.

In addition, a set of logic analyzer connector is featured matching the new high density HP16500 logic

analyzer adaptors, this to provide fast connection to logic analyzer while saving on board’s space and

reducing EMI.

1•2

Abbreviations’ List

C

•

FADS - the MPC8XXFADS, to which this board connects.

UPM - User Programmable Machine

GPCM - General Purpose Chip-select Machine

GPL - General Purpose Line (associated with the UPM)

DB - Daughter Board the MPC860TFADSDB, the subject of this document.

MPC860T - MPC860 + Fast Ethernet Controller.

BSCR - Board Control & Status Register.

ZIF - Zero Input Force

BGA - Ball Grid Array

Spec - engineering Specification Document.

1•3


型号：	KMPC860SRCZQ50D4
厂家：	NXP
描述：	KMPC860SRCZQ50D4 PC
文件：	总242页 (文件大小：3218K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KMPC860SRCZQ50D4 [NXP]

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