LF298 [NXP]
Sample-and-hold amplifiers; 采样和保持放大器
| 型号： | LF298 |
| 厂家： | 
NXP |
| 描述： | Sample-and-hold amplifiers |
| 文件： | 总5页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
DESCRIPTION
PIN CONFIGURATIONS
The LF198/LF298/LF398 are monolithic sample-and-hold circuits
which utilize high-voltage ion-implant JFET technology to obtain
ultra-high DC accuracy with fast acquisition of signal and low droop
rate. Operating as a unity gain follower, DC gain accuracy is 0.002%
typical and acquisition time is as low as 6µs to 0.01%. A bipolar
input stage is used to achieve low offset voltage and wide
bandwidth. Input offset adjust is accomplished with a single pin and
does not degrade input offset drift. The wide bandwidth allows the
LF198 to be included inside the feedback loop of 1MHz op amps
FE, N Packages
1
2
3
4
8
7
6
5
V+
OFFSET VOLTAGE
INPUT
LOGIC
LOGIC REFERENCE
C
h
OUTPUT
V–
10
without having stability problems. Input impedance of 10 Ω allows
high source impedances to be used without degrading accuracy.
TOP VIEW
P-channel junction FETs are combined with bipolar devices in the
output amplifier to give droop rates as low as 5mV/min with a 1µF
hold capacitor. The JFETs have much lower noise than MOS
devices used in previous designs and do not exhibit high
temperature instabilities. The overall design guarantees no
feedthrough from input to output in the hold mode even for input
signals equal to the supply voltages.
1
D Package
1
14
13
12
11
10
9
INPUT
NC
V
Adj
OS
2
3
4
5
6
7
NC
V+
V–
LOGIC
LOGIC REF
NC
NC
Logic inputs are fully differential with low input current, allowing
direct connection to TTL, PMOS, and CMOS; differential threshold is
1.4V. The LF198/LF298/LF398 will operate from ±5V to ±18V
supplies. They are available in 8-pin plastic DIP, 8-pin Cerdip, and
14-pin plastic SO packages.
NC
NC
8
C
h
OUTPUT
TOP VIEW
FEATURES
NOTE:
1. SO and non-standard pinouts.
• Operates from ±5V to ±18V supplies
• Less than 10µs acquisition time
• TTL, PMOS, CMOS compatible logic input
• 0.5mV typical hold step at CH=0.01µF
• Low input offset
APPLICATION
• The LF198/LF298/LF398 are ideally suited for a wide variety of
sample-and-hold applications, including data acquisition,
analog-to-digital conversion, synchronous demodulation, and
automatic test setup
• 0.002% gain accuracy
• Low output noise in hold mode
• Input characteristics do not change during hold mode
• High supply rejection ratio in sample or hold
• Wide bandwidth
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
-55°C to +125°C
0 to +70°C
ORDER CODE
LF198FE
LF398D
DWG #
0580A
0175D
0580A
0404B
0580A
0404B
8-Pin Ceramic Dual In-Line Package (CERDIP)
14-Pin Plastic Small Outline (SO) Package
8-Pin Ceramic Dual In-Line Package (CERDIP)
8-Pin Plastic Dual In-Line Package (DIP)
8-Pin Ceramic Dual In-Line Package (CERDIP)
8-Pin Plastic Dual In-Line Package (DIP)
0 to +70°C
LF398FE
LF398N
0 to +70°C
-25°C to +85°C
-25°C to +85°C
LF298FE
LF298N
879
August 31, 1994
853-0135 13721
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
FUNCTIONAL DIAGRAM
TYPICAL APPLICATIONS
OFFSET
V+
30k
V–
4
–
5
1
OUTPUT
+
3
3
5
6
S/H
OUTPUT
INPUT
ANALOG INPUT
8
C
LOGIC
7
h
300
SAMPLE 5V
HOLD 0V
8
7
LOGIC
INPUT
LOGIC
REFERENCE
6
HOLD
CAPACITOR
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNIT
V
S
Supply voltage
±18
V
Maximum power dissipation
3
T =25°C (still-air)
A
F package
N package
D package
780
1160
1040
mW
mW
mW
T
A
Operating ambient temperature range
LF198
-55 to +125
-25 to +85
0 to +70
°C
°C
°C
°C
LF298
LF398
T
STG
Storage temperature range
-65 to +150
Equal to
supply voltage
V
IN
Input voltage
Logic-to-logic reference differential
voltage
+7, -30
V
2
Output short-circuit duration
Indefinite
10
Hold capacitor short-circuit duration
Lead soldering temperature (10sec max)
sec
T
SOLD
300
°C
NOTES:
1. The maximum junction temperature of the LF398 is 150°C. When operating at elevated ambient temperature, the packages must be derated
based on the thermal resistance specified.
2. Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins must always be at least 2V
below the positive supply and 3V above the negative supply.
3. Derate above 25°C, at the following rates:
F package at 6.2mW/°C
N package at 9.3mW/°C
D package at 8.3mW/°C
880
August 31, 1994
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following conditions apply: unit is in “sample” mode; V = ±15V; T = 25°C; -11.5V3 V ≤ +11.5V; C =0.01µF;
S
J
IN
H
and R = 10kΩ. Logic reference voltage = 0V and logic voltage = 2.5V.
L
LF198/LF298
LF398
Typ
2
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Typ
Max
Min
Max
7
T =25°C
J
1
3
5
4
V
OS
Input offset voltage
mV
Full temperature range
10
T =25°C
5
25
75
10
50
J
4
I
Input bias current
nA
BIAS
Full temperature range
100
10
10
Input impedance
Gain error
T =25°C
10
10
Ω
J
0.002 0.005
0.02
0.004 0.01
0.02
T =25°C, RL=10k
Full temperature range
J
%
dB
Ω
Feedthrough attenuation
ratio at 1kHz
86
96
80
90
T =25°C, C =0.01µF
J
h
0.5
2
0.5
4
T =25°C, “HOLD“ mode
J
Output impedance
Full temperature range
4
6
2
“HOLD“ step
T =25°C, C =0.01µF, V =0
OUT
0.5
4.5
2.0
5.5
1.0
4.5
2.5
6.5
mV
mA
J
h
4
I
t
Supply current
T ≤ 25°C
J
CC
Logic and logic reference
input current
T = 25°C
2
10
2
10
µA
J
Leakage current into hold
T =25°C, “HOLD“ mode
30
100
30
200
pA
J
4
capacitor
∆V
=10V, C =1000pF
4
4
OUT
h
Acquisition time to 0.1%
µs
AC
C =0.01µF
h
20
20
Hold capacitor charging
current
V -V =2V
IN OUT
5
5
mA
Supply voltage rejection
ratio
V
=0
80
110
1.4
80
110
1.4
dB
V
OUT
Differential logic threshold
T =25°C
J
0.8
2.4
0.8
2.4
NOTES:
1. Unless otherwise specified, the following conditions apply. Unit is in “sample“ mode, V =±15V, T =25°C, -11.5V ≤ V ≤ +11.5V, C = 0.01µF,
S
J
IN
h
and R = 10kΩ. Logic reference voltage = 0V and logic voltage = 2.5V.
L
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an
additional 0.5mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
3. Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated
ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input
signal range.
4. The parameters are guaranteed over a supply voltage of ±5 to ±18V.
881
August 31, 1994
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
TYPICAL DC PERFORMANCE CHARACTERISTICS
Input Bias Current
Output Short Circuit Current
Gain Error
1
0.8
25
20
15
10
5
20
18
16
14
12
10
8
T
= 25°C
J
L
R
= 10k
0.6
SAMPLE MODE
0.4
SOURCING
SINKING
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
6
–5
–10
–15
4
2
0
–15 –10
–5
0
5
10
15
–50 –25
0
25
50
75 100 125 150
–50 –25
0
25
50
75 100 125 150
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
Leakage Current Into
Hold Capacitor
Hold Step
Hold Step Input Voltage
100
10
2
100
10
V+ = V– = 15V
1.8
1.6
1.4
1.2
1
V
= ±15V
S
T
= 25°C
J
V
= 0
OUT
HOLD MODE
T
= 100°C
J
1
1
T
= 25°C
J
0.8
0.6
0.4
0.2
0
–1
0.1
10
T
= 55°C
J
–2
0.01
10
0.01µF
0.1µF
1µF
100pF
1000pF
–50 –25
0
25
50
75 100 125 150
–15 –10
–5
0
5
10
15
JUNCTION TEMPERATURE (°C)
INPUT VOLTAGE (V)
HOLD CAPACITOR
TYPICAL AC PERFORMANCE CHARACTERISTICS
Acquisition Time
Aperture Time
Capacitor Hysteresis
1
250
225
200
175
150
125
100
75
100
V
= 0 TO ±10V
IN
V+ = V– = 15V
∆V ≤ 1mV
T
= 25°C
J
OUT
1%
10
0.1%
∆V = 10V
10
1
NEGATIVE
INPUT
STEP
IN
0.01%
100
1000
50
POSITIVE
INPUT
STEP
25
0.1
0
0.001
0.01
HOLD CAPACITOR (µF)
0.1
–50 –25
0
25
50
75 100 125 150
0.1
1
10
100
JUNCTION TEMPERATURE (°C)
SAMPLE TIME (ms)
882
August 31, 1994
Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
TYPICAL AC PERFORMANCE CHARACTERISTICS (Continued)
Dynamic Sampling Error
Output Droop Rate
‘Hold’ Sampling Time
0
2
1.8
1.6
1.4
1.2
1
10
100
10
V+ = V– = 15V
330pF
SETTLING TIME
–1
–2
10
10
T
=85°C
J
330pF
1
±
0.8
0.6
0.4
0.2
0
T
=25°C
J
–3
–4
–10
10
10
1000pF
–100
0.1
1
10
100
1000
–50 –25
0
25 50 75 100 125 150
100pF
1000pF
0.01µF
0.1µF
1µF
INPUT SLEW RATE (V/ms)
JUNCTION TEMPERATURE (°C)
HOLD CAPACITOR
Phase And Gain
(Input to Output, Small-Signal)
Power Supply Rejection
Output Noise
5
0
80
160
140
120
100
80
160
140
120
100
80
C
= 0
h
T
=25°C
J
70
60
50
40
30
20
10
0
V+ = V– = 15V
C
= 1000pF
h
V
= 0°C
–5
OUT
C
≥ 0.01µF
h
–10
C
= 1000pF
h
‘HOLD’ MODE
POSITIVE
MODE
C
= 0.01µF
h
NEGATIVE
MODE
60
60
40
40
C
≥ 0.01µF
SAMPLE
MODE
h
20
20
C
= 0
h
0
0
100
1k
10k
100k
1M
1k
10k
100k
1M
10M
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
Feedthrough Rejection Ratio
(Hold Mode)
–130
V+ = V– = 15V
–120
–110
–100
–90
T
=25°C
J
V
= 10Vp-p
IN
V
= 0
7.8
C
= 0.1µF
h
C
= 0.01µF
h
–80
C
= 1000pF
h
–70
–60
–50
10
100
100
1k
10k 100k
1M
FREQUENCY (Hz)
883
August 31, 1994
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