LH79524 [NXP]
System-on-Chip; 系统级芯片
| 型号： | LH79524 |
| 厂家： | 
NXP |
| 描述： | System-on-Chip |
| 文件： | 总64页 (文件大小：968K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LH79524/LH79525 (A.1)
System-on-Chip
Preliminary data sheet
2
• I C Module
FEATURES
• Highly Integrated System-on-Chip
2
• Integrated Codec Interface Support Features (I S)
• High Performance: 76.205 MHz CPU Speed,
50.803 MHz maximum AHB clock (HCLK)
• Watchdog Timer
• Vectored Interrupt Controller
• 32-bit ARM720T™ RISC Core
– LH79524: 32-bit External Data Bus
– 208 LFBGA package
– 16 Standard and 16 Vectored IRQ Interrupts
– Interrupts Individually Configurable as IRQ or FIQ
• Three UARTs
– LH79525: 16-bit External Data Bus
– 176 LQFP package
– 16-entry FIFOs for Rx and Tx
– IrDA SIR Support on all UARTs
• 8 kB Cache with Write Back Buffer
• MMU (Windows CE™ Enabled)
• 16 kB On-Chip SRAM
• Three 16-bit Timers with PWM capability
• Real Time Clock
– 32-bit Up-counter with Programmable Load
– Programmable 32-bit Match Compare Register
• Flexible, Programmable Memory Interface
– SDRAM Interface
• Programmable General Purpose I/O Signals
– LH79524: 108 available pins on 14 ports
– LH79525: 86 available pins on 12 ports
– 512 MB External Address Space
– 32-bit External Data Bus (LH79524)
– 16-bit External Data Bus (LH79525)
– SRAM/Flash/ROM Interface
• Programmable Color LCD Controller
– 16 (LH79524) or 12 (LH79525) Bits-per-Pixel
– 15-bit External Address Bus
– Up to 800 × 600 resolution
– 32-bit External Data Bus (LH79524)
– 16-bit External Data Bus (LH79525)
– STN, Color STN, HR-TFT, AD-TFT, TFT
– TFT: Supports 64 k (LH79524) or 4 k (LH79525)
Direct Colors or 256 colors selected from a
Palette of 64 k Colors; 15 Shades of Gray
– Color STN: Supports 3,375 Direct Colors or 256
Colors Selected from a Palette of 3,375 Colors
• Multi-stream DMA Controller
– Four 32-bit Burst-Based Data Streams
• Clock and Power Management
– 32.768 kHz Oscillator for Real Time Clock
– 10 MHz to 20 MHz Oscillator and On-chip PLL
– Active, Standby, Sleep, Stop1, and Stop2 Modes
– Externally-supplied Clock Options
• Synchronous Serial Port
– Supports Data Rates Up to 1.8452 Mbit/s
– Compatible with Common Interface Schemes
• JTAG Debug Interface and Boundary Scan
• On-Chip Boot ROM
• 5 V Tolerant Digital Inputs (excludes oscillator pins)
– XTALIN and XTAL32IN pins are 1.8 V 10%
– Allows Booting from 8-, 16-, or 32-bit Devices
– NAND Flash Boot
• On-Chip regulator allows single 3.3 V supply
• Low Power Modes
– Active Mode: 85 mA (MAX.)
– Standby Mode: 50 mA (MAX.)
– Sleep Mode: 3.8 mA (TYP.)
– Stop Mode 1: 420 µA (TYP.)
– Stop Mode 2: 25 µA (TYP.)
DESCRIPTION
The LH79524/LH79525, powered by an ARM720T,
is a complete System-on-Chip with a high level of inte-
gration to satisfy a wide range of requirements and
applications. The SoC has a fully static design, power
management unit, and low voltage operation (1.8 V
Core, 3.3 V I/O). With the on-chip voltage regulator, a
single 3.3 V supply can be used as well. Robust periph-
erals and a low-power RISC core provide high perfor-
mance at a reasonable price.
• USB Device
– Compliant with USB 2.0 Specifications (Full Speed)
– Four Endpoints
• Ethernet MAC, with MII and MDIO Interfaces
– IEEE 802.3 Compliant
– 10 and 100 Mbit/s Operation
• Analog-to-Digital Converter/Brownout Detector
– 10-bit ADC
– Pen Sense Interrupt
– Integrated Touch Screen Controller (TSC)
Preliminary data sheet
1
LH79524/LH79525
System-on-Chip
NXP Semiconductors
ORDERING INFORMATION
Table 1. Ordering information
Package
Type number
Version
Name
Description
plastic low profile fine-pitch ball grid array pack-
age; 208 balls
LH79524N0F100A0
LH79524N0F100A1
LH79525N0Q100A0
LH79525N0Q100A1
LFBGA208
LFBGA208
LQFP176
LQFP176
SOT1019-1
SOT1019-1
SOT1017-1
SOT1017-1
plastic low profile fine-pitch ball grid array pack-
age; 208 balls
plastic low profile quad flat package; 176 leads;
body 20 x 20 x 1.4 mm
plastic low profile quad flat package; 176 leads;
body 20 x 20 x 1.4 mm
2
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
LH79524/LH79525
10 - 20 MHz 32.768 kHz
OSCILLATOR,
PLL(2), POWER
MANAGEMENT, and
RESET CONTROL
REAL TIME
CLOCK
GENERAL
PURPOSE I/O
ARM720T
CONDITIONED
EXTERNAL
INTERRUPTS
I/O
CONFIGURATION
CACHE
VECTORED
INTERRUPT
CONTROLLER
INTERNAL
INTERRUPTS
SYNCHRONOUS
SERIAL PORT
ETHERNET
MAC
SSP - I2S
CONVERTER
(WITH CODEC
INTERFACE)
INTERNAL
16KB SRAM
BOOT
CONTROLLER
BOOT
ROM
COUNTER/
TIMER (3)
4 CHANNEL
DMA
CONTROLLER
EXTERNAL
MEMORY
CONTROLLER
WATCHDOG
TIMER
ADVANCED
PERIPHERAL
BUS BRIDGE
I2C
USB
DEVICE
16550
UART (3) w/SIR
COLOR
LCD
TEST
SUPPORT
CONTROLLER
10 CHANNEL
10-BIT ADC
(WITH TSC and
BROWNOUT
DETECTOR)
LINEAR
REGULATOR
ADVANCED
LCD
INTERFACE
ADVANCED
PERPHERAL
BUS (APB)
ADVANCED HIGH
PERFORMANCE
BUS (AHB)
LH79525-1
Figure 1. LH79524/LH79525 block diagram
Preliminary data sheet
Rev. 01 — 16 July 2007
3
LH79524/LH79525
System-on-Chip
NXP Semiconductors
LH79524
ball A1
index area
2
4
6
8
10 12 14 16
9 11 13 15
1
3
5
7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
002aad214
Transparent top view
Figure 2. LH79524 pin configuration (LFBGA208)
1
132
LH79525
44
89
002aad213
Figure 3. LH79525 pin configuration (LQFP176)
4
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
SIGNAL DESCRIPTIONS
Table 2. LH79524 Pin Descriptions
LFBGA
SIGNAL NAME
PIN
TYPE
DESCRIPTION
T12
R11
T11
P10
R10
T10
P9
A0
A1
A2
A3
A4
A5
A6
R9
A7
O
External Address Bus
T9
A8
T8
A9
R8
A10
P8
A11
T7
A12
R7
A13
P7
A14
T6
A15
M15
N16
L13
M14
N15
P16
M13
N14
F14
G15
D13
E13
E14
G14
G16
H14
H15
H16
L16
L15
M16
L14
J15
J14
K16
K15
D0
D1
D2
D3
I/O
External Data Bus
D4
D5
D6
D7
SDCLK
SDCKE
DQM0
DQM1
DQM2
DQM3
nDCS0
nDCS1
nRAS
nCAS
nCS0/PM0
nCS1/PM1
nCS2/PM2
nCS3/PM3
nBLE0/PM4
nBLE1/PM5
nBLE2/PM6
nBLE3/PM7
O
O
SDRAM Clock
SDRAM Clock Enable
O
Data Mask Output to SDRAMs
O
O
O
O
SDRAM Chip Select
SDRAM Chip Select
Row Address Strobe
Column Address Strobe
O
O
Static Memory Chip Select; multiplexed with GPIO Port M[3:0] (output only)
Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with
GPIO Port M[7:4] (output only)
Preliminary data sheet
Rev. 01 — 16 July 2007
5
LH79524/LH79525
LFBGA
System-on-Chip
NXP Semiconductors
Table 2. LH79524 Pin Descriptions (Cont’d)
SIGNAL NAME
TYPE
DESCRIPTION
PIN
K14
J16
A16
A15
E2
nOE
O
O
I/O
I/O
I
Static Memory Output Enable
Static Memory Write Enable
nWE
USBDN
USBDP
AN0/UL/X+
AN1/UR/X–
USB Data Negative (Differential Pair output, single ended and Differential pair input)
USB Data Positive (Differential Pair output, single ended and Differential pair input)
ADC Input 0, 4-wire touch screen Upper Left, 5-wire touch screen X+
ADC Input 1, 4-wire touch screen Upper Right, 5-wire touch screen X–
F2
I
ADC Input 2, 4-wire touch screen Lower Left, 5-wire touch screen Y+; multiplexed
with GPIO Port J3 (input only)
G2
H2
H3
AN2/LL/Y+/PJ3
AN3/LR/Y–/PJ0
AN4/WIPER/PJ1
I
I
I
ADC Input 3, 4-wire touch screen Upper Right, 5-wire touch screen Y–;
multiplexed with GPIO Port J0 (input only)
ADC Input 4, 5-wire touch screen Wiper input; multiplexed with GPIO Port J1
(input only)
F1
F3
E1
G3
G1
J3
AN5/PJ5/INT5
AN6/PJ7/INT7
AN7/PJ6/INT6
AN8/PJ4
I
ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5
ADC Input 6; multiplexed with GPIO Port J7 (input only) and External Interrupt 7
ADC Input 7; multiplexed with GPIO Port J6 (input only) and External Interrupt 6
ADC Input 8; multiplexed with GPIO Port J4 (input only)
I
I
I
I
AN9/PJ2
ADC Input 9; multiplexed with GPIO Port J2 (input only)
CTCLK/INT4/BATCNTL
I/O
Timer[2:0] External Clock input; muxed with External Int 4 and Battery Control
PA0/INT2/UARTRX2/
UARTIRRX2
General Purpose I/O Signal — Port A0; multiplexed with UART2 Received Serial
Data Input, UART2 Infrared Received Serial Data In, and External Interrupt 2
N1
M2
L3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PA1/INT3/UARTTX2/
UARTIRTX2
General Purpose I/O Signal — Port A1; multiplexed with UART2 Transmitted
Serial Data Output, UART2 Serial Transmit Data Out, and External Interrupt 3
PA2/CTCAP0A/
CTCMP0A
General Purpose I/O Signal — Port A2; multiplexed with Counter/Timer 0
Capture A input and Counter/Timer 0 Compare A output
PA3/CTCAP0B/
CTCMP0B
General Purpose I/O Signal — Port A3; multiplexed with Counter/Timer 0
Capture B input and Counter/Timer 0 Compare B output
M1
L2
PA4/CTCAP1A/
CTCMP1A
General Purpose I/O Signal — Port A4; multiplexed with Counter/Timer 1
Capture A input and Counter/Timer 1 Compare A output
PA5/CTCAP1B/
CTCMP1B
General Purpose I/O Signal — Port A5; multiplexed with Counter/Timer 1
Capture B input and Counter/Timer 1 Compare B output
L1
PA6/CTCAP2A/
CTCMP2A/SDA
General Purpose I/O Signal — Port A6; multiplexed with Counter/Timer 2
Capture A input, Counter/Timer 2 Compare A output, I2C Bus Data (open drain)
K3
K2
R2
R1
PA7/CTCAP2B/
CTCMP2B/SCL
General Purpose I/O Signal — Port A7; multiplexed with Counter/Timer 2
Capture B input, Counter/Timer 2 Compare B output, I2C Bus Clock (open drain)
PB0/nDACK/
nUARTCTS0
General Purpose I/O Signal — Port B0; multiplexed with DMA Acknowledge and
UART0 CTS
PB1/DREQ/
nUARTRTS0
General Purpose I/O Signal — Port B1; multiplexed with DMA Request and
UART0 RTS
General Purpose I/O Signal — Port B2; multiplexed with SSP Serial Frame Output
and I2S Frame Output
General Purpose I/O Signal — Port B3; multiplexed with SSP Clock and I2S Clock
P2
N3
PB2/SSPFRM/I2SWS
PB3/SSPCLK/I2SCLK
I/O
I/O
PB4/SSPRX/I2SRXD/
UARTRX1/
UARTIRRX1
General Purpose I/O Signal — Port B4; multiplexed with SSP Data In, I2S Data In,
UART1 Serial Data In, and UART1 Infrared Data In
M4
I/O
PB5/SSPTX/I2STXD/
UARTTX1/UARTIRTX1
General Purpose I/O Signal — Port B5; multiplexed with SSP Data Out, I2S Data
Out, UART1 Data Out, and UART1 IR Data Out
P1
N2
I/O
I/O
PB6/INT0/UARTRX0/
UARTIRRX0
General Purpose I/O Signal — Port B6; multiplexed with UART0 Infrared Received
Serial Data Input, UART0 Received Serial Data In, and External Interrupt 0
6
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LFBGA
LH79524/LH79525
NXP Semiconductors
Table 2. LH79524 Pin Descriptions (Cont’d)
SIGNAL NAME
TYPE
DESCRIPTION
PIN
PB7/INT1/UARTTX0/
UARTIRTX0
General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmit-
ted Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1.
M3
I/O
N7
R6
T5
P6
R5
T4
PC0/A16
PC1/A17
PC2/A18
PC3/A19
PC4/A20
PC5/A21
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signal — Port C0; multiplexed with Address A16
General Purpose I/O Signal — Port C1; multiplexed with Address A17
General Purpose I/O Signal — Port C2; multiplexed with Address A18
General Purpose I/O Signal — Port C3; multiplexed with Address A19
General Purpose I/O Signal — Port C4; multiplexed with Address A20
General Purpose I/O Signal — Port C5; multiplexed with Address A21
General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND
Flash Write Enable
P5
R4
PC6/A22/nFWE
PC7/A23/nFRE
I/O
I/O
General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND
Flash Read Enable
P15
P14
N13
T15
N12
T14
P12
T13
PD0/D8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signal — Port D0; multiplexed with Data D8
General Purpose I/O Signal — Port D1; multiplexed with Data D9
General Purpose I/O Signal — Port D2; multiplexed with Data D10
General Purpose I/O Signal — Port D3; multiplexed with Data D11
General Purpose I/O Signal — Port D4; multiplexed with Data D12
General Purpose I/O Signal — Port D5; multiplexed with Data D13
General Purpose I/O Signal — Port D6; multiplexed with Data D14
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PD6/D14
PD7/D15
I/O
I/O
General Purpose I/O Signal — Port D7; multiplexed with Data D15
PE0/LCDLP/
LCDHRLP
General Purpose I/O Signals — Port E0; multiplexed with LCD Line Pulse and
AD-TFT/HR-TFT Line Pulse
B12
D11
B13
C13
PE1/LCDDCLK
PE2/LCDPS
I/O
I/O
I/O
General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock
General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save
General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock
PE3/LCDCLS
PE4/LCDDSPLEN/
LCDREV
General Purpose I/O Signals — Port E4; multiplexed with LCD Panel Power
Enable and LCD Reverse
D12
B16
B15
I/O
I/O
I/O
PE5/LCDVDDEN
General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable
PE6/LCDVEEN/
LCDMOD
General Purpose I/O Signals — Port E6; multiplexed with LCD Analog Power
Enable and MOD
General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA End of
Transfer
D14
PE7/nWAIT/nDEOT
I/O
A8
A9
PF0/LCDVD6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6
General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7
General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8
General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9
General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10
General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11
General Purpose I/O Signals — Port F6; multiplexed with LCD Start Pulse Left
PF1/LCDVD7
B9
PF2/LCDVD8
C9
PF3/LCDVD9
B10
A11
B11
PF4/LCDVD10
PF5/LCDVD11
PF6/LCDEN/LCDSPL
General Purpose I/O Signals — Port F7; multiplexed with LCD Row Driver
Counter reset
A12
PF7/LCDFP/LCDSPS
I/O
A5
B6
A6
C7
B7
PG0/ETHERTXEN
PG1/ETHERTXCLK
PG2/LCDVD0
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signals — Port G0; multiplexed with Ethernet TX Enable
General Purpose I/O Signals — Port G1; multiplexed with Ethernet TX Clock
General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0
General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1
General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2
PG3/LCDVD1
PG4/LCDVD2
Preliminary data sheet
Rev. 01 — 16 July 2007
7
LH79524/LH79525
LFBGA
System-on-Chip
NXP Semiconductors
Table 2. LH79524 Pin Descriptions (Cont’d)
SIGNAL NAME
TYPE
DESCRIPTION
PIN
A7
C8
B8
PG5/LCDVD3
PG6/LCDVD4
PG7/LCDVD5
I/O
I/O
I/O
General Purpose I/O Signals — Port G5; multiplexed with LCD Video Data bit 3
General Purpose I/O Signals — Port G6; multiplexed with LCD Video Data bit 4
General Purpose I/O Signals — Port G7; multiplexed with LCD Video Data bit 5
General Purpose I/O Signals — Port H0; multiplexed with Ethernet Receive
Channel 3
C4
PH0/ETHERRX3
I/O
A3
B4
C5
PH1/ETHERRXDV
PH2/ETHERRXCLK
PH3/ETHERTXER
I/O
I/O
I/O
General Purpose I/O Signals — Port H1; multiplexed with Ethernet Data Valid
General Purpose I/O Signals — Port H2; multiplexed with Ethernet Receive Clock
General Purpose I/O Signals — Port H3; multiplexed with Ethernet Transmit Error
General Purpose I/O Signals — Port H4; multiplexed with Ethernet Transmit
Channel 0
D6
A4
B5
C6
D3
B1
PH4/ETHERTX0
PH5/ETHERTX1
PH6/ETHERTX2
PH7/ETHERTX3
PI0/ETHERMDC
PI1/ETHERMDIO
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signals — Port H5; multiplexed with Ethernet Transmit
Channel 1
General Purpose I/O Signals — Port H6; multiplexed with Ethernet Transmit
Channel 2
General Purpose I/O Signals — Port H7; multiplexed with Ethernet Transmit
Channel 3
General Purpose I/O Signals — Port I0; multiplexed with Ethernet Management
Data Clock
General Purpose I/O Signals — Port I1; multiplexed with Ethernet Management
Data I/O
I/O
I/O
B2
D4
C3
PI2/ETHERCOL
PI3/ETHERCRS
PI4/ETHERRXER
General Purpose I/O Signals — Port I2; multiplexed with Ethernet Collision Detect
I/O
I/O
General Purpose I/O Signals — Port I3; multiplexed with Ethernet Carrier Sense
General Purpose I/O Signals — Port I4; multiplexed with Ethernet Receive Error
General Purpose I/O Signals — Port I5; multiplexed with Ethernet Receive
Channel 0
A1
A2
B3
PI5/ETHERRX0
PI6/ETHERRX1
PI7/ETHERRX2
I/O
I/O
I/O
General Purpose I/O Signals — Port I6; multiplexed with Ethernet Receive Channel 1
General Purpose I/O Signals — Port I7; multiplexed with Ethernet Receive
Channel 2
R16
M12
T16
R15
P13
R14
R13
N11
C1
PK0/D16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signals — Port K0; multiplexed with data bit D16
General Purpose I/O Signals — Port K1; multiplexed with data bit D17
General Purpose I/O Signals — Port K2; multiplexed with data bit D18
General Purpose I/O Signals — Port K3; multiplexed with data bit D19
General Purpose I/O Signals — Port K4; multiplexed with data bit D20
General Purpose I/O Signals — Port K5; multiplexed with data bit D21
General Purpose I/O Signals — Port K6; multiplexed with data bit D22
General Purpose I/O Signals — Port K7; multiplexed with data bit D23
General Purpose I/O Signals — Port L0; multiplexed with LCD Video Data bit 14
General Purpose I/O Signals — Port L1; multiplexed with LCD Video Data bit 15
General Purpose I/O Signals — Port L2; multiplexed with LCD Video Data bit 12
General Purpose I/O Signals — Port L3; multiplexed with LCD Video Data bit 13
General Purpose I/O Signals — Port L4; multiplexed with Data bit D28
General Purpose I/O Signals — Port L5; multiplexed with Data bit D29
General Purpose I/O Signals — Port L6; multiplexed with Data bit D30
General Purpose I/O Signals — Port L7; multiplexed with Data bit D31
General Purpose I/O Signals — Port N0; multiplexed with Data bit D26
General Purpose I/O Signals — Port N1; multiplexed with Data bit D27
General Purpose I/O Signals — Port N2; multiplexed with Data bit D24
PK1/D17
PK2/D18
PK3/D19
PK4/D20
PK5/D21
PK6/D22
PK7/D23
PL0/LCDVD14
PL1/LCDVD15
PL2/LCDVD12
PL3/LCDVD13
PL4/D28
C2
A10
C10
C12
A14
B14
C14
C11
A13
R12
PL5/D29
PL6/D30
PL7/D31
PN0/D26
PN1/D27
PN2/D24
8
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LFBGA
LH79524/LH79525
NXP Semiconductors
Table 2. LH79524 Pin Descriptions (Cont’d)
SIGNAL NAME
TYPE
DESCRIPTION
PIN
P11
J2
PN3/D25
nRESETIN
nRESETOUT
XTALIN
XTALOUT
XTAL32IN
XTAL32OUT
CLKOUT
nTRST
I/O
I
General Purpose I/O Signals — Port N3; multiplexed with Data bit D25
Reset Input
H1
O
I
Reset Output
C16
C15
D16
D15
K1
Crystal Input
O
I
Crystal Output
32.768 kHz Crystal Oscillator Input
32.768 kHz Crystal Oscillator Output
Clock Out (selectable from the internal bus clock or 32.768 kHz crystal)
JTAG Test Reset Input
O
O
I
D2
P4
TMS
I
JTAG Test Mode Select Input
T3
TCK
I
JTAG Test Clock Input
T1
TDI
I
JTAG Test Serial Data Input
P3
TDO
O
I
JTAG Test Data Serial Output
T2
TEST1
Tie HIGH for Normal Operation; pull LOW to enable Embedded ICE Debugging
Tie HIGH for Normal Operation; pull HIGH to enable Embedded ICE Debugging
Linear Regulator Enable
R3
TEST2
I
E3
LINREGEN
I
D5, E4,
E5,H13, VDDC
N5
Power Core Power Supply
Ground Core GND
D10, F4,
VSSC
J13, N4
D7, D8,
D9, F13,
G4,
G13,H4,
J4, K4,
VDD
Power Input/Output Power Supply
K13, L4,
N6, N8,
N9, N10
E12,G8,
G9, H7,
H8, H9,
H10, J7, VSS
J8, J9,
Ground Input/Output GND
J10, K8,
K9, M5
D1
F16
E16
J1
VDDA0
VDDA1
VDDA2
VSSA0
VSSA1
VSSA2
Power Analog Power Supply for Analog-to-Digital Converter
Power Analog Power Supply for the USB PLL
Power Analog Power Supply for System PLL
Ground Analog GND for Analog-to-Digital Converter
Ground Analog GND for the USB PLL
F15
E15
Ground Analog GND for System PLL
Preliminary data sheet
Rev. 01 — 16 July 2007
9
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Table 3. LH79524 Numerical Pin List
Table 3. LH79524 Numerical Pin List (Cont’d)
LFBGA FUNCTION
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
LFBGA FUNCTION
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
NOTES
NOTES
NO.
AT RESET
NO.
AT RESET
A1
A2
PI5
PI6
ETHERRX0
ETHERRX1
ETHERRXDV
ETHERTX1
ETHERTXEN
LCDVD0
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
1
1
1
1
1
1
1
2
1
1
1
3
3
2
1
1
1
1
1
1
1
2
2
1
1
1
1
C13
C14
C15
C16
D1
PE3
PL7
LCDCLS
D31
8 mA
8 mA
1
1
4
5
A3
PH1
PH5
PG0
PG2
PG5
PF0
PF1
PL2
XTALOUT
XTALIN
VDDA0
nTRST
PI0
A4
A5
A6
D2
2, 6
1
A7
LCDVD3
D3
ETHERMDC
ETHERCRS
8 mA
8 mA
A8
LCDVD6
D4
PI3
1
A9
LCDVD7
D5
VDDC
PH4
A10
A11
A12
A13
A14
A15
A16
B1
LCDVD12
LCDVD11
LCDFP/LCDSPS
D27
D6
ETHERTX0
8 mA
1
PF5
PF7
PN1
PL5
D7
VDD
D8
VDD
D9
VDD
D29
D10
D11
VSSC
PE1
USBDP
USBDN
PI1
LCDDCLK
8 mA
8 mA
1
1
LCDDSPLEN/
LCDREV
D12
PE4
ETHERMDIO
ETHERCOL
ETHERRX2
ETHERRXCLK
ETHERTX2
ETHERTXCLK
LCDVD2
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
D13
D14
D15
D16
E1
DQM0
PE7
8 mA
8 mA
B2
PI2
nWAIT/nDEOT
PJ6/INT6
2, 6
4
B3
PI7
XTAL32OUT
XTAL32IN
AN7
B4
PH2
PH6
PG1
PG4
PG7
PF2
PF4
PF6
PE0
PE2
PL6
5
B5
B6
E2
AN0/UL/X+
LINREGEN
VDDC
B7
E3
B8
LCDVD5
E4
B9
LCDVD8
E5
VDDC
B10
B11
B12
B13
B14
LCDVD10
E12
E13
E14
E15
E16
F1
VSS
LCDEN/LCDSPL
LCDLP/LCDHRLP
LCDPS
DQM1
8 mA
8 mA
DQM2
VSSA2
VDDA2
AN5
D30
LCDVEEN/
LCDMOD
B15
PE6
8 mA
1
PJ5/INT5
PJ7/INT7
B16
C1
PE5
PL0
PL1
PI4
LCDVDDEN
LCDVD14
LCDVD15
ETHERRXER
ETHERRX3
ETHERTXER
ETHERTX3
LCDVD1
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
1
1
1
1
1
1
2
1
1
1
F2
AN1/UR/X-
AN6
F3
C2
F4
VSSC
C3
F13
F14
F15
F16
G1
VDD
C4
PH0
PH3
PH7
PG3
PG6
PF3
PL3
PN0
PL4
SDCLK
VSSA1
VDDA1
AN9
12 mA
C5
C6
C7
PJ2
C8
LCDVD4
G2
AN2/LL/Y+ PJ3
C9
LCDVD9
G3
AN8
VDD
VSS
VSS
PJ4
C10
C11
C12
LCDVD13
D26
G4
G8
D28
G9
10
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Table 3. LH79524 Numerical Pin List (Cont’d)
Table 3. LH79524 Numerical Pin List (Cont’d)
LFBGA FUNCTION
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
LFBGA FUNCTION
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
NOTES
NOTES
NO.
AT RESET
NO.
AT RESET
G13
G14
G15
G16
H1
VDD
DQM3
L4
VDD
D2
8 mA
8 mA
8 mA
8 mA
L13
L14
L15
L16
8 mA
8 mA
8 mA
8 mA
1
SDCKE
nCS3
nCS1
nCS0
PM3
nDCS0
PM1
PM0
nRESETOUT
H2
AN3/LR/Y- PJ0
AN4/WIPER PJ1
VDD
CTCAP0B/
CTCMP0B
M1
M2
M3
PA3
PA1
PB7
8 mA
8 mA
8 mA
1, 6
1, 6
1, 6
H3
INT3/UARTTX2/
UARTIRTX2
H4
H7
VSS
INT1/UARTTX0/
UARTIRTX0
H8
VSS
H9
VSS
SSPRX/I2SRXD/
UARTRX1/
UARTIRRX1
M4
PB4
8 mA
2
H10
H13
H14
H15
H16
J1
VSS
VDDC
M5
VSS
PK1
D6
nDCS1
nRAS
8 mA
8 mA
8 mA
M12
M13
M14
M15
M16
D17
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
1
nCAS
D3
VSSA0
nRESETIN
D0
J2
2, 6
2, 6
nCS2
PM2
J3
CTCLK
VDD
INT4/BATCNTL
8 mA
INT2/UARTRX2/
UARTIRRX2
N1
N2
PA0
PB6
8 mA
1, 6
J4
J7
VSS
INT0/UARTRX0/
UARTIRRX0
8 mA
8 mA
1, 6
1
J8
VSS
J9
VSS
N3
N4
PB3
VSSC
VDDC
VDD
PC0
VDD
VDD
VDD
PK7
PD4
PD2
D7
SSPCLK/I2SCLK
J10
J13
J14
J15
J16
K1
VSS
VSSC
nBLE1
nBLE0
nWE
N5
PM5
PM4
8 mA
8 mA
8 mA
8 mA
N6
N7
A16
8 mA
1
N8
CLKOUT
N9
CTCAP2B/
CTCMP2B/SCL
N10
N11
N12
N13
N14
N15
N16
K2
K3
PA7
PA6
8 mA
8 mA
2, 6
2, 6
D23
D12
D10
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
1
1
1
CTCAP2A/
CTCMP2A/SDA
K4
K8
VDD
VSS
D4
K9
VSS
D1
K13
K14
K15
K16
VDD
SSPTX/I2STXD/
UARTTX1/
UARTIRTX1
nOE
8 mA
8 mA
8 mA
P1
PB5
8 mA
1
2
nBLE3
nBLE2
PM7
PM6
P2
P3
P4
P5
P6
P7
PB2
TDO
TMS
PC6
PC3
A14
SSPFRM/I2SWS
8 mA
4 mA
CTCAP1B/
CTCMP1B
L1
L2
L3
PA5
PA4
PA2
8 mA
8 mA
8 mA
1, 6
1, 6
1, 6
2, 6
1
CTCAP1A/
CTCMP1A
A22/nFWE
A19
8 mA
8 mA
8 mA
1
CTCAP0A/
CTCMP0A
Preliminary data sheet
Rev. 01 — 16 July 2007
11
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Table 3. LH79524 Numerical Pin List (Cont’d)
Table 3. LH79524 Numerical Pin List (Cont’d)
LFBGA FUNCTION
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
LFBGA FUNCTION
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
NOTES
NOTES
NO.
AT RESET
NO.
AT RESET
PC5
PC2
A15
A12
A9
T4
A21
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
P8
A11
A6
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
T5
A18
P9
T6
P10
P11
P12
P13
P14
P15
P16
A3
T7
PN3
PD6
PK4
PD1
PD0
D5
D25
1
1
1
1
1
1
T8
D14
D20
D9
T9
A8
T10
T11
T12
T13
T14
T15
T16
A5
A2
D8
A0
PD7
PD5
PD3
PK2
D15
D13
D11
D18
1
1
1
1
DREQ/
nUARTRTS0
R1
R2
PB1
PB0
8 mA
8 mA
2
2
nDACK/
nUARTCTS0
R3
R4
TEST2
PC7
PC4
PC1
A13
A10
A7
2, 6
1
NOTES:
A23/nFRE
A20
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1. Internal pull-down. The internal pullup and pulldown resistance
on all digital I/O pins is 50KΩ.
R5
1
2. Internal pull-up. The internal pullup and pulldown resistance on all
digital I/O pins is 50KΩ.
3. USB Inputs/outputs are tristated.
4. Output is for crystal oscillator only, no drive capability.
5. Crystal Oscillator Inputs should be driven to a maximum of
1.8 V 10%.
R6
A17
1
R7
R8
R9
R10
R11
R12
R13
R14
A4
6. Input with Schmitt Trigger.
7. Output Drive Values are MAX. See ‘DC Specifications’.
8. All unused analog pins, and XTAL32IN (if unused) should be tied
to ground through a 33KΩ resistor.
A1
PN2
PK6
PK5
D24
D22
D21
1
1
1
Table 4. TESTx PIN FUNCTION
R15
R16
T1
PK3
PK0
D19
D16
8 mA
8 mA
1
MODE
Embedded ICE
Normal
TEST1
TEST2
nBLE0
1
0
1
1
1
1
x
TDI
2, 6
2, 6
2, 6
T2
TEST1
TCK
T3
12
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Table 5. LH79525 Pin Descriptions
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
80
79
A0
A1
78
A2
77
A3
76
A4
74
A5
73
A6
72
A7
O
External Address Bus
71
A8
70
A9
69
A10
67
A11
65
A12
63
A13
62
A14
61
A15
99
D0
98
D1
97
D2
96
D3
I/O
External Data Bus
95
D4
94
D5
93
D6
91
D7
117
116
119
118
115
114
113
112
104
103
102
100
110
109
106
111
130
131
11
SDCLK
SDCKE
DQM0
DQM1
nDCS0
nDCS1
nRAS
nCAS
nCS0/PM0
nCS1/PM1
nCS2/PM2
nCS3/PM3
nBLE0/PM4
nBLE1/PM5
nOE
O
O
SDRAM Clock
SDRAM Clock Enable
O
Data Mask Output to SDRAMs
O
O
O
O
SDRAM Chip Select
SDRAM Chip Select
Row Address Strobe
Column Address Strobe
O
Static Memory Chip Select; multiplexed with GPO Port M[3:0]
Static Memory Byte Lane Enable / Byte Write Enable; multiplexed with
GPIO Port M[5:4]
O
O
O
I/O
I/O
I
Static Memory Output Enable
nWE
Static Memory Write Enable
USBDN
USBDP
AN0/UL/X+
AN1/UR/X–
USB Data Negative (Differential Pair output, single ended and Differential input)
USB Data Positive (Differential Pair output, single ended and Differential input)
ADC Input 0, 4 wire touch screen Upper Left, 5 wire touch screen X+
ADC Input 1, 4 wire touch screen Upper Right, 5 wire touch screen X–
14
I
ADC Input 2, 4 wire touch screen Lower Left, 5 wire touch screen Y+; multiplexed with
GPIO Port J3 (input only)
17
AN2/LL/Y+/PJ3
I
Preliminary data sheet
Rev. 01 — 16 July 2007
13
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Table 5. LH79525 Pin Descriptions (Cont’d)
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
ADC Input 3, 4 wire touch screen Upper Right, 5 wire touch screen Y–; multiplexed
with GPIO Port J0 (input only)
20
AN3/LR/Y–/PJ0
I
19
15
12
13
16
18
AN4/WIPER/PJ1
AN5/PJ5/INT5
AN6/PJ7/INT7
AN7/PJ6/INT6
AN8/PJ4
I
I
I
I
I
I
ADC Input 4, 5 wire touch screen Wiper input; multiplexed with Port J1 (input only)
ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5
ADC Input 6; multiplexed with GPIO Port J7 (input only) and External Interrupt 7
ADC Input 7; multiplexed with GPIO Port J6 (input only) and External Interrupt 6
ADC Input 8; multiplexed with GPIO Port J4 (input only)
AN9/PJ2
ADC Input 9; multiplexed with GPIO Port J2 (input only)
CTCLK/INT4/
BATCNTL
25
36
35
34
32
31
30
29
28
44
43
42
41
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Timer[2:0] External Clock input; multiplexed with Battery Control and Interrupt 4
PA0/UARTRX2/
UARTIRRX2/INT2
General Purpose I/O Signal — Port A0; multiplexed with UART2 Received Serial
Data Input, UART2 Infrared Received Serial Data In, and External Interrupt 2
PA1/UARTTX2/
UARTIRRX2/INT3
General Purpose I/O Signal — Port A1; multiplexed with UART2 Transmitted
Serial Data Output, UART2 Serial Transmit Data Out, and External Interrupt 3
PA2/CTCAP0A/
CTCMP0A
General Purpose I/O Signal — Port A2; multiplexed with Counter/Timer 0 Capture A
input and Counter/Timer 0 Compare A output
PA3/CTCAP0B/
CTCMP0B
General Purpose I/O Signal — Port A3; multiplexed with Counter/Timer 0 Capture B
input and Counter/Timer 0 Compare B output
PA4/CTCAP1A/
CTCMP1A
General Purpose I/O Signal — Port A4; multiplexed with Counter/Timer 1 Capture A
input and Counter/Timer 1 Compare A output
PA5/CTCAP1B/
CTCMP1B
General Purpose I/O Signal — Port A5; multiplexed with Counter/Timer 1 Capture B
input and Counter/Timer 1 Compare B output
PA6/CTCAP2A/
CTCMP2A/SDA
General Purpose I/O Signal — Port A6; multiplexed with Counter/Timer 2 Capture A
input, Counter/Timer 2 Compare A output, and I2C Bus Data (open drain)
PA7/CTCAP2B/
CTCMP2B/SLC
General Purpose I/O Signal — Port A7; multiplexed with Counter/Timer 2 Capture B
input, Counter/Timer 2 Compare B output, and I2C Bus Clock (open drain)
PB0/nDACK/
nUARTCTS0
General Purpose I/O Signal — Port B0; multiplexed with DMA Acknowledge and
UART0 CTS
PB1/DREQ/
nUARTRTS0
General Purpose I/O Signal — Port B1; multiplexed with DMA Request and
UART0 RTS
PB2/SSPFRM/
I2SWS
General Purpose I/O Signal — Port B2; multiplexed with SSP Serial Frame Output
and I2S Frame Output
PB3/SSPCLK/
I2SCLK
General Purpose I/O Signal — Port B3; multiplexed with SSP Clock and I2S Clock
PB4/SSPRX/
I2SRXD/UARTRX1/
UARTIRRX1
General Purpose I/O Signal — Port B4; multiplexed with SSP Data In, I2S Data In,
UART1 Serial Data In, and UART1 Infrared Data In
40
39
38
37
I/O
I/O
I/O
I/O
PB5/SSPTX/
I2STXD/UARTTX1/
UARTIRTX1
General Purpose I/O Signal — Port B5; multiplexed with SSP Data Out, I2S Data Out,
UART1 Data Out, and UART1 IR Data Out
PB6/INT0/
UARTRX0/
UARTIRRX0
General Purpose I/O Signal — Port B6; multiplexed with UART0 Infrared Received
Serial Data Input, UART0 Received Serial Data In, and External Interrupt 0
PB7/INT1/
UARTTX0/
UARTIRTX0
General Purpose I/O Signal — Port B7; multiplexed with UART0 Infrared Transmitted
Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1
60
59
58
56
55
54
PC0/A16
PC1/A17
PC2/A18
PC3/A19
PC4/A20
PC5/A21
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signal — Port C0; multiplexed with Address A16
General Purpose I/O Signal — Port C1; multiplexed with Address A17
General Purpose I/O Signal — Port C2; multiplexed with Address A18
General Purpose I/O Signal — Port C3; multiplexed with Address A19
General Purpose I/O Signal — Port C4; multiplexed with Address A20
General Purpose I/O Signal — Port C5; multiplexed with Address A21
14
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Table 5. LH79525 Pin Descriptions (Cont’d)
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND
Flash Write Enable
53
PC6/A22/nFWE
PC7/A23/nFRE
I/O
I/O
General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND
Flash Read Enable
52
90
89
88
87
85
84
83
82
PD0/D8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signal — Port D0; multiplexed with Data D8
General Purpose I/O Signal — Port D1; multiplexed with Data D9
General Purpose I/O Signal — Port D2; multiplexed with Data D10
General Purpose I/O Signal — Port D3; multiplexed with Data D11
General Purpose I/O Signal — Port D4; multiplexed with Data D12
General Purpose I/O Signal — Port D5; multiplexed with Data D13
General Purpose I/O Signal — Port D6; multiplexed with Data D14
General Purpose I/O Signal — Port D7; multiplexed with Data D15
PD1/D9
PD2/D10
PD3/D11
PD4/D12
PD5/D13
PD6/D14
PD7/D15
PE0/LCDLP/
LCDHRLP
General Purpose I/O Signals — Port E0; multiplexed with LCD Line Pulse and
AD-TFT/HR-TFT Line Pulse
141
I/O
139
138
137
PE1/LCDDCLK
PE2/LCDPS
I/O
I/O
I/O
General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock
General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save
General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock
PE3/LCDCLS
PE4/LCDDSPLEN/
LCDREV
General Purpose I/O Signals — Port E4; multiplexed with LCD Panel Power
Enable and LCD Reverse
136
134
133
I/O
I/O
I/O
PE5/LCDVDDEN
General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable
PE6LCDVEEN/
LCDMOD
General Purpose I/O Signals — Port E6; multiplexed with LCD Analog Power
Enable and MOD
General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA
End of Transfer
120
PE7/nWAIT/nDEOT
I/O
153
151
149
147
146
145
PF0/LCDVD6
PF1/LCDVD7
PF2/LCDVD8
PF3/LCDVD9
PF4/LCDVD10
PF5/LCDVD11
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6
General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7
General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8
General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9
General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10
General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11
PF6/LCDEN/
LCDSPL
143
142
I/O
I/O
General Purpose I/O Signals — Port F6; multiplexed with LCD Start Pulse Left
General Purpose I/O Signals — Port F7; multiplexed with LCD Row Driver Counter reset
PF7/LCDFP/
LCDSPS
162
161
159
158
157
156
155
154
171
170
169
167
166
165
PG0/ETHERTXEN
PG1/ETHERTXCLK
PG2/LCDVD0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General Purpose I/O Signals — Port G0; multiplexed with Ethernet Transmit Enable
General Purpose I/O Signals — Port G1; multiplexed with Ethernet Clock
General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0
General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1
General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2
General Purpose I/O Signals — Port G5; multiplexed with LCD Video Data bit 3
General Purpose I/O Signals — Port G6; multiplexed with LCD Video Data bit 4
General Purpose I/O Signals — Port G7; multiplexed with LCD Video Data bit 5
General Purpose I/O Signals — Port H0; multiplexed with Ethernet Receive Channel 3
General Purpose I/O Signals — Port H1; multiplexed with Ethernet Data Valid
General Purpose I/O Signals — Port H2; multiplexed with Ethernet Receive Clock
General Purpose I/O Signals — Port H3; multiplexed with Ethernet Transmit Error
General Purpose I/O Signals — Port H4; multiplexed with Ethernet Transmit Channel 0
General Purpose I/O Signals — Port H5; multiplexed with Ethernet Transmit Channel 1
PG3/LCDVD1
PG4/LCDVD2
PG5/LCDVD3
PG6/LCDVD4
PG7/LCDVD5
PH0/ETHERRX3
PH1/ETHERRXDV
PH2/ETHERRXCLK
PH3/ETHERTXER
PH4/ETHERTX0
PH5/ETHERTX1
164
PH6/ETHERTX2
I/O
General Purpose I/O Signals — Port H6; multiplexed with Ethernet Transmit Channel 2
Preliminary data sheet
Rev. 01 — 16 July 2007
15
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Table 5. LH79525 Pin Descriptions (Cont’d)
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
163
PH7/ETHERTX3
I/O
General Purpose I/O Signals — Port H7; multiplexed with Ethernet Transmit Channel 3
General Purpose I/O Signals — Port I0; multiplexed with Ethernet Management
Data Clock
4
PI0/ETHERMDC
I/O
2
PI1/ETHERMDIO
PI2/ETHERCOL
PI3/ETHERCRS
PI4/ETHERRXER
PI5/ETHERRX0
PI6/ETHERRX1
PI7/ETHERRX2
nRESETIN
nRESETOUT
XTALIN
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General Purpose I/O Signals — Port I1; multiplexed with Ethernet Management Data I/O
General Purpose I/O Signals — Port I2; multiplexed with Ethernet Collision Detect
General Purpose I/O Signals — Port I3; multiplexed with Ethernet Carrier Sense
General Purpose I/O Signals — Port I4; multiplexed with Ethernet Receive Error
General Purpose I/O Signals — Port I5; multiplexed with Ethernet Receive Channel 0
General Purpose I/O Signals — Port I6; multiplexed with Ethernet Receive Channel 1
General Purpose I/O Signals — Port I7; multiplexed with Ethernet Receive Channel 2
Reset Input
1
176
175
174
173
172
24
22
O
I
Reset Output
127
128
125
126
23
Crystal Input, or external clock input
XTALOUT
XTAL32IN
XTAL32OUT
CLKOUT
O
I
Crystal Output
32.768 kHz Crystal Oscillator Input, or external clock input,
32.768 kHz Crystal Oscillator Output
O
O
I
Clock Out (selectable from the internal bus clock or 32.768 MHz)
JTAG Test Reset Input
8
nTRST
50
TMS
I
JTAG Test Mode Select Input
51
TCK
I
JTAG Test Clock Input
46
TDI
I
JTAG Test Serial Data Input
45
TDO
O
I
JTAG Test Data Serial Output
47
TEST1
Tie HIGH for Normal Operation; pull LOW to enable embedded ICE Debugging
Tie HIGH for Normal Operation; pull HIGH to enable embedded ICE Debugging
Linear Regulator Enable (Requires pull-up. See User’s Guide)
48
TEST2
I
9
LINREGEN
I
6, 66,
107, 150
VDDC
VSSC
Power Core Power Supply
Ground Core GND
7, 64,
105,148
3, 26, 33,
57, 75,
86, 101, VDD
129, 135,
Power Input/Output Power Supply
Ground Input/Output GND
144, 160
5, 27, 49,
68, 81,
92, 108, VSS
132, 140,
152, 168
10
122
123
21
VDDA0
Power Analog Power Supply for Analog-to-Digital Converter
Power Analog Power Supply for the USB PLL
Power Analog Power Supply for System PLL
Ground Analog GND for Analog-to-Digital Converter
Ground Analog GND for the USB PLL
VDDA1
VDDA2
VSSA0
VSSA1
VSSA2
121
124
Ground Analog GND for System PLL
Table 6. LH79525 Numerical Pin List
Table 6. LH79525 Numerical Pin List (Cont’d)
PIN FUNCTION
NO. AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
PIN FUNCTION
NO. AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
NOTES
NOTES
2
PI1
ETHERMDIO
8 mA
2
1
PI2
ETHERCOL
8 mA
1
16
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Table 6. LH79525 Numerical Pin List (Cont’d)
Table 6. LH79525 Numerical Pin List (Cont’d)
PIN FUNCTION
NO. AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
PIN FUNCTION
NO. AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
NOTES
NOTES
3
4
VDD
PI0
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
TEST1
TEST2
VSS
TMS
TCK
PC7
PC6
PC5
PC4
PC3
VDD
PC2
PC1
PC0
A15
A14
A13
VSSC
A12
VDDC
A11
VSS
A10
A9
2, 3
2, 3
ETHERMDC
8 mA
1
5
VSS
6
VDDC
VSSC
2, 3
2, 3
1
7
8
nTRST
LINREGEN
VDDA0
AN0/UL/X+
AN6
2, 3
A23/nFRE
8 mA
8 mA
8 mA
8 mA
8 mA
9
A22/nFWE
A21
1
10
11
12
13
14
15
16
17
18
1
A20
1
PJ7/INT7
PJ6/INT6
A19
1
AN7
AN1/UR/X-
AN5
A18
A17
A16
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
PJ5/INT5
PJ4
AN8
AN2/LL/Y+ PJ3
AN9 PJ2
19 AN4/WIPER PJ1
20
21
AN3/LR/Y- PJ0
VSSA0
8 mA
8 mA
22 nRESETOUT
8 mA
8 mA
23
24
25
26
27
CLKOUT
nRESETIN
CTCLK
VDD
2, 3
2, 3
INT4/BATCNTL
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
VSS
A8
CTCAP2B/CTCMP2B/
SCL
A7
28
29
PA7
PA6
8 mA
8 mA
2, 3
2, 3
A6
CTCAP2A/CTCMP2A/
SDA
A5
VDD
A4
30
31
32
33
34
PA5
PA4
PA3
VDD
PA2
CTCAP1B/CTCMP1B
CTCAP1A/CTCMP1A
CTCAP0B/CTCMP0B
8 mA
8 mA
8 mA
1, 3
1, 3
1, 3
8 mA
8 mA
8 mA
8 mA
8 mA
A3
A2
A1
CTCAP0A/CTCMP0A
8 mA
8 mA
1, 3
1, 3
A0
INT3/UARTTX2/
UARTIRTX2
35
36
37
38
39
40
PA1
PA0
PB7
PB6
PB5
PB4
VSS
PD7
PD6
PD5
PD4
VDD
PD3
PD2
PD1
PD0
D7
D15
D14
D13
D12
8 mA
8 mA
8 mA
8 mA
1
1
1
1
INT2/UARTRX2/
UARTIRRX2
8 mA
8 mA
8 mA
8 mA
8 mA
1, 3
1, 3
1, 3
1
INT1/UARTTX0/
UARTIRTX0
INT0/UARTRX0/
UARTIRRX0
D11
D10
D9
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
1
1
SSPTX/I2STXD/
UARTTX1/UARTIRTX1
SSPRX/I2SRXD/
UARTRX1/UARTIRRX1
2
D8
41
42
43
44
45
PB3
PB2
PB1
PB0
TDO
SSPCLK/I2SCLK
SSPFRM/I2SWS
8 mA
8 mA
8 mA
8 mA
4 mA
1
2
2
2
VSS
D6
8 mA
8 mA
8 mA
8 mA
1
1
1
1
DREQ/nUARTRTS0
nDACK/nUARTCTS0
D5
D4
D3
46
TDI
2, 3
Preliminary data sheet
Rev. 01 — 16 July 2007
17
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Table 6. LH79525 Numerical Pin List (Cont’d)
Table 6. LH79525 Numerical Pin List (Cont’d)
PIN FUNCTION
NO. AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
PIN FUNCTION
NO. AT RESET
MULTIPLEXED
FUNCTION(S)
OUTPUT
DRIVE
NOTES
NOTES
97
D2
D1
8 mA
8 mA
8 mA
8 mA
1
1
1
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
PF4
PF3
VSSC
PF2
VDDC
PF1
VSS
PF0
PG7
PG6
PG5
PG4
PG3
PG2
VDD
PG1
PG0
PH7
PH6
PH5
PH4
PH3
VSS
PH2
PH1
PH0
PI7
LCDVD10
8 mA
8 mA
2
2
98
LCDVD9
LCDVD8
LCDVD7
99
D0
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
nCS3
VDD
PM3
8 mA
8 mA
2
1
nCS2
nCS1
nCS0
VSSC
nOE
PM2
PM1
PM0
8 mA
8 mA
8 mA
LCDVD6
LCDVD5
LCDVD4
LCDVD3
LCDVD2
LCDVD1
LCDVD0
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
1
1
1
1
8 mA
VDDC
VSS
nBLE1
nBLE0
nWE
PM5
PM4
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
12 mA
8 mA
8 mA
8 mA
nCAS
nRAS
nDCS1
nDCS0
SDCKE
SDCLK
DQM1
DQM0
PE7
ETHERTXCLK
ETHERTXEN
ETHERTX3
ETHERTX2
ETHERTX1
ETHERTX0
ETHERTXER
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
1
1
1
1
nWAIT/nDEOT
2, 3
ETHERRXCLK
ETHERRXDV
ETHERRX3
ETHERRX2
ETHERRX1
ETHERRX0
ETHERRXER
ETHERCRS
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
1
1
1
1
1
1
1
1
VSSA1
VDDA1
VDDA2
VSSA2
XTAL32IN
PI6
5
6
5
6
PI5
126 XTAL32OUT
PI4
PI3
127
128
129
130
131
132
XTALIN
XTALOUT
VDD
USBDN
USBDP
VSS
4
4
LCDVEEN/
LCDMOD
NOTES:
133
PE6
8 mA
8 mA
1
1
1. Internal pull-down. The internal pullup and pulldown resistance
on all digital I/O pins is 50KΩ.
134
135
136
137
138
139
140
141
142
143
144
145
PE5
VDD
PE4
PE3
PE2
PE1
VSS
PE0
PF7
PF6
VDD
PF5
LCDVDDEN
2. Internal pull-up. The internal pullup and pulldown resistance on all
digital I/O pins is 50KΩ.
3. Input with Schmitt Trigger.
LCDDSPLEN/LCDREV
LCDCLS
8 mA
8 mA
8 mA
8 mA
1
1
1
1
4. USB Inputs/outputs are tristated.
5. Crystal Inputs should be driven to a maximum of 1.8 V 10%.
6. Output is for crystal oscillator only, no drive capability.
7. Output Drive Values shown are MAX. See ‘DC Specifications’.
8. All unused analog pins, and XTAL32IN (if unused) should be tied
to ground through a 33KΩ resistor.
LCDPS
LCDDCLK
LCDLP/LCDHRLP
LCDFP/LCDSPS
LCDEN/LCDSPL
8 mA
8 mA
8 mA
1
1
1
LCDVD11
8 mA
2
18
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Table 7. TESTx PIN FUNCTION
MODE
TEST1
TEST2
nBLE0
Embedded ICE
Normal
0
1
1
1
1
x
Table 8. LH79524 LCD Data Multiplexing
STN
TFT
LFBGA
BALL
NO.
LFBGA
BALL NAME
MONO 4-BIT
MONO 8-BIT
COLOR
COLOR
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
DUAL
PANEL
SINGLE
PANEL
C2
C1
C10
A10
A11
B10
C9
B9
LCDVD15
LCDVD14
LCDVD13
LCDVD12
LCDVD11
LCDVD10
LCDVD9
LCDVD8
LCDVD7
LCDVD6
LCDVD5
LCDVD4
LCDVD3
LCDVD2
LCDVD1
LCDVD0
MUSTN0
MUSTN0
MUSTN0
MUSTN0
MLSTN4
MUSTN6
MLSTN7
MLSTN6
MLSTN5
MLSTN3
MLSTN2
MLSTN1
MLSTN0
MUSTN7
MUSTN5
MUSTN4
MUSTN3
MUSTN2
MUSTN1
CUSTN0
CUSTN0
CLSTN4
CUSTN6
CLSTN7
CLSTN6
CLSTN5
CLSTN3
CLSTN2
CLSTN1
CLSTN0
CUSTN7
CUSTN5
CUSTN4
CUSTN3
CUSTN2
CUSTN1
INTENSITY
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED4
X
X
X
X
X
X
MUSTN6
CUSTN6
X
X
X
X
X
X
X
X
X
X
X
X
X
MLSTN3
MLSTN2
MLSTN1
MLSTN0
X
X
X
X
X
X
A9
X
X
X
A8
X
X
X
B8
X
MUSTN7
MUSTN5
MUSTN4
MUSTN3
MUSTN2
MUSTN1
CUSTN7
CUSTN5
CUSTN4
CUSTN3
CUSTN2
CUSTN1
C8
A7
X
X
X
X
RED3
B7
MUSTN3
MUSTN2
MUSTN1
MUSTN3
MUSTN2
MUSTN1
RED2
C7
A6
RED1
RED0
NOTES:
1. Recommended hookups for TFT 5:5:5 + Intensity and 5:6:5 are shown.
2. The Intensity bit is identically generated for all three colors.
3. Connect to the LSB of the Red, Green, and Blue inputs of a 6:6:6 panel.
4. CLSTN = Color Lower data bit for STN panel.
5. CUSTN = Color Upper data bit for STN panel.
6. MLSTN = Monochrome Lower data bit for STN panel.
7. MUSTN = Monochrome Upper data bit for STN panel.
Table 9. LH79525 LCD Data Multiplexing
STN MONO 4-BIT
PIN NO. PIN NAME
SINGLE PANEL DUAL PANEL
145
146
147
149
151
153
154
155
156
LCDVD11
LCDVD10
LCDVD9
LCDVD8
LCDVD7
LCDVD6
LCDVD5
LCDVD4
LCDVD3
MUSTN1
MUSTN0
MUSTN1
MUSTN0
MLSTN3
MLSTN2
MLSTN1
MLSTN0
Preliminary data sheet
Rev. 01 — 16 July 2007
19
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Table 9. LH79525 LCD Data Multiplexing
STN MONO 4-BIT
PIN NAME
PIN NO.
SINGLE PANEL DUAL PANEL
157
158
159
LCDVD2
LCDVD1
LCDVD0
MUSTN3
MUSTN2
MUSTN3
MUSTN2
TOUCH SCREEN
LCD
WIRELESS
ROUTER/
SWITCHER
ETHERNET
TRANSCEIVER
ETHERNET
MAC
STN/TFT,
AD-TFT
A/D
UART
FLASH
I2S
LH79524/LH79525
CODEC
SRAM or
SDRAM
A/D
UART
USB
GPIO
SSP
BOOT
ROM
SENSOR
ARRAY
1
4
7
2
5
8
0
3
6
9
#
SERIAL
EEPROM
*
KEY
MATRIX
LH79525-19A
Figure 4. LH79524/LH79525 Application Diagram Example
The LH79524/LH79525 MMU allows mapping Phys-
ical Memory (PA) addresses to virtual memory
addresses. This allows physical memory, which is
constrained by hardware to specific addresses, to be
reorganized at addresses identified by the user. These
user identified locations are called Virtual Addresses
(VA). When the MMU is enabled, Code and Data must
be built, loaded, and executed using Virtual Addresses
which the MMU translates to Physical Addresses. In
addition, the user may implement a memory protection
scheme by using the features of the MMU. Address
translation and memory protection services provided
by the MMU are controlled by the user. The MMU
is directly controlled through the System Control
Coprocessor, Coprocessor 15 (CP15). The MMU is
indirectly controlled by a Translation Table (TT) and
Page Tables (PT) prepared by the user and estab-
lished using a portion of physical memory dedicated by
the user to storing the TT and PT’s.
SYSTEM DESCRIPTIONS
ARM720T Processor
The LH79524/LH79525 microcontrollers feature
the ARM720T cached core with an Advanced High-Per-
formance Bus (AHB) interface. The ARM720T features:
• 32-bit ARM720T RISC Core
• 8 kB Cache
• MMU (Windows CE enabled)
The core processor for both is a member of the
ARM7T family of processors. For more information, see
the ARM document, ‘ARM720T (Rev 3) Technical
Reference Manual’, available on ARM’s website at
www.ARM.com.
20
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
External Memory Controller
An integrated External Memory Controller (EMC)
provides a glueless interface to external SDRAM, Low
Power SDRAM, Flash, SRAM, ROM, and burst ROM.
Three remap options for the physical memory are
selectable by software, as shown in Figure 5 through
Figure 8.
0xFFFFFFFF
0xFFFF1000
0xFFFF0000
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
RESERVED
ADVANCED PERIPHERAL BUS
PERIPHERALS
The EMC supports six banks of external memory. Two
chip selects for synchronous memory, and either two
(LH79525) or four (LH79524) static memory chip selects
are available. The static interface also includes two
(LH79525) or four (LH79524) byte lane enable signals.
0xFFFC0000
0xA0000000
RESERVED
BOOT ROM
0x80000000
0x60000000
0x40000000
16KB INTERNAL SRAM
EXTERNAL STATIC MEMORY
EXTERNAL SDRAM
EXTERNAL SDRAM nDCS0
REMAP = 01
0xFFFFFFFF
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
0xFFFF1000
0x20000000
0x00000000
RESERVED
0xFFFF0000
ADVANCED PERIPHERAL BUS
PERIPHERALS
0xFFFC0000
LH79525-16
RESERVED
0xA0000000
Figure 6. Memory Remap ‘01’
BOOT ROM
0x80000000
16KB INTERNAL SRAM
0x60000000
0xFFFFFFFF
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
EXTERNAL STATIC MEMORY
0x40000000
0xFFFF1000
0xFFFF0000
RESERVED
EXTERNAL SDRAM
0x20000000
ADVANCED PERIPHERAL BUS
PERIPHERALS
EXTERNAL SRAM nCS1
0x00000000
0xFFFC0000
0xA0000000
RESERVED
BOOT ROM
REMAP = 00
LH79525-15
Figure 5. Memory Remap ‘00’
0x80000000
0x60000000
0x40000000
16KB INTERNAL SRAM
EXTERNAL STATIC MEMORY
EXTERNAL SDRAM
INTERNAL SRAM
REMAP = 10
0x20000000
0x00000000
LH79525-17
Figure 7. Memory Remap ‘10’
Preliminary data sheet
Rev. 01 — 16 July 2007
21
LH79524/LH79525
System-on-Chip
NXP Semiconductors
• Supports Thin Film Transistor (TFT) color displays
• Programmable resolution up to 1,024 × 1,024
0xFFFFFFFF
• 15 gray-level mono, 3,375 color STN, and 64 k color
TFT support
ADVANCED HIGH-PERFORMANCE BUS
PERIPHERALS
0xFFFF1000
0xFFFF0000
• 1, 2, or 4 bits-per-pixel (BPP) for monochrome STN
RESERVED
• 1-, 2-, 4-, or 8-BPP palettized color displays for color
STN and TFT (1-, 2-, or 4-bit only on LH79525)
ADVANCED PERIPHERAL BUS
PERIPHERALS
0xFFFC0000
0xA0000000
• True-color non-palettized, for color STN and TFT
• Programmable timing for different display panels
• 256-entry, 16-bit palette fast-access RAM
• Frame, line and pixel clock signals
RESERVED
BOOT ROM
0x80000000
0x60000000
0x40000000
16KB INTERNAL SRAM
EXTERNAL STATIC MEMORY
EXTERNAL SDRAM
EXTERNAL SRAM nCS0
REMAP = 11
• AC bias signal for STN or data enable signal for
TFT panels
• Patented grayscale algorithm
• Interrupt Generation Events
0x20000000
0x00000000
• Dual 16-deep programmable 32-bit wide FIFOs for
buffering incoming data.
ADVANCED LCD INTERFACE
The Advanced LCD Interface (ALI) allows for direct
connection to ultra-thin panels that do not include a tim-
ing ASIC. It converts TFT signals from the Color LCD
controller to provide the proper signals, timing and levels
for direct connection to a panel’s Row and Column driv-
ers for AD-TFT, HR-TFT, or any technology of panel that
allows for a connection of this type. The Advanced LCD
Interface peripheral also provides a bypass mode that
allows the LH79524/LH79525 to interface to the built-in
timing ASIC in standard TFT and STN panels.
LH79525-18
Figure 8. Memory Remap ‘11’
DMA Controller
The DMA Controller provides support for DMA-capa-
ble peripherals. The LCD controller uses its own DMA
port, connecting directly to memory for retrieving dis-
play data.
• Simultaneous servicing of up to 4 data streams
• Three transfer modes are supported:
– Memory to Memory
Synchronous Serial Port (SSP)
The SSP is a master or slave interface for synchro-
nous serial communication with master or slave periph-
eral devices that support protocols for Motorola SPI,
National Semiconductor MICROWIRE, or Texas Instru-
ments Synchronous Serial Interface.
– Peripheral to Memory
– Memory to Peripheral
• Identical source and destination capabilities
• Transfer Size Programmable (byte, half-word, word)
• Burst Size Programmable
• Address Increment or Address Freeze
• Transfer Error interrupt for each stream
• 16-word FIFO array with pack and unpack logic
• Master or slave operation
• Programmable clock rate
• Separate transmit FIFO and receive FIFO buffers, 16
bits wide, 8 locations deep
Handles all combinations of byte, half-word or word
transfers from input to output.
• DMA for transmit and receive
• Programmable interface protocols: Motorola SPI,
National Semiconductor MICROWIRE, or Texas
Instruments Synchronous Serial Port
Color LCD Controller (CLCDC)
The CLCDC provides all the necessary control and
drive signals to interface directly with a variety of color
and monochrome LCD panels.
• LH79524 has 16 LCD Data bits; LH79525 has 12
LCD Data bits.
• Supports single and dual scan color and mono-
chrome Super Twisted Nematic (STN) displays with
4- or 8-bit interfaces (LH79524 only)
• Programmable data frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive FIFO
and receive overrun interrupts
• Available internal loopback test mode.
22
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
interrupt vector logic with programmable priority for up
to 16 interrupt sources. This logic reduces the interrupt
response time for IRQ type interrupts compared to
solutions using software polling to determine the high-
est priority interrupt source. This significantly improves
the real-time capabilities of the LH79524/LH79525 in
embedded control applications.
Universal Asynchronous Receiver
Transmitter (UART)
The LH79524/LH79525 incorporates three UARTs.
UART0, UART1, and UART2 offer similar functionality
to the industry-standard 16C550. They perform serial-
to-parallel conversion on data received from a periph-
eral device and parallel-to-serial conversion on data
transmitted to the UART. The CPU reads and writes
data and control status information through the AMBA
APB interface. The transmit and receive paths are buff-
ered with internal FIFO memories that support pro-
grammable-service 'trigger levels', and overrun
protection. These FIFO memories enable up to 32
characters to be stored independently in both transmit
and receive modes.
• 20 internal and eight external interrupt sources
– Individually maskable
– Status accessible for software polling
• IRQ interrupt vector logic for up to 16 channels with
programmable priorities
• All of the interrupt channels, with the exception of the
Watchdog Timer interrupt, can be programmed to
generate:
• Programmable bits-per-character (5, 6, 7, or 8)
– FIQ interrupt request
– Non-vectored IRQ interrupt request (software to
poll IRQ source)
• Optional nine-bit mode to tag and recognize
characters as either data or address
• Nine-bit Transmit FIFO and 12-bit Receive FIFO
• Programmable FIFO trigger points
– Vectored IRQ interrupt request (up to 16 chan-
nels total)
• DMA support for UART0
• The Watchdog timer can only generate FIQ interrupt
requests
• Programmable IrDA SIR input/output for each UART
• External interrupt inputs programmable
– Edge triggered or level triggered
– Rising edge/active HIGH or falling edge/active
LOW
• Separate 16-byte transmit and receive FIFOs to
reduce CPU interrupts
• Programmable FIFO disabling for 1-byte depth
• Programmable baud rate generator
The 32 interrupt channels are shown in Table 10.
• Independent masking of transmit FIFO, receive
FIFO, receive timeout and modem status interrupts
Table 10. Interrupt Channels
• False start bit detection
• Line break generation and detection
CHANNEL
INTERRUPT SOURCE
• Fully-programmable serial interface characteristics:
– 5-, 6-, 7-, or 8-bit data word length
– Even-, odd-, or no-parity bit generation and
detection
0
1
WDT
Not Used
2
COMRX (used for debug)
COMTX (used for debug)
Counter/Timer0 Combined
Counter/Timer1 Combined
Counter/Timer2 Combined
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
RTC_ALARM
3
– 1 or 2 stop bit generation
4
• IrDA SIR Encode/Decode block, providing:
– Programmable use of IrDA SIR or UART input/
output
5
6
– Supports data rates up to 115.2 kbit/s half-duplex
– Programmable internal clock generator, allowing
division of the Reference clock in increments of 1
to 512 for low-power mode bit durations.
– Loopback for testing
7
8
9
10
11
12
13
14
15
16
17
Vectored Interrupt Controller (VIC)
The Vectored Interrupt Controller combines the
interrupt request signals from 20 internal and eight
external interrupt sources and applies them, after
masking and prioritization, to the IRQ and FIQ interrupt
inputs of the ARM7TDMI processor core.
ACD TSIRQ Combined
ADC Brown Out INTR
The Interrupt Controller incorporates a hardware
Preliminary data sheet
Rev. 01 — 16 July 2007
23
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Table 10. Interrupt Channels (Cont’d)
Table 11. Maximum Clock Speeds
CHANNEL
INTERRUPT SOURCE
ADC Pen IRQ
FREQUENCY
(MAX.)
NAME
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Oscillator Clock (CLK OSC)
PLL System Clock (CLK PLL)
PLL USB Clock
20.0 MHz
304.819 MHz
48.0 MHz
CLCD Combined Interrupt
DMA Stream 0
DMA Stream 1
32.768 kHz Oscillator Clock
AHB Clock (HCLK)
32.768 kHz
50.803 MHz
76.205 MHz
50.803 MHz
50.803 MHz
50.803 MHz
DMA Stream 2
DMA Stream 3
SSP I2S Interrupt
Ethernet Interrupt
USB Interrupt
AHB Fast CPU Clock (FCLK CPU)
Ethernet Clock
DMA Clock
External Memory Controller Clock
UART 0 Interrupt
UART 1 Interrupt
UART 2 Interrupt
USB DMA Interrupt
I2C Interrupt
SSP Clock
50.803 MHz
50.803 MHz
20.0 MHz
1.0 Hz
CLCD Clock
UART[2:0] Clock
RTC Clock
Reset, Clock, and Power Controller
(RCPC)
Table 12. Clock Activity for Different Power Modes
DEVICE
ACTIVE STANDBY SLEEP STOP1 STOP2
The RCPC generates the various clock signals for
the operation of the LH79524/LH79525 and provides for
an orderly start-up after power-on and during a wake-up
from one of the power saving operating modes. The
RCPC allows the software to individually select the fre-
quency of the various on-chip clock signals as required
to operate the chip in the most power-efficient mode.
The maximum speeds of the various clocks in the SoC
are shown in Table 11. More detailed descriptions of
each clock appear in the User’s Guide.
RTC 32 kHz
Oscillator
ON
ON
ON
ON
ON
10 - 20 MHz
Oscillator
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
PLL
OFF
OFF
OFF
Peripheral
Clock
ON
OFF
OFF
CPU Clock
OFF
Real Time Clock
The RCPC features:
The RTC provides an alarm or long time base
counter. An interrupt is generated following counting a
programmed number of one-second periods. The 1 Hz
RTC clock is internally derived. The RTC features:
• 10 - 20 MHz crystal oscillator and PLL for on-chip
Clock generation (11.2896 MHz recommended)
• External Clock input if on-chip oscillator and PLL are
not used
• 32-bit up counter with programmable load
• Programmable 32-bit match compare register
• 32.768 kHz crystal oscillator generating 1 Hz clock
for Real Time Clock
• Software maskable interrupt when counter and com-
pare registers are identical.
• Individually controlled clocks for peripherals and CPU
• Programmable clock prescalers for UARTs and PWMs
RTC input clock sources:
• PLL clock
• Five global power control modes are available:
– Active
– Standby
– Sleep
– Stop1
– Stop2
• 32.768 kHz clock
• 1 Hz clock (default).
• CPU/Bus clock frequency can be changed on the fly
• Selectable clock output
• Hardware reset (nRESETIN) and software reset.
24
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Watchdog Timer
General Purpose Input/Output (GPIO)
The Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer to be
reset by software at regular intervals. Failure to reset
the timer will cause a FIQ interrupt. Failure to service
the FIQ interrupt will then generate a System Reset.
The features of the Watchdog Timer are:
The LH79524 provides up to 108 bits of programma-
ble input/output, and the LH79525 provides 86 bits.
Many of the GPIO pins are multiplexed with other sig-
nals. All GPIO feature:
• Individually programmable input/output pins
• All default to Input on power-up.
• Driven by the bus clock
• LH79524
16
31
• 16 programmable time-out periods: 2 through 2
– Ports A-I, K, L, and N: Bidirectional I/O (Port N is
4 bits wide)
clock cycles
– Port J: Input only
– Port M: Output only
• Generates a reset or an FIQ Interrupt whenever a
time-out period is reached
• Software enable, lockout, and counter-reset mecha-
nisms add security against inadvertent writes
• LH79525
– Ports A-I: Bidirectional I/O
– Port J: Input only
– Port M: Output only (6 bits wide)
• Protection mechanism guards against interrupt-ser-
vice failure:
– The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag
Boot Controller
– If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a system reset.
The boot controller allows selection of the hardware
device to be used for booting.
• Supports booting from 8-, 16-, or 32-bit devices,
selectable via external pins at power-on reset
Timers
The LH79524 and LH79525 incorporate three 16-bit
independently programmable Timer modules. The tim-
ers are clocked by the system clock, but have an inter-
nal scaled-down system clock that is used for the Pulse
Width Modulator (PWM) and compare functions.
• Configures the byte lane boot state for nCS1,
selectable via external pins at power-on reset.
• Supports booting from alternate external devices
(e.g., NAND flash) via external pins on power-on reset
• Glueless interface to external NAND flash.
All counters are incremented by an internal pre-
scaled counter clock or external clock and can gener-
ate an overflow interrupt. All three timers have separate
internal prescaled counter clocks, with either a com-
mon external clock or a prescaled version of the sys-
tem clock.
USB Device
The USB Device integrated into the LH79524/
LH79525 is compliant with the USB 1.1 and 2.0 speci-
fication, and compatible with both the OpenHCI and
Intel UHCI standards. The USB Device:
• Timer 0 has five Capture Registers and two Com-
pare Registers.
• Supports Full-Speed (12 Mbit/s) operation, and
suspend and resume signaling
• Timer 1 and Timer 2 have two Capture and two Com-
pare Registers each.
• Four Endpoints
The Capture Registers have edge-selectable inputs
and can generate an interrupt. The Compare Registers
can force the compare output pin either HIGH or LOW
upon a match.
• Bulk/Interrupt or Isochronous Transfers
• FIFO for each Endpoint direction (except EP0 which
shares a FIFO between IN/OUT). FIFOs exist in
2464 × 8 RAM
The timers support a PWM Mode that uses the two
Timer Compare Registers associated with a timer to
create a PWM. Each timer can generate a separate
interrupt. The interrupt becomes active if any enabled
compare, capture, or overflow interrupt condition
occurs. The interrupt remains active until all compare,
capture, and overflow interrupts are cleared.
• Supports DMA accesses to FIFO.
Preliminary data sheet
Rev. 01 — 16 July 2007
25
LH79524/LH79525
System-on-Chip
NXP Semiconductors
2
Ethernet MAC Controller
SSP To I S Converter
2
The on-board Ethernet MAC Controller (EMAC) is
compatible with IEEE 802.3, and has passed the Uni-
versity of New Hampshire (UNH) testing. It supports
both 10- and 100-Mbit/s, and full and half duplex oper-
ation. Other features include:
The SSP to I S converter is an interface that con-
verts a synchronous serial communication stream in TI
DSP-compatible mode into an I S compliant synchro-
nous serial stream. The I S converter operates on
serial data in both master and slave mode.
2
2
2
• Statistics counter registers for RMON/MIB
• MII interface to the physical layer
The I S converter provides:
• Programmable Word Select (WS) delay
• Interrupt generation to signal receive and transmit
completion
• Left/right channel information:
– Current WS value at the pin
– WS value associated with next entry written to
TX FIFO
• Transmit and receive FIFOs
• Automatic pad and CRC generation on transmitted
frames
– WS value associated with next entry read from
RX FIFO
• Automatic discard of frames received with errors
• Ability to invert WS state
• Address checking logic supports up to four specific
(hardware) 48-bit addresses
• Ability to invert the bit clock
• Supports frame size of 16 bits only. Any other frame
size will result in a frame size error. Each frame
transmits starting with the most-significant bit.
• Supports promiscuous mode where all valid
received frames are copied to memory
• Hash matching of unicast and multicast destination
addresses
• Master and slave modes supported
• As with the SSP, a single combined interrupt is gen-
erated as an OR function of the individual interrupt
requests. This interrupt replaces the SSP interrupt,
• Supports physical layer management through MDIO
interface
2
• Supports serial network interface operation
which is used solely as an input to the I S converter.
• Support for:
• Additional interrupts:
– Half duplex flow control by forcing collisions on in-
coming frames
– Full duplex flow control with recognition of incom-
ing pause frames and hardware generation of
transmitted pause frames
– Transmit FIFO underrun
– Transmit frame size error
– Receive frame size error
• A set of Interrupt registers contain all the information
in the SSPIMSC, SSPRIS, and SSPMIS registers,
plus the transmit underrun error and frame size errors
– 802.Q VLAN tagging with recognition of incoming
VLAN and priority tagged frames
• Additional status bits:
– Transmit FIFO Full
– Receive FIFO Empty
• Multiple buffers per receive and transmit frame
• Software configures the MAC address
• Jumbo frames of up to 10,240 bytes supported.
• Passes SSP data unaltered when module is not
enabled
2
I C Controller
The I C Controller includes a two-wire I C serial
interface capable of operating in either Master or Slave
• Loopback Test Mode support.
2
2
2
mode. The block conforms to the I C 2.1 Bus Specifi-
cation for data rates up to 400 kbit/s. The two wires are
2
SCL (serial clock) and SDA (serial data). The I C mod-
ule provides the following features:
• Two-wire synchronous serial interface
• Operates in both the standard mode, for data rates
up to 100 kbit/s, and the fast mode, with data rates
up to 400 kbit/s
• Communicates with devices in the fast mode as well
as the standard mode if both are attached to the bus.
26
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
• Front bias-and-control network for touch screen
interface and support functions, which are compati-
ble with industry-standard 4- and 5-wire touch-sensi-
tive panels
ADC and Brownout Detector
The ADC block consists of an 10-channel, 10-bit
Analog-to-Digital Converter with integrated Touch
Screen Controller (TSC). The complete touch screen
interface is achieved by combining the front-end bias-
ing, control circuitry with analog-to-digital conversion,
reference generation, and digital control.
• Touch-pressure sensing circuits
• Pen-down sensing circuit and interrupt generator
• Independent voltage reference generator
The ADC has a bias-and-control network that allows
correct operation with both 4- and 5-wire touch panels.
A 16-entry × 16-bit wide FIFO holds a 10-bit ADC
output and a 4-bit tag number.
• Conversion automation function to minimize
interrupt overhead
• Brownout Detector
When the screen is touched, it pushes the conduc-
tive coating on the coversheet against the coating
on the glass, making electrical contact. The voltages
produced are the analog representation of the position
touched. The voltage level of the coversheet is
converted continuously by the ADC and monitored by
the system.
• Battery Control Signal.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
DC Core Supply Voltage
DC I/O Supply Voltage
VDDC
VDD
-0.3 to 2.4
-0.3 to 4.6
-0.3 to 4.6
-0.3 to 2.4
-0.3 to 2.4
-55 to +125
V
V
Other features include:
• 10-bit fully differential Successive Approximation
Register (SAR) with integrated sample/hold
VDDA0
VDDA1
VDDA2
TSTG
V
DC Analog Supply
Voltage for ADC
V
• A 10-channel multiplexer that routes user-selected
inputs to the ADC in single-ended and differential
modes
V
Storage Temperature
°C
• A 16-entry × 16-bit wide FIFO that holds the 10-bit
ADC output
NOTE: These stress ratings are only for transient conditions. Oper-
ation at or beyond absolute maximum rating conditions may
affect reliability and cause permanent damage to the device.
Recommended Operating Conditions
PARAMETER
MINIMUM
TYPICAL
MAXIMUM
NOTES
DC Core Supply Voltage (VDDC)
DC I/O Supply Voltage (VDD)
DC Analog Supply Voltage (VDDA0)
DC Analog Supply Voltage (VDDA1)
DC Analog Supply Voltage (VDDA2)
Clock Frequency
1.7 V
3.0 V
1.8 V
3.3 V
3.3 V
1.8 V
1.8 V
1.9 V
3.6 V
1, 4
4
3.0 V
3.6 V
1.7 V
1.9 V
1.7 V
1.9 V
3.27 MHz
76.205 MHz
20.0 MHz
+85°C
2
3
Crystal Frequency
10.0 MHz 11.2896 MHz
-40°C 25°C
Operating Temperature (Industrial)
NOTES:
1. Linear Regulator disabled.
2. With PLL enabled. Without PLL, minimum frequency is 0 MHz.
Some peripherals may not operate at minimum frequency.
3. Choose 11.2896 MHz to ensure proper operation of the I2S, USB,
and UART peripherals.
4. Core Voltage should never exceed I/O Voltage after initial power
up. See “Power Supply Sequencing” on page 28.
Preliminary data sheet
Rev. 01 — 16 July 2007
27
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Power Supply Sequencing
DC/AC Specifications
When the linear regulator is not enabled, NXP rec-
ommends that the 1.8 V power supply be energized
before the 3.3 V supply. If this is not possible, the 1.8 V
supply may not lag the 3.3 V supply by more than 100
µs. If longer delay time is needed, it is recommended
that the voltage difference between the two power sup-
plies be within 1.5 V during power supply ramp up. To
avoid a potential latchup condition, voltage should be
applied to input pins only after the device is powered-
on as described above.
Unless noted, all data provided are based on:
• -40°C to +85°C (Industrial temperature range)
• VDDC = 1.7 V to 1.9 V
• VDD = 3.0 V to 3.6 V, VDDA = 1.7 V to 1.9 V.
DC SPECIFICATIONS
SYMBOL
VIH
PARAMETER
CMOS input HIGH voltage
CMOS input LOW voltage
MIN. TYP. MAX. UNIT
CONDITIONS
2.0
5.5
0.8
V
V
V
V
V
V
V
V
V
V
V
V
V
CEN = 1
VIL
CEN = 1
VIT+
VIT-
Positive Input threshold voltage (Schmitt pins) 2.0
Negative Input threshold voltage (Schmitt pins)
Schmitt trigger hysteresis
CSEN = 1
CSEN = 1
CSEN = 1
0.8
VHYST
0.35
Output drive (2 mA type)
Output drive (4 mA type)
Output drive (8 mA type)
Output drive (12 mA type)
Output drive (2 mA type)
Output drive (4 mA type)
Output drive (8 mA type)
Output drive (12 mA type)
2.6
2.6
2.6
2.6
IOH = -2 mA
IOH = -4 mA
IOH = -8 mA
IOH = -12 mA
IOL = 2 mA
IOL = 4 mA
IOL = 7 mA
IOH = 12 mA
VOH1
VOL1
0.4
0.4
0.4
2.6
VIN = VDD or GND (Calculate input
leakage current at desired VDD)
RIN
Input leakage pull-up/pull-down resistors
40
kΩ
IACTIVE
Active current
85
50
mA Note 2
ISTANDBY Standby current
mA Notes 2, 3
ISLEEP
ISTOP1
ISTOP2
ISTOP2
ISTOP2
ISTOP2
Sleep current
Stop1 current
Stop2 current
Stop2 current
Stop2 current
Stop2 current
3.8
420
115
95
mA
µA
µA RTC ON, Linear Regulator ON
µA RTC OFF, Linear Regulator ON
µA RTC ON, Linear Regulator OFF
µA RTC OFF, Linear Regulator OFF
45
25
NOTES:
1. Table 2 details each pin’s buffer type.
2. Running Typical Application over operating range.
3. Current measured with CPU stopped and all peripherals enabled
Linear Regulator DC Characteristics.
SYMBOL
PARAMETER
MIN. TYP. MAX. UNIT
IQUIESCENT Quiescent Current
75
8
µA
µA
mA
V
ISLEEPLR
IOLR
Current with Linear Regulator disabled
Output Current Range
0.0
200
VOLR
Output Voltage, Linear Regulator
1.84
28
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
AC Test Conditions
AC Specifications
All signals described in Table 14 relate to transitions
after a reference clock signal. The illustration in Figure
9 represents all cases of these sets of measurement
parameters; except for the Asynchronous Memory
Interface — which are referenced to Address Valid.
PARAMETER
RATING
UNIT
Supply Voltage (VDD)
Core Voltage (VDDC)
Input Pulse Levels
3.0 to 3.6
1.7 to 1.9
VSS to VDD
2
V
V
V
Input Rise and Fall Times
ns
The reference clock signals in this design are:
• HCLK, the System Bus clock
Input and Output Timing
Reference Levels
VDD/2
V
• PCLK, the Peripheral Bus clock (locked to HCLK in
the LH79524/LH79525)
Power Consumption By Peripheral Device
Table 13 shows the typical power consumption by
individual peripheral device.
• SSPCLK, the Synchronous Serial Interface clock
• UARTCLK, the UART Interface clock
• LCDDCLK, the LCD Data clock from the
LCD Controller
Table 13. Peripheral Current Consumption
• and SDCLK, the SDRAM clock.
PERIPHERAL
TYPICAL
UNITS
µA
All signal transitions are measured from the 50%
point of the clock to the 50% point of the signal. See
Figure 9.
ADC/TSC
Counter/Timers
DMA
590
203
4.2
µA
mA
µA
For outputs from the LH79524/LH79525, tOVXXX
(e.g. tOVA) represents the amount of time for the out-
put to become valid from the rising edge of the refer-
ence clock signal. Maximum requirements for tOVXXX
are shown in Table 14.
Ethernet Controller
670
200
2.2
2
I S
µA
LCD Controller
RTC
mA
µA
5.1
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the ris-
ing edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 14.
SSP
508
µA
µA
UARTs
203
USB Device (+PLL)
5.6 (+3.3)
mA
For Inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 14.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid from the
rising edge of the reference clock signal. Minimum
requirements are shown in Table 14.
REFERENCE
CLOCK
tOHXXX
tOVXXX
OUTPUT
SIGNAL (O)
tISXXX tIHXXX
INPUT
SIGNAL (I)
LH79525-28
Figure 9. LH79524/LH79525 Signal Timing
Preliminary data sheet
Rev. 01 — 16 July 2007
29
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Table 14. AC Signal Characteristics
SIGNAL
TYPE LOAD
SYMBOL
MIN.
MAX.
DESCRIPTION
ASYNCHRONOUS MEMORY INTERFACE SIGNALS
Output 50 pF
Input
tWC
tRC
3 × tHCLK – 5.0 ns
2 × tHCLK – 5.0 ns
tHCLK – 5.5 ns
tHCLK – 4.5 ns
14.0 ns
Write Cycle time
A[27:0]
Read Cycle time
tDHWE
tDWE
tDSCS
tDSOE
tDSB
tDHCS
tDHOE
tAV
Data out hold to nWE release
Data out valid to nWE release
Data valid to nCSx release
Data valid to nOE release
Data valid to nBLEx release
nCSx release to data invalid
nOE release to data invalid
nCSx valid to Address valid
Address hold after nCSx release
Address hold after nOE release
Address valid to nCSx valid
D[31:0]
Output 50 pF
12.5 ns
12.0 ns
0.0 ns
0.0 ns
2.5 ns
2.5 ns
tAHCS
tAHOE
tASCS
tCW
tHCLK – 3.0 ns
tHCLK - 1.0 ns
nCS[3:0]
Output 50 pF
2 × tHCLK + 3.0 ns nCSx valid to nWE release
tCB
2 × tHCLK
nCSx valid to nBLE release
nCSx width
tCS
tHCLK – 3.5 ns
tBV
1.5 ns
nCSx valid to nBLE valid
Address hold after nBLE release
Data out valid to nBLE release
Data in hold to nBLE release
Data out hold to nBLE release
Address hold to nBLE release
Address valid to nBLE release
Address valid to nBLE valid
nBLE width (read)
tAHB
tDB
tHCLK – 2.0 ns
tHCLK – 6.0 ns
0.0 ns
tDHBR
tDHBW
tBR
tHCLK + 9 ns
–2.0 ns
nBLE
Output 50 pF
tAB
2 × tHCLK ns
1.0 ns
tASB
tBLE
tBP
tHCLK – 4.5 ns
tHCLK – 4.5 ns
nBLE width (write)
tASWE
tAW
tHCLK + 1.5 ns
Address valid to nWE valid
2 × tHCLK + 0.5 ns Address valid to nWE release
Address Hold to nWE release
Write Enable width
nWE
Output 50 pF
Output 50 pF
tWR
tHCLK – 3.0 ns
tHCLK – 1 ns
tHCLK – 1 ns
tWP
tOE
Ouput Enable width
nOE
tOEV
– 0.5 ns
nOE valid after nCSx valid
SYNCHRONOUS MEMORY INTERFACE SIGNALS
A[23:0]
D[31:0]
Ouput 50 pF
Output 50 pF
tOVA
tOVD
tOHD
tISD
tSDCLK/2 + 4.5 ns Address Valid
tSDCLK/2 + 7.0 ns Output Data Valid
tSDCLK/2 – 4.0 ns
5.0 ns
Output Data Hold
Input Data Setup
Input Data Hold
Input
tIHD
1.5 ns
tOVCA
tOHCA
tSDCLK/2 + 4.0 ns CAS Valid
nCAS
nRAS
Output 50 pF
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
CAS Hold
tOVRA
tOHRA
tSDCLK/2 + 4.5 ns RAS Valid
RAS Hold
Output 50 pF
30
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
DESCRIPTION
NXP Semiconductors
Table 14. AC Signal Characteristics (Cont’d)
SIGNAL
nWE
TYPE LOAD
SYMBOL
tOVSDW
tOHSDW
tOVC0
MIN.
MAX.
tSDCLK/2 + 4.5 ns SDWE Write Enable Valid
SDWE Write Enable Hold
Output 30 pF
Output 30 pF
Output 30 pF
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
tSDCLK/2 – 4.0 ns
tSDCLK/2 + 4.5 ns SDCKE Clock Enable Valid
SDCKE Clock Enable Hold
SDCKE
tOHC0
tOVDQ
tOHDQ
tOVSC
tSDCLK/2 + 5.0 ns DQM Data Mask Valid
DQM Data Mask Hold
DQM[3:0]
tSDCLK/2 + 4.5 ns SDCS Data Mask Valid
SDCS Data Mask Hold
nSDCS[1:0]
SDCLK
Output 30 pF
Output 30 pF
tOHSC
tSDCLK/2 – 4.0 ns
19.37 ns
tSDCLK
SDRAM Clock Period
SYNCHRONOUS SERIAL PORT (SSP)
tOVSSPFRM Output Valid,
Referenced to SSPCLK
SSPFRM
Output 50 pF tOVSSPFRM
14 ns
SSPTX
SSPRX
Output 50 pF tOVSSPTX
14 ns
SSP Transmit Valid
SSP Receive Setup
Input
tISSPRX
20 ns
ETHERNET MAC CONTROLLER (EMC)
Transmit Data Valid after
ETHERTXCLK
tOVTXER
25 ns
25 ns
25 ns
ETHERTXER Output 50 pF
ETHERTX[3:0] Output 50 pF
ETHERTXEN Output 50 pF
ETHERTXCLK/2 +
2.0 ns
Transmit Data Hold after
ETHERTXCLK
tOHTXER
tOVTXD
tOHTXD
tOVTXEN
tOHTXEN
tISRXDV
tIHRXDV
tISRXD
Transmit Data Valid after
ETHERTXCLK
ETHERTXCLK/2 +
2.0 ns
Transmit Data Hold after
ETHERTXCLK
Transmit Data Valid after
ETHERTXCLK
ETHERTXCLK/2 +
2.0 ns
Transmit Data Hold after
ETHERTXCLK
Receive Data Setup prior to
ETHERRXCLK
10 ns
10 ns
10 ns
10 ns
ETHERRXDV
Input
Receive Data Hold prior to
ETHERRXCLK
Receive Data Setup prior to
ETHERRXCLK
ETHERRX[3:0] Input
Receive Data Hold prior to
ETHERRXCLK
tIHRXD
Preliminary data sheet
Rev. 01 — 16 July 2007
31
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Analog-To-Digital Converter
Electrical Characteristics
Table 15 shows the ADC electrical characteristics.
See Figure 10 for the ADC transfer characteristics.
Table 15. ADC Electrical Characteristics
PARAMETER
A/D Resolution
MIN.
TYP.
MAX.
UNITS
NOTES
10
17
3
10
Bits
Throughput Conversion
Acquisition Time
CLK Cycles
CLK Cycles
1
Data Format
binary
CLK Frequency
500
-0.99
-3.0
5,000
3.0
ns
LSB
LSB
mV
LSB
V
Differential Non-Linearity
Integral Non-Linearity
Offset Error
+3.0
-10
+10
Gain Error
-2.0
+2.0
Reference Voltage Output
VREF-
1.85
VSSA
2.0
2.15
VSSA
(VREF+) -1.0 V
VDDA
V
2
2
VREF+
(VREF-) +1.0 V VREF
V
Crosstalk between channels
Analog Input Voltage Range
Analog Input Current
Reference Input Current
Analog input capacitance
Operating Supply Voltage
Operating Current, VDDA0
Powerdown Current, VDDA0
Standby Current
-60
dB
V
0
VDDA
5
3
µA
µA
pF
V
5
15
3.0
590
1
3.6
1000
10
µA
µA
µA
V
180
300
2.9
4
Brown Out Trip Point (falling point)
Brown Out Hysterisis
Operating Temperature
2.36
-40
2.63
120
mV
°C
85
NOTES:
1. The analog section of the ADC takes 16 × A2DCLK cycles per conversion plus 1 × A2DCLK cycles to be made available in the PCLK
domain. An additional 3 × PCLK cycles are required before being available on the APB.
2. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer, alternative low impedance
(RS < 500) voltages can be selected as reference voltages. The range of voltages allowed are specified above. However, the on-chip
reference cannot drive the ADC unless the reference buffer is switched on.
3. The analog input pins can be driven anywhere between the power supply rails. If the voltage at the input to the ADC exceeds VREF+
or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale. Trying to pull the analog input pins above
or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible
damage to the ADC.
4. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down.
32
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
OFFSET GAIN
ERROR ERROR
1024
1023
1022
1021
1020
1019
1018
IDEAL
TRANSFER CURVE
9
8
7
6
5
4
3
2
1
CENTER OF A
STEP OF THE ACTUAL
TRANSFER CURVE
ACTUAL
TRANSFER CURVE
INTEGRAL
NON-LINEARITY
CENTER OF STEP
1
2
3
4
5
6
7
8
9
1,015 1,016 1,017 1,018 1,019 1,020 1,021 1,022 1,023 1,024
LSB
OFFSET
ERROR
DNL
LH79525-2
Figure 10. ADC Transfer Characteristics
Preliminary data sheet
Rev. 01 — 16 July 2007
33
LH79524/LH79525
System-on-Chip
NXP Semiconductors
In Figure 18, nCSx is asserted coincident (following
a small propagation delay) with Valid Address. Data
becomes valid another small propagation delay later.
Unlike Read transactions, nWE (or nBLEx) assertion is
always delayed one HCLK cycle. The nBLEx signal has
the same timing as nWE for write to 8-bit devices that
use the byte lane enables instead of the write enables.
External Memory Controller Waveforms
The External Memory Controller (EMC) handles
transactions with both static and dynamic memory.
STATIC MEMORY WAVEFORMS
This section illustrates static memory transaction
waveforms. Each wait state is one HCLK period.
The nWE (or nBLEx) signal remains asserted for one
HCLK cycle when the nWE (or nBLEx) signal is deas-
serted and the data is latched into the external memory
device. Valid address is held for one additional cycle
before deassertion (‘C’ in the figure), as is the Chip
Select. The minimum Write cycle is three HCLK periods.
nWAIT Input
The EMC’s Static Memory Controller supports an
nWAIT input that can be used by an external device to
extend the wait time during a memory access. The
SMC samples nWAIT at the beginning of at the begin-
ning of each system clock cycle. The system clock
cycle in which the nCSx signal is asserted counts as
the first wait state. See Figure 11 through Figure 20.
Read wait state programming uses the SWAITRDx
register. Figure 19 shows the results of programming
SWAITRDx to 0x3, setting the EMC for three wait
states. The deassertion of nOE is delayed from the first
rising HCLK edge following Valid Address, as in Figure
17, to the fourth rising edge, a delay of 3 HCLK periods.
Read and Write Waveforms
Figure 17 shows the Read cycle with zero wait
states. As shown in the figure, SWAITOENx and
SWAITRDx are programmed to 0 for minimum Read
cycle time.
Figure 20 shows the results of programming the
SWAITWRx and SWAITWENx registers for two Write
wait states: register SWAITWENx = 0x0, and SWAIT-
WRx = 0x2. Assertion of nCSx precedes nWE (nBLEx)
by one HCLK period. Then, instead of the nWE
(nBLEx) signal deasserting one HCLK period after
assertion, it is delayed two wait states and the signal
deasserts on the rising edge following two wait states.
The zero programmed into the SWAITRDx indicates
that the read occurs with zero wait states, on the first
rising edge following Address Valid. After a small prop-
agation delay, nOE is deasserted (as is nCSx), latching
the data into the SoC. The address line is held valid
one more HCLK period (‘C’ in the figure). Thus, the
minimum Read cycle is two HCLK periods.
Chapter 7 of the User’s Guide has detailed register
descriptions and additional programming examples.
Figure 18 shows the minimum write cycle time with
both SWAITWRx and SWAITWENx programmed to
zero. The write access time is determined by the number
of wait states programmed in the SWAITWRx register.
34
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
tDD_nWAIT_nCS(x)
tDD_nWAIT_nOE
tDA_nCS(x)_nWAIT
nCS(x)
nOE
tA_nWAIT
nWAIT
HCLK
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
Transaction
Sequence
WST-3 WST-2 WST-1 nWAIT nWAIT nWAIT nWAIT nWAIT WST-0
DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-133
Figure 11. nWAIT Read Sequence (SWAITRDx = 3)
Table 16. nWAIT Read Sequence Parameter Definitions
PARAMETER
DESCRIPTION
MIN.
MAX.
UNIT 1
tDA_nCS(x)_nWAIT
tDD_nWAIT_nCS(x)
tDD_nWAIT_nOE
tA_nWAIT
Delay from nCS(x) assertion to nWAIT assertion
Delay from nWAIT deassertion to nCS(x) deassertion
Delay from nWAIT deassertion to nOE deassertion
Assertion time of nWAIT
0
16,365
HCLK periods
HCLK periods
HCLK periods
HCLK periods
4
4
2
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O conditioning will cause
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
2. The Read Wait States register (SWAITRDx) must be set to a minimum value of 3.
3. For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, another read wait state (SWAITRDx) must be
added to the minimum requirement.
4. nWAIT delay cycles are not added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
5. nWAIT delay cycles are added for all nWAIT assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
once the wait state countdown has reached WST-1.
6. Once nWAIT is sampled high, the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
8. Timing assumes Output Enable Delay register (SWAITOENx) is programmed to 0.
Preliminary data sheet
Rev. 01 — 16 July 2007
35
LH79524/LH79525
System-on-Chip
NXP Semiconductors
tDD_nWAIT_nCS(x)
tDD_nWAIT_nOE)
tDA_nCS(x)_nWAIT
nCS(x)
nOE
tA_nWAIT
nWAIT
HCLK
SI
SI
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
nWAIT nWAIT nWAIT nWAIT nWAIT
DELAY DELAY DELAY DELAY DELAY
Transaction
Sequence
WST-5 WST-4
DELAY DELAY DELAY DELAY DELAY
WST-3 WST-2 WST-1
WST-0
DELAY
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-134
Figure 12. nWAIT Read Sequence (SWAITRDx = 5)
tDA_nCS(x)_nWAIT
nCS(x)
nOE
tA_nWAIT
SI
SI
nWAIT
HCLK
WST-0
DELAY
WST-5 WST-4 WST-3 WST-2 WST-1
DELAY DELAY DELAY DELAY DELAY
Transaction
Sequence
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-135
Figure 13. nWAIT Read Sequence (SWAITRDx = 5): nWAIT has no effect on the current transaction
36
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
tDD_nWAIT_nCS(x)
tDD_nWAIT_nWE
tDA_nCS(x)_nWAIT
nCS(x)
nWE
tA_nWAIT
nWAIT
HCLK
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
END
END
Transaction
Sequence
WST-3 WST-2 WST-1 nWAIT nWAIT nWAIT nWAIT nWAIT WST-0 CYCLE CYCLE
DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY DELAY nWE
nCS(x)
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-136
Figure 14. nWAIT Write Sequence (SWAITWRx = 3)
Table 17. nWAIT Write Sequence Parameter Definitions
PARAMETER
DESCRIPTION
MIN.
MAX.
UNIT1
tIDA_nCS(x)_nWAIT
tDD_nWAIT_nCS(x)
tDD_nWAIT_nWE
tA_nWAIT
Delay from nCS(x) assertion to nWAIT assertion
Delay from nWAIT deassertion to nCS(x) deassertion
Delay from nWAIT deassertion to nWE deassertion
Assertion time of nWAIT
0
16,365
HCLK periods
HCLK periods
HCLK periods
HCLK periods
6
5
2
NOTES:
1. The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O conditioning will cause
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
2. The Write Wait States register (SWAITWRx) must be set to a minimum value of 3.
3. For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, another write wait state (SWAITRDx) must be
added to the minimum requirement.
4. nWAIT delay cycles are not added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
5. nWAIT delay cycles are added for all nWAIT assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
once the wait state countdown has reached WST-1.
6. Once nWAIT is sampled high, the current memory transaction is queued to complete.
7. Since static and dynamic memory cannot be accessed at the same time, any prolonged access (either due to nWAIT or the Extended Wait
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
8. Timing assumes Write Enable Delay register (SWAITWENx) is programmed to 0.
Preliminary data sheet
Rev. 01 — 16 July 2007
37
LH79524/LH79525
System-on-Chip
NXP Semiconductors
tDD_nWAIT_nCS(x)
tDD_nWAIT_nWE
tDA_nCS(x)_nWAIT
nCS(x)
nWE
tA_nWAIT
nWAIT
HCLK
SI
SI
SQ-4
SQ-3
SQ-2
SQ-1
SQ-0
END
END
CYCLE
CYCLE
nCS(x)
nWE
SQ-1
nWAIT nWAIT
DELAY DELAY
SQ-0
SQ-4
SQ-3
SQ-2
Transaction
Sequence
nWAIT nWAIT nWAIT
DELAY DELAY DELAY
WST-5 WST-4 WST-3
DELAY DELAY DELAY DELAY DELAY
WST-2
WST-1
WST-0
DELAY
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-137
Figure 15. nWAIT Write Sequence (SWAITWRx = 5)
tDA_nCS(x)_nWAIT
nCS(x)
nWE
tA_nWAIT
SI
SI
nWAIT
HCLK
END
WST-5 WST-4 WST-3 WST-2 WST-1 WST-0 CYCLE CYCLE
DELAY DELAY DELAY DELAY DELAY DELAY
nWE nCS(x)
END
Transaction
Sequence
NOTES:
SQ: nWAIT Sampled and Queued
SI: nWAIT Sampled and Ignored
LH79525-138
Figure 16. nWAIT Write Sequence (SWAITWRx = 5): nWAIT has no effect on the current transaction
38
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
tRC
tDSB
tDSCS,
tDSOE
tAHCS, tAHOE
tAHB
tASCS
HCLK
A[23:0]
D[31:0]
VALID ADDRESS
VALID DATA
tCS
nCS
nOE
tOEV
tOE
tDHCS
tDHBR
tDHOE
tBV
nBLEx
tBLE
DATA
CAPTURED
LH79525-105
Figure 17. External Static Memory Read, Zero Wait States
Preliminary data sheet
Rev. 01 — 16 July 2007
39
LH79524/LH79525
System-on-Chip
NXP Semiconductors
tWC
HCLK
A[23: 0]
VALID ADDRESS
tAW, tAB
tASCS
D[ 31:0 ]
VALID DATA
tCW
tCB
nCS
tDWE
tDHWE, tWR
tDB
nWE
tBR
tASB
tASWE
tWP
tBP
nBLEx
LH79525-71
Figure 18. External Static Memory Write, Zero Wait States
HCLK
tRC
VALID ADDRESS
VALID DATA
A[23:0]
D[31:0]
nCSx
DATA
CAPTURED
nOE
LH79525-72
Figure 19. External Static Memory Read with Three Wait States
40
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
HCLK
tWC
A[23:0]
D[31:0]
nCSx
VALID ADDRESS
VALID DATA
nWE or nBLEx
LH79525-73
Figure 20. External Static Memory Write with Two Wait States
Preliminary data sheet
Rev. 01 — 16 July 2007
41
LH79524/LH79525
System-on-Chip
NXP Semiconductors
SDRAM MEMORY CONTROLLER WAVEFORMS
Figure 21 shows the waveform and timing for an
SDRAM Burst Read (page already open). Figure 22
shows the waveform and timing for SDRAM to Activate
a Bank and Write.
tSDCLK
SCLK
tOVXXX tOHXXX
READ
tOVDQ
NOP
NOP
SDRAMcmd
DQMx
NOP
NOP READ
tOHDQ
NOP
tOVA
A[14:0]
D[31:0]
BANK,
COLUMN
tISD tIHD
DATA n
CAS
LATENCY = 2
DATA n + 2
DATA n + 1
DATA n + 3
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. SDCKE is HIGH.
LH79525-3
Figure 21. SDRAM Burst Read
42
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Figure 22. SDRAM Bank Activate and Write
Preliminary data sheet
Rev. 01 — 16 July 2007
43
LH79524/LH79525
System-on-Chip
NXP Semiconductors
DACK/DEOT TIMING
External DMA Handshake Signal Timing
These timing diagrams indicate when nDACK and
DEOT occur in relation to an external bus access to/from
the external peripheral that requested the DMA transfer.
DREQ TIMING
Once asserted, DREQ must not transition from LOW
to HIGH again until after nDACK has been asserted.
The first diagram shows the timing with relation to a
single read or the last word of a burst read from the
requesting peripheral. The remaining diagrams show
timing for data transfers.
DREQ MAY
TRANSITON
DREQ
tDREQ0L,
tDREQ1L
MUST NOT
TRANSITON
DREQ0,
DREQ1
DACK0
nDACK1
NOTE: tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
LH79525-5
Figure 23. DREQ Timing Restrictions
HCLK
(See Note)
A[23:0]
D[31:0]
ADDRESS
DATA
nCSx
nWEN
nBLE[1:0]
nOE
DACK0/
DEOT0/DEOT1
nDACK1
NOTE: * HCLK is an internal signal provided for reference only.
LH79525-6
Figure 24. Read, from Peripheral to Memory, Burst Size = 1
44
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
HCLK
(See Note)
A[23:0]
ADDRESS
D[15:0]
DATA
nCSx
nWEN
nBLE[1:0]
nOE
DACK0/
DEOT0/DEOT1
nDACK1
NOTE: * HCLK is an internal signal provided for reference only.
LH79525-7
Figure 25. Write, from Memory to Peripheral, Burst Size = 1
HCLK*
A[23:0]
ADDRESS
DATA #1
DATA #2
DATA #3
DATA #4
D[31:0]
nCSx
nWEN
nBLE[1:0]
nOE
DACK0/DEOT0/DEOT1
nDACK1
NOTE: * HCLK is an internal signal, provided for reference only.
LH79525-8
Figure 26. Read, Peripheral to Memory: Peripheral Burst Size = 4
Preliminary data sheet
Rev. 01 — 16 July 2007
45
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Figure 27. Write, Memory-to-Peripheral: Burst Size = 4; Destination Width > External Access Width
46
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Color LCD Controller Timing Diagrams
Figure 28. STN Horizontal Timing
Preliminary data sheet
Rev. 01 — 16 July 2007
47
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Figure 29. STN Vertical Timing
48
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Figure 30. TFT Horizontal Timing
Preliminary data sheet
Rev. 01 — 16 July 2007
49
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Figure 31. TFT Vertical Timing
50
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
1 AD-TFT or HR-TFT HORIZONTAL LINE
* CLCDCLK
(INTERNAL)
APBPERIPHCLKCTRL1:LCD
CLKPRESCALE:LCDPS
(SHOWN FOR REFERENCE)
AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED
TIMING0:HSW
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDDCLK
(PANEL CLOCK)
TIMING2:PCD
TIMING2:BCD
TIMING2:IPC
TIMING2:CPL
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
16 × (TIMING0:PPL+1)
001 002 003 004 005 006 007 008
320
PIXEL DATA
TIMING0:HSW +
TIMING0: HBP
LCDEN
(INTERNAL DATA ENABLE)
LCDDCLK
(DELAYED FOR
AD-TFT, HR-TFT)
LCDVD[11:0] (LH79525)
LCDVD[15:0] (LH79524)
(DELAYED FOR
001 002 003 004 005 006
317 318 319 320
AD-TFT, HR-TFT)
1 LCDDCLK
ALITIMING2:SPLDEL
LCDSPL
(AD-TFT, HR-TFT
START PULSE LEFT)
1 LCDDCLK
ALITIMING1:LPDEL
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
ALITIMING2:PS2CLS2
ALITIMING1:PSCLS
LCDCLS
LCDPS
LCDREV
NOTE: * Source is RCPC.
LH79525-42
Figure 32. AD-TFT, HR-TFT Horizontal Timing
TIMING1:VSW
1.5 µs - 4 µs
LCDSPS
(VERTICAL
SYNCHRONIZATION)
LCDLP
(HORIZONTAL
SYNCHRONIZATION
PULSE)
LCDVD[11:0]
(LCD VIDEO DATA)
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
LH79525-43
Figure 33. AD-TFT, HR-TFT Vertical Timing
Preliminary data sheet
Rev. 01 — 16 July 2007
51
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Synchronous Serial Port
The SSP timing is illustrated in Figure 34.
Figure 34. Synchronous Serial Port Waveform
52
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
Ethernet MAC Controller Waveforms
The timing for the EMC is presented in the following
two illustrations. Figure 35 shows an Ethernet transmit
and Figure 36 shows an Ethernet receive.
ETHERTXCLK
tOVTXER,
tOVTXD,
tOVTXEN
tOHTXER,
tOHTXD,
tOHTXEN
ETHERTXER,
ETHERTX[3:0],
ETHERTXEN
LH79525-13
Figure 35. Ethernet Transmit Timing
ETHERRXCLK
tISRXDV,
tISRXD
tIHRXDV,
tIHRXD
ETHERRXDV,
ETHERRX[3:0]
LH79525-14
Figure 36. Ethernet Receive Timing
Preliminary data sheet
Rev. 01 — 16 July 2007
53
LH79524/LH79525
System-on-Chip
NXP Semiconductors
Figure 38 shows external reset timing, and Table 18
gives the timing parameters.
Reset, Clock, and Power Controller
(RCPC) Waveforms
Figure 37 shows the method the LH79524/LH79525
uses when coming out of Reset or Power On.
Table 18. Reset AC Timing
DESCRIPTION
PARAMETER
MIN. TYP. MAX.
UNIT
tOSC32
Oscillator stabilization time after Power Up (VDDC = VDDCMIN)
550
ms
Oscillator stabilization time after Power Up (VDDC = VDDCMIN) or
exiting STOP2
tOSC14
2.5
ms
tRSTIH
tRSTIW
nRESETIN hold time after crystal stabilization
nRESETIN Pulse Width (once sampled LOW)
200
2
µS
HCLK
nRESETIN LOW to nRESETOUT valid
(once nRESETIN sampled LOW)
tRSTOV
tRSTOH
3.5
1
HCLK
HCLK
nRESETOUT hold relative to nRESETIN HIGH
VDDCmin
VDDC
tOSC32
XTAL32
XTAL14
tRSTIH
tOSC14
nRESETIN
tRSTOH
nRESETOUT
LH79525-22
Figure 37. PLL Start-up
tRSTIW
nRESETIN
tRSTOH
tRSTOV
nRESETOUT
LH79525-23
Figure 38. External Reset
54
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
UNUSED INPUT SIGNAL CONDITIONING
depend upon a number of factors, including the trace
width, dielectric material the circuit board is made from
and proximity to ground and power planes.
Floating input signals can cause excessive power
consumption. Unused inputs which do not include inter-
nal pull-up or pull-down resistors should be pulled up or
down externally, to tie the signal to its inactive state.
Attention to power supply decoupling and printed cir-
cuit board layout becomes more critical in systems with
higher capacitive loads. As these capacitive loads
increase, transient currents in the power supply and
ground return paths also increase.
Some GPIO signals may default to inputs. If the pins
which carry these signals are unused, software can
program these signals as outputs, to eliminate the need
for pull-ups or pull-downs. Power consumption may be
higher than expected until such software executes.
Add pull-ups to all unused inputs unless an
internal pull-down resistor has been specified; see
Table 3. Consider all signals that are Inputs at Reset.
Some LH79524/LH79525 inputs have internal pull-
ups or pull-downs. If unused, these inputs do not
require external conditioning.
SUGGESTED EXTERNAL COMPONENTS
Figure 39 shows the suggested external compo-
nents for the 32.768 kHz crystal circuit to be used with
the NXP LH79524/LH79525. The NAND gate repre-
sents the logic inside the SoC. See the table in
Figure 39 for crystal specifics.
OTHER CIRCUIT BOARD LAYOUT PRACTICES
All output pins on the LH79524/LH79525 have fast
rise and fall times. Printed circuit trace interconnection
length must therefore be reduced to minimize over-
shoot, undershoot and reflections caused by transmis-
sion line effects of these fast output switching times.
This recommendation particularly applies to the
address and data buses.
Figure 40 shows the suggested external compo-
nents for the 10 - 20 MHz crystal circuit to be used with
the NXP LH79524/LH79525. The NAND gate
rep-
resents the logic inside the SoC. See the chart for crys-
tal specifics.
When considering capacitance, calculations must
consider all device loads and capacitances due to the
circuit board traces. Capacitance due to the traces will
ENABLE
INTERNAL TO
THE LH79524/LH79525
EXTERNAL TO
THE LH79524/LH79525
XTAL32IN
XTAL32OUT
Y1
32.768 kHz
R1
10 MΩ
C1
15 pF
C2
18 pF
GND
GND
RECOMMENDED CRYSTAL SPECIFICATIONS
NOTES:
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 12.5 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
PARAMETER
DESCRIPTION
32.768 kHz Crystal
Tolerance
Aging
Load Capacitance
ESR (MAX.)
Drive Level
Parallel Mode
30 ppm
3 ppm
12.5 pF
50 kΩ
1.0 µW (MAX.)
MTRON SX1555 or equivalent
4. R1 must be in the circuit.
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
Recommended Part
6. Tolerance for R1, C1, C2 is ≤ 5%.
LH79525-11
Figure 39. Suggested External Components, 32.768 kHz Oscillator (XTAL32IN and XTAL32OUT)
Preliminary data sheet
Rev. 01 — 16 July 2007
55
LH79524/LH79525
System-on-Chip
NXP Semiconductors
ENABLE
INTERNAL TO
THE LH79524/LH79525
EXTERNAL TO
THE LH79524/LH79525
XTALIN
XTALOUT
Y1
10 - 20 MHz
R1
1 MΩ
C1
18 pF
C2
22 pF
GND
GND
RECOMMENDED CRYSTAL SPECIFICATIONS
PARAMETER DESCRIPTION
11.2896 MHz Crystal (AT-Cut) Parallel Mode
NOTES:
1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for
a crystal specified at 18 pF load capacitance (CL).
3. The values for C1 and C2 are dependent upon
the cystal's specified load capacitance and PCB
stray capacitance.
Tolerance
Stability
Aging
50 ppm
100 ppm
5 ppm
Load Capacitance
ESR (MAX.)
Drive Level
Recommended Part
18 pF
40 Ω
4. R1 must be in the circuit.
5. Ground connections should be short and return
to the ground plane which is connected to the
processor's core ground pins.
100 µW (MAX.)
CITIZEN CM309S - 11.2896 MABJTR
or equivalent
6. Tolerance for R1, C1, C2 is ≤ 5%.
LH79525-12
Figure 40. Suggested External Components, 10 MHz to 20 MHz Oscillator
56
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
PACKAGE SPECIFICATIONS
LQFP176: plastic low profile quad flat package; 176 leads; body 20 x 20 x 1.4 mm
SOT1017-1
c
y
X
A
89
132
Z
E
133
88
e
(A )
3
A
2
A
1
H
E
A
E
M
w
θ
b
L
p
p
L
pin 1 index
176
45
detail X
44
1
M
M
v
A
B
M
w
e
b
Z
D
p
D
B
H
v
D
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
(1)
UNIT
A
1
A
2
A
3
b
p
c
D
E
e
H
D
H
E
L
L
p
v
w
y
Z
D
Z
E
θ
max
°
°
0.15 1.45
0.05 1.35
0.23 0.20 20.2 20.2
0.13 0.09 19.8 19.8
22.2 22.2
21.8 21.8
0.75
0.45
1.5
1.3
1.5
1.3
7
0
mm
1.6
0.25
0.4
1
0.2
0.07 0.08
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
07-07-07
07-07-07
SOT1017-1
Figure 41. Package outline SOT1017-1 (LQFP176)
Preliminary data sheet
Rev. 01 — 16 July 2007
57
LH79524/LH79525
System-on-Chip
NXP Semiconductors
LFBGA208: plastic low profile fine-pitch ball grid array package; 208 balls
SOT1019-1
D
B
A
ball A1
index area
A
2
A
1
E
A
detail X
e
1
C
M
∅ v
∅ w
C
C
A
B
b
e
1/2 e
y
1
y
M
C
T
R
P
N
M
K
H
e
L
J
e
2
G
1/2 e
F
E
D
B
C
A
ball A1
index area
1
3
5
7
9
11
13
15
X
2
4
6
8
10
12
14
16
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
1
A
2
D
E
e
e
1
e
2
v
w
y
y
1
b
max
0.4
0.3
1.35
1.20
0.5
0.4
14.1 14.1
13.9 13.9
mm
1.7
0.8
12
12
0.15 0.08 0.12
0.1
REFERENCES
JEDEC JEITA
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC
07-07-07
07-07-07
SOT1019-1
Figure 42. Package outline SOT1019-1 (LFBGA208)
58
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
21.25
0.4
1.70
17.2
NOTE: Dimensions in mm.
176LQFP-FP
Figure 43. LH79525: LQFP176 PCB Footprint
208-BALL CABGA
TOP VIEW
A1 BALL
PAD CORNER
3
4 5 6 7 8 9 10
11 12 13 14 15 16
1
2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
0.80
NOTES:
1. Dimensions in mm.
2. Recommended PCB pad diameter: 0.30 mm.
1.00
208CABGA-FP
Figure 44. LH79524: LFBGA208 PCB Footprint
Preliminary data sheet
Rev. 01 — 16 July 2007
59
LH79524/LH79525
System-on-Chip
NXP Semiconductors
REVISION HISTORY
Table 19. Revision history
Document ID
Release date Data sheet status
20070716 Preliminary data
sheet
Change notice Supersedes
LH79524_525_N_1
-
9-29-06 LH79524-525 Data Sheet REV A1
Modifications:
• First NXP version based on the LH79524/LH79525 data sheet of 20060929
60
Rev. 01 — 16 July 2007
Preliminary data sheet
System-on-Chip
LH79524/LH79525
NXP Semiconductors
9. Legal information
9.1
Data sheet status
[1][2]
[3]
Document status
Product status
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the full
data sheet shall prevail.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without limitation
specifications and product descriptions, at any time and without notice. This
document supersedes and replaces all information supplied prior to the
publication hereof.
9.4
Trademarks
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
10. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: salesaddresses@nxp.com
© NXP B.V. 2007. All rights reserved.
IMPORTANT NOTICE
Dear customer,
As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from
Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data
sheets where the previous Sharp or Sharp Corporation references remain, please use the new
links as shown below.
For www.sharpsma.com use www.nxp.com/microcontrollers
for indicated sales addresses use salesaddresses@nxp.com (email)
The copyright notice at the bottom of each page (or elsewhere in the document, depending on the
version)
- Copyright © (year) by SHARP Corporation.
is replaced with:
- © NXP B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via
e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and
understanding, In addition to that the Annex A (attached hereto) is added to the document.
NXP Semiconductors
ANNEX A: Disclaimers (11)
1. t001dis100.fm: General (DS, AN, UM)
General — Information in this document is believed to be accurate and reliable. However, NXP
Semiconductors does not give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability for the consequences of
use of such information.
2. t001dis101.fm: Right to make changes (DS, AN, UM)
Right to make changes — NXP Semiconductors reserves the right to make changes to
information published in this document, including without limitation specifications and product
descriptions, at any time and without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
3. t001dis102.fm: Suitability for use (DS, AN, UM)
Suitability for use — NXP Semiconductors products are not designed, authorized or warranted
to be suitable for use in medical, military, aircraft, space or life support equipment, nor in
applications where failure or malfunction of a NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe property or environmental damage. NXP
Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in
such equipment or applications and therefore such inclusion and/or use is at the customer’s own
risk.
4. t001dis103.fm: Applications (DS, AN, UM)
Applications — Applications that are described herein for any of these products are for
illustrative purposes only. NXP Semiconductors makes no representation or warranty that such
applications will be suitable for the specified use without further testing or modification.
5. t001dis104.fm: Limiting values (DS)
Limiting values — Stress above one or more limiting values (as defined in the Absolute
Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting
values are stress ratings only and operation of the device at these or any other conditions above
those given in the Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
6. t001dis105.fm: Terms and conditions of sale (DS)
Terms and conditions of sale — NXP Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms,
including those pertaining to warranty, intellectual property rights infringement and limitation of
liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any
inconsistency or conflict between information in this document and such terms and conditions, the
latter will prevail.
7. t001dis106.fm: No offer to sell or license (DS)
No offer to sell or license — Nothing in this document may be interpreted or construed as an
offer to sell products that is open for acceptance or the grant, conveyance or implication of any
license under any copyrights, patents or other industrial or intellectual property rights.
8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable)
Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit
voltages up to 60 V may appear when operating this product, depending on settings and
application. Customers incorporating or otherwise using these products in applications where
such high voltages may appear during operation, assembly, test etc. of such application, do so at
their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages
resulting from or in connection with such high voltages. Furthermore, customers are drawn to
safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements
applying to such high voltages.
9. t001dis108.2.fm: Bare die (DS; if applicable)
Bare die (if applicable) — Products indicated as Bare Die are subject to separate specifications
and are not tested in accordance with standard testing procedures. Product warranties and
guarantees as stated in this document are not applicable to Bare Die Products unless such
warranties and guarantees are explicitly stated in a valid separate agreement entered into by
NXP Semiconductors and customer.
10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable)
AEC unqualified products — This product has not been qualified to the appropriate Automotive
Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical
applications, including but not limited to applications where failure or malfunction of an NXP
Semiconductors product can reasonably be expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or
use of NXP Semiconductors products in such equipment or applications and therefore such
inclusion and/or use is for the customer’s own risk.
11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if
applicable)
Suitability for use in automotive applications only — This NXP Semiconductors product has
been developed for use in automotive applications only. The product is not designed, authorized
or warranted to be suitable for any other use, including medical, military, aircraft, space or life
support equipment, nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or severe property or
environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore such inclusion and/or
use is at the customer’s own risk.
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